ar71xx: fix ar724x clock calculation

ar71xx: fix ar724x clock calculation

According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.

The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2.

This patch is compatible with the current calculation procedure with default
DIV and REF_DIV values.

Test on both AR7240, AR7241 and AR7242.

Signed-off-by: Weijie Gao <hackpascal@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@46856 3c298f89-4303-0410-b956-a3cf2f4a3e73