ar71xx: Remove TX/RX delay from pll_1000 for OM5P-AN
authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 20 Apr 2015 15:00:20 +0000 (15:00 +0000)
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 20 Apr 2015 15:00:20 +0000 (15:00 +0000)
commit2d5eb6da31bf46bbc86735d333950e42fa1d3b03
tree212539f2a327c465570dfd0e11c627e9ce5892cf
parenta45f9c063ad5aa990764d99abf049148b512de4a
ar71xx: Remove TX/RX delay from pll_1000 for OM5P-AN

The tx/rx delay bits in the ETH_XMII_CONTROL register have to be unset when the
enable_rgmii_rx_delay/enable_rgmii_tx_delay will be set in the AT803x PHY.
Othwise the throughput in gigabit mode is heavily reduced.

Signed-off-by: Sven Eckelmann <sven@open-mesh.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45521 3c298f89-4303-0410-b956-a3cf2f4a3e73
target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c