ramips: add support for Tenda 3G150B

[openwrt.git] / target / linux / ramips / dts / mt7621.dtsi

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index 7130b67..50cd144 100644 (file)
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -5,7 +5,11 @@
 
        cpus {
                cpu@0 {
-                       compatible = "mips,mips24KEc";
+                       compatible = "mips,mips1004Kc";
+               };
+
+               cpu@1 {
+                       compatible = "mips,mips1004Kc";
                };
        };
 
@@ -98,40 +102,9 @@
                        m25p80@0 {
                                #address-cells = <1>;
                                #size-cells = <1>;
-                               compatible = "en25q64";
                                reg = <0 0>;
-                               linux,modalias = "m25p80", "en25q64";
                                spi-max-frequency = <10000000>;
-
-                               m25p,chunked-io;
-
-                               partition@0 {
-                                       label = "u-boot";
-                                       reg = <0x0 0x30000>;
-                                       read-only;
-                               };
-
-                               partition@30000 {
-                                       label = "u-boot-env";
-                                       reg = <0x30000 0x10000>;
-                                       read-only;
-                               };
-
-                               factory: partition@40000 {
-                                       label = "factory";
-                                       reg = <0x40000 0x10000>;
-                                       read-only;
-                               };
-
-                               partition@50000 {
-                                       label = "firmware";
-                                       reg = <0x50000 0x7a0000>;
-                               };
-
-                               partition@7f0000 {
-                                       label = "test";
-                                       reg = <0x7f0000 0x10000>;
-                               };
+                               m25p,chunked-io = <32>;
                        };
                };
        };
@@ -220,7 +193,7 @@
        };
 
        sdhci@1E130000 {
-               compatible = "ralink,mt7620a-sdhci";
+               compatible = "ralink,mt7620-sdhci";
                reg = <0x1E130000 4000>;
 
                interrupt-parent = <&gic>;
@@ -228,6 +201,8 @@
        };
 
        xhci@1E1C0000 {
+               status = "disabled";
+
                compatible = "xhci-platform";
                reg = <0x1E1C0000 4000>;
 
@@ -279,6 +254,9 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
+               resets = <&rstctrl 6 &rstctrl 23>;
+               reset-names = "fe", "eth";
+
                interrupt-parent = <&gic>;
                interrupts = <3>;
 
@@ -299,4 +277,53 @@
                interrupt-parent = <&gic>;
                interrupts = <23>; 
        };
+
+       pcie@1e140000 {
+               compatible = "mediatek,mt7621-pci";
+               reg = <0x1e140000 0x100
+                       0x1e142000 0x100>;
+
+               #address-cells = <3>;
+               #size-cells = <2>;
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&pcie_pins>;
+
+               device_type = "pci";
+
+               bus-range = <0 255>;
+               ranges = <
+                       0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
+                       0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
+               >;
+
+               status = "okay";
+
+               pcie0 {
+                       reg = <0x0000 0 0 0 0>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       device_type = "pci";
+               };
+
+               pcie1 {
+                       reg = <0x0800 0 0 0 0>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       device_type = "pci";
+               };
+
+               pcie2 {
+                       reg = <0x1000 0 0 0 0>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       device_type = "pci";
+               };
+       };
 };