ipq806x: fix device tree nodes for PCI to get rid of I/O and memory offsets

[openwrt.git] / target / linux / ipq806x / patches-4.1 / 112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch

diff --git a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
index df96ad5..3fbcc39 100644 (file)
--- a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
@@ -15,14 +15,15 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -35,6 +35,22 @@
+@@ -35,6 +35,24 @@
                                bias-disable;
                        };
  
 +                      pcie0_pins: pcie0_pinmux {
 +                              mux {
 +                                      pins = "gpio3";
-+                                      drive-strength = <2>;
++                                      function = "pcie1_rst";
++                                      drive-strength = <12>;
 +                                      bias-disable;
 +                              };
 +                      };
@@ -30,7 +31,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      pcie1_pins: pcie1_pinmux {
 +                              mux {
 +                                      pins = "gpio48";
-+                                      drive-strength = <2>;
++                                      function = "pcie2_rst";
++                                      drive-strength = <12>;
 +                                      bias-disable;
 +                              };
 +                      };
@@ -38,7 +40,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                        spi_pins: spi_pins {
                                mux {
                                        pins = "gpio18", "gpio19", "gpio21";
-@@ -114,5 +130,19 @@
+@@ -91,5 +109,19 @@
                sata@29000000 {
                        status = "ok";
                };
@@ -60,14 +62,15 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  };
 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
-@@ -30,6 +30,30 @@
+@@ -30,6 +30,33 @@
                                bias-disable;
                        };
  
 +                      pcie0_pins: pcie0_pinmux {
 +                              mux {
 +                                      pins = "gpio3";
-+                                      drive-strength = <2>;
++                                      function = "pcie1_rst";
++                                      drive-strength = <12>;
 +                                      bias-disable;
 +                              };
 +                      };
@@ -75,7 +78,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      pcie1_pins: pcie1_pinmux {
 +                              mux {
 +                                      pins = "gpio48";
-+                                      drive-strength = <2>;
++                                      function = "pcie2_rst";
++                                      drive-strength = <12>;
 +                                      bias-disable;
 +                              };
 +                      };
@@ -83,7 +87,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      pcie2_pins: pcie2_pinmux {
 +                              mux {
 +                                      pins = "gpio63";
-+                                      drive-strength = <2>;
++                                      function = "pcie3_rst";
++                                      drive-strength = <12>;
 +                                      bias-disable;
 +                              };
 +                      };
@@ -91,7 +96,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                        spi_pins: spi_pins {
                                mux {
                                        pins = "gpio18", "gpio19", "gpio21";
-@@ -128,5 +152,26 @@
+@@ -128,5 +155,26 @@
                usb30@1 {
                        status = "ok";
                };
@@ -129,10 +134,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  
  / {
        model = "Qualcomm IPQ8064";
-@@ -329,5 +331,127 @@
-                       #reset-cells = <1>;
+@@ -333,6 +335,129 @@
+                       compatible = "syscon";
+                       reg = <0x01200600 0x100>;
                };
- 
++
 +              pcie0: pci@1b500000 {
 +                      compatible = "qcom,pcie-v0";
 +                      reg = <0x1b500000 0x1000
@@ -147,8 +153,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      #address-cells = <3>;
 +                      #size-cells = <2>;
 +
-+                      ranges = <0x81000000 0 0          0x0fe00000 0 0x00100000   /* downstream I/O */
-+                                0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
++                      ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
++                                0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 +
 +                      interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 +                      interrupt-names = "msi";
@@ -188,8 +194,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      #address-cells = <3>;
 +                      #size-cells = <2>;
 +
-+                      ranges = <0x81000000 0 0          0x31e00000 0 0x00100000   /* downstream I/O */
-+                                0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
++                      ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
++                                0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 +
 +                      interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
 +                      interrupt-names = "msi";
@@ -229,8 +235,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      #address-cells = <3>;
 +                      #size-cells = <2>;
 +
-+                      ranges = <0x81000000 0 0          0x35e00000 0 0x00100000   /* downstream I/O */
-+                                0x82000000 0 0x00000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
++                      ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
++                                0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 +
 +                      interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
 +                      interrupt-names = "msi";
@@ -256,4 +262,5 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      status = "disabled";
 +              };
        };
- };
+ 
+       sfpb_mutex: sfpb-mutex {