-diff -Nur linux-2.6.17/arch/mips/aruba/Makefile linux-2.6.17-owrt/arch/mips/aruba/Makefile
---- linux-2.6.17/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/arch/mips/aruba/Makefile 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,49 @@
-+###############################################################################
-+#
-+# BRIEF MODULE DESCRIPTION
-+# Makefile for IDT EB434 BSP
-+#
-+# Copyright 2004 IDT Inc. (rischelp@idt.com)
-+#
-+# This program is free software; you can redistribute it and/or modify it
-+# under the terms of the GNU General Public License as published by the
-+# Free Software Foundation; either version 2 of the License, or (at your
-+# option) any later version.
-+#
-+# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+#
-+# You should have received a copy of the GNU General Public License along
-+# with this program; if not, write to the Free Software Foundation, Inc.,
-+# 675 Mass Ave, Cambridge, MA 02139, USA.
-+#
-+#
-+###############################################################################
-+# May 2004 rkt, neb
-+#
-+# Initial Release
-+#
-+#
-+#
-+###############################################################################
-+
-+
-+# .S.s:
-+# $(CPP) $(CFLAGS) $< -o $*.s
-+# .S.o:
-+# $(CC) $(CFLAGS) -c $< -o $*.o
-+
-+obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o
-+obj-$(CONFIG_SERIAL_8250) += serial.o
-+
-+subdir-y += nvram
-+obj-y += nvram/built-in.o
-+
-diff -Nur linux-2.6.17/arch/mips/aruba/nvram/Makefile linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile
---- linux-2.6.17/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,46 @@
-+###############################################################################
-+#
-+# BRIEF MODULE DESCRIPTION
-+# Makefile for IDT EB434 nvram access routines
-+#
-+# Copyright 2004 IDT Inc. (rischelp@idt.com)
-+#
-+# This program is free software; you can redistribute it and/or modify it
-+# under the terms of the GNU General Public License as published by the
-+# Free Software Foundation; either version 2 of the License, or (at your
-+# option) any later version.
-+#
-+# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+#
-+# You should have received a copy of the GNU General Public License along
-+# with this program; if not, write to the Free Software Foundation, Inc.,
-+# 675 Mass Ave, Cambridge, MA 02139, USA.
-+#
-+#
-+###############################################################################
-+# May 2004 rkt, neb
+diff -Nur linux-2.6.21.1/arch/mips/Kconfig linux-2.6.21.1-owrt/arch/mips/Kconfig
+--- linux-2.6.21.1/arch/mips/Kconfig 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/arch/mips/Kconfig 2007-05-23 23:34:01.000000000 +0200
+@@ -220,6 +220,17 @@
+ <http://www.marvell.com/>. Say Y here if you wish to build a
+ kernel for this platform.
+
++config MACH_ARUBA
++ bool "Support for the ARUBA product line"
++ select DMA_NONCOHERENT
++ select CPU_HAS_PREFETCH
++ select HW_HAS_PCI
++ select SWAP_IO_SPACE
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_SUPPORTS_BIG_ENDIAN
++
++
+ config MACH_JAZZ
+ bool "Jazz family of machines"
+ select ARC
+diff -Nur linux-2.6.21.1/arch/mips/Makefile linux-2.6.21.1-owrt/arch/mips/Makefile
+--- linux-2.6.21.1/arch/mips/Makefile 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/arch/mips/Makefile 2007-05-23 23:34:01.000000000 +0200
+@@ -158,6 +158,14 @@
+ #
+
+ #
++# Aruba
+#
-+# Initial Release
++
++core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
++cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
++load-$(CONFIG_MACH_ARUBA) += 0x80100000
++
+#
+ # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
+ #
+ core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
+diff -Nur linux-2.6.21.1/arch/mips/pci/Makefile linux-2.6.21.1-owrt/arch/mips/pci/Makefile
+--- linux-2.6.21.1/arch/mips/pci/Makefile 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/arch/mips/pci/Makefile 2007-05-23 23:36:48.000000000 +0200
+@@ -53,3 +53,4 @@
+ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
+ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
+ obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
++obj-$(CONFIG_MACH_ARUBA) += fixup-aruba.o ops-aruba.o pci-aruba.o
+diff -Nur linux-2.6.21.1/drivers/char/watchdog/Makefile linux-2.6.21.1-owrt/drivers/char/watchdog/Makefile
+--- linux-2.6.21.1/drivers/char/watchdog/Makefile 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/drivers/char/watchdog/Makefile 2007-05-23 23:36:53.000000000 +0200
+@@ -82,5 +82,8 @@
+
+ # SPARC64 Architecture
+
++# Aruba Architecture
++obj-$(CONFIG_MACH_ARUBA) += wdt_merlot.o
++
+ # Architecture Independant
+ obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
+diff -Nur linux-2.6.21.1/drivers/char/watchdog/Makefile.orig linux-2.6.21.1-owrt/drivers/char/watchdog/Makefile.orig
+--- linux-2.6.21.1/drivers/char/watchdog/Makefile.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/drivers/char/watchdog/Makefile.orig 2007-04-27 23:49:26.000000000 +0200
+@@ -0,0 +1,86 @@
+#
++# Makefile for the WatchDog device drivers.
+#
-+###############################################################################
+
-+obj-y := nvram434.o
-+obj-m := $(O_TARGET)
++# Only one watchdog can succeed. We probe the ISA/PCI/USB based
++# watchdog-cards first, then the architecture specific watchdog
++# drivers and then the architecture independant "softdog" driver.
++# This means that if your ISA/PCI/USB card isn't detected that
++# you can fall back to an architecture specific driver and if
++# that also fails then you can fall back to the software watchdog
++# to give you some cover.
++
++# ISA-based Watchdog Cards
++obj-$(CONFIG_PCWATCHDOG) += pcwd.o
++obj-$(CONFIG_MIXCOMWD) += mixcomwd.o
++obj-$(CONFIG_WDT) += wdt.o
++
++# PCI-based Watchdog Cards
++obj-$(CONFIG_PCIPCWATCHDOG) += pcwd_pci.o
++obj-$(CONFIG_WDTPCI) += wdt_pci.o
++
++# USB-based Watchdog Cards
++obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
++
++# ARM Architecture
++obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
++obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
++obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
++obj-$(CONFIG_977_WATCHDOG) += wdt977.o
++obj-$(CONFIG_IXP2000_WATCHDOG) += ixp2000_wdt.o
++obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
++obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
++obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
++obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
++obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
++obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
++
++# X86 (i386 + ia64 + x86_64) Architecture
++obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o
++obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o
++obj-$(CONFIG_ALIM1535_WDT) += alim1535_wdt.o
++obj-$(CONFIG_ALIM7101_WDT) += alim7101_wdt.o
++obj-$(CONFIG_SC520_WDT) += sc520_wdt.o
++obj-$(CONFIG_EUROTECH_WDT) += eurotechwdt.o
++obj-$(CONFIG_IB700_WDT) += ib700wdt.o
++obj-$(CONFIG_IBMASR) += ibmasr.o
++obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
++obj-$(CONFIG_I6300ESB_WDT) += i6300esb.o
++obj-$(CONFIG_I8XX_TCO) += i8xx_tco.o
++obj-$(CONFIG_ITCO_WDT) += iTCO_wdt.o iTCO_vendor_support.o
++obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
++obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
++obj-$(CONFIG_PC87413_WDT) += pc87413_wdt.o
++obj-$(CONFIG_60XX_WDT) += sbc60xxwdt.o
++obj-$(CONFIG_SBC8360_WDT) += sbc8360.o
++obj-$(CONFIG_CPU5_WDT) += cpu5wdt.o
++obj-$(CONFIG_SMSC37B787_WDT) += smsc37b787_wdt.o
++obj-$(CONFIG_W83627HF_WDT) += w83627hf_wdt.o
++obj-$(CONFIG_W83697HF_WDT) += w83697hf_wdt.o
++obj-$(CONFIG_W83877F_WDT) += w83877f_wdt.o
++obj-$(CONFIG_W83977F_WDT) += w83977f_wdt.o
++obj-$(CONFIG_MACHZ_WDT) += machzwd.o
++obj-$(CONFIG_SBC_EPX_C3_WATCHDOG) += sbc_epx_c3.o
++
++# PowerPC Architecture
++obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o
++obj-$(CONFIG_83xx_WDT) += mpc83xx_wdt.o
++obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o
++obj-$(CONFIG_BOOKE_WDT) += booke_wdt.o
++
++# PPC64 Architecture
++obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o
++
++# MIPS Architecture
++obj-$(CONFIG_INDYDOG) += indydog.o
++obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
++
++# S390 Architecture
++
++# SUPERH Architecture
++obj-$(CONFIG_SH_WDT) += shwdt.o
++
++# SPARC64 Architecture
++
++# Architecture Independant
++obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
+diff -Nur linux-2.6.21.1/drivers/mtd/chips/cfi_probe.c linux-2.6.21.1-owrt/drivers/mtd/chips/cfi_probe.c
+--- linux-2.6.21.1/drivers/mtd/chips/cfi_probe.c 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/drivers/mtd/chips/cfi_probe.c 2007-05-23 23:36:42.000000000 +0200
+@@ -25,6 +25,74 @@
+ static void print_cfi_ident(struct cfi_ident *);
+ #endif
+
++#if 1
++
++#define AMD_AUTOSEL_OFF1 0xAAA
++#define AMD_AUTOSEL_OFF2 0x555
++#define AMD_MANUF_ID 0x1
++#define AMD_DEVICE_ID1 0xF6 /* T */
++#define AMD_DEVICE_ID2 0xF9 /* B */
++/* Foll. are definitions for Macronix Flash Part */
++#define MCX_MANUF_ID 0xC2
++#define MCX_DEVICE_ID1 0xA7
++#define MCX_DEVICE_ID2 0xA8
++/* Foll. common to both AMD and Macronix */
++#define FACTORY_LOCKED 0x99
++#define USER_LOCKED 0x19
++
++/* NOTE: AP-70/6x use BYTE mode flash access. Therefore the
++ * lowest Addr. pin in the flash is not A0 but A-1 (A minus 1).
++ * CPU's A0 is tied to Flash's A-1, A1 to A0 and so on. This
++ * gives 4MB of byte-addressable mem. In byte mode, all addr
++ * need to be multiplied by 2 (i.e compared to word mode).
++ * NOTE: AMD_AUTOSEL_OFF1 and OFF2 are already mult. by 2
++ * Just blindly use the addr offsets suggested in the manual
++ * for byte mode and you'll be OK. Offs. in Table 6 need to
++ * be mult by 2 (for getting autosel params)
++ */
++void
++flash_detect(struct map_info *map, __u32 base, struct cfi_private *cfi)
++{
++ map_word val[3];
++ int osf = cfi->interleave * cfi->device_type; // =2 for AP70/6x
++ char *manuf, *part, *lock ;
+
++ if (osf != 1) return ;
+
++ cfi_send_gen_cmd(0xAA, AMD_AUTOSEL_OFF1, base, map, cfi, cfi->device_type, NULL);
++ cfi_send_gen_cmd(0x55, AMD_AUTOSEL_OFF2, base, map, cfi, cfi->device_type, NULL);
++ cfi_send_gen_cmd(0x90, AMD_AUTOSEL_OFF1, base, map, cfi, cfi->device_type, NULL);
++ val[0] = map_read(map, base) ; // manuf ID
++ val[1] = map_read(map, base+2) ; // device ID
++ val[2] = map_read(map, base+6) ; // lock indicator
++#if 0
++printk("v1=0x%x v2=0x%x v3=0x%x\n", val[0], val[1], val[2]) ;
++#endif
++ if (val[0].x[0] == AMD_MANUF_ID) {
++ manuf = "AMD Flash" ;
++ if (val[1].x[0] == AMD_DEVICE_ID1)
++ part = "AM29LV320D (Top)" ;
++ else if (val[1].x[0] == AMD_DEVICE_ID2)
++ part = "AM29LV320D (Bot)" ;
++ else part = "Unknown" ;
++ } else if (val[0].x[0] == MCX_MANUF_ID) {
++ manuf = "Macronix Flash" ;
++ if (val[1].x[0] == MCX_DEVICE_ID1)
++ part = "MX29LV320A (Top)" ;
++ else if (val[1].x[0] == MCX_DEVICE_ID2)
++ part = "MX29LV320A (Bot)" ;
++ else part = "Unknown" ;
++ } else
++ return ;
++ if (val[2].x[0] == FACTORY_LOCKED)
++ lock = "Factory Locked" ;
++ else if (val[2].x[0] == USER_LOCKED)
++ lock = "User Locked" ;
++ else lock = "Unknown locking" ;
++ printk("%s %s (%s)\n", manuf, part, lock) ;
++}
++#endif
+
+ static int cfi_probe_chip(struct map_info *map, __u32 base,
+ unsigned long *chip_map, struct cfi_private *cfi);
+ static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi);
+@@ -117,6 +185,10 @@
+ }
+
+ xip_disable();
++#if 1
++ //cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
++ flash_detect(map, base, cfi) ;
++#endif
+ cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
+ cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
+ cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL);
+diff -Nur linux-2.6.21.1/drivers/mtd/chips/cfi_probe.c.orig linux-2.6.21.1-owrt/drivers/mtd/chips/cfi_probe.c.orig
+--- linux-2.6.21.1/drivers/mtd/chips/cfi_probe.c.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/drivers/mtd/chips/cfi_probe.c.orig 2007-04-27 23:49:26.000000000 +0200
+@@ -0,0 +1,444 @@
++/*
++ Common Flash Interface probe code.
++ (C) 2000 Red Hat. GPL'd.
++ $Id: cfi_probe.c,v 1.86 2005/11/29 14:48:31 gleixner Exp $
++*/
+
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <asm/io.h>
++#include <asm/byteorder.h>
++#include <linux/errno.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
+
++#include <linux/mtd/xip.h>
++#include <linux/mtd/map.h>
++#include <linux/mtd/cfi.h>
++#include <linux/mtd/gen_probe.h>
+
++//#define DEBUG_CFI
+
-diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.c linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c
---- linux-2.6.17/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,392 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * nvram interface routines.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++#ifdef DEBUG_CFI
++static void print_cfi_ident(struct cfi_ident *);
++#endif
+
-+#include <linux/ctype.h>
-+#include <linux/string.h>
++static int cfi_probe_chip(struct map_info *map, __u32 base,
++ unsigned long *chip_map, struct cfi_private *cfi);
++static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi);
+
-+//#include <asm/ds1553rtc.h>
-+#include "nvram434.h"
-+#define NVRAM_BASE 0xbfff8000
++struct mtd_info *cfi_probe(struct map_info *map);
+
-+extern void setenv (char *e, char *v, int rewrite);
-+extern void unsetenv (char *e);
-+extern void mapenv (int (*func)(char *, char *));
-+extern char *getenv (char *s);
-+extern void purgeenv(void);
++#ifdef CONFIG_MTD_XIP
+
-+static void nvram_initenv(void);
++/* only needed for short periods, so this is rather simple */
++#define xip_disable() local_irq_disable()
+
-+static unsigned char
-+nvram_getbyte(int offs)
-+{
-+ return(*((unsigned char*)(NVRAM_BASE + offs)));
-+}
++#define xip_allowed(base, map) \
++do { \
++ (void) map_read(map, base); \
++ asm volatile (".rep 8; nop; .endr"); \
++ local_irq_enable(); \
++} while (0)
+
-+static void
-+nvram_setbyte(int offs, unsigned char val)
-+{
-+ unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
++#define xip_enable(base, map, cfi) \
++do { \
++ cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); \
++ cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); \
++ xip_allowed(base, map); \
++} while (0)
+
-+ *nvramDataPointer = val;
-+}
++#define xip_disable_qry(base, map, cfi) \
++do { \
++ xip_disable(); \
++ cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); \
++ cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); \
++ cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL); \
++} while (0)
+
-+/*
-+ * BigEndian!
-+ */
-+static unsigned short
-+nvram_getshort(int offs)
-+{
-+ return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
-+}
++#else
+
-+static void
-+nvram_setshort(int offs, unsigned short val)
-+{
-+ nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
-+ nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
-+}
-+#if 0
-+static unsigned int
-+nvram_getint(int offs)
-+{
-+ unsigned int val;
-+ val = nvram_getbyte(offs) << 24;
-+ val |= nvram_getbyte(offs + 1) << 16;
-+ val |= nvram_getbyte(offs + 2) << 8;
-+ val |= nvram_getbyte(offs + 3);
-+ return(val);
-+}
++#define xip_disable() do { } while (0)
++#define xip_allowed(base, map) do { } while (0)
++#define xip_enable(base, map, cfi) do { } while (0)
++#define xip_disable_qry(base, map, cfi) do { } while (0)
+
-+static void
-+nvram_setint(int offs, unsigned int val)
-+{
-+ nvram_setbyte(offs, val >> 24);
-+ nvram_setbyte(offs + 1, val >> 16);
-+ nvram_setbyte(offs + 2, val >> 8);
-+ nvram_setbyte(offs + 3, val);
-+}
+#endif
-+/*
-+ * calculate NVRAM checksum
++
++/* check for QRY.
++ in: interleave,type,mode
++ ret: table index, <0 for error
+ */
-+static unsigned short
-+nvram_calcsum(void)
++static int __xipram qry_present(struct map_info *map, __u32 base,
++ struct cfi_private *cfi)
+{
-+ unsigned short sum = NV_MAGIC;
-+ int i;
++ int osf = cfi->interleave * cfi->device_type; // scale factor
++ map_word val[3];
++ map_word qry[3];
+
-+ for (i = ENV_BASE; i < ENV_TOP; i += 2)
-+ sum += nvram_getshort(i);
-+ return(sum);
-+}
++ qry[0] = cfi_build_cmd('Q', map, cfi);
++ qry[1] = cfi_build_cmd('R', map, cfi);
++ qry[2] = cfi_build_cmd('Y', map, cfi);
+
-+/*
-+ * update the nvram checksum
-+ */
-+static void
-+nvram_updatesum (void)
-+{
-+ nvram_setshort(NVOFF_CSUM, nvram_calcsum());
-+}
++ val[0] = map_read(map, base + osf*0x10);
++ val[1] = map_read(map, base + osf*0x11);
++ val[2] = map_read(map, base + osf*0x12);
+
-+/*
-+ * test validity of nvram by checksumming it
-+ */
-+static int
-+nvram_isvalid(void)
-+{
-+ static int is_valid;
++ if (!map_word_equal(map, qry[0], val[0]))
++ return 0;
+
-+ if (is_valid)
-+ return(1);
++ if (!map_word_equal(map, qry[1], val[1]))
++ return 0;
++
++ if (!map_word_equal(map, qry[2], val[2]))
++ return 0;
+
-+ if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
-+ printk("nvram_isvalid FAILED\n");
-+ //nvram_initenv();
-+ }
-+ is_valid = 1;
-+ return(1);
++ return 1; // "QRY" found
+}
+
-+/* return nvram address of environment string */
-+static int
-+nvram_matchenv(char *s)
++static int __xipram cfi_probe_chip(struct map_info *map, __u32 base,
++ unsigned long *chip_map, struct cfi_private *cfi)
+{
-+ int envsize, envp, n, i, varsize;
-+ char *var;
-+
-+ envsize = nvram_getshort(NVOFF_ENVSIZE);
-+
-+ if (envsize > ENV_AVAIL)
-+ return(0); /* sanity */
-+
-+ envp = ENV_BASE;
-+
-+ if ((n = strlen (s)) > 255)
-+ return(0);
-+
-+ while (envsize > 0) {
-+ varsize = nvram_getbyte(envp);
-+ if (varsize == 0 || (envp + varsize) > ENV_TOP)
-+ return(0); /* sanity */
-+ for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
-+ char c1 = nvram_getbyte(i);
-+ char c2 = *var;
-+ if (islower(c1))
-+ c1 = toupper(c1);
-+ if (islower(c2))
-+ c2 = toupper(c2);
-+ if (c1 != c2)
-+ break;
-+ }
-+ if (i > envp + n) { /* match so far */
-+ if (n == varsize - 1) /* match on boolean */
-+ return(envp);
-+ if (nvram_getbyte(i) == '=') /* exact match on variable */
-+ return(envp);
-+ }
-+ envsize -= varsize;
-+ envp += varsize;
-+ }
-+ return(0);
-+}
-+
-+static void nvram_initenv(void)
-+{
-+ nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
-+ nvram_setshort(NVOFF_ENVSIZE, 0);
++ int i;
+
-+ nvram_updatesum();
-+}
++ if ((base + 0) >= map->size) {
++ printk(KERN_NOTICE
++ "Probe at base[0x00](0x%08lx) past the end of the map(0x%08lx)\n",
++ (unsigned long)base, map->size -1);
++ return 0;
++ }
++ if ((base + 0xff) >= map->size) {
++ printk(KERN_NOTICE
++ "Probe at base[0x55](0x%08lx) past the end of the map(0x%08lx)\n",
++ (unsigned long)base + 0x55, map->size -1);
++ return 0;
++ }
+
-+static void
-+nvram_delenv(char *s)
-+{
-+ int nenvp, envp, envsize, nbytes;
++ xip_disable();
++ cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
++ cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
++ cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL);
+
-+ envp = nvram_matchenv(s);
-+ if (envp == 0)
-+ return;
++ if (!qry_present(map,base,cfi)) {
++ xip_enable(base, map, cfi);
++ return 0;
++ }
+
-+ nenvp = envp + nvram_getbyte(envp);
-+ envsize = nvram_getshort(NVOFF_ENVSIZE);
-+ nbytes = envsize - (nenvp - ENV_BASE);
-+ nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
-+ while (nbytes--) {
-+ nvram_setbyte(envp, nvram_getbyte(nenvp));
-+ envp++;
-+ nenvp++;
-+ }
-+ nvram_updatesum();
-+}
++ if (!cfi->numchips) {
++ /* This is the first time we're called. Set up the CFI
++ stuff accordingly and return */
++ return cfi_chip_setup(map, cfi);
++ }
+
-+static int
-+nvram_setenv(char *s, char *v)
-+{
-+ int ns, nv, total;
-+ int envp;
-+
-+ if (!nvram_isvalid())
-+ return(-1);
-+
-+ nvram_delenv(s);
-+ ns = strlen(s);
-+ if (ns == 0)
-+ return (-1);
-+ if (v && *v) {
-+ nv = strlen(v);
-+ total = ns + nv + 2;
-+ }
-+ else {
-+ nv = 0;
-+ total = ns + 1;
-+ }
-+ if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
-+ return(-1);
-+
-+ envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
-+
-+ nvram_setbyte(envp, (unsigned char) total);
-+ envp++;
-+
-+ while (ns--) {
-+ nvram_setbyte(envp, *s);
-+ envp++;
-+ s++;
-+ }
-+
-+ if (nv) {
-+ nvram_setbyte(envp, '=');
-+ envp++;
-+ while (nv--) {
-+ nvram_setbyte(envp, *v);
-+ envp++;
-+ v++;
-+ }
-+ }
-+ nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
-+ nvram_updatesum();
-+ return 0;
-+}
-+
-+static char *
-+nvram_getenv(char *s)
-+{
-+ static char buf[256]; /* FIXME: this cannot be static */
-+ int envp, ns, nbytes, i;
-+
-+ if (!nvram_isvalid())
-+ return "INVALID NVRAM"; //((char *)0);
-+
-+ envp = nvram_matchenv(s);
-+ if (envp == 0)
-+ return "NOT FOUND"; //((char *)0);
-+ ns = strlen(s);
-+ if (nvram_getbyte(envp) == ns + 1) /* boolean */
-+ buf[0] = '\0';
-+ else {
-+ nbytes = nvram_getbyte(envp) - (ns + 2);
-+ envp += ns + 2;
-+ for (i = 0; i < nbytes; i++)
-+ buf[i] = nvram_getbyte(envp++);
-+ buf[i] = '\0';
-+ }
-+ return(buf);
-+}
++ /* Check each previous chip to see if it's an alias */
++ for (i=0; i < (base >> cfi->chipshift); i++) {
++ unsigned long start;
++ if(!test_bit(i, chip_map)) {
++ /* Skip location; no valid chip at this address */
++ continue;
++ }
++ start = i << cfi->chipshift;
++ /* This chip should be in read mode if it's one
++ we've already touched. */
++ if (qry_present(map, start, cfi)) {
++ /* Eep. This chip also had the QRY marker.
++ * Is it an alias for the new one? */
++ cfi_send_gen_cmd(0xF0, 0, start, map, cfi, cfi->device_type, NULL);
++ cfi_send_gen_cmd(0xFF, 0, start, map, cfi, cfi->device_type, NULL);
++
++ /* If the QRY marker goes away, it's an alias */
++ if (!qry_present(map, start, cfi)) {
++ xip_allowed(base, map);
++ printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
++ map->name, base, start);
++ return 0;
++ }
++ /* Yes, it's actually got QRY for data. Most
++ * unfortunate. Stick the new chip in read mode
++ * too and if it's the same, assume it's an alias. */
++ /* FIXME: Use other modes to do a proper check */
++ cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
++ cfi_send_gen_cmd(0xFF, 0, start, map, cfi, cfi->device_type, NULL);
++
++ if (qry_present(map, base, cfi)) {
++ xip_allowed(base, map);
++ printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
++ map->name, base, start);
++ return 0;
++ }
++ }
++ }
+
-+static void
-+nvram_unsetenv(char *s)
-+{
-+ if (!nvram_isvalid())
-+ return;
++ /* OK, if we got to here, then none of the previous chips appear to
++ be aliases for the current one. */
++ set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */
++ cfi->numchips++;
+
-+ nvram_delenv(s);
-+}
++ /* Put it back into Read Mode */
++ cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
++ cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
++ xip_allowed(base, map);
+
-+/*
-+ * apply func to each string in environment
-+ */
-+static void
-+nvram_mapenv(int (*func)(char *, char *))
-+{
-+ int envsize, envp, n, i, seeneql;
-+ char name[256], value[256];
-+ char c, *s;
-+
-+ if (!nvram_isvalid())
-+ return;
-+
-+ envsize = nvram_getshort(NVOFF_ENVSIZE);
-+ envp = ENV_BASE;
-+
-+ while (envsize > 0) {
-+ value[0] = '\0';
-+ seeneql = 0;
-+ s = name;
-+ n = nvram_getbyte(envp);
-+ for (i = envp + 1; i < envp + n; i++) {
-+ c = nvram_getbyte(i);
-+ if ((c == '=') && !seeneql) {
-+ *s = '\0';
-+ s = value;
-+ seeneql = 1;
-+ continue;
-+ }
-+ *s++ = c;
-+ }
-+ *s = '\0';
-+ (*func)(name, value);
-+ envsize -= n;
-+ envp += n;
-+ }
++ printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n",
++ map->name, cfi->interleave, cfi->device_type*8, base,
++ map->bankwidth*8);
++
++ return 1;
+}
-+#if 0
-+static unsigned int
-+digit(char c)
++
++static int __xipram cfi_chip_setup(struct map_info *map,
++ struct cfi_private *cfi)
+{
-+ if ('0' <= c && c <= '9')
-+ return (c - '0');
-+ if ('A' <= c && c <= 'Z')
-+ return (10 + c - 'A');
-+ if ('a' <= c && c <= 'z')
-+ return (10 + c - 'a');
-+ return (~0);
-+}
++ int ofs_factor = cfi->interleave*cfi->device_type;
++ __u32 base = 0;
++ int num_erase_regions = cfi_read_query(map, base + (0x10 + 28)*ofs_factor);
++ int i;
++
++ xip_enable(base, map, cfi);
++#ifdef DEBUG_CFI
++ printk("Number of erase regions: %d\n", num_erase_regions);
+#endif
-+/*
-+ * Wrappers to allow 'special' environment variables to get processed
-+ */
-+void
-+setenv(char *e, char *v, int rewrite)
-+{
-+ if (nvram_getenv(e) && !rewrite)
-+ return;
-+
-+ nvram_setenv(e, v);
-+}
++ if (!num_erase_regions)
++ return 0;
+
-+char *
-+getenv(char *e)
-+{
-+ return(nvram_getenv(e));
-+}
++ cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
++ if (!cfi->cfiq) {
++ printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name);
++ return 0;
++ }
+
-+void
-+unsetenv(char *e)
-+{
-+ nvram_unsetenv(e);
-+}
++ memset(cfi->cfiq,0,sizeof(struct cfi_ident));
+
-+void
-+purgeenv()
-+{
-+ int i;
-+ unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
-+
-+ for (i = ENV_BASE; i < ENV_TOP; i++)
-+ *nvramDataPointer++ = 0;
-+ nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
-+ nvram_setshort(NVOFF_ENVSIZE, 0);
-+ nvram_setshort(NVOFF_CSUM, NV_MAGIC);
-+}
++ cfi->cfi_mode = CFI_MODE_CFI;
+
-+void
-+mapenv(int (*func)(char *, char *))
-+{
-+ nvram_mapenv(func);
-+}
-diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.h linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h
---- linux-2.6.17/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,66 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * nvram definitions.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ /* Read the CFI info structure */
++ xip_disable_qry(base, map, cfi);
++ for (i=0; i<(sizeof(struct cfi_ident) + num_erase_regions * 4); i++)
++ ((unsigned char *)cfi->cfiq)[i] = cfi_read_query(map,base + (0x10 + i)*ofs_factor);
+
++ /* Note we put the device back into Read Mode BEFORE going into Auto
++ * Select Mode, as some devices support nesting of modes, others
++ * don't. This way should always work.
++ * On cmdset 0001 the writes of 0xaa and 0x55 are not needed, and
++ * so should be treated as nops or illegal (and so put the device
++ * back into Read Mode, which is a nop in this case).
++ */
++ cfi_send_gen_cmd(0xf0, 0, base, map, cfi, cfi->device_type, NULL);
++ cfi_send_gen_cmd(0xaa, 0x555, base, map, cfi, cfi->device_type, NULL);
++ cfi_send_gen_cmd(0x55, 0x2aa, base, map, cfi, cfi->device_type, NULL);
++ cfi_send_gen_cmd(0x90, 0x555, base, map, cfi, cfi->device_type, NULL);
++ cfi->mfr = cfi_read_query16(map, base);
++ cfi->id = cfi_read_query16(map, base + ofs_factor);
++
++ /* Put it back into Read Mode */
++ cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
++ /* ... even if it's an Intel chip */
++ cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
++ xip_allowed(base, map);
++
++ /* Do any necessary byteswapping */
++ cfi->cfiq->P_ID = le16_to_cpu(cfi->cfiq->P_ID);
++
++ cfi->cfiq->P_ADR = le16_to_cpu(cfi->cfiq->P_ADR);
++ cfi->cfiq->A_ID = le16_to_cpu(cfi->cfiq->A_ID);
++ cfi->cfiq->A_ADR = le16_to_cpu(cfi->cfiq->A_ADR);
++ cfi->cfiq->InterfaceDesc = le16_to_cpu(cfi->cfiq->InterfaceDesc);
++ cfi->cfiq->MaxBufWriteSize = le16_to_cpu(cfi->cfiq->MaxBufWriteSize);
++
++#ifdef DEBUG_CFI
++ /* Dump the information therein */
++ print_cfi_ident(cfi->cfiq);
++#endif
+
-+#ifndef _NVRAM_
-+#define _NVRAM_
-+#define NVOFFSET 0 /* use all of NVRAM */
++ for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
++ cfi->cfiq->EraseRegionInfo[i] = le32_to_cpu(cfi->cfiq->EraseRegionInfo[i]);
+
-+/* Offsets to reserved locations */
-+ /* size description */
-+#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
-+#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
-+#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
-+#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
-+#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
-+#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
++#ifdef DEBUG_CFI
++ printk(" Erase Region #%d: BlockSize 0x%4.4X bytes, %d blocks\n",
++ i, (cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff,
++ (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1);
++#endif
++ }
+
-+#define NV_MAGIC 0xdeaf /* nvram magic number */
-+#define NV_RESERVED 6 /* number of reserved bytes */
++ printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n",
++ map->name, cfi->interleave, cfi->device_type*8, base,
++ map->bankwidth*8);
+
-+#undef NVOFF_ETHADDR
-+#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
++ return 1;
++}
+
-+/* number of bytes available for environment */
-+#define ENV_BASE (NVOFFSET + NV_RESERVED)
-+#define ENV_TOP 0x2000
-+#define ENV_AVAIL (ENV_TOP - ENV_BASE)
++#ifdef DEBUG_CFI
++static char *vendorname(__u16 vendor)
++{
++ switch (vendor) {
++ case P_ID_NONE:
++ return "None";
+
-+#endif /* _NVRAM_ */
++ case P_ID_INTEL_EXT:
++ return "Intel/Sharp Extended";
+
++ case P_ID_AMD_STD:
++ return "AMD/Fujitsu Standard";
+
-diff -Nur linux-2.6.17/arch/mips/aruba/prom.c linux-2.6.17-owrt/arch/mips/aruba/prom.c
---- linux-2.6.17/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/arch/mips/aruba/prom.c 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,111 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * prom interface routines
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ case P_ID_INTEL_STD:
++ return "Intel/Sharp Standard";
+
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/module.h>
-+#include <linux/string.h>
-+#include <linux/console.h>
-+#include <asm/bootinfo.h>
-+#include <linux/bootmem.h>
-+#include <linux/ioport.h>
-+#include <linux/serial.h>
-+#include <linux/serialP.h>
-+#include <asm/serial.h>
-+#include <linux/ioport.h>
++ case P_ID_AMD_EXT:
++ return "AMD/Fujitsu Extended";
+
-+unsigned int idt_cpu_freq;
-+EXPORT_SYMBOL(idt_cpu_freq);
++ case P_ID_WINBOND:
++ return "Winbond Standard";
+
-+unsigned int arch_has_pci=0;
++ case P_ID_ST_ADV:
++ return "ST Advanced";
+
-+/* Kernel Boot parameters */
-+static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
++ case P_ID_MITSUBISHI_STD:
++ return "Mitsubishi Standard";
+
-+extern unsigned long mips_machgroup;
-+extern unsigned long mips_machtype;
++ case P_ID_MITSUBISHI_EXT:
++ return "Mitsubishi Extended";
+
-+extern void setup_serial_port(void);
-+extern char * getenv(char *e);
++ case P_ID_SST_PAGE:
++ return "SST Page Write";
+
-+/* IDT 79EB434 memory map -- we really should be auto sizing it */
-+#define RAM_SIZE 32*1024*1024
++ case P_ID_INTEL_PERFORMANCE:
++ return "Intel Performance Code";
+
-+char *__init prom_getcmdline(void)
-+{
-+ return &(arcs_cmdline[0]);
++ case P_ID_INTEL_DATA:
++ return "Intel Data";
++
++ case P_ID_RESERVED:
++ return "Not Allowed / Reserved for Future Use";
++
++ default:
++ return "Unknown";
++ }
+}
+
-+void __init prom_init(void)
++
++static void print_cfi_ident(struct cfi_ident *cfip)
+{
-+ char *boardname;
-+ sprintf(arcs_cmdline, "%s", bootparm);
-+
-+ /* set our arch type */
-+ mips_machgroup = MACH_GROUP_ARUBA;
-+ mips_machtype = MACH_ARUBA_UNKNOWN;
-+
-+ boardname=getenv("boardname");
-+
-+ if (!strcmp(boardname,"Muscat")) {
-+ mips_machtype = MACH_ARUBA_AP70;
-+ idt_cpu_freq = 133000000;
-+ arch_has_pci=1;
-+ } else if (!strcmp(boardname,"Mataro")) {
-+ mips_machtype = MACH_ARUBA_AP65;
-+ idt_cpu_freq = 110000000;
-+ } else if (!strcmp(boardname,"Merlot")) {
-+ mips_machtype = MACH_ARUBA_AP60;
-+ idt_cpu_freq = 90000000;
++#if 0
++ if (cfip->qry[0] != 'Q' || cfip->qry[1] != 'R' || cfip->qry[2] != 'Y') {
++ printk("Invalid CFI ident structure.\n");
++ return;
+ }
++#endif
++ printk("Primary Vendor Command Set: %4.4X (%s)\n", cfip->P_ID, vendorname(cfip->P_ID));
++ if (cfip->P_ADR)
++ printk("Primary Algorithm Table at %4.4X\n", cfip->P_ADR);
++ else
++ printk("No Primary Algorithm Table\n");
+
-+ /* turn on the console */
-+ setup_serial_port();
-+
-+ /*
-+ * give all RAM to boot allocator,
-+ * except where the kernel was loaded
-+ */
-+ add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
-+}
++ printk("Alternative Vendor Command Set: %4.4X (%s)\n", cfip->A_ID, vendorname(cfip->A_ID));
++ if (cfip->A_ADR)
++ printk("Alternate Algorithm Table at %4.4X\n", cfip->A_ADR);
++ else
++ printk("No Alternate Algorithm Table\n");
+
-+void prom_free_prom_memory(void)
-+{
-+ printk("stubbed prom_free_prom_memory()\n");
-+}
-diff -Nur linux-2.6.17/arch/mips/aruba/serial.c linux-2.6.17-owrt/arch/mips/aruba/serial.c
---- linux-2.6.17/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/arch/mips/aruba/serial.c 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,94 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Serial port initialisation.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
+
++ printk("Vcc Minimum: %2d.%d V\n", cfip->VccMin >> 4, cfip->VccMin & 0xf);
++ printk("Vcc Maximum: %2d.%d V\n", cfip->VccMax >> 4, cfip->VccMax & 0xf);
++ if (cfip->VppMin) {
++ printk("Vpp Minimum: %2d.%d V\n", cfip->VppMin >> 4, cfip->VppMin & 0xf);
++ printk("Vpp Maximum: %2d.%d V\n", cfip->VppMax >> 4, cfip->VppMax & 0xf);
++ }
++ else
++ printk("No Vpp line\n");
+
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/pci.h>
-+#include <linux/interrupt.h>
-+#include <linux/tty.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
++ printk("Typical byte/word write timeout: %d µs\n", 1<<cfip->WordWriteTimeoutTyp);
++ printk("Maximum byte/word write timeout: %d µs\n", (1<<cfip->WordWriteTimeoutMax) * (1<<cfip->WordWriteTimeoutTyp));
+
-+#include <asm/time.h>
-+#include <asm/cpu.h>
-+#include <asm/bootinfo.h>
-+#include <asm/irq.h>
-+#include <asm/serial.h>
++ if (cfip->BufWriteTimeoutTyp || cfip->BufWriteTimeoutMax) {
++ printk("Typical full buffer write timeout: %d µs\n", 1<<cfip->BufWriteTimeoutTyp);
++ printk("Maximum full buffer write timeout: %d µs\n", (1<<cfip->BufWriteTimeoutMax) * (1<<cfip->BufWriteTimeoutTyp));
++ }
++ else
++ printk("Full buffer write not supported\n");
+
-+#include <asm/idt-boards/rc32434/rc32434.h>
++ printk("Typical block erase timeout: %d ms\n", 1<<cfip->BlockEraseTimeoutTyp);
++ printk("Maximum block erase timeout: %d ms\n", (1<<cfip->BlockEraseTimeoutMax) * (1<<cfip->BlockEraseTimeoutTyp));
++ if (cfip->ChipEraseTimeoutTyp || cfip->ChipEraseTimeoutMax) {
++ printk("Typical chip erase timeout: %d ms\n", 1<<cfip->ChipEraseTimeoutTyp);
++ printk("Maximum chip erase timeout: %d ms\n", (1<<cfip->ChipEraseTimeoutMax) * (1<<cfip->ChipEraseTimeoutTyp));
++ }
++ else
++ printk("Chip erase not supported\n");
++
++ printk("Device size: 0x%X bytes (%d MiB)\n", 1 << cfip->DevSize, 1<< (cfip->DevSize - 20));
++ printk("Flash Device Interface description: 0x%4.4X\n", cfip->InterfaceDesc);
++ switch(cfip->InterfaceDesc) {
++ case 0:
++ printk(" - x8-only asynchronous interface\n");
++ break;
++
++ case 1:
++ printk(" - x16-only asynchronous interface\n");
++ break;
++
++ case 2:
++ printk(" - supports x8 and x16 via BYTE# with asynchronous interface\n");
++ break;
++
++ case 3:
++ printk(" - x32-only asynchronous interface\n");
++ break;
++
++ case 4:
++ printk(" - supports x16 and x32 via Word# with asynchronous interface\n");
++ break;
++
++ case 65535:
++ printk(" - Not Allowed / Reserved\n");
++ break;
++
++ default:
++ printk(" - Unknown\n");
++ break;
++ }
+
-+extern int __init early_serial_setup(struct uart_port *port);
++ printk("Max. bytes in buffer write: 0x%x\n", 1<< cfip->MaxBufWriteSize);
++ printk("Number of Erase Block Regions: %d\n", cfip->NumEraseRegions);
+
-+#define BASE_BAUD (1843200 / 16)
++}
++#endif /* DEBUG_CFI */
+
-+extern unsigned int idt_cpu_freq;
++static struct chip_probe cfi_chip_probe = {
++ .name = "CFI",
++ .probe_chip = cfi_probe_chip
++};
+
-+extern int __init setup_serial_port(void)
++struct mtd_info *cfi_probe(struct map_info *map)
+{
-+ static struct uart_port serial_req[2];
-+
-+ memset(serial_req, 0, sizeof(serial_req));
-+ serial_req[0].type = PORT_16550A;
-+ serial_req[0].line = 0;
-+ serial_req[0].flags = STD_COM_FLAGS;
-+ serial_req[0].iotype = SERIAL_IO_MEM;
-+ serial_req[0].regshift = 2;
-+
-+ switch (mips_machtype) {
-+ case MACH_ARUBA_AP70:
-+ serial_req[0].irq = 104;
-+ serial_req[0].mapbase = KSEG1ADDR(0x18058003);
-+ serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
-+ serial_req[0].uartclk = idt_cpu_freq;
-+ break;
-+ case MACH_ARUBA_AP65:
-+ case MACH_ARUBA_AP60:
-+ default:
-+ serial_req[0].irq = 12;
-+ serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
-+ serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
-+ serial_req[0].uartclk = idt_cpu_freq / 2;
-+ break;
-+ }
-+
-+ early_serial_setup(&serial_req[0]);
-+
-+ return(0);
++ /*
++ * Just use the generic probe stuff to call our CFI-specific
++ * chip_probe routine in all the possible permutations, etc.
++ */
++ return mtd_do_chip_probe(map, &cfi_chip_probe);
+}
-diff -Nur linux-2.6.17/arch/mips/aruba/setup.c linux-2.6.17-owrt/arch/mips/aruba/setup.c
---- linux-2.6.17/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/arch/mips/aruba/setup.c 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,134 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * setup routines for IDT EB434 boards
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/mm.h>
-+#include <linux/sched.h>
-+#include <linux/irq.h>
-+#include <asm/bootinfo.h>
-+#include <asm/io.h>
-+#include <linux/ioport.h>
-+#include <asm/mipsregs.h>
-+#include <asm/pgtable.h>
-+#include <asm/reboot.h>
-+#include <asm/addrspace.h> /* for KSEG1ADDR() */
-+#include <asm/idt-boards/rc32434/rc32434.h>
-+#include <linux/pm.h>
-+
-+extern char *__init prom_getcmdline(void);
+
-+extern void (*board_time_init) (void);
-+extern void (*board_timer_setup) (struct irqaction * irq);
-+extern void aruba_time_init(void);
-+extern void aruba_timer_setup(struct irqaction *irq);
-+extern void aruba_reset(void);
-+
-+#define epldMask ((volatile unsigned char *)0xB900000d)
++static struct mtd_chip_driver cfi_chipdrv = {
++ .probe = cfi_probe,
++ .name = "cfi_probe",
++ .module = THIS_MODULE
++};
+
-+static void aruba_machine_restart(char *command)
++static int __init cfi_probe_init(void)
+{
-+ switch (mips_machtype) {
-+ case MACH_ARUBA_AP70:
-+ *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
-+ break;
-+ case MACH_ARUBA_AP65:
-+ case MACH_ARUBA_AP60:
-+ default:
-+ /* Reset*/
-+ *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
-+ udelay(100);
-+ *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
-+ udelay(100);
-+ *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
-+ break;
-+ }
++ register_mtd_chip_driver(&cfi_chipdrv);
++ return 0;
+}
+
-+static void aruba_machine_halt(void)
++static void __exit cfi_probe_exit(void)
+{
-+ for (;;) continue;
++ unregister_mtd_chip_driver(&cfi_chipdrv);
+}
+
-+extern char * getenv(char *e);
-+extern void unlock_ap60_70_flash(void);
-+
-+void __init plat_setup(void)
-+{
-+ board_time_init = aruba_time_init;
++module_init(cfi_probe_init);
++module_exit(cfi_probe_exit);
+
-+ board_timer_setup = aruba_timer_setup;
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org> et al.");
++MODULE_DESCRIPTION("Probe code for CFI-compliant flash chips");
+diff -Nur linux-2.6.21.1/drivers/net/Kconfig linux-2.6.21.1-owrt/drivers/net/Kconfig
+--- linux-2.6.21.1/drivers/net/Kconfig 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/drivers/net/Kconfig 2007-05-23 23:37:01.000000000 +0200
+@@ -201,6 +201,19 @@
+
+ source "drivers/net/arm/Kconfig"
+
++config AR2313
++ tristate "AR2313 Ethernet support"
++ depends on NET_ETHERNET && MACH_ARUBA
++ help
++ Support for the AR2313 Ethernet part on Aruba AP60/61
+
-+ _machine_restart = aruba_machine_restart;
-+ _machine_halt = aruba_machine_halt;
-+ pm_power_off = aruba_machine_halt;
++config IDT_RC32434_ETH
++ tristate "IDT RC32434 Local Ethernet support"
++ depends on NET_ETHERNET
++ help
++ IDT RC32434 has one local ethernet port. Say Y here to enable it.
++ To compile this driver as a module, choose M here.
+
-+ set_io_port_base(KSEG1);
+ config MACE
+ tristate "MACE (Power Mac ethernet) support"
+ depends on NET_ETHERNET && PPC_PMAC && PPC32
+diff -Nur linux-2.6.21.1/drivers/net/Kconfig.orig linux-2.6.21.1-owrt/drivers/net/Kconfig.orig
+--- linux-2.6.21.1/drivers/net/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/drivers/net/Kconfig.orig 2007-05-23 23:34:01.000000000 +0200
+@@ -0,0 +1,2952 @@
+
-+ /* Enable PCI interrupts in EPLD Mask register */
-+ *epldMask = 0x0;
-+ *(epldMask + 1) = 0x0;
++#
++# Network device configuration
++#
+
-+ write_c0_wired(0);
-+ unlock_ap60_70_flash();
++menu "Network device support"
++ depends on NET
++
++config NETDEVICES
++ default y if UML
++ bool "Network device support"
++ ---help---
++ You can say N here if you don't intend to connect your Linux box to
++ any other computer at all.
++
++ You'll have to say Y if your computer contains a network card that
++ you want to use under Linux. If you are going to run SLIP or PPP over
++ telephone line or null modem cable you need say Y here. Connecting
++ two machines with parallel ports using PLIP needs this, as well as
++ AX.25/KISS for sending Internet traffic over amateur radio links.
++
++ See also "The Linux Network Administrator's Guide" by Olaf Kirch and
++ Terry Dawson. Available at <http://www.tldp.org/guides.html>.
++
++ If unsure, say Y.
++
++# All the following symbols are dependent on NETDEVICES - do not repeat
++# that for each of the symbols.
++if NETDEVICES
++
++config IFB
++ tristate "Intermediate Functional Block support"
++ depends on NET_CLS_ACT
++ ---help---
++ This is an intermediate driver that allows sharing of
++ resources.
++ To compile this driver as a module, choose M here: the module
++ will be called ifb. If you want to use more than one ifb
++ device at a time, you need to compile this driver as a module.
++ Instead of 'ifb', the devices will then be called 'ifb0',
++ 'ifb1' etc.
++ Look at the iproute2 documentation directory for usage etc
++
++config DUMMY
++ tristate "Dummy net driver support"
++ ---help---
++ This is essentially a bit-bucket device (i.e. traffic you send to
++ this device is consigned into oblivion) with a configurable IP
++ address. It is most commonly used in order to make your currently
++ inactive SLIP address seem like a real address for local programs.
++ If you use SLIP or PPP, you might want to say Y here. Since this
++ thing often comes in handy, the default is Y. It won't enlarge your
++ kernel either. What a deal. Read about it in the Network
++ Administrator's Guide, available from
++ <http://www.tldp.org/docs.html#guide>.
++
++ To compile this driver as a module, choose M here: the module
++ will be called dummy. If you want to use more than one dummy
++ device at a time, you need to compile this driver as a module.
++ Instead of 'dummy', the devices will then be called 'dummy0',
++ 'dummy1' etc.
++
++config BONDING
++ tristate "Bonding driver support"
++ depends on INET
++ ---help---
++ Say 'Y' or 'M' if you wish to be able to 'bond' multiple Ethernet
++ Channels together. This is called 'Etherchannel' by Cisco,
++ 'Trunking' by Sun, 802.3ad by the IEEE, and 'Bonding' in Linux.
++
++ The driver supports multiple bonding modes to allow for both high
++ performance and high availability operation.
++
++ Refer to <file:Documentation/networking/bonding.txt> for more
++ information.
++
++ To compile this driver as a module, choose M here: the module
++ will be called bonding.
++
++config EQUALIZER
++ tristate "EQL (serial line load balancing) support"
++ ---help---
++ If you have two serial connections to some other computer (this
++ usually requires two modems and two telephone lines) and you use
++ SLIP (the protocol for sending Internet traffic over telephone
++ lines) or PPP (a better SLIP) on them, you can make them behave like
++ one double speed connection using this driver. Naturally, this has
++ to be supported at the other end as well, either with a similar EQL
++ Linux driver or with a Livingston Portmaster 2e.
++
++ Say Y if you want this and read
++ <file:Documentation/networking/eql.txt>. You may also want to read
++ section 6.2 of the NET-3-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here: the module
++ will be called eql. If unsure, say N.
++
++config TUN
++ tristate "Universal TUN/TAP device driver support"
++ select CRC32
++ ---help---
++ TUN/TAP provides packet reception and transmission for user space
++ programs. It can be viewed as a simple Point-to-Point or Ethernet
++ device, which instead of receiving packets from a physical media,
++ receives them from user space program and instead of sending packets
++ via physical media writes them to the user space program.
++
++ When a program opens /dev/net/tun, driver creates and registers
++ corresponding net device tunX or tapX. After a program closed above
++ devices, driver will automatically delete tunXX or tapXX device and
++ all routes corresponding to it.
++
++ Please read <file:Documentation/networking/tuntap.txt> for more
++ information.
++
++ To compile this driver as a module, choose M here: the module
++ will be called tun.
++
++ If you don't know what to use this for, you don't need it.
++
++config NET_SB1000
++ tristate "General Instruments Surfboard 1000"
++ depends on PNP
++ ---help---
++ This is a driver for the General Instrument (also known as
++ NextLevel) SURFboard 1000 internal
++ cable modem. This is an ISA card which is used by a number of cable
++ TV companies to provide cable modem access. It's a one-way
++ downstream-only cable modem, meaning that your upstream net link is
++ provided by your regular phone modem.
++
++ At present this driver only compiles as a module, so say M here if
++ you have this card. The module will be called sb1000. Then read
++ <file:Documentation/networking/README.sb1000> for information on how
++ to use this module, as it needs special ppp scripts for establishing
++ a connection. Further documentation and the necessary scripts can be
++ found at:
++
++ <http://www.jacksonville.net/~fventuri/>
++ <http://home.adelphia.net/~siglercm/sb1000.html>
++ <http://linuxpower.cx/~cable/>
++
++ If you don't have this card, of course say N.
++
++source "drivers/net/arcnet/Kconfig"
++
++source "drivers/net/phy/Kconfig"
+
-+ printk("BOARD - %s\n",getenv("boardname"));
++#
++# Ethernet
++#
+
-+ return 0;
-+}
++menu "Ethernet (10 or 100Mbit)"
++ depends on !UML
++
++config NET_ETHERNET
++ bool "Ethernet (10 or 100Mbit)"
++ ---help---
++ Ethernet (also called IEEE 802.3 or ISO 8802-2) is the most common
++ type of Local Area Network (LAN) in universities and companies.
++
++ Common varieties of Ethernet are: 10BASE-2 or Thinnet (10 Mbps over
++ coaxial cable, linking computers in a chain), 10BASE-T or twisted
++ pair (10 Mbps over twisted pair cable, linking computers to central
++ hubs), 10BASE-F (10 Mbps over optical fiber links, using hubs),
++ 100BASE-TX (100 Mbps over two twisted pair cables, using hubs),
++ 100BASE-T4 (100 Mbps over 4 standard voice-grade twisted pair
++ cables, using hubs), 100BASE-FX (100 Mbps over optical fiber links)
++ [the 100BASE varieties are also known as Fast Ethernet], and Gigabit
++ Ethernet (1 Gbps over optical fiber or short copper links).
++
++ If your Linux machine will be connected to an Ethernet and you have
++ an Ethernet network interface card (NIC) installed in your computer,
++ say Y here and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>. You will then also have
++ to say Y to the driver for your particular NIC.
++
++ Note that the answer to this question won't directly affect the
++ kernel: saying N will just cause the configurator to skip all
++ the questions about Ethernet network cards. If unsure, say N.
++
++config MII
++ tristate "Generic Media Independent Interface device support"
++ depends on NET_ETHERNET
++ help
++ Most ethernet controllers have MII transceiver either as an external
++ or internal device. It is safe to say Y or M here even if your
++ ethernet card lack MII.
++
++config MACB
++ tristate "Atmel MACB support"
++ depends on NET_ETHERNET && (AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263)
++ select MII
++ help
++ The Atmel MACB ethernet interface is found on many AT32 and AT91
++ parts. Say Y to include support for the MACB chip.
++
++ To compile this driver as a module, choose M here: the module
++ will be called macb.
++
++source "drivers/net/arm/Kconfig"
+
-+int page_is_ram(unsigned long pagenr)
-+{
-+ return 1;
-+}
++config IDT_RC32434_ETH
++ tristate "IDT RC32434 Local Ethernet support"
++ depends on NET_ETHERNET
++ help
++ IDT RC32434 has one local ethernet port. Say Y here to enable it.
++ To compile this driver as a module, choose M here.
+
-+const char *get_system_type(void)
-+{
-+ switch (mips_machtype) {
-+ case MACH_ARUBA_AP70:
-+ return "Aruba AP70";
-+ case MACH_ARUBA_AP65:
-+ return "Aruba AP65";
-+ case MACH_ARUBA_AP60:
-+ return "Aruba AP60/AP61";
-+ default:
-+ return "Aruba UNKNOWN";
-+ }
-+}
++config MACE
++ tristate "MACE (Power Mac ethernet) support"
++ depends on NET_ETHERNET && PPC_PMAC && PPC32
++ select CRC32
++ help
++ Power Macintoshes and clones with Ethernet built-in on the
++ motherboard will usually use a MACE (Medium Access Control for
++ Ethernet) interface. Say Y to include support for the MACE chip.
++
++ To compile this driver as a module, choose M here: the module
++ will be called mace.
++
++config MACE_AAUI_PORT
++ bool "Use AAUI port instead of TP by default"
++ depends on MACE
++ help
++ Some Apple machines (notably the Apple Network Server) which use the
++ MACE ethernet chip have an Apple AUI port (small 15-pin connector),
++ instead of an 8-pin RJ45 connector for twisted-pair ethernet. Say
++ Y here if you have such a machine. If unsure, say N.
++ The driver will default to AAUI on ANS anyway, and if you use it as
++ a module, you can provide the port_aaui=0|1 to force the driver.
++
++config BMAC
++ tristate "BMAC (G3 ethernet) support"
++ depends on NET_ETHERNET && PPC_PMAC && PPC32
++ select CRC32
++ help
++ Say Y for support of BMAC Ethernet interfaces. These are used on G3
++ computers.
++
++ To compile this driver as a module, choose M here: the module
++ will be called bmac.
++
++config ARIADNE
++ tristate "Ariadne support"
++ depends on NET_ETHERNET && ZORRO
++ help
++ If you have a Village Tronic Ariadne Ethernet adapter, say Y.
++ Otherwise, say N.
++
++ To compile this driver as a module, choose M here: the module
++ will be called ariadne.
++
++config A2065
++ tristate "A2065 support"
++ depends on NET_ETHERNET && ZORRO
++ select CRC32
++ help
++ If you have a Commodore A2065 Ethernet adapter, say Y. Otherwise,
++ say N.
++
++ To compile this driver as a module, choose M here: the module
++ will be called a2065.
++
++config HYDRA
++ tristate "Hydra support"
++ depends on NET_ETHERNET && ZORRO
++ select CRC32
++ help
++ If you have a Hydra Ethernet adapter, say Y. Otherwise, say N.
++
++ To compile this driver as a module, choose M here: the module
++ will be called hydra.
++
++config ZORRO8390
++ tristate "Zorro NS8390-based Ethernet support"
++ depends on NET_ETHERNET && ZORRO
++ select CRC32
++ help
++ This driver is for Zorro Ethernet cards using an NS8390-compatible
++ chipset, like the Village Tronic Ariadne II and the Individual
++ Computers X-Surf Ethernet cards. If you have such a card, say Y.
++ Otherwise, say N.
++
++ To compile this driver as a module, choose M here: the module
++ will be called zorro8390.
++
++config APNE
++ tristate "PCMCIA NE2000 support"
++ depends on NET_ETHERNET && AMIGA_PCMCIA
++ select CRC32
++ help
++ If you have a PCMCIA NE2000 compatible adapter, say Y. Otherwise,
++ say N.
++
++ To compile this driver as a module, choose M here: the module
++ will be called apne.
++
++config APOLLO_ELPLUS
++ tristate "Apollo 3c505 support"
++ depends on NET_ETHERNET && APOLLO
++ help
++ Say Y or M here if your Apollo has a 3Com 3c505 ISA Ethernet card.
++ If you don't have one made for Apollos, you can use one from a PC,
++ except that your Apollo won't be able to boot from it (because the
++ code in the ROM will be for a PC).
++
++config MAC8390
++ bool "Macintosh NS 8390 based ethernet cards"
++ depends on NET_ETHERNET && MAC
++ select CRC32
++ help
++ If you want to include a driver to support Nubus or LC-PDS
++ Ethernet cards using an NS8390 chipset or its equivalent, say Y
++ and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++config MAC89x0
++ tristate "Macintosh CS89x0 based ethernet cards"
++ depends on NET_ETHERNET && MAC && BROKEN
++ ---help---
++ Support for CS89x0 chipset based Ethernet cards. If you have a
++ Nubus or LC-PDS network (Ethernet) card of this type, say Y and
++ read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. This module will
++ be called mac89x0.
++
++config MACSONIC
++ tristate "Macintosh SONIC based ethernet (onboard, NuBus, LC, CS)"
++ depends on NET_ETHERNET && MAC
++ ---help---
++ Support for NatSemi SONIC based Ethernet devices. This includes
++ the onboard Ethernet in many Quadras as well as some LC-PDS,
++ a few Nubus and all known Comm Slot Ethernet cards. If you have
++ one of these say Y and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. This module will
++ be called macsonic.
++
++config MACMACE
++ bool "Macintosh (AV) onboard MACE ethernet (EXPERIMENTAL)"
++ depends on NET_ETHERNET && MAC && EXPERIMENTAL
++ select CRC32
++ help
++ Support for the onboard AMD 79C940 MACE Ethernet controller used in
++ the 660AV and 840AV Macintosh. If you have one of these Macintoshes
++ say Y and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++config MVME147_NET
++ tristate "MVME147 (Lance) Ethernet support"
++ depends on NET_ETHERNET && MVME147
++ select CRC32
++ help
++ Support for the on-board Ethernet interface on the Motorola MVME147
++ single-board computer. Say Y here to include the
++ driver for this chip in your kernel.
++ To compile this driver as a module, choose M here.
++
++config MVME16x_NET
++ tristate "MVME16x Ethernet support"
++ depends on NET_ETHERNET && MVME16x
++ help
++ This is the driver for the Ethernet interface on the Motorola
++ MVME162, 166, 167, 172 and 177 boards. Say Y here to include the
++ driver for this chip in your kernel.
++ To compile this driver as a module, choose M here.
++
++config BVME6000_NET
++ tristate "BVME6000 Ethernet support"
++ depends on NET_ETHERNET && BVME6000
++ help
++ This is the driver for the Ethernet interface on BVME4000 and
++ BVME6000 VME boards. Say Y here to include the driver for this chip
++ in your kernel.
++ To compile this driver as a module, choose M here.
++
++config ATARILANCE
++ tristate "Atari Lance support"
++ depends on NET_ETHERNET && ATARI
++ help
++ Say Y to include support for several Atari Ethernet adapters based
++ on the AMD Lance chipset: RieblCard (with or without battery), or
++ PAMCard VME (also the version by Rhotron, with different addresses).
++
++config ATARI_BIONET
++ tristate "BioNet-100 support"
++ depends on NET_ETHERNET && ATARI && ATARI_ACSI && BROKEN
++ help
++ Say Y to include support for BioData's BioNet-100 Ethernet adapter
++ for the ACSI port. The driver works (has to work...) with a polled
++ I/O scheme, so it's rather slow :-(
++
++config ATARI_PAMSNET
++ tristate "PAMsNet support"
++ depends on NET_ETHERNET && ATARI && ATARI_ACSI && BROKEN
++ help
++ Say Y to include support for the PAMsNet Ethernet adapter for the
++ ACSI port ("ACSI node"). The driver works (has to work...) with a
++ polled I/O scheme, so it's rather slow :-(
++
++config SUN3LANCE
++ tristate "Sun3/Sun3x on-board LANCE support"
++ depends on NET_ETHERNET && (SUN3 || SUN3X)
++ help
++ Most Sun3 and Sun3x motherboards (including the 3/50, 3/60 and 3/80)
++ featured an AMD Lance 10Mbit Ethernet controller on board; say Y
++ here to compile in the Linux driver for this and enable Ethernet.
++ General Linux information on the Sun 3 and 3x series (now
++ discontinued) is at
++ <http://www.angelfire.com/ca2/tech68k/sun3.html>.
++
++ If you're not building a kernel for a Sun 3, say N.
++
++config SUN3_82586
++ bool "Sun3 on-board Intel 82586 support"
++ depends on NET_ETHERNET && SUN3
++ help
++ This driver enables support for the on-board Intel 82586 based
++ Ethernet adapter found on Sun 3/1xx and 3/2xx motherboards. Note
++ that this driver does not support 82586-based adapters on additional
++ VME boards.
++
++config HPLANCE
++ bool "HP on-board LANCE support"
++ depends on NET_ETHERNET && DIO
++ select CRC32
++ help
++ If you want to use the builtin "LANCE" Ethernet controller on an
++ HP300 machine, say Y here.
++
++config LASI_82596
++ tristate "Lasi ethernet"
++ depends on NET_ETHERNET && GSC
++ help
++ Say Y here to support the builtin Intel 82596 ethernet controller
++ found in Hewlett-Packard PA-RISC machines with 10Mbit ethernet.
++
++config MIPS_JAZZ_SONIC
++ tristate "MIPS JAZZ onboard SONIC Ethernet support"
++ depends on NET_ETHERNET && MACH_JAZZ
++ help
++ This is the driver for the onboard card of MIPS Magnum 4000,
++ Acer PICA, Olivetti M700-10 and a few other identical OEM systems.
++
++config MIPS_AU1X00_ENET
++ bool "MIPS AU1000 Ethernet support"
++ depends on NET_ETHERNET && SOC_AU1X00
++ select PHYLIB
++ select CRC32
++ help
++ If you have an Alchemy Semi AU1X00 based system
++ say Y. Otherwise, say N.
++
++config NET_SB1250_MAC
++ tristate "SB1250 Ethernet support"
++ depends on NET_ETHERNET && SIBYTE_SB1xxx_SOC
++
++config SGI_IOC3_ETH
++ bool "SGI IOC3 Ethernet"
++ depends on NET_ETHERNET && PCI && SGI_IP27
++ select CRC32
++ select MII
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++config SGI_IOC3_ETH_HW_RX_CSUM
++ bool "Receive hardware checksums"
++ depends on SGI_IOC3_ETH && INET
++ default y
++ help
++ The SGI IOC3 network adapter supports TCP and UDP checksums in
++ hardware to offload processing of these checksums from the CPU. At
++ the moment only acceleration of IPv4 is supported. This option
++ enables offloading for checksums on receive. If unsure, say Y.
++
++config SGI_IOC3_ETH_HW_TX_CSUM
++ bool "Transmit hardware checksums"
++ depends on SGI_IOC3_ETH && INET
++ default y
++ help
++ The SGI IOC3 network adapter supports TCP and UDP checksums in
++ hardware to offload processing of these checksums from the CPU. At
++ the moment only acceleration of IPv4 is supported. This option
++ enables offloading for checksums on transmit. If unsure, say Y.
++
++config MIPS_SIM_NET
++ tristate "MIPS simulator Network device (EXPERIMENTAL)"
++ depends on MIPS_SIM && EXPERIMENTAL
++ help
++ The MIPSNET device is a simple Ethernet network device which is
++ emulated by the MIPS Simulator.
++ If you are not using a MIPSsim or are unsure, say N.
++
++config SGI_O2MACE_ETH
++ tristate "SGI O2 MACE Fast Ethernet support"
++ depends on NET_ETHERNET && SGI_IP32=y
++
++config STNIC
++ tristate "National DP83902AV support"
++ depends on NET_ETHERNET && SUPERH
++ select CRC32
++ help
++ Support for cards based on the National Semiconductor DP83902AV
++ ST-NIC Serial Network Interface Controller for Twisted Pair. This
++ is a 10Mbit/sec Ethernet controller. Product overview and specs at
++ <http://www.national.com/pf/DP/DP83902A.html>.
++
++ If unsure, say N.
++
++config SUNLANCE
++ tristate "Sun LANCE support"
++ depends on NET_ETHERNET && SBUS
++ select CRC32
++ help
++ This driver supports the "le" interface present on all 32-bit Sparc
++ systems, on some older Ultra systems and as an Sbus option. These
++ cards are based on the AMD Lance chipset, which is better known
++ via the NE2100 cards.
++
++ To compile this driver as a module, choose M here: the module
++ will be called sunlance.
++
++config HAPPYMEAL
++ tristate "Sun Happy Meal 10/100baseT support"
++ depends on NET_ETHERNET && (SBUS || PCI)
++ select CRC32
++ help
++ This driver supports the "hme" interface present on most Ultra
++ systems and as an option on older Sbus systems. This driver supports
++ both PCI and Sbus devices. This driver also supports the "qfe" quad
++ 100baseT device available in both PCI and Sbus configurations.
++
++ To compile this driver as a module, choose M here: the module
++ will be called sunhme.
++
++config SUNBMAC
++ tristate "Sun BigMAC 10/100baseT support (EXPERIMENTAL)"
++ depends on NET_ETHERNET && SBUS && EXPERIMENTAL
++ select CRC32
++ help
++ This driver supports the "be" interface available as an Sbus option.
++ This is Sun's older 100baseT Ethernet device.
++
++ To compile this driver as a module, choose M here: the module
++ will be called sunbmac.
++
++config SUNQE
++ tristate "Sun QuadEthernet support"
++ depends on NET_ETHERNET && SBUS
++ select CRC32
++ help
++ This driver supports the "qe" 10baseT Ethernet device, available as
++ an Sbus option. Note that this is not the same as Quad FastEthernet
++ "qfe" which is supported by the Happy Meal driver instead.
++
++ To compile this driver as a module, choose M here: the module
++ will be called sunqe.
++
++config SUNGEM
++ tristate "Sun GEM support"
++ depends on NET_ETHERNET && PCI
++ select CRC32
++ help
++ Support for the Sun GEM chip, aka Sun GigabitEthernet/P 2.0. See also
++ <http://www.sun.com/products-n-solutions/hardware/docs/pdf/806-3985-10.pdf>.
++
++config CASSINI
++ tristate "Sun Cassini support"
++ depends on NET_ETHERNET && PCI
++ select CRC32
++ help
++ Support for the Sun Cassini chip, aka Sun GigaSwift Ethernet. See also
++ <http://www.sun.com/products-n-solutions/hardware/docs/pdf/817-4341-10.pdf>
++
++config NET_VENDOR_3COM
++ bool "3COM cards"
++ depends on NET_ETHERNET && (ISA || EISA || MCA || PCI)
++ help
++ If you have a network (Ethernet) card belonging to this class, say Y
++ and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ Note that the answer to this question doesn't directly affect the
++ kernel: saying N will just cause the configurator to skip all
++ the questions about 3COM cards. If you say Y, you will be asked for
++ your specific card in the following questions.
++
++config EL1
++ tristate "3c501 \"EtherLink\" support"
++ depends on NET_VENDOR_3COM && ISA
++ ---help---
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>. Also, consider buying a
++ new card, since the 3c501 is slow, broken, and obsolete: you will
++ have problems. Some people suggest to ping ("man ping") a nearby
++ machine every minute ("man cron") when using this card.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called 3c501.
++
++config EL2
++ tristate "3c503 \"EtherLink II\" support"
++ depends on NET_VENDOR_3COM && ISA
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called 3c503.
++
++config ELPLUS
++ tristate "3c505 \"EtherLink Plus\" support"
++ depends on NET_VENDOR_3COM && ISA && ISA_DMA_API
++ ---help---
++ Information about this network (Ethernet) card can be found in
++ <file:Documentation/networking/3c505.txt>. If you have a card of
++ this type, say Y and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called 3c505.
++
++config EL16
++ tristate "3c507 \"EtherLink 16\" support (EXPERIMENTAL)"
++ depends on NET_VENDOR_3COM && ISA && EXPERIMENTAL
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called 3c507.
++
++config EL3
++ tristate "3c509/3c529 (MCA)/3c579 \"EtherLink III\" support"
++ depends on NET_VENDOR_3COM && (ISA || EISA || MCA)
++ ---help---
++ If you have a network (Ethernet) card belonging to the 3Com
++ EtherLinkIII series, say Y and read the Ethernet-HOWTO, available
++ from <http://www.tldp.org/docs.html#howto>.
++
++ If your card is not working you may need to use the DOS
++ setup disk to disable Plug & Play mode, and to select the default
++ media type.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called 3c509.
++
++config 3C515
++ tristate "3c515 ISA \"Fast EtherLink\""
++ depends on NET_VENDOR_3COM && (ISA || EISA) && ISA_DMA_API
++ help
++ If you have a 3Com ISA EtherLink XL "Corkscrew" 3c515 Fast Ethernet
++ network card, say Y and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called 3c515.
++
++config ELMC
++ tristate "3c523 \"EtherLink/MC\" support"
++ depends on NET_VENDOR_3COM && MCA_LEGACY
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called 3c523.
++
++config ELMC_II
++ tristate "3c527 \"EtherLink/MC 32\" support (EXPERIMENTAL)"
++ depends on NET_VENDOR_3COM && MCA && MCA_LEGACY
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called 3c527.
++
++config VORTEX
++ tristate "3c590/3c900 series (592/595/597) \"Vortex/Boomerang\" support"
++ depends on NET_VENDOR_3COM && (PCI || EISA)
++ select MII
++ ---help---
++ This option enables driver support for a large number of 10Mbps and
++ 10/100Mbps EISA, PCI and PCMCIA 3Com network cards:
++
++ "Vortex" (Fast EtherLink 3c590/3c592/3c595/3c597) EISA and PCI
++ "Boomerang" (EtherLink XL 3c900 or 3c905) PCI
++ "Cyclone" (3c540/3c900/3c905/3c980/3c575/3c656) PCI and Cardbus
++ "Tornado" (3c905) PCI
++ "Hurricane" (3c555/3cSOHO) PCI
++
++ If you have such a card, say Y and read the Ethernet-HOWTO,
++ available from <http://www.tldp.org/docs.html#howto>. More
++ specific information is in
++ <file:Documentation/networking/vortex.txt> and in the comments at
++ the beginning of <file:drivers/net/3c59x.c>.
++
++ To compile this support as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>.
++
++config TYPHOON
++ tristate "3cr990 series \"Typhoon\" support"
++ depends on NET_VENDOR_3COM && PCI
++ select CRC32
++ ---help---
++ This option enables driver support for the 3cr990 series of cards:
++
++ 3C990-TX, 3CR990-TX-95, 3CR990-TX-97, 3CR990-FX-95, 3CR990-FX-97,
++ 3CR990SVR, 3CR990SVR95, 3CR990SVR97, 3CR990-FX-95 Server,
++ 3CR990-FX-97 Server, 3C990B-TX-M, 3C990BSVR
++
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called typhoon.
++
++config LANCE
++ tristate "AMD LANCE and PCnet (AT1500 and NE2100) support"
++ depends on NET_ETHERNET && ISA && ISA_DMA_API
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>. Some LinkSys cards are
++ of this type.
++
++ To compile this driver as a module, choose M here: the module
++ will be called lance. This is recommended.
++
++config NET_VENDOR_SMC
++ bool "Western Digital/SMC cards"
++ depends on NET_ETHERNET && (ISA || MCA || EISA || MAC)
++ help
++ If you have a network (Ethernet) card belonging to this class, say Y
++ and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ Note that the answer to this question doesn't directly affect the
++ kernel: saying N will just cause the configurator to skip all
++ the questions about Western Digital cards. If you say Y, you will be
++ asked for your specific card in the following questions.
++
++config WD80x3
++ tristate "WD80*3 support"
++ depends on NET_VENDOR_SMC && ISA
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called wd.
++
++config ULTRAMCA
++ tristate "SMC Ultra MCA support"
++ depends on NET_VENDOR_SMC && MCA
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type and are running
++ an MCA based system (PS/2), say Y and read the Ethernet-HOWTO,
++ available from <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called smc-mca.
++
++config ULTRA
++ tristate "SMC Ultra support"
++ depends on NET_VENDOR_SMC && ISA
++ select CRC32
++ ---help---
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ Important: There have been many reports that, with some motherboards
++ mixing an SMC Ultra and an Adaptec AHA154x SCSI card (or compatible,
++ such as some BusLogic models) causes corruption problems with many
++ operating systems. The Linux smc-ultra driver has a work-around for
++ this but keep it in mind if you have such a SCSI card and have
++ problems.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called smc-ultra.
++
++config ULTRA32
++ tristate "SMC Ultra32 EISA support"
++ depends on NET_VENDOR_SMC && EISA
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called smc-ultra32.
++
++config SMC91X
++ tristate "SMC 91C9x/91C1xxx support"
++ select CRC32
++ select MII
++ depends on NET_ETHERNET && (ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || SOC_AU1X00)
++ help
++ This is a driver for SMC's 91x series of Ethernet chipsets,
++ including the SMC91C94 and the SMC91C111. Say Y if you want it
++ compiled into the kernel, and read the file
++ <file:Documentation/networking/smc9.txt> and the Ethernet-HOWTO,
++ available from <http://www.linuxdoc.org/docs.html#howto>.
++
++ This driver is also available as a module ( = code which can be
++ inserted in and removed from the running kernel whenever you want).
++ The module will be called smc91x. If you want to compile it as a
++ module, say M here and read <file:Documentation/modules.txt> as well
++ as <file:Documentation/networking/net-modules.txt>.
++
++config SMC9194
++ tristate "SMC 9194 support"
++ depends on NET_VENDOR_SMC && (ISA || MAC && BROKEN)
++ select CRC32
++ ---help---
++ This is support for the SMC9xxx based Ethernet cards. Choose this
++ option if you have a DELL laptop with the docking station, or
++ another SMC9192/9194 based chipset. Say Y if you want it compiled
++ into the kernel, and read the file
++ <file:Documentation/networking/smc9.txt> and the Ethernet-HOWTO,
++ available from <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called smc9194.
++
++config NET_NETX
++ tristate "NetX Ethernet support"
++ select MII
++ depends on NET_ETHERNET && ARCH_NETX
++ help
++ This is support for the Hilscher netX builtin Ethernet ports
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called netx-eth.
++
++config DM9000
++ tristate "DM9000 support"
++ depends on (ARM || MIPS) && NET_ETHERNET
++ select CRC32
++ select MII
++ ---help---
++ Support for DM9000 chipset.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module will be
++ called dm9000.
++
++config SMC911X
++ tristate "SMSC LAN911[5678] support"
++ select CRC32
++ select MII
++ depends on NET_ETHERNET && ARCH_PXA
++ help
++ This is a driver for SMSC's LAN911x series of Ethernet chipsets
++ including the new LAN9115, LAN9116, LAN9117, and LAN9118.
++ Say Y if you want it compiled into the kernel,
++ and read the Ethernet-HOWTO, available from
++ <http://www.linuxdoc.org/docs.html#howto>.
++
++ This driver is also available as a module. The module will be
++ called smc911x. If you want to compile it as a module, say M
++ here and read <file:Documentation/modules.txt>
++
++config NET_VENDOR_RACAL
++ bool "Racal-Interlan (Micom) NI cards"
++ depends on NET_ETHERNET && ISA
++ help
++ If you have a network (Ethernet) card belonging to this class, such
++ as the NI5010, NI5210 or NI6210, say Y and read the Ethernet-HOWTO,
++ available from <http://www.tldp.org/docs.html#howto>.
++
++ Note that the answer to this question doesn't directly affect the
++ kernel: saying N will just cause the configurator to skip all
++ the questions about NI cards. If you say Y, you will be asked for
++ your specific card in the following questions.
++
++config NI5010
++ tristate "NI5010 support (EXPERIMENTAL)"
++ depends on NET_VENDOR_RACAL && ISA && EXPERIMENTAL && BROKEN_ON_SMP
++ ---help---
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>. Note that this is still
++ experimental code.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called ni5010.
++
++config NI52
++ tristate "NI5210 support"
++ depends on NET_VENDOR_RACAL && ISA
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called ni52.
++
++config NI65
++ tristate "NI6510 support"
++ depends on NET_VENDOR_RACAL && ISA && ISA_DMA_API
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called ni65.
++
++source "drivers/net/tulip/Kconfig"
++
++config AT1700
++ tristate "AT1700/1720 support (EXPERIMENTAL)"
++ depends on NET_ETHERNET && (ISA || MCA_LEGACY) && EXPERIMENTAL
++ select CRC32
++ ---help---
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called at1700.
++
++config DEPCA
++ tristate "DEPCA, DE10x, DE200, DE201, DE202, DE422 support"
++ depends on NET_ETHERNET && (ISA || EISA || MCA)
++ select CRC32
++ ---help---
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto> as well as
++ <file:drivers/net/depca.c>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called depca.
++
++config HP100
++ tristate "HP 10/100VG PCLAN (ISA, EISA, PCI) support"
++ depends on NET_ETHERNET && (ISA || EISA || PCI)
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called hp100.
++
++config NET_ISA
++ bool "Other ISA cards"
++ depends on NET_ETHERNET && ISA
++ ---help---
++ If your network (Ethernet) card hasn't been mentioned yet and its
++ bus system (that's the way the cards talks to the other components
++ of your computer) is ISA (as opposed to EISA, VLB or PCI), say Y.
++ Make sure you know the name of your card. Read the Ethernet-HOWTO,
++ available from <http://www.tldp.org/docs.html#howto>.
++
++ If unsure, say Y.
++
++ Note that the answer to this question doesn't directly affect the
++ kernel: saying N will just cause the configurator to skip all
++ the remaining ISA network card questions. If you say Y, you will be
++ asked for your specific card in the following questions.
++
++config E2100
++ tristate "Cabletron E21xx support"
++ depends on NET_ISA
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called e2100.
++
++config EWRK3
++ tristate "EtherWORKS 3 (DE203, DE204, DE205) support"
++ depends on NET_ISA
++ select CRC32
++ ---help---
++ This driver supports the DE203, DE204 and DE205 network (Ethernet)
++ cards. If this is for you, say Y and read
++ <file:Documentation/networking/ewrk3.txt> in the kernel source as
++ well as the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called ewrk3.
++
++config EEXPRESS
++ tristate "EtherExpress 16 support"
++ depends on NET_ISA
++ ---help---
++ If you have an EtherExpress16 network (Ethernet) card, say Y and
++ read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>. Note that the Intel
++ EtherExpress16 card used to be regarded as a very poor choice
++ because the driver was very unreliable. We now have a new driver
++ that should do better.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called eexpress.
++
++config EEXPRESS_PRO
++ tristate "EtherExpressPro support/EtherExpress 10 (i82595) support"
++ depends on NET_ISA
++ ---help---
++ If you have a network (Ethernet) card of this type, say Y. This
++ driver supports Intel i82595{FX,TX} based boards. Note however
++ that the EtherExpress PRO/100 Ethernet card has its own separate
++ driver. Please read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called eepro.
++
++config HPLAN_PLUS
++ tristate "HP PCLAN+ (27247B and 27252A) support"
++ depends on NET_ISA
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called hp-plus.
++
++config HPLAN
++ tristate "HP PCLAN (27245 and other 27xxx series) support"
++ depends on NET_ISA
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called hp.
++
++config LP486E
++ tristate "LP486E on board Ethernet"
++ depends on NET_ISA
++ help
++ Say Y here to support the 82596-based on-board Ethernet controller
++ for the Panther motherboard, which is one of the two shipped in the
++ Intel Professional Workstation.
++
++config ETH16I
++ tristate "ICL EtherTeam 16i/32 support"
++ depends on NET_ISA
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called eth16i.
++
++config NE2000
++ tristate "NE2000/NE1000 support"
++ depends on NET_ISA || (Q40 && m) || M32R
++ select CRC32
++ ---help---
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>. Many Ethernet cards
++ without a specific driver are compatible with NE2000.
++
++ If you have a PCI NE2000 card however, say N here and Y to "PCI
++ NE2000 and clone support" under "EISA, VLB, PCI and on board
++ controllers" below. If you have a NE2000 card and are running on
++ an MCA system (a bus system used on some IBM PS/2 computers and
++ laptops), say N here and Y to "NE/2 (ne2000 MCA version) support",
++ below.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called ne.
++
++config ZNET
++ tristate "Zenith Z-Note support (EXPERIMENTAL)"
++ depends on NET_ISA && EXPERIMENTAL && ISA_DMA_API
++ help
++ The Zenith Z-Note notebook computer has a built-in network
++ (Ethernet) card, and this is the Linux driver for it. Note that the
++ IBM Thinkpad 300 is compatible with the Z-Note and is also supported
++ by this driver. Read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++config SEEQ8005
++ tristate "SEEQ8005 support (EXPERIMENTAL)"
++ depends on NET_ISA && EXPERIMENTAL
++ help
++ This is a driver for the SEEQ 8005 network (Ethernet) card. If this
++ is for you, read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called seeq8005.
++
++config NE2_MCA
++ tristate "NE/2 (ne2000 MCA version) support"
++ depends on NET_ETHERNET && MCA_LEGACY
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called ne2.
++
++config IBMLANA
++ tristate "IBM LAN Adapter/A support"
++ depends on NET_ETHERNET && MCA && MCA_LEGACY
++ ---help---
++ This is a Micro Channel Ethernet adapter. You need to set
++ CONFIG_MCA to use this driver. It is both available as an in-kernel
++ driver and as a module.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The only
++ currently supported card is the IBM LAN Adapter/A for Ethernet. It
++ will both support 16K and 32K memory windows, however a 32K window
++ gives a better security against packet losses. Usage of multiple
++ boards with this driver should be possible, but has not been tested
++ up to now due to lack of hardware.
++
++config IBMVETH
++ tristate "IBM LAN Virtual Ethernet support"
++ depends on NET_ETHERNET && PPC_PSERIES
++ ---help---
++ This driver supports virtual ethernet adapters on newer IBM iSeries
++ and pSeries systems.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module will
++ be called ibmveth.
++
++config IBM_EMAC
++ tristate "PowerPC 4xx on-chip Ethernet support"
++ depends on 4xx
++ help
++ This driver supports the PowerPC 4xx EMAC family of on-chip
++ Ethernet controllers.
++
++config IBM_EMAC_RXB
++ int "Number of receive buffers"
++ depends on IBM_EMAC
++ default "128"
++
++config IBM_EMAC_TXB
++ int "Number of transmit buffers"
++ depends on IBM_EMAC
++ default "64"
++
++config IBM_EMAC_POLL_WEIGHT
++ int "MAL NAPI polling weight"
++ depends on IBM_EMAC
++ default "32"
++
++config IBM_EMAC_RX_COPY_THRESHOLD
++ int "RX skb copy threshold (bytes)"
++ depends on IBM_EMAC
++ default "256"
++
++config IBM_EMAC_RX_SKB_HEADROOM
++ int "Additional RX skb headroom (bytes)"
++ depends on IBM_EMAC
++ default "0"
++ help
++ Additional receive skb headroom. Note, that driver
++ will always reserve at least 2 bytes to make IP header
++ aligned, so usually there is no need to add any additional
++ headroom.
++
++ If unsure, set to 0.
++
++config IBM_EMAC_PHY_RX_CLK_FIX
++ bool "PHY Rx clock workaround"
++ depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR)
++ help
++ Enable this if EMAC attached to a PHY which doesn't generate
++ RX clock if there is no link, if this is the case, you will
++ see "TX disable timeout" or "RX disable timeout" in the system
++ log.
++
++ If unsure, say N.
++
++config IBM_EMAC_DEBUG
++ bool "Debugging"
++ depends on IBM_EMAC
++ default n
++
++config IBM_EMAC_ZMII
++ bool
++ depends on IBM_EMAC && (NP405H || NP405L || 44x)
++ default y
++
++config IBM_EMAC_RGMII
++ bool
++ depends on IBM_EMAC && 440GX
++ default y
++
++config IBM_EMAC_TAH
++ bool
++ depends on IBM_EMAC && 440GX
++ default y
++
++config NET_PCI
++ bool "EISA, VLB, PCI and on board controllers"
++ depends on NET_ETHERNET && (ISA || EISA || PCI)
++ help
++ This is another class of network cards which attach directly to the
++ bus. If you have one of those, say Y and read the Ethernet-HOWTO,
++ available from <http://www.tldp.org/docs.html#howto>.
++
++ Note that the answer to this question doesn't directly affect the
++ kernel: saying N will just cause the configurator to skip all
++ the questions about this class of network cards. If you say Y, you
++ will be asked for your specific card in the following questions. If
++ you are unsure, say Y.
++
++config PCNET32
++ tristate "AMD PCnet32 PCI support"
++ depends on NET_PCI && PCI
++ select CRC32
++ select MII
++ help
++ If you have a PCnet32 or PCnetPCI based network (Ethernet) card,
++ answer Y here and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called pcnet32.
++
++config PCNET32_NAPI
++ bool "Use RX polling (NAPI)"
++ depends on PCNET32
++ help
++ NAPI is a new driver API designed to reduce CPU and interrupt load
++ when the driver is receiving lots of packets from the card. It is
++ still somewhat experimental and thus not yet enabled by default.
++
++ If your estimated Rx load is 10kpps or more, or if the card will be
++ deployed on potentially unfriendly networks (e.g. in a firewall),
++ then say Y here.
++
++ See <file:Documentation/networking/NAPI_HOWTO.txt> for more
++ information.
++
++ If in doubt, say N.
++
++config AMD8111_ETH
++ tristate "AMD 8111 (new PCI lance) support"
++ depends on NET_PCI && PCI
++ select CRC32
++ select MII
++ help
++ If you have an AMD 8111-based PCI lance ethernet card,
++ answer Y here and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called amd8111e.
++config AMD8111E_NAPI
++ bool "Enable NAPI support"
++ depends on AMD8111_ETH
++ help
++ NAPI is a new driver API designed to reduce CPU and interrupt load
++ when the driver is receiving lots of packets from the card. It is
++ still somewhat experimental and thus not yet enabled by default.
++
++ If your estimated Rx load is 10kpps or more, or if the card will be
++ deployed on potentially unfriendly networks (e.g. in a firewall),
++ then say Y here.
++
++ See <file:Documentation/networking/NAPI_HOWTO.txt> for more
++ information.
++
++ If in doubt, say N.
++
++config ADAPTEC_STARFIRE
++ tristate "Adaptec Starfire/DuraLAN support"
++ depends on NET_PCI && PCI
++ select CRC32
++ select MII
++ help
++ Say Y here if you have an Adaptec Starfire (or DuraLAN) PCI network
++ adapter. The DuraLAN chip is used on the 64 bit PCI boards from
++ Adaptec e.g. the ANA-6922A. The older 32 bit boards use the tulip
++ driver.
++
++ To compile this driver as a module, choose M here: the module
++ will be called starfire. This is recommended.
++
++config ADAPTEC_STARFIRE_NAPI
++ bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
++ depends on ADAPTEC_STARFIRE && EXPERIMENTAL
++ help
++ NAPI is a new driver API designed to reduce CPU and interrupt load
++ when the driver is receiving lots of packets from the card. It is
++ still somewhat experimental and thus not yet enabled by default.
++
++ If your estimated Rx load is 10kpps or more, or if the card will be
++ deployed on potentially unfriendly networks (e.g. in a firewall),
++ then say Y here.
++
++ See <file:Documentation/networking/NAPI_HOWTO.txt> for more
++ information.
++
++ If in doubt, say N.
++
++config AC3200
++ tristate "Ansel Communications EISA 3200 support (EXPERIMENTAL)"
++ depends on NET_PCI && (ISA || EISA) && EXPERIMENTAL
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called ac3200.
++
++config APRICOT
++ tristate "Apricot Xen-II on board Ethernet"
++ depends on NET_PCI && ISA
++ help
++ If you have a network (Ethernet) controller of this type, say Y and
++ read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module will be
++ called apricot.
++
++config B44
++ tristate "Broadcom 4400 ethernet support"
++ depends on NET_PCI && PCI
++ select MII
++ help
++ If you have a network (Ethernet) controller of this type, say Y and
++ read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module will be
++ called b44.
++
++config FORCEDETH
++ tristate "nForce Ethernet support"
++ depends on NET_PCI && PCI
++ help
++ If you have a network (Ethernet) controller of this type, say Y and
++ read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module will be
++ called forcedeth.
++
++config FORCEDETH_NAPI
++ bool "Use Rx and Tx Polling (NAPI) (EXPERIMENTAL)"
++ depends on FORCEDETH && EXPERIMENTAL
++ help
++ NAPI is a new driver API designed to reduce CPU and interrupt load
++ when the driver is receiving lots of packets from the card. It is
++ still somewhat experimental and thus not yet enabled by default.
++
++ If your estimated Rx load is 10kpps or more, or if the card will be
++ deployed on potentially unfriendly networks (e.g. in a firewall),
++ then say Y here.
++
++ See <file:Documentation/networking/NAPI_HOWTO.txt> for more
++ information.
++
++ If in doubt, say N.
++
++config CS89x0
++ tristate "CS89x0 support"
++ depends on NET_PCI && (ISA || MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X)
++ ---help---
++ Support for CS89x0 chipset based Ethernet cards. If you have a
++ network (Ethernet) card of this type, say Y and read the
++ Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto> as well as
++ <file:Documentation/networking/cs89x0.txt>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module will be
++ called cs89x0.
++
++config TC35815
++ tristate "TOSHIBA TC35815 Ethernet support"
++ depends on NET_PCI && PCI && TOSHIBA_JMR3927
++
++config DGRS
++ tristate "Digi Intl. RightSwitch SE-X support"
++ depends on NET_PCI && (PCI || EISA)
++ ---help---
++ This is support for the Digi International RightSwitch series of
++ PCI/EISA Ethernet switch cards. These include the SE-4 and the SE-6
++ models. If you have a network card of this type, say Y and read the
++ Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>. More specific
++ information is contained in <file:Documentation/networking/dgrs.txt>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called dgrs.
++
++config EEPRO100
++ tristate "EtherExpressPro/100 support (eepro100, original Becker driver)"
++ depends on NET_PCI && PCI
++ select MII
++ help
++ If you have an Intel EtherExpress PRO/100 PCI network (Ethernet)
++ card, say Y and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called eepro100.
++
++
++config E100
++ tristate "Intel(R) PRO/100+ support"
++ depends on NET_PCI && PCI
++ select MII
++ ---help---
++ This driver supports Intel(R) PRO/100 family of adapters.
++ To verify that your adapter is supported, find the board ID number
++ on the adapter. Look for a label that has a barcode and a number
++ in the format 123456-001 (six digits hyphen three digits).
++
++ Use the above information and the Adapter & Driver ID Guide at:
++
++ <http://support.intel.com/support/network/adapter/pro100/21397.htm>
++
++ to identify the adapter.
++
++ For the latest Intel PRO/100 network driver for Linux, see:
++
++ <http://appsr.intel.com/scripts-df/support_intel.asp>
++
++ More specific information on configuring the driver is in
++ <file:Documentation/networking/e100.txt>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called e100.
++
++config LNE390
++ tristate "Mylex EISA LNE390A/B support (EXPERIMENTAL)"
++ depends on NET_PCI && EISA && EXPERIMENTAL
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called lne390.
++
++config FEALNX
++ tristate "Myson MTD-8xx PCI Ethernet support"
++ depends on NET_PCI && PCI
++ select CRC32
++ select MII
++ help
++ Say Y here to support the Mysom MTD-800 family of PCI-based Ethernet
++ cards. Specifications and data at
++ <http://www.myson.com.hk/mtd/datasheet/>.
++
++config NATSEMI
++ tristate "National Semiconductor DP8381x series PCI Ethernet support"
++ depends on NET_PCI && PCI
++ select CRC32
++ help
++ This driver is for the National Semiconductor DP83810 series,
++ which is used in cards from PureData, NetGear, Linksys
++ and others, including the 83815 chip.
++ More specific information and updates are available from
++ <http://www.scyld.com/network/natsemi.html>.
++
++config NE2K_PCI
++ tristate "PCI NE2000 and clones support (see help)"
++ depends on NET_PCI && PCI
++ select CRC32
++ ---help---
++ This driver is for NE2000 compatible PCI cards. It will not work
++ with ISA NE2000 cards (they have their own driver, "NE2000/NE1000
++ support" below). If you have a PCI NE2000 network (Ethernet) card,
++ say Y and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ This driver also works for the following NE2000 clone cards:
++ RealTek RTL-8029 Winbond 89C940 Compex RL2000 KTI ET32P2
++ NetVin NV5000SC Via 86C926 SureCom NE34 Winbond
++ Holtek HT80232 Holtek HT80229
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called ne2k-pci.
++
++config NE3210
++ tristate "Novell/Eagle/Microdyne NE3210 EISA support (EXPERIMENTAL)"
++ depends on NET_PCI && EISA && EXPERIMENTAL
++ select CRC32
++ ---help---
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>. Note that this driver
++ will NOT WORK for NE3200 cards as they are completely different.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called ne3210.
++
++config ES3210
++ tristate "Racal-Interlan EISA ES3210 support (EXPERIMENTAL)"
++ depends on NET_PCI && EISA && EXPERIMENTAL
++ select CRC32
++ help
++ If you have a network (Ethernet) card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called es3210.
++
++config 8139CP
++ tristate "RealTek RTL-8139 C+ PCI Fast Ethernet Adapter support (EXPERIMENTAL)"
++ depends on NET_PCI && PCI && EXPERIMENTAL
++ select CRC32
++ select MII
++ help
++ This is a driver for the Fast Ethernet PCI network cards based on
++ the RTL8139C+ chips. If you have one of those, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here: the module
++ will be called 8139cp. This is recommended.
++
++config 8139TOO
++ tristate "RealTek RTL-8129/8130/8139 PCI Fast Ethernet Adapter support"
++ depends on NET_PCI && PCI
++ select CRC32
++ select MII
++ ---help---
++ This is a driver for the Fast Ethernet PCI network cards based on
++ the RTL 8129/8130/8139 chips. If you have one of those, say Y and
++ read the Ethernet-HOWTO <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here: the module
++ will be called 8139too. This is recommended.
++
++config 8139TOO_PIO
++ bool "Use PIO instead of MMIO"
++ default y
++ depends on 8139TOO
++ help
++ This instructs the driver to use programmed I/O ports (PIO) instead
++ of PCI shared memory (MMIO). This can possibly solve some problems
++ in case your mainboard has memory consistency issues. If unsure,
++ say N.
++
++config 8139TOO_TUNE_TWISTER
++ bool "Support for uncommon RTL-8139 rev. K (automatic channel equalization)"
++ depends on 8139TOO
++ help
++ This implements a function which might come in handy in case you
++ are using low quality on long cabling. It is required for RealTek
++ RTL-8139 revision K boards, and totally unused otherwise. It tries
++ to match the transceiver to the cable characteristics. This is
++ experimental since hardly documented by the manufacturer.
++ If unsure, say Y.
++
++config 8139TOO_8129
++ bool "Support for older RTL-8129/8130 boards"
++ depends on 8139TOO
++ help
++ This enables support for the older and uncommon RTL-8129 and
++ RTL-8130 chips, which support MII via an external transceiver,
++ instead of an internal one. Disabling this option will save some
++ memory by making the code size smaller. If unsure, say Y.
++
++config 8139_OLD_RX_RESET
++ bool "Use older RX-reset method"
++ depends on 8139TOO
++ help
++ The 8139too driver was recently updated to contain a more rapid
++ reset sequence, in the face of severe receive errors. This "new"
++ RX-reset method should be adequate for all boards. But if you
++ experience problems, you can enable this option to restore the
++ old RX-reset behavior. If unsure, say N.
++
++config SIS900
++ tristate "SiS 900/7016 PCI Fast Ethernet Adapter support"
++ depends on NET_PCI && PCI
++ select CRC32
++ select MII
++ ---help---
++ This is a driver for the Fast Ethernet PCI network cards based on
++ the SiS 900 and SiS 7016 chips. The SiS 900 core is also embedded in
++ SiS 630 and SiS 540 chipsets.
++
++ This driver also supports AMD 79C901 HomePNA so that you can use
++ your phone line as a network cable.
++
++ To compile this driver as a module, choose M here: the module
++ will be called sis900. This is recommended.
++
++config EPIC100
++ tristate "SMC EtherPower II"
++ depends on NET_PCI && PCI
++ select CRC32
++ select MII
++ help
++ This driver is for the SMC EtherPower II 9432 PCI Ethernet NIC,
++ which is based on the SMC83c17x (EPIC/100).
++ More specific information and updates are available from
++ <http://www.scyld.com/network/epic100.html>.
++
++config SUNDANCE
++ tristate "Sundance Alta support"
++ depends on NET_PCI && PCI
++ select CRC32
++ select MII
++ help
++ This driver is for the Sundance "Alta" chip.
++ More specific information and updates are available from
++ <http://www.scyld.com/network/sundance.html>.
++
++config SUNDANCE_MMIO
++ bool "Use MMIO instead of PIO"
++ depends on SUNDANCE
++ help
++ Enable memory-mapped I/O for interaction with Sundance NIC registers.
++ Do NOT enable this by default, PIO (enabled when MMIO is disabled)
++ is known to solve bugs on certain chips.
++
++ If unsure, say N.
++
++config TLAN
++ tristate "TI ThunderLAN support"
++ depends on NET_PCI && (PCI || EISA) && !64BIT
++ ---help---
++ If you have a PCI Ethernet network card based on the ThunderLAN chip
++ which is supported by this driver, say Y and read the
++ Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ Devices currently supported by this driver are Compaq Netelligent,
++ Compaq NetFlex and Olicom cards. Please read the file
++ <file:Documentation/networking/tlan.txt> for more details.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called tlan.
++
++ Please email feedback to <torben.mathiasen@compaq.com>.
++
++config VIA_RHINE
++ tristate "VIA Rhine support"
++ depends on NET_PCI && PCI
++ select CRC32
++ select MII
++ help
++ If you have a VIA "Rhine" based network card (Rhine-I (VT86C100A),
++ Rhine-II (VT6102), or Rhine-III (VT6105)), say Y here. Rhine-type
++ Ethernet functions can also be found integrated on South Bridges
++ (e.g. VT8235).
++
++ To compile this driver as a module, choose M here. The module
++ will be called via-rhine.
++
++config VIA_RHINE_MMIO
++ bool "Use MMIO instead of PIO"
++ depends on VIA_RHINE
++ help
++ This instructs the driver to use PCI shared memory (MMIO) instead of
++ programmed I/O ports (PIO). Enabling this gives an improvement in
++ processing time in parts of the driver.
++
++ If unsure, say Y.
++
++config VIA_RHINE_NAPI
++ bool "Use Rx Polling (NAPI)"
++ depends on VIA_RHINE
++ help
++ NAPI is a new driver API designed to reduce CPU and interrupt load
++ when the driver is receiving lots of packets from the card.
++
++ If your estimated Rx load is 10kpps or more, or if the card will be
++ deployed on potentially unfriendly networks (e.g. in a firewall),
++ then say Y here.
++
++ See <file:Documentation/networking/NAPI_HOWTO.txt> for more
++ information.
++
++config LAN_SAA9730
++ bool "Philips SAA9730 Ethernet support"
++ depends on NET_PCI && PCI && MIPS_ATLAS
++ help
++ The SAA9730 is a combined multimedia and peripheral controller used
++ in thin clients, Internet access terminals, and diskless
++ workstations.
++ See <http://www.semiconductors.philips.com/pip/SAA9730_flyer_1>.
++
++config SC92031
++ tristate "Silan SC92031 PCI Fast Ethernet Adapter driver (EXPERIMENTAL)"
++ depends on NET_PCI && PCI && EXPERIMENTAL
++ select CRC32
++ ---help---
++ This is a driver for the Fast Ethernet PCI network cards based on
++ the Silan SC92031 chip (sometimes also called Rsltek 8139D). If you
++ have one of these, say Y here.
++
++ To compile this driver as a module, choose M here: the module
++ will be called sc92031. This is recommended.
++
++config NET_POCKET
++ bool "Pocket and portable adapters"
++ depends on NET_ETHERNET && PARPORT
++ ---help---
++ Cute little network (Ethernet) devices which attach to the parallel
++ port ("pocket adapters"), commonly used with laptops. If you have
++ one of those, say Y and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ If you want to plug a network (or some other) card into the PCMCIA
++ (or PC-card) slot of your laptop instead (PCMCIA is the standard for
++ credit card size extension cards used by all modern laptops), you
++ need the pcmcia-cs package (location contained in the file
++ <file:Documentation/Changes>) and you can say N here.
++
++ Laptop users should read the Linux Laptop home page at
++ <http://www.linux-on-laptops.com/> or
++ Tuxmobil - Linux on Mobile Computers at <http://www.tuxmobil.org/>.
++
++ Note that the answer to this question doesn't directly affect the
++ kernel: saying N will just cause the configurator to skip all
++ the questions about this class of network devices. If you say Y, you
++ will be asked for your specific device in the following questions.
++
++config ATP
++ tristate "AT-LAN-TEC/RealTek pocket adapter support"
++ depends on NET_POCKET && PARPORT && X86
++ select CRC32
++ ---help---
++ This is a network (Ethernet) device which attaches to your parallel
++ port. Read <file:drivers/net/atp.c> as well as the Ethernet-HOWTO,
++ available from <http://www.tldp.org/docs.html#howto>, if you
++ want to use this. If you intend to use this driver, you should have
++ said N to the "Parallel printer support", because the two drivers
++ don't like each other.
++
++ To compile this driver as a module, choose M here: the module
++ will be called atp.
++
++config DE600
++ tristate "D-Link DE600 pocket adapter support"
++ depends on NET_POCKET && PARPORT
++ ---help---
++ This is a network (Ethernet) device which attaches to your parallel
++ port. Read <file:Documentation/networking/DLINK.txt> as well as the
++ Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>, if you want to use
++ this. It is possible to have several devices share a single parallel
++ port and it is safe to compile the corresponding drivers into the
++ kernel.
++
++ To compile this driver as a module, choose M here: the module
++ will be called de600.
++
++config DE620
++ tristate "D-Link DE620 pocket adapter support"
++ depends on NET_POCKET && PARPORT
++ ---help---
++ This is a network (Ethernet) device which attaches to your parallel
++ port. Read <file:Documentation/networking/DLINK.txt> as well as the
++ Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>, if you want to use
++ this. It is possible to have several devices share a single parallel
++ port and it is safe to compile the corresponding drivers into the
++ kernel.
++
++ To compile this driver as a module, choose M here: the module
++ will be called de620.
++
++config SGISEEQ
++ tristate "SGI Seeq ethernet controller support"
++ depends on NET_ETHERNET && SGI_IP22
++ help
++ Say Y here if you have an Seeq based Ethernet network card. This is
++ used in many Silicon Graphics machines.
++
++config DECLANCE
++ tristate "DEC LANCE ethernet controller support"
++ depends on NET_ETHERNET && MACH_DECSTATION
++ select CRC32
++ help
++ This driver is for the series of Ethernet controllers produced by
++ DEC (now Compaq) based on the AMD Lance chipset, including the
++ DEPCA series. (This chipset is better known via the NE2100 cards.)
++
++config 68360_ENET
++ bool "Motorola 68360 ethernet controller"
++ depends on M68360
++ help
++ Say Y here if you want to use the built-in ethernet controller of
++ the Motorola 68360 processor.
++
++config FEC
++ bool "FEC ethernet controller (of ColdFire CPUs)"
++ depends on M523x || M527x || M5272 || M528x || M520x
++ help
++ Say Y here if you want to use the built-in 10/100 Fast ethernet
++ controller on some Motorola ColdFire processors.
++
++config FEC2
++ bool "Second FEC ethernet controller (on some ColdFire CPUs)"
++ depends on FEC
++ help
++ Say Y here if you want to use the second built-in 10/100 Fast
++ ethernet controller on some Motorola ColdFire processors.
++
++config NE_H8300
++ tristate "NE2000 compatible support for H8/300"
++ depends on H8300 && NET_ETHERNET
++ help
++ Say Y here if you want to use the NE2000 compatible
++ controller on the Renesas H8/300 processor.
++
++source "drivers/net/fec_8xx/Kconfig"
++source "drivers/net/fs_enet/Kconfig"
++
++endmenu
+
-+EXPORT_SYMBOL(get_system_type);
-diff -Nur linux-2.6.17/arch/mips/aruba/time.c linux-2.6.17-owrt/arch/mips/aruba/time.c
---- linux-2.6.17/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/arch/mips/aruba/time.c 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,108 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * timer routines for IDT EB434 boards
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++#
++# Gigabit Ethernet
++#
+
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/kernel_stat.h>
-+#include <linux/sched.h>
-+#include <linux/spinlock.h>
-+#include <linux/mc146818rtc.h>
-+#include <linux/irq.h>
-+#include <linux/timex.h>
++menu "Ethernet (1000 Mbit)"
++ depends on !UML
++
++config ACENIC
++ tristate "Alteon AceNIC/3Com 3C985/NetGear GA620 Gigabit support"
++ depends on PCI
++ ---help---
++ Say Y here if you have an Alteon AceNIC, 3Com 3C985(B), NetGear
++ GA620, SGI Gigabit or Farallon PN9000-SX PCI Gigabit Ethernet
++ adapter. The driver allows for using the Jumbo Frame option (9000
++ bytes/frame) however it requires that your switches can handle this
++ as well. To enable Jumbo Frames, add `mtu 9000' to your ifconfig
++ line.
++
++ To compile this driver as a module, choose M here: the
++ module will be called acenic.
++
++config ACENIC_OMIT_TIGON_I
++ bool "Omit support for old Tigon I based AceNICs"
++ depends on ACENIC
++ help
++ Say Y here if you only have Tigon II based AceNICs and want to leave
++ out support for the older Tigon I based cards which are no longer
++ being sold (ie. the original Alteon AceNIC and 3Com 3C985 (non B
++ version)). This will reduce the size of the driver object by
++ app. 100KB. If you are not sure whether your card is a Tigon I or a
++ Tigon II, say N here.
++
++ The safe and default value for this is N.
++
++config DL2K
++ tristate "D-Link DL2000-based Gigabit Ethernet support"
++ depends on PCI
++ select CRC32
++ help
++ This driver supports D-Link 2000-based gigabit ethernet cards, which
++ includes
++ D-Link DGE-550T Gigabit Ethernet Adapter.
++ D-Link DL2000-based Gigabit Ethernet Adapter.
++
++ To compile this driver as a module, choose M here: the
++ module will be called dl2k.
++
++config E1000
++ tristate "Intel(R) PRO/1000 Gigabit Ethernet support"
++ depends on PCI
++ ---help---
++ This driver supports Intel(R) PRO/1000 gigabit ethernet family of
++ adapters. For more information on how to identify your adapter, go
++ to the Adapter & Driver ID Guide at:
++
++ <http://support.intel.com/support/network/adapter/pro100/21397.htm>
++
++ For general information and support, go to the Intel support
++ website at:
++
++ <http://support.intel.com>
++
++ More specific information on configuring the driver is in
++ <file:Documentation/networking/e1000.txt>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called e1000.
++
++config E1000_NAPI
++ bool "Use Rx Polling (NAPI)"
++ depends on E1000
++ help
++ NAPI is a new driver API designed to reduce CPU and interrupt load
++ when the driver is receiving lots of packets from the card. It is
++ still somewhat experimental and thus not yet enabled by default.
++
++ If your estimated Rx load is 10kpps or more, or if the card will be
++ deployed on potentially unfriendly networks (e.g. in a firewall),
++ then say Y here.
++
++ See <file:Documentation/networking/NAPI_HOWTO.txt> for more
++ information.
++
++ If in doubt, say N.
++
++config E1000_DISABLE_PACKET_SPLIT
++ bool "Disable Packet Split for PCI express adapters"
++ depends on E1000
++ help
++ Say Y here if you want to use the legacy receive path for PCI express
++ hardware.
++
++ If in doubt, say N.
++
++source "drivers/net/ixp2000/Kconfig"
++
++config MYRI_SBUS
++ tristate "MyriCOM Gigabit Ethernet support"
++ depends on SBUS
++ help
++ This driver supports MyriCOM Sbus gigabit Ethernet cards.
++
++ To compile this driver as a module, choose M here: the module
++ will be called myri_sbus. This is recommended.
++
++config NS83820
++ tristate "National Semiconductor DP83820 support"
++ depends on PCI
++ help
++ This is a driver for the National Semiconductor DP83820 series
++ of gigabit ethernet MACs. Cards using this chipset include
++ the D-Link DGE-500T, PureData's PDP8023Z-TG, SMC's SMC9462TX,
++ SOHO-GA2000T, SOHO-GA2500T. The driver supports the use of
++ zero copy.
++
++config HAMACHI
++ tristate "Packet Engines Hamachi GNIC-II support"
++ depends on PCI
++ select MII
++ help
++ If you have a Gigabit Ethernet card of this type, say Y and read
++ the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module will be
++ called hamachi.
++
++config YELLOWFIN
++ tristate "Packet Engines Yellowfin Gigabit-NIC support (EXPERIMENTAL)"
++ depends on PCI && EXPERIMENTAL
++ select CRC32
++ ---help---
++ Say Y here if you have a Packet Engines G-NIC PCI Gigabit Ethernet
++ adapter or the SYM53C885 Ethernet controller. The Gigabit adapter is
++ used by the Beowulf Linux cluster project. See
++ <http://cesdis.gsfc.nasa.gov/linux/drivers/yellowfin.html> for more
++ information about this driver in particular and Beowulf in general.
++
++ To compile this driver as a module, choose M here: the module
++ will be called yellowfin. This is recommended.
++
++config R8169
++ tristate "Realtek 8169 gigabit ethernet support"
++ depends on PCI
++ select CRC32
++ ---help---
++ Say Y here if you have a Realtek 8169 PCI Gigabit Ethernet adapter.
++
++ To compile this driver as a module, choose M here: the module
++ will be called r8169. This is recommended.
++
++config R8169_NAPI
++ bool "Use Rx and Tx Polling (NAPI) (EXPERIMENTAL)"
++ depends on R8169 && EXPERIMENTAL
++ help
++ NAPI is a new driver API designed to reduce CPU and interrupt load
++ when the driver is receiving lots of packets from the card. It is
++ still somewhat experimental and thus not yet enabled by default.
++
++ If your estimated Rx load is 10kpps or more, or if the card will be
++ deployed on potentially unfriendly networks (e.g. in a firewall),
++ then say Y here.
++
++ See <file:Documentation/networking/NAPI_HOWTO.txt> for more
++ information.
++
++ If in doubt, say N.
++
++config R8169_VLAN
++ bool "VLAN support"
++ depends on R8169 && VLAN_8021Q
++ ---help---
++ Say Y here for the r8169 driver to support the functions required
++ by the kernel 802.1Q code.
++
++ If in doubt, say Y.
++
++config SIS190
++ tristate "SiS190/SiS191 gigabit ethernet support"
++ depends on PCI
++ select CRC32
++ select MII
++ ---help---
++ Say Y here if you have a SiS 190 PCI Fast Ethernet adapter or
++ a SiS 191 PCI Gigabit Ethernet adapter. Both are expected to
++ appear in lan on motherboard designs which are based on SiS 965
++ and SiS 966 south bridge.
++
++ To compile this driver as a module, choose M here: the module
++ will be called sis190. This is recommended.
++
++config SKGE
++ tristate "New SysKonnect GigaEthernet support"
++ depends on PCI
++ select CRC32
++ ---help---
++ This driver support the Marvell Yukon or SysKonnect SK-98xx/SK-95xx
++ and related Gigabit Ethernet adapters. It is a new smaller driver
++ with better performance and more complete ethtool support.
++
++ It does not support the link failover and network management
++ features that "portable" vendor supplied sk98lin driver does.
++
++ This driver supports adapters based on the original Yukon chipset:
++ Marvell 88E8001, Belkin F5D5005, CNet GigaCard, DLink DGE-530T,
++ Linksys EG1032/EG1064, 3Com 3C940/3C940B, SysKonnect SK-9871/9872.
++
++ It does not support the newer Yukon2 chipset: a separate driver,
++ sky2, is provided for Yukon2-based adapters.
++
++ To compile this driver as a module, choose M here: the module
++ will be called skge. This is recommended.
++
++config SKY2
++ tristate "SysKonnect Yukon2 support (EXPERIMENTAL)"
++ depends on PCI
++ select CRC32
++ ---help---
++ This driver supports Gigabit Ethernet adapters based on the
++ Marvell Yukon 2 chipset:
++ Marvell 88E8021/88E8022/88E8035/88E8036/88E8038/88E8050/88E8052/
++ 88E8053/88E8055/88E8061/88E8062, SysKonnect SK-9E21D/SK-9S21
++
++ There is companion driver for the older Marvell Yukon and
++ Genesis based adapters: skge.
++
++ To compile this driver as a module, choose M here: the module
++ will be called sky2. This is recommended.
++
++config SK98LIN
++ tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support (DEPRECATED)"
++ depends on PCI
++ ---help---
++ Say Y here if you have a Marvell Yukon or SysKonnect SK-98xx/SK-95xx
++ compliant Gigabit Ethernet Adapter.
++
++ This driver supports the original Yukon chipset. This driver is
++ deprecated and will be removed from the kernel in the near future,
++ it has been replaced by the skge driver. skge is cleaner and
++ seems to work better.
++
++ This driver does not support the newer Yukon2 chipset. A separate
++ driver, sky2, is provided to support Yukon2-based adapters.
++
++ The following adapters are supported by this driver:
++ - 3Com 3C940 Gigabit LOM Ethernet Adapter
++ - 3Com 3C941 Gigabit LOM Ethernet Adapter
++ - Allied Telesyn AT-2970LX Gigabit Ethernet Adapter
++ - Allied Telesyn AT-2970LX/2SC Gigabit Ethernet Adapter
++ - Allied Telesyn AT-2970SX Gigabit Ethernet Adapter
++ - Allied Telesyn AT-2970SX/2SC Gigabit Ethernet Adapter
++ - Allied Telesyn AT-2970TX Gigabit Ethernet Adapter
++ - Allied Telesyn AT-2970TX/2TX Gigabit Ethernet Adapter
++ - Allied Telesyn AT-2971SX Gigabit Ethernet Adapter
++ - Allied Telesyn AT-2971T Gigabit Ethernet Adapter
++ - Belkin Gigabit Desktop Card 10/100/1000Base-T Adapter, Copper RJ-45
++ - EG1032 v2 Instant Gigabit Network Adapter
++ - EG1064 v2 Instant Gigabit Network Adapter
++ - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Abit)
++ - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Albatron)
++ - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Asus)
++ - Marvell 88E8001 Gigabit LOM Ethernet Adapter (ECS)
++ - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Epox)
++ - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Foxconn)
++ - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Gigabyte)
++ - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Iwill)
++ - Marvell 88E8050 Gigabit LOM Ethernet Adapter (Intel)
++ - Marvell RDK-8001 Adapter
++ - Marvell RDK-8002 Adapter
++ - Marvell RDK-8003 Adapter
++ - Marvell RDK-8004 Adapter
++ - Marvell RDK-8006 Adapter
++ - Marvell RDK-8007 Adapter
++ - Marvell RDK-8008 Adapter
++ - Marvell RDK-8009 Adapter
++ - Marvell RDK-8010 Adapter
++ - Marvell RDK-8011 Adapter
++ - Marvell RDK-8012 Adapter
++ - Marvell RDK-8052 Adapter
++ - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (32 bit)
++ - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (64 bit)
++ - N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)
++ - SK-9521 10/100/1000Base-T Adapter
++ - SK-9521 V2.0 10/100/1000Base-T Adapter
++ - SK-9821 Gigabit Ethernet Server Adapter (SK-NET GE-T)
++ - SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter
++ - SK-9822 Gigabit Ethernet Server Adapter (SK-NET GE-T dual link)
++ - SK-9841 Gigabit Ethernet Server Adapter (SK-NET GE-LX)
++ - SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter
++ - SK-9842 Gigabit Ethernet Server Adapter (SK-NET GE-LX dual link)
++ - SK-9843 Gigabit Ethernet Server Adapter (SK-NET GE-SX)
++ - SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter
++ - SK-9844 Gigabit Ethernet Server Adapter (SK-NET GE-SX dual link)
++ - SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter
++ - SK-9861 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition)
++ - SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter
++ - SK-9862 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition dual link)
++ - SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)
++ - SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter
++ - SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)
++ - SMC EZ Card 1000 (SMC9452TXV.2)
++
++ The adapters support Jumbo Frames.
++ The dual link adapters support link-failover and dual port features.
++ Both Marvell Yukon and SysKonnect SK-98xx/SK-95xx adapters support
++ the scatter-gather functionality with sendfile(). Please refer to
++ <file:Documentation/networking/sk98lin.txt> for more information about
++ optional driver parameters.
++ Questions concerning this driver may be addressed to:
++ <linux@syskonnect.de>
++
++ If you want to compile this driver as a module ( = code which can be
++ inserted in and removed from the running kernel whenever you want),
++ say M here and read <file:Documentation/kbuild/modules.txt>. The module will
++ be called sk98lin. This is recommended.
++
++config VIA_VELOCITY
++ tristate "VIA Velocity support"
++ depends on NET_PCI && PCI
++ select CRC32
++ select CRC_CCITT
++ select MII
++ help
++ If you have a VIA "Velocity" based network card say Y here.
++
++ To compile this driver as a module, choose M here. The module
++ will be called via-velocity.
++
++config TIGON3
++ tristate "Broadcom Tigon3 support"
++ depends on PCI
++ help
++ This driver supports Broadcom Tigon3 based gigabit Ethernet cards.
++
++ To compile this driver as a module, choose M here: the module
++ will be called tg3. This is recommended.
++
++config BNX2
++ tristate "Broadcom NetXtremeII support"
++ depends on PCI
++ select CRC32
++ select ZLIB_INFLATE
++ help
++ This driver supports Broadcom NetXtremeII gigabit Ethernet cards.
++
++ To compile this driver as a module, choose M here: the module
++ will be called bnx2. This is recommended.
++
++config SPIDER_NET
++ tristate "Spider Gigabit Ethernet driver"
++ depends on PCI && (PPC_IBM_CELL_BLADE || PPC_CELLEB)
++ select FW_LOADER
++ help
++ This driver supports the Gigabit Ethernet chips present on the
++ Cell Processor-Based Blades from IBM.
++
++config TSI108_ETH
++ tristate "Tundra TSI108 gigabit Ethernet support"
++ depends on TSI108_BRIDGE
++ help
++ This driver supports Tundra TSI108 gigabit Ethernet ports.
++ To compile this driver as a module, choose M here: the module
++ will be called tsi108_eth.
++
++config GIANFAR
++ tristate "Gianfar Ethernet"
++ depends on 85xx || 83xx || PPC_86xx
++ select PHYLIB
++ select CRC32
++ help
++ This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx,
++ and MPC86xx family of chips, and the FEC on the 8540.
++
++config GFAR_NAPI
++ bool "NAPI Support"
++ depends on GIANFAR
++
++config UCC_GETH
++ tristate "Freescale QE UCC GETH"
++ depends on QUICC_ENGINE && UCC_FAST
++ help
++ This driver supports the Gigabit Ethernet mode of QE UCC.
++ QE can be found on MPC836x CPUs.
++
++config UGETH_NAPI
++ bool "NAPI Support"
++ depends on UCC_GETH
++
++config UGETH_MAGIC_PACKET
++ bool "Magic Packet detection support"
++ depends on UCC_GETH
++
++config UGETH_FILTERING
++ bool "Mac address filtering support"
++ depends on UCC_GETH
++
++config UGETH_TX_ON_DEMOND
++ bool "Transmit on Demond support"
++ depends on UCC_GETH
++
++config UGETH_HAS_GIGA
++ bool
++ depends on UCC_GETH && PPC_MPC836x
++
++config MV643XX_ETH
++ tristate "MV-643XX Ethernet support"
++ depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32)
++ select MII
++ help
++ This driver supports the gigabit Ethernet on the Marvell MV643XX
++ chipset which is used in the Momenco Ocelot C and Jaguar ATX and
++ Pegasos II, amongst other PPC and MIPS boards.
++
++config QLA3XXX
++ tristate "QLogic QLA3XXX Network Driver Support"
++ depends on PCI
++ help
++ This driver supports QLogic ISP3XXX gigabit Ethernet cards.
++
++ To compile this driver as a module, choose M here: the module
++ will be called qla3xxx.
++
++config ATL1
++ tristate "Attansic L1 Gigabit Ethernet support (EXPERIMENTAL)"
++ depends on PCI && EXPERIMENTAL
++ select CRC32
++ select MII
++ help
++ This driver supports the Attansic L1 gigabit ethernet adapter.
++
++ To compile this driver as a module, choose M here. The module
++ will be called atl1.
++
++endmenu
+
-+#include <linux/param.h>
-+#include <asm/mipsregs.h>
-+#include <asm/ptrace.h>
-+#include <asm/time.h>
-+#include <asm/hardirq.h>
++#
++# 10 Gigabit Ethernet
++#
+
-+#include <asm/mipsregs.h>
-+#include <asm/ptrace.h>
-+#include <asm/debug.h>
-+#include <asm/time.h>
++menu "Ethernet (10000 Mbit)"
++ depends on !UML
+
-+#include <asm/idt-boards/rc32434/rc32434.h>
++config CHELSIO_T1
++ tristate "Chelsio 10Gb Ethernet support"
++ depends on PCI
++ select CRC32
++ help
++ This driver supports Chelsio gigabit and 10-gigabit
++ Ethernet cards. More information about adapter features and
++ performance tuning is in <file:Documentation/networking/cxgb.txt>.
+
-+static unsigned long r4k_offset; /* Amount to incr compare reg each time */
-+static unsigned long r4k_cur; /* What counter should be at next timer irq */
++ For general information about Chelsio and our products, visit
++ our website at <http://www.chelsio.com>.
+
-+extern unsigned int idt_cpu_freq;
++ For customer support, please visit our customer support page at
++ <http://www.chelsio.com/support.htm>.
+
-+static unsigned long __init cal_r4koff(void)
-+{
-+ mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
-+ return (mips_hpt_frequency / HZ);
-+}
++ Please send feedback to <linux-bugs@chelsio.com>.
+
-+void __init aruba_time_init(void)
-+{
-+ unsigned int est_freq, flags;
-+ local_irq_save(flags);
++ To compile this driver as a module, choose M here: the module
++ will be called cxgb.
+
-+ printk("calculating r4koff... ");
-+ r4k_offset = cal_r4koff();
-+ printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
++config CHELSIO_T1_1G
++ bool "Chelsio gigabit Ethernet support"
++ depends on CHELSIO_T1
++ help
++ Enables support for Chelsio's gigabit Ethernet PCI cards. If you
++ are using only 10G cards say 'N' here.
++
++config CHELSIO_T1_NAPI
++ bool "Use Rx Polling (NAPI)"
++ depends on CHELSIO_T1
++ default y
++ help
++ NAPI is a driver API designed to reduce CPU and interrupt load
++ when the driver is receiving lots of packets from the card.
++
++config CHELSIO_T3
++ tristate "Chelsio Communications T3 10Gb Ethernet support"
++ depends on PCI
++ select FW_LOADER
++ help
++ This driver supports Chelsio T3-based gigabit and 10Gb Ethernet
++ adapters.
++
++ For general information about Chelsio and our products, visit
++ our website at <http://www.chelsio.com>.
++
++ For customer support, please visit our customer support page at
++ <http://www.chelsio.com/support.htm>.
++
++ Please send feedback to <linux-bugs@chelsio.com>.
++
++ To compile this driver as a module, choose M here: the module
++ will be called cxgb3.
++
++config EHEA
++ tristate "eHEA Ethernet support"
++ depends on IBMEBUS
++ ---help---
++ This driver supports the IBM pSeries eHEA ethernet adapter.
++
++ To compile the driver as a module, choose M here. The module
++ will be called ehea.
++
++config IXGB
++ tristate "Intel(R) PRO/10GbE support"
++ depends on PCI
++ ---help---
++ This driver supports Intel(R) PRO/10GbE family of
++ adapters. For more information on how to identify your adapter, go
++ to the Adapter & Driver ID Guide at:
+
-+ est_freq = 2 * r4k_offset * HZ;
-+ est_freq += 5000; /* round */
-+ est_freq -= est_freq % 10000;
-+ printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
-+ (est_freq % 1000000) * 100 / 1000000);
-+ local_irq_restore(flags);
++ <http://support.intel.com/support/network/adapter/pro100/21397.htm>
++
++ For general information and support, go to the Intel support
++ website at:
++
++ <http://support.intel.com>
++
++ More specific information on configuring the driver is in
++ <file:Documentation/networking/ixgb.txt>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called ixgb.
++
++config IXGB_NAPI
++ bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
++ depends on IXGB && EXPERIMENTAL
++ help
++ NAPI is a new driver API designed to reduce CPU and interrupt load
++ when the driver is receiving lots of packets from the card. It is
++ still somewhat experimental and thus not yet enabled by default.
++
++ If your estimated Rx load is 10kpps or more, or if the card will be
++ deployed on potentially unfriendly networks (e.g. in a firewall),
++ then say Y here.
++
++ See <file:Documentation/networking/NAPI_HOWTO.txt> for more
++ information.
++
++ If in doubt, say N.
++
++config S2IO
++ tristate "S2IO 10Gbe XFrame NIC"
++ depends on PCI
++ ---help---
++ This driver supports the 10Gbe XFrame NIC of S2IO.
++ More specific information on configuring the driver is in
++ <file:Documentation/networking/s2io.txt>.
++
++config S2IO_NAPI
++ bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
++ depends on S2IO && EXPERIMENTAL
++ help
++ NAPI is a new driver API designed to reduce CPU and interrupt load
++ when the driver is receiving lots of packets from the card. It is
++ still somewhat experimental and thus not yet enabled by default.
++
++ If your estimated Rx load is 10kpps or more, or if the card will be
++ deployed on potentially unfriendly networks (e.g. in a firewall),
++ then say Y here.
++
++ See <file:Documentation/networking/NAPI_HOWTO.txt> for more
++ information.
++
++ If in doubt, say N.
++
++config MYRI10GE
++ tristate "Myricom Myri-10G Ethernet support"
++ depends on PCI
++ select FW_LOADER
++ select CRC32
++ ---help---
++ This driver supports Myricom Myri-10G Dual Protocol interface in
++ Ethernet mode. If the eeprom on your board is not recent enough,
++ you will need a newer firmware image.
++ You may get this image or more information, at:
++
++ <http://www.myri.com/scs/download-Myri10GE.html>
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module
++ will be called myri10ge.
++
++config NETXEN_NIC
++ tristate "NetXen Multi port (1/10) Gigabit Ethernet NIC"
++ depends on PCI
++ help
++ This enables the support for NetXen's Gigabit Ethernet card.
++
++config PASEMI_MAC
++ tristate "PA Semi 1/10Gbit MAC"
++ depends on PPC64 && PCI
++ help
++ This driver supports the on-chip 1/10Gbit Ethernet controller on
++ PA Semi's PWRficient line of chips.
++
++endmenu
++
++source "drivers/net/tokenring/Kconfig"
++
++source "drivers/net/wireless/Kconfig"
++
++source "drivers/net/pcmcia/Kconfig"
++
++source "drivers/net/wan/Kconfig"
++
++source "drivers/atm/Kconfig"
++
++source "drivers/s390/net/Kconfig"
++
++config ISERIES_VETH
++ tristate "iSeries Virtual Ethernet driver support"
++ depends on PPC_ISERIES
++
++config RIONET
++ tristate "RapidIO Ethernet over messaging driver support"
++ depends on RAPIDIO
++
++config RIONET_TX_SIZE
++ int "Number of outbound queue entries"
++ depends on RIONET
++ default "128"
++
++config RIONET_RX_SIZE
++ int "Number of inbound queue entries"
++ depends on RIONET
++ default "128"
++
++config FDDI
++ bool "FDDI driver support"
++ depends on (PCI || EISA || TC)
++ help
++ Fiber Distributed Data Interface is a high speed local area network
++ design; essentially a replacement for high speed Ethernet. FDDI can
++ run over copper or fiber. If you are connected to such a network and
++ want a driver for the FDDI card in your computer, say Y here (and
++ then also Y to the driver for your FDDI card, below). Most people
++ will say N.
++
++config DEFXX
++ tristate "Digital DEFTA/DEFEA/DEFPA adapter support"
++ depends on FDDI && (PCI || EISA || TC)
++ ---help---
++ This is support for the DIGITAL series of TURBOchannel (DEFTA),
++ EISA (DEFEA) and PCI (DEFPA) controllers which can connect you
++ to a local FDDI network.
++
++ To compile this driver as a module, choose M here: the module
++ will be called defxx. If unsure, say N.
++
++config DEFXX_MMIO
++ bool
++ prompt "Use MMIO instead of PIO" if PCI || EISA
++ depends on DEFXX
++ default n if PCI || EISA
++ default y
++ ---help---
++ This instructs the driver to use EISA or PCI memory-mapped I/O
++ (MMIO) as appropriate instead of programmed I/O ports (PIO).
++ Enabling this gives an improvement in processing time in parts
++ of the driver, but it may cause problems with EISA (DEFEA)
++ adapters. TURBOchannel does not have the concept of I/O ports,
++ so MMIO is always used for these (DEFTA) adapters.
++
++ If unsure, say N.
++
++config SKFP
++ tristate "SysKonnect FDDI PCI support"
++ depends on FDDI && PCI
++ select BITREVERSE
++ ---help---
++ Say Y here if you have a SysKonnect FDDI PCI adapter.
++ The following adapters are supported by this driver:
++ - SK-5521 (SK-NET FDDI-UP)
++ - SK-5522 (SK-NET FDDI-UP DAS)
++ - SK-5541 (SK-NET FDDI-FP)
++ - SK-5543 (SK-NET FDDI-LP)
++ - SK-5544 (SK-NET FDDI-LP DAS)
++ - SK-5821 (SK-NET FDDI-UP64)
++ - SK-5822 (SK-NET FDDI-UP64 DAS)
++ - SK-5841 (SK-NET FDDI-FP64)
++ - SK-5843 (SK-NET FDDI-LP64)
++ - SK-5844 (SK-NET FDDI-LP64 DAS)
++ - Netelligent 100 FDDI DAS Fibre SC
++ - Netelligent 100 FDDI SAS Fibre SC
++ - Netelligent 100 FDDI DAS UTP
++ - Netelligent 100 FDDI SAS UTP
++ - Netelligent 100 FDDI SAS Fibre MIC
++
++ Read <file:Documentation/networking/skfp.txt> for information about
++ the driver.
++
++ Questions concerning this driver can be addressed to:
++ <linux@syskonnect.de>
++
++ To compile this driver as a module, choose M here: the module
++ will be called skfp. This is recommended.
++
++config HIPPI
++ bool "HIPPI driver support (EXPERIMENTAL)"
++ depends on EXPERIMENTAL && INET && PCI
++ help
++ HIgh Performance Parallel Interface (HIPPI) is a 800Mbit/sec and
++ 1600Mbit/sec dual-simplex switched or point-to-point network. HIPPI
++ can run over copper (25m) or fiber (300m on multi-mode or 10km on
++ single-mode). HIPPI networks are commonly used for clusters and to
++ connect to super computers. If you are connected to a HIPPI network
++ and have a HIPPI network card in your computer that you want to use
++ under Linux, say Y here (you must also remember to enable the driver
++ for your HIPPI card below). Most people will say N here.
++
++config ROADRUNNER
++ tristate "Essential RoadRunner HIPPI PCI adapter support (EXPERIMENTAL)"
++ depends on HIPPI && PCI
++ help
++ Say Y here if this is your PCI HIPPI network card.
++
++ To compile this driver as a module, choose M here: the module
++ will be called rrunner. If unsure, say N.
++
++config ROADRUNNER_LARGE_RINGS
++ bool "Use large TX/RX rings (EXPERIMENTAL)"
++ depends on ROADRUNNER
++ help
++ If you say Y here, the RoadRunner driver will preallocate up to 2 MB
++ of additional memory to allow for fastest operation, both for
++ transmitting and receiving. This memory cannot be used by any other
++ kernel code or by user space programs. Say Y here only if you have
++ the memory.
++
++config PLIP
++ tristate "PLIP (parallel port) support"
++ depends on PARPORT
++ ---help---
++ PLIP (Parallel Line Internet Protocol) is used to create a
++ reasonably fast mini network consisting of two (or, rarely, more)
++ local machines. A PLIP link from a Linux box is a popular means to
++ install a Linux distribution on a machine which doesn't have a
++ CD-ROM drive (a minimal system has to be transferred with floppies
++ first). The kernels on both machines need to have this PLIP option
++ enabled for this to work.
++
++ The PLIP driver has two modes, mode 0 and mode 1. The parallel
++ ports (the connectors at the computers with 25 holes) are connected
++ with "null printer" or "Turbo Laplink" cables which can transmit 4
++ bits at a time (mode 0) or with special PLIP cables, to be used on
++ bidirectional parallel ports only, which can transmit 8 bits at a
++ time (mode 1); you can find the wiring of these cables in
++ <file:Documentation/networking/PLIP.txt>. The cables can be up to
++ 15m long. Mode 0 works also if one of the machines runs DOS/Windows
++ and has some PLIP software installed, e.g. the Crynwr PLIP packet
++ driver (<http://oak.oakland.edu/simtel.net/msdos/pktdrvr-pre.html>)
++ and winsock or NCSA's telnet.
++
++ If you want to use PLIP, say Y and read the PLIP mini-HOWTO as well
++ as the NET-3-HOWTO, both available from
++ <http://www.tldp.org/docs.html#howto>. Note that the PLIP
++ protocol has been changed and this PLIP driver won't work together
++ with the PLIP support in Linux versions 1.0.x. This option enlarges
++ your kernel by about 8 KB.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module will be
++ called plip. If unsure, say Y or M, in case you buy a laptop
++ later.
++
++config PPP
++ tristate "PPP (point-to-point protocol) support"
++ select SLHC
++ ---help---
++ PPP (Point to Point Protocol) is a newer and better SLIP. It serves
++ the same purpose: sending Internet traffic over telephone (and other
++ serial) lines. Ask your access provider if they support it, because
++ otherwise you can't use it; most Internet access providers these
++ days support PPP rather than SLIP.
++
++ To use PPP, you need an additional program called pppd as described
++ in the PPP-HOWTO, available at
++ <http://www.tldp.org/docs.html#howto>. Make sure that you have
++ the version of pppd recommended in <file:Documentation/Changes>.
++ The PPP option enlarges your kernel by about 16 KB.
++
++ There are actually two versions of PPP: the traditional PPP for
++ asynchronous lines, such as regular analog phone lines, and
++ synchronous PPP which can be used over digital ISDN lines for
++ example. If you want to use PPP over phone lines or other
++ asynchronous serial lines, you need to say Y (or M) here and also to
++ the next option, "PPP support for async serial ports". For PPP over
++ synchronous lines, you should say Y (or M) here and to "Support
++ synchronous PPP", below.
++
++ If you said Y to "Version information on all symbols" above, then
++ you cannot compile the PPP driver into the kernel; you can then only
++ compile it as a module. To compile this driver as a module, choose M
++ here and read <file:Documentation/networking/net-modules.txt>.
++ The module will be called ppp_generic.
++
++config PPP_MULTILINK
++ bool "PPP multilink support (EXPERIMENTAL)"
++ depends on PPP && EXPERIMENTAL
++ help
++ PPP multilink is a protocol (defined in RFC 1990) which allows you
++ to combine several (logical or physical) lines into one logical PPP
++ connection, so that you can utilize your full bandwidth.
++
++ This has to be supported at the other end as well and you need a
++ version of the pppd daemon which understands the multilink protocol.
++
++ If unsure, say N.
++
++config PPP_FILTER
++ bool "PPP filtering"
++ depends on PPP
++ help
++ Say Y here if you want to be able to filter the packets passing over
++ PPP interfaces. This allows you to control which packets count as
++ activity (i.e. which packets will reset the idle timer or bring up
++ a demand-dialed link) and which packets are to be dropped entirely.
++ You need to say Y here if you wish to use the pass-filter and
++ active-filter options to pppd.
++
++ If unsure, say N.
++
++config PPP_ASYNC
++ tristate "PPP support for async serial ports"
++ depends on PPP
++ select CRC_CCITT
++ ---help---
++ Say Y (or M) here if you want to be able to use PPP over standard
++ asynchronous serial ports, such as COM1 or COM2 on a PC. If you use
++ a modem (not a synchronous or ISDN modem) to contact your ISP, you
++ need this option.
++
++ To compile this driver as a module, choose M here.
++
++ If unsure, say Y.
++
++config PPP_SYNC_TTY
++ tristate "PPP support for sync tty ports"
++ depends on PPP
++ help
++ Say Y (or M) here if you want to be able to use PPP over synchronous
++ (HDLC) tty devices, such as the SyncLink adapter. These devices
++ are often used for high-speed leased lines like T1/E1.
++
++ To compile this driver as a module, choose M here.
++
++config PPP_DEFLATE
++ tristate "PPP Deflate compression"
++ depends on PPP
++ select ZLIB_INFLATE
++ select ZLIB_DEFLATE
++ ---help---
++ Support for the Deflate compression method for PPP, which uses the
++ Deflate algorithm (the same algorithm that gzip uses) to compress
++ each PPP packet before it is sent over the wire. The machine at the
++ other end of the PPP link (usually your ISP) has to support the
++ Deflate compression method as well for this to be useful. Even if
++ they don't support it, it is safe to say Y here.
++
++ To compile this driver as a module, choose M here.
++
++config PPP_BSDCOMP
++ tristate "PPP BSD-Compress compression"
++ depends on PPP
++ ---help---
++ Support for the BSD-Compress compression method for PPP, which uses
++ the LZW compression method to compress each PPP packet before it is
++ sent over the wire. The machine at the other end of the PPP link
++ (usually your ISP) has to support the BSD-Compress compression
++ method as well for this to be useful. Even if they don't support it,
++ it is safe to say Y here.
++
++ The PPP Deflate compression method ("PPP Deflate compression",
++ above) is preferable to BSD-Compress, because it compresses better
++ and is patent-free.
++
++ Note that the BSD compression code will always be compiled as a
++ module; it is called bsd_comp and will show up in the directory
++ modules once you have said "make modules". If unsure, say N.
++
++config PPP_MPPE
++ tristate "PPP MPPE compression (encryption) (EXPERIMENTAL)"
++ depends on PPP && EXPERIMENTAL
++ select CRYPTO
++ select CRYPTO_SHA1
++ select CRYPTO_ARC4
++ select CRYPTO_ECB
++ ---help---
++ Support for the MPPE Encryption protocol, as employed by the
++ Microsoft Point-to-Point Tunneling Protocol.
++
++ See http://pptpclient.sourceforge.net/ for information on
++ configuring PPTP clients and servers to utilize this method.
++
++config PPPOE
++ tristate "PPP over Ethernet (EXPERIMENTAL)"
++ depends on EXPERIMENTAL && PPP
++ help
++ Support for PPP over Ethernet.
++
++ This driver requires the latest version of pppd from the CVS
++ repository at cvs.samba.org. Alternatively, see the
++ RoaringPenguin package (<http://www.roaringpenguin.com/pppoe>)
++ which contains instruction on how to use this driver (under
++ the heading "Kernel mode PPPoE").
++
++config PPPOATM
++ tristate "PPP over ATM"
++ depends on ATM && PPP
++ help
++ Support PPP (Point to Point Protocol) encapsulated in ATM frames.
++ This implementation does not yet comply with section 8 of RFC2364,
++ which can lead to bad results if the ATM peer loses state and
++ changes its encapsulation unilaterally.
++
++config SLIP
++ tristate "SLIP (serial line) support"
++ ---help---
++ Say Y if you intend to use SLIP or CSLIP (compressed SLIP) to
++ connect to your Internet service provider or to connect to some
++ other local Unix box or if you want to configure your Linux box as a
++ Slip/CSlip server for other people to dial in. SLIP (Serial Line
++ Internet Protocol) is a protocol used to send Internet traffic over
++ serial connections such as telephone lines or null modem cables;
++ nowadays, the protocol PPP is more commonly used for this same
++ purpose.
++
++ Normally, your access provider has to support SLIP in order for you
++ to be able to use it, but there is now a SLIP emulator called SLiRP
++ around (available from
++ <ftp://ibiblio.org/pub/Linux/system/network/serial/>) which
++ allows you to use SLIP over a regular dial up shell connection. If
++ you plan to use SLiRP, make sure to say Y to CSLIP, below. The
++ NET-3-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>, explains how to
++ configure SLIP. Note that you don't need this option if you just
++ want to run term (term is a program which gives you almost full
++ Internet connectivity if you have a regular dial up shell account on
++ some Internet connected Unix computer. Read
++ <http://www.bart.nl/~patrickr/term-howto/Term-HOWTO.html>). SLIP
++ support will enlarge your kernel by about 4 KB. If unsure, say N.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module will be
++ called slip.
++
++config SLIP_COMPRESSED
++ bool "CSLIP compressed headers"
++ depends on SLIP
++ select SLHC
++ ---help---
++ This protocol is faster than SLIP because it uses compression on the
++ TCP/IP headers (not on the data itself), but it has to be supported
++ on both ends. Ask your access provider if you are not sure and
++ answer Y, just in case. You will still be able to use plain SLIP. If
++ you plan to use SLiRP, the SLIP emulator (available from
++ <ftp://ibiblio.org/pub/Linux/system/network/serial/>) which
++ allows you to use SLIP over a regular dial up shell connection, you
++ definitely want to say Y here. The NET-3-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>, explains how to configure
++ CSLIP. This won't enlarge your kernel.
++
++config SLHC
++ tristate
++ help
++ This option enables Van Jacobsen serial line header compression
++ routines.
++
++config SLIP_SMART
++ bool "Keepalive and linefill"
++ depends on SLIP
++ help
++ Adds additional capabilities to the SLIP driver to support the
++ RELCOM line fill and keepalive monitoring. Ideal on poor quality
++ analogue lines.
++
++config SLIP_MODE_SLIP6
++ bool "Six bit SLIP encapsulation"
++ depends on SLIP
++ help
++ Just occasionally you may need to run IP over hostile serial
++ networks that don't pass all control characters or are only seven
++ bit. Saying Y here adds an extra mode you can use with SLIP:
++ "slip6". In this mode, SLIP will only send normal ASCII symbols over
++ the serial device. Naturally, this has to be supported at the other
++ end of the link as well. It's good enough, for example, to run IP
++ over the async ports of a Camtec JNT Pad. If unsure, say N.
++
++config NET_FC
++ bool "Fibre Channel driver support"
++ depends on SCSI && PCI
++ help
++ Fibre Channel is a high speed serial protocol mainly used to connect
++ large storage devices to the computer; it is compatible with and
++ intended to replace SCSI.
++
++ If you intend to use Fibre Channel, you need to have a Fibre channel
++ adaptor card in your computer; say Y here and to the driver for your
++ adaptor below. You also should have said Y to "SCSI support" and
++ "SCSI generic support".
++
++config SHAPER
++ tristate "Traffic Shaper (OBSOLETE)"
++ depends on EXPERIMENTAL
++ ---help---
++ The traffic shaper is a virtual network device that allows you to
++ limit the rate of outgoing data flow over some other network device.
++ The traffic that you want to slow down can then be routed through
++ these virtual devices. See
++ <file:Documentation/networking/shaper.txt> for more information.
++
++ An alternative to this traffic shaper are traffic schedulers which
++ you'll get if you say Y to "QoS and/or fair queuing" in
++ "Networking options".
++
++ To compile this driver as a module, choose M here: the module
++ will be called shaper. If unsure, say N.
++
++config NETCONSOLE
++ tristate "Network console logging support (EXPERIMENTAL)"
++ depends on EXPERIMENTAL
++ ---help---
++ If you want to log kernel messages over the network, enable this.
++ See <file:Documentation/networking/netconsole.txt> for details.
++
++endif #NETDEVICES
++
++config NETPOLL
++ def_bool NETCONSOLE
++
++config NETPOLL_RX
++ bool "Netpoll support for trapping incoming packets"
++ default n
++ depends on NETPOLL
++
++config NETPOLL_TRAP
++ bool "Netpoll traffic trapping"
++ default n
++ depends on NETPOLL
++
++config NET_POLL_CONTROLLER
++ def_bool NETPOLL
++
++endmenu
+diff -Nur linux-2.6.21.1/drivers/net/Makefile linux-2.6.21.1-owrt/drivers/net/Makefile
+--- linux-2.6.21.1/drivers/net/Makefile 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/drivers/net/Makefile 2007-05-23 23:37:01.000000000 +0200
+@@ -11,6 +11,7 @@
+ obj-$(CONFIG_BONDING) += bonding/
+ obj-$(CONFIG_ATL1) += atl1/
+ obj-$(CONFIG_GIANFAR) += gianfar_driver.o
++obj-$(CONFIG_AR2313) += ar2313/
+
+ gianfar_driver-objs := gianfar.o \
+ gianfar_ethtool.o \
+@@ -38,6 +39,7 @@
+ obj-$(CONFIG_MACE) += mace.o
+ obj-$(CONFIG_BMAC) += bmac.o
+
++obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
+ obj-$(CONFIG_DGRS) += dgrs.o
+ obj-$(CONFIG_VORTEX) += 3c59x.o
+ obj-$(CONFIG_TYPHOON) += typhoon.o
+diff -Nur linux-2.6.21.1/drivers/net/Makefile.orig linux-2.6.21.1-owrt/drivers/net/Makefile.orig
+--- linux-2.6.21.1/drivers/net/Makefile.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/drivers/net/Makefile.orig 2007-05-23 23:34:01.000000000 +0200
+@@ -0,0 +1,221 @@
++#
++# Makefile for the Linux network (ethercard) device drivers.
++#
+
-+}
++obj-$(CONFIG_E1000) += e1000/
++obj-$(CONFIG_IBM_EMAC) += ibm_emac/
++obj-$(CONFIG_IXGB) += ixgb/
++obj-$(CONFIG_CHELSIO_T1) += chelsio/
++obj-$(CONFIG_CHELSIO_T3) += cxgb3/
++obj-$(CONFIG_EHEA) += ehea/
++obj-$(CONFIG_BONDING) += bonding/
++obj-$(CONFIG_ATL1) += atl1/
++obj-$(CONFIG_GIANFAR) += gianfar_driver.o
+
-+void __init aruba_timer_setup(struct irqaction *irq)
-+{
-+ /* we are using the cpu counter for timer interrupts */
-+ setup_irq(MIPS_CPU_TIMER_IRQ, irq);
++gianfar_driver-objs := gianfar.o \
++ gianfar_ethtool.o \
++ gianfar_mii.o \
++ gianfar_sysfs.o
+
-+ /* to generate the first timer interrupt */
-+ r4k_cur = (read_c0_count() + r4k_offset);
-+ write_c0_compare(r4k_cur);
++obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
++ucc_geth_driver-objs := ucc_geth.o ucc_geth_phy.o
+
-+}
++#
++# link order important here
++#
++obj-$(CONFIG_PLIP) += plip.o
+
-+asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
-+{
-+ irq_enter();
-+ kstat_this_cpu.irqs[irq]++;
-+
-+ timer_interrupt(irq, NULL, regs);
-+ irq_exit();
-+}
-diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
---- linux-2.6.17/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 12:44:28.000000000 +0200
-@@ -227,6 +227,17 @@
- either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
- a kernel for this platform.
-
-+config MACH_ARUBA
-+ bool "Support for the ARUBA product line"
-+ select DMA_NONCOHERENT
-+ select CPU_HAS_PREFETCH
-+ select HW_HAS_PCI
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_SUPPORTS_BIG_ENDIAN
++obj-$(CONFIG_ROADRUNNER) += rrunner.o
+
++obj-$(CONFIG_HAPPYMEAL) += sunhme.o
++obj-$(CONFIG_SUNLANCE) += sunlance.o
++obj-$(CONFIG_SUNQE) += sunqe.o
++obj-$(CONFIG_SUNBMAC) += sunbmac.o
++obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
++obj-$(CONFIG_SUNGEM) += sungem.o sungem_phy.o
++obj-$(CONFIG_CASSINI) += cassini.o
+
- config MACH_JAZZ
- bool "Jazz family of machines"
- select ARC
-diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
---- linux-2.6.17/arch/mips/Makefile 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/arch/mips/Makefile 2006-06-18 12:44:28.000000000 +0200
-@@ -145,6 +145,14 @@
- #
-
- #
-+# Aruba
-+#
++obj-$(CONFIG_MACE) += mace.o
++obj-$(CONFIG_BMAC) += bmac.o
+
-+core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
-+cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
-+load-$(CONFIG_MACH_ARUBA) += 0x80100000
++obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
++obj-$(CONFIG_DGRS) += dgrs.o
++obj-$(CONFIG_VORTEX) += 3c59x.o
++obj-$(CONFIG_TYPHOON) += typhoon.o
++obj-$(CONFIG_NE2K_PCI) += ne2k-pci.o 8390.o
++obj-$(CONFIG_PCNET32) += pcnet32.o
++obj-$(CONFIG_EEPRO100) += eepro100.o
++obj-$(CONFIG_E100) += e100.o
++obj-$(CONFIG_TLAN) += tlan.o
++obj-$(CONFIG_EPIC100) += epic100.o
++obj-$(CONFIG_SIS190) += sis190.o
++obj-$(CONFIG_SIS900) += sis900.o
++obj-$(CONFIG_YELLOWFIN) += yellowfin.o
++obj-$(CONFIG_ACENIC) += acenic.o
++obj-$(CONFIG_ISERIES_VETH) += iseries_veth.o
++obj-$(CONFIG_NATSEMI) += natsemi.o
++obj-$(CONFIG_NS83820) += ns83820.o
++obj-$(CONFIG_STNIC) += stnic.o 8390.o
++obj-$(CONFIG_FEALNX) += fealnx.o
++obj-$(CONFIG_TIGON3) += tg3.o
++obj-$(CONFIG_BNX2) += bnx2.o
++spidernet-y += spider_net.o spider_net_ethtool.o
++obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o
++obj-$(CONFIG_TC35815) += tc35815.o
++obj-$(CONFIG_SKGE) += skge.o
++obj-$(CONFIG_SKY2) += sky2.o
++obj-$(CONFIG_SK98LIN) += sk98lin/
++obj-$(CONFIG_SKFP) += skfp/
++obj-$(CONFIG_VIA_RHINE) += via-rhine.o
++obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o
++obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o
++obj-$(CONFIG_RIONET) += rionet.o
+
+#
- # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
- #
- core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
-diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
---- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c 2006-06-18 12:48:27.000000000 +0200
-@@ -876,7 +876,6 @@
- case CPU_R10000:
- case CPU_R12000:
- case CPU_R14000:
-- case CPU_4KC:
- case CPU_SB1:
- case CPU_SB1A:
- case CPU_4KSC:
-@@ -904,6 +903,7 @@
- tlbw(p);
- break;
-
-+ case CPU_4KC:
- case CPU_4KEC:
- case CPU_24K:
- case CPU_34K:
-diff -Nur linux-2.6.17/drivers/net/Kconfig linux-2.6.17-owrt/drivers/net/Kconfig
---- linux-2.6.17/drivers/net/Kconfig 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/drivers/net/Kconfig 2006-06-18 12:44:28.000000000 +0200
-@@ -187,6 +187,13 @@
-
- source "drivers/net/arm/Kconfig"
-
-+config IDT_RC32434_ETH
-+ tristate "IDT RC32434 Local Ethernet support"
-+ depends on NET_ETHERNET
-+ help
-+ IDT RC32434 has one local ethernet port. Say Y here to enable it.
-+ To compile this driver as a module, choose M here.
++# end link order section
++#
+
- config MACE
- tristate "MACE (Power Mac ethernet) support"
- depends on NET_ETHERNET && PPC_PMAC && PPC32
-diff -Nur linux-2.6.17/drivers/net/Makefile linux-2.6.17-owrt/drivers/net/Makefile
---- linux-2.6.17/drivers/net/Makefile 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/drivers/net/Makefile 2006-06-18 12:44:28.000000000 +0200
-@@ -38,6 +38,7 @@
-
- obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
-
-+obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
- obj-$(CONFIG_DGRS) += dgrs.o
- obj-$(CONFIG_VORTEX) += 3c59x.o
- obj-$(CONFIG_TYPHOON) += typhoon.o
-diff -Nur linux-2.6.17/drivers/net/natsemi.c linux-2.6.17-owrt/drivers/net/natsemi.c
---- linux-2.6.17/drivers/net/natsemi.c 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/drivers/net/natsemi.c 2006-06-18 12:44:28.000000000 +0200
-@@ -771,6 +771,49 @@
++obj-$(CONFIG_MII) += mii.o
++obj-$(CONFIG_PHYLIB) += phy/
++
++obj-$(CONFIG_SUNDANCE) += sundance.o
++obj-$(CONFIG_HAMACHI) += hamachi.o
++obj-$(CONFIG_NET) += Space.o loopback.o
++obj-$(CONFIG_SEEQ8005) += seeq8005.o
++obj-$(CONFIG_NET_SB1000) += sb1000.o
++obj-$(CONFIG_MAC8390) += mac8390.o
++obj-$(CONFIG_APNE) += apne.o 8390.o
++obj-$(CONFIG_PCMCIA_PCNET) += 8390.o
++obj-$(CONFIG_SHAPER) += shaper.o
++obj-$(CONFIG_HP100) += hp100.o
++obj-$(CONFIG_SMC9194) += smc9194.o
++obj-$(CONFIG_FEC) += fec.o
++obj-$(CONFIG_68360_ENET) += 68360enet.o
++obj-$(CONFIG_WD80x3) += wd.o 8390.o
++obj-$(CONFIG_EL2) += 3c503.o 8390.o
++obj-$(CONFIG_NE2000) += ne.o 8390.o
++obj-$(CONFIG_NE2_MCA) += ne2.o 8390.o
++obj-$(CONFIG_HPLAN) += hp.o 8390.o
++obj-$(CONFIG_HPLAN_PLUS) += hp-plus.o 8390.o
++obj-$(CONFIG_ULTRA) += smc-ultra.o 8390.o
++obj-$(CONFIG_ULTRAMCA) += smc-mca.o 8390.o
++obj-$(CONFIG_ULTRA32) += smc-ultra32.o 8390.o
++obj-$(CONFIG_E2100) += e2100.o 8390.o
++obj-$(CONFIG_ES3210) += es3210.o 8390.o
++obj-$(CONFIG_LNE390) += lne390.o 8390.o
++obj-$(CONFIG_NE3210) += ne3210.o 8390.o
++obj-$(CONFIG_NET_SB1250_MAC) += sb1250-mac.o
++obj-$(CONFIG_B44) += b44.o
++obj-$(CONFIG_FORCEDETH) += forcedeth.o
++obj-$(CONFIG_NE_H8300) += ne-h8300.o
++
++obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
++obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
++obj-$(CONFIG_QLA3XXX) += qla3xxx.o
++
++obj-$(CONFIG_PPP) += ppp_generic.o
++obj-$(CONFIG_PPP_ASYNC) += ppp_async.o
++obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o
++obj-$(CONFIG_PPP_DEFLATE) += ppp_deflate.o
++obj-$(CONFIG_PPP_BSDCOMP) += bsd_comp.o
++obj-$(CONFIG_PPP_MPPE) += ppp_mppe.o
++obj-$(CONFIG_PPPOE) += pppox.o pppoe.o
++
++obj-$(CONFIG_SLIP) += slip.o
++obj-$(CONFIG_SLHC) += slhc.o
++
++obj-$(CONFIG_DUMMY) += dummy.o
++obj-$(CONFIG_IFB) += ifb.o
++obj-$(CONFIG_DE600) += de600.o
++obj-$(CONFIG_DE620) += de620.o
++obj-$(CONFIG_LANCE) += lance.o
++obj-$(CONFIG_SUN3_82586) += sun3_82586.o
++obj-$(CONFIG_SUN3LANCE) += sun3lance.o
++obj-$(CONFIG_DEFXX) += defxx.o
++obj-$(CONFIG_SGISEEQ) += sgiseeq.o
++obj-$(CONFIG_SGI_O2MACE_ETH) += meth.o
++obj-$(CONFIG_AT1700) += at1700.o
++obj-$(CONFIG_EL1) += 3c501.o
++obj-$(CONFIG_EL16) += 3c507.o
++obj-$(CONFIG_ELMC) += 3c523.o
++obj-$(CONFIG_IBMLANA) += ibmlana.o
++obj-$(CONFIG_ELMC_II) += 3c527.o
++obj-$(CONFIG_EL3) += 3c509.o
++obj-$(CONFIG_3C515) += 3c515.o
++obj-$(CONFIG_EEXPRESS) += eexpress.o
++obj-$(CONFIG_EEXPRESS_PRO) += eepro.o
++obj-$(CONFIG_8139CP) += 8139cp.o
++obj-$(CONFIG_8139TOO) += 8139too.o
++obj-$(CONFIG_ZNET) += znet.o
++obj-$(CONFIG_LAN_SAA9730) += saa9730.o
++obj-$(CONFIG_DEPCA) += depca.o
++obj-$(CONFIG_EWRK3) += ewrk3.o
++obj-$(CONFIG_ATP) += atp.o
++obj-$(CONFIG_NI5010) += ni5010.o
++obj-$(CONFIG_NI52) += ni52.o
++obj-$(CONFIG_NI65) += ni65.o
++obj-$(CONFIG_ELPLUS) += 3c505.o
++obj-$(CONFIG_AC3200) += ac3200.o 8390.o
++obj-$(CONFIG_APRICOT) += 82596.o
++obj-$(CONFIG_LASI_82596) += lasi_82596.o
++obj-$(CONFIG_MVME16x_NET) += 82596.o
++obj-$(CONFIG_BVME6000_NET) += 82596.o
++obj-$(CONFIG_SC92031) += sc92031.o
++
++# This is also a 82596 and should probably be merged
++obj-$(CONFIG_LP486E) += lp486e.o
++
++obj-$(CONFIG_ETH16I) += eth16i.o
++obj-$(CONFIG_ZORRO8390) += zorro8390.o
++obj-$(CONFIG_HPLANCE) += hplance.o 7990.o
++obj-$(CONFIG_MVME147_NET) += mvme147.o 7990.o
++obj-$(CONFIG_EQUALIZER) += eql.o
++obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o
++obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o
++obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o
++obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o
++obj-$(CONFIG_DECLANCE) += declance.o
++obj-$(CONFIG_ATARILANCE) += atarilance.o
++obj-$(CONFIG_ATARI_BIONET) += atari_bionet.o
++obj-$(CONFIG_ATARI_PAMSNET) += atari_pamsnet.o
++obj-$(CONFIG_A2065) += a2065.o
++obj-$(CONFIG_HYDRA) += hydra.o
++obj-$(CONFIG_ARIADNE) += ariadne.o
++obj-$(CONFIG_CS89x0) += cs89x0.o
++obj-$(CONFIG_MACSONIC) += macsonic.o
++obj-$(CONFIG_MACMACE) += macmace.o
++obj-$(CONFIG_MAC89x0) += mac89x0.o
++obj-$(CONFIG_TUN) += tun.o
++obj-$(CONFIG_NET_NETX) += netx-eth.o
++obj-$(CONFIG_DL2K) += dl2k.o
++obj-$(CONFIG_R8169) += r8169.o
++obj-$(CONFIG_AMD8111_ETH) += amd8111e.o
++obj-$(CONFIG_IBMVETH) += ibmveth.o
++obj-$(CONFIG_S2IO) += s2io.o
++obj-$(CONFIG_MYRI10GE) += myri10ge/
++obj-$(CONFIG_SMC91X) += smc91x.o
++obj-$(CONFIG_SMC911X) += smc911x.o
++obj-$(CONFIG_DM9000) += dm9000.o
++obj-$(CONFIG_FEC_8XX) += fec_8xx/
++obj-$(CONFIG_PASEMI_MAC) += pasemi_mac.o
++
++obj-$(CONFIG_MACB) += macb.o
++
++obj-$(CONFIG_ARM) += arm/
++obj-$(CONFIG_DEV_APPLETALK) += appletalk/
++obj-$(CONFIG_TR) += tokenring/
++obj-$(CONFIG_WAN) += wan/
++obj-$(CONFIG_ARCNET) += arcnet/
++obj-$(CONFIG_NET_PCMCIA) += pcmcia/
++obj-$(CONFIG_NET_RADIO) += wireless/
++obj-$(CONFIG_NET_TULIP) += tulip/
++obj-$(CONFIG_HAMRADIO) += hamradio/
++obj-$(CONFIG_IRDA) += irda/
++obj-$(CONFIG_ETRAX_ETHERNET) += cris/
++obj-$(CONFIG_ENP2611_MSF_NET) += ixp2000/
++
++obj-$(CONFIG_NETCONSOLE) += netconsole.o
++
++obj-$(CONFIG_FS_ENET) += fs_enet/
++
++obj-$(CONFIG_NETXEN_NIC) += netxen/
+diff -Nur linux-2.6.21.1/drivers/net/natsemi.c linux-2.6.21.1-owrt/drivers/net/natsemi.c
+--- linux-2.6.21.1/drivers/net/natsemi.c 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/drivers/net/natsemi.c 2007-05-23 23:34:01.000000000 +0200
+@@ -656,6 +656,49 @@
static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
- static struct ethtool_ops ethtool_ops;
+ static const struct ethtool_ops ethtool_ops;
+#ifdef CONFIG_MACH_ARUBA
+
static inline void __iomem *ns_ioaddr(struct net_device *dev)
{
return (void __iomem *) dev->base_addr;
-@@ -871,6 +914,7 @@
+@@ -794,6 +837,7 @@
goto err_ioremap;
}
/* Work around the dropped serial bit. */
prev_eedata = eeprom_read(ioaddr, 6);
for (i = 0; i < 3; i++) {
-@@ -879,6 +923,19 @@
+@@ -802,6 +846,19 @@
dev->dev_addr[i*2+1] = eedata >> 7;
prev_eedata = eedata;
}
dev->base_addr = (unsigned long __force) ioaddr;
dev->irq = irq;
-diff -Nur linux-2.6.17/drivers/net/rc32434_eth.c linux-2.6.17-owrt/drivers/net/rc32434_eth.c
---- linux-2.6.17/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/drivers/net/rc32434_eth.c 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,1273 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Driver for the IDT RC32434 on-chip ethernet controller.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb
-+ *
-+ * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
-+ *
-+ * Aug 2004 Sadik
-+ *
-+ * Added NAPI
-+ *
-+ **************************************************************************
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/version.h>
+diff -Nur linux-2.6.21.1/drivers/pci/access.c linux-2.6.21.1-owrt/drivers/pci/access.c
+--- linux-2.6.21.1/drivers/pci/access.c 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/drivers/pci/access.c 2007-05-23 23:36:48.000000000 +0200
+@@ -23,6 +23,7 @@
+ #define PCI_word_BAD (pos & 1)
+ #define PCI_dword_BAD (pos & 3)
+
++#ifdef __MIPSEB__
+ #define PCI_OP_READ(size,type,len) \
+ int pci_bus_read_config_##size \
+ (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
+@@ -33,11 +34,32 @@
+ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
+ spin_lock_irqsave(&pci_lock, flags); \
+ res = bus->ops->read(bus, devfn, pos, len, &data); \
++ if (len == 1) \
++ *value = (type)((data >> 24) & 0xff); \
++ else if (len == 2) \
++ *value = (type)((data >> 16) & 0xffff); \
++ else \
+ *value = (type)data; \
+ spin_unlock_irqrestore(&pci_lock, flags); \
+ return res; \
+ }
++#else
+
++#define PCI_OP_READ(size,type,len) \
++int pci_bus_read_config_##size \
++ (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
++{ \
++ int res; \
++ unsigned long flags; \
++ u32 data = 0; \
++ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
++ spin_lock_irqsave(&pci_lock, flags); \
++ res = bus->ops->read(bus, devfn, pos, len, &data); \
++ *value = (type)data; \
++ spin_unlock_irqrestore(&pci_lock, flags); \
++ return res; \
++}
++#endif
+ #define PCI_OP_WRITE(size,type,len) \
+ int pci_bus_write_config_##size \
+ (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
+diff -Nur linux-2.6.21.1/drivers/pci/access.c.orig linux-2.6.21.1-owrt/drivers/pci/access.c.orig
+--- linux-2.6.21.1/drivers/pci/access.c.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/drivers/pci/access.c.orig 2007-04-27 23:49:26.000000000 +0200
+@@ -0,0 +1,173 @@
++#include <linux/pci.h>
+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/moduleparam.h>
+#include <linux/sched.h>
-+#include <linux/ctype.h>
-+#include <linux/types.h>
-+#include <linux/fcntl.h>
-+#include <linux/interrupt.h>
-+#include <linux/ptrace.h>
-+#include <linux/init.h>
+#include <linux/ioport.h>
-+#include <linux/proc_fs.h>
-+#include <linux/in.h>
-+#include <linux/slab.h>
-+#include <linux/string.h>
-+#include <linux/delay.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/skbuff.h>
-+#include <linux/errno.h>
-+#include <asm/bootinfo.h>
-+#include <asm/system.h>
-+#include <asm/bitops.h>
-+#include <asm/pgtable.h>
-+#include <asm/segment.h>
-+#include <asm/io.h>
-+#include <asm/dma.h>
++#include <linux/wait.h>
+
-+#include "rc32434_eth.h"
++#include "pci.h"
+
-+#define DRIVER_VERSION "(mar2904)"
-+
-+#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
-+
-+
-+#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
-+ ((dev)->dev_addr[1]))
-+#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
-+ ((dev)->dev_addr[3] << 16) | \
-+ ((dev)->dev_addr[4] << 8) | \
-+ ((dev)->dev_addr[5]))
++/*
++ * This interrupt-safe spinlock protects all accesses to PCI
++ * configuration space.
++ */
+
-+#define MII_CLOCK 1250000 /* no more than 2.5MHz */
-+static char mac0[18] = "08:00:06:05:40:01";
++static DEFINE_SPINLOCK(pci_lock);
+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,17)
-+module_param_string(mac0, mac0, 18, 0);
-+#else
-+MODULE_PARM(mac0, "c18");
-+#endif
-+MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
-+
-+static struct rc32434_if_t {
-+ char *name;
-+ struct net_device *dev;
-+ char* mac_str;
-+ int weight;
-+ u32 iobase;
-+ u32 rxdmabase;
-+ u32 txdmabase;
-+ int rx_dma_irq;
-+ int tx_dma_irq;
-+ int rx_ovr_irq;
-+ int tx_und_irq;
-+} rc32434_iflist[] =
-+{
-+ {
-+ "rc32434_eth0", NULL, mac0,
-+ 64,
-+ ETH0_PhysicalAddress,
-+ ETH0_RX_DMA_ADDR,
-+ ETH0_TX_DMA_ADDR,
-+ ETH0_DMA_RX_IRQ,
-+ ETH0_DMA_TX_IRQ,
-+ ETH0_RX_OVR_IRQ,
-+ ETH0_TX_UND_IRQ
-+ }
-+};
++/*
++ * Wrappers for all PCI configuration access functions. They just check
++ * alignment, do locking and call the low-level functions pointed to
++ * by pci_dev->ops.
++ */
+
++#define PCI_byte_BAD 0
++#define PCI_word_BAD (pos & 1)
++#define PCI_dword_BAD (pos & 3)
++
++#define PCI_OP_READ(size,type,len) \
++int pci_bus_read_config_##size \
++ (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
++{ \
++ int res; \
++ unsigned long flags; \
++ u32 data = 0; \
++ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
++ spin_lock_irqsave(&pci_lock, flags); \
++ res = bus->ops->read(bus, devfn, pos, len, &data); \
++ *value = (type)data; \
++ spin_unlock_irqrestore(&pci_lock, flags); \
++ return res; \
++}
+
-+static int parse_mac_addr(struct net_device *dev, char* macstr)
-+{
-+ int i, j;
-+ unsigned char result, value;
-+
-+ for (i=0; i<6; i++) {
-+ result = 0;
-+ if (i != 5 && *(macstr+2) != ':') {
-+ ERR("invalid mac address format: %d %c\n",
-+ i, *(macstr+2));
-+ return -EINVAL;
-+ }
-+ for (j=0; j<2; j++) {
-+ if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
-+ toupper(*macstr)-'A'+10) < 16) {
-+ result = result*16 + value;
-+ macstr++;
-+ }
-+ else {
-+ ERR("invalid mac address "
-+ "character: %c\n", *macstr);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ macstr++;
-+ dev->dev_addr[i] = result;
-+ }
-+
-+ return 0;
++#define PCI_OP_WRITE(size,type,len) \
++int pci_bus_write_config_##size \
++ (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
++{ \
++ int res; \
++ unsigned long flags; \
++ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
++ spin_lock_irqsave(&pci_lock, flags); \
++ res = bus->ops->write(bus, devfn, pos, len, value); \
++ spin_unlock_irqrestore(&pci_lock, flags); \
++ return res; \
+}
+
++PCI_OP_READ(byte, u8, 1)
++PCI_OP_READ(word, u16, 2)
++PCI_OP_READ(dword, u32, 4)
++PCI_OP_WRITE(byte, u8, 1)
++PCI_OP_WRITE(word, u16, 2)
++PCI_OP_WRITE(dword, u32, 4)
+
++EXPORT_SYMBOL(pci_bus_read_config_byte);
++EXPORT_SYMBOL(pci_bus_read_config_word);
++EXPORT_SYMBOL(pci_bus_read_config_dword);
++EXPORT_SYMBOL(pci_bus_write_config_byte);
++EXPORT_SYMBOL(pci_bus_write_config_word);
++EXPORT_SYMBOL(pci_bus_write_config_dword);
+
-+static inline void rc32434_abort_tx(struct net_device *dev)
-+{
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+ rc32434_abort_dma(dev, lp->tx_dma_regs);
-+
-+}
++/*
++ * The following routines are to prevent the user from accessing PCI config
++ * space when it's unsafe to do so. Some devices require this during BIST and
++ * we're required to prevent it during D-state transitions.
++ *
++ * We have a bit per device to indicate it's blocked and a global wait queue
++ * for callers to sleep on until devices are unblocked.
++ */
++static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait);
+
-+static inline void rc32434_abort_rx(struct net_device *dev)
++static noinline void pci_wait_ucfg(struct pci_dev *dev)
+{
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+ rc32434_abort_dma(dev, lp->rx_dma_regs);
-+
-+}
++ DECLARE_WAITQUEUE(wait, current);
+
-+static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
-+{
-+ rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
++ __add_wait_queue(&pci_ucfg_wait, &wait);
++ do {
++ set_current_state(TASK_UNINTERRUPTIBLE);
++ spin_unlock_irq(&pci_lock);
++ schedule();
++ spin_lock_irq(&pci_lock);
++ } while (dev->block_ucfg_access);
++ __remove_wait_queue(&pci_ucfg_wait, &wait);
+}
+
-+static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
-+{
-+ rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
++#define PCI_USER_READ_CONFIG(size,type) \
++int pci_user_read_config_##size \
++ (struct pci_dev *dev, int pos, type *val) \
++{ \
++ int ret = 0; \
++ u32 data = -1; \
++ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
++ spin_lock_irq(&pci_lock); \
++ if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
++ ret = dev->bus->ops->read(dev->bus, dev->devfn, \
++ pos, sizeof(type), &data); \
++ spin_unlock_irq(&pci_lock); \
++ *val = (type)data; \
++ return ret; \
+}
+
-+static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
-+{
-+ rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
++#define PCI_USER_WRITE_CONFIG(size,type) \
++int pci_user_write_config_##size \
++ (struct pci_dev *dev, int pos, type val) \
++{ \
++ int ret = -EIO; \
++ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
++ spin_lock_irq(&pci_lock); \
++ if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
++ ret = dev->bus->ops->write(dev->bus, dev->devfn, \
++ pos, sizeof(type), val); \
++ spin_unlock_irq(&pci_lock); \
++ return ret; \
+}
+
-+static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
-+{
-+ rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
-+}
++PCI_USER_READ_CONFIG(byte, u8)
++PCI_USER_READ_CONFIG(word, u16)
++PCI_USER_READ_CONFIG(dword, u32)
++PCI_USER_WRITE_CONFIG(byte, u8)
++PCI_USER_WRITE_CONFIG(word, u16)
++PCI_USER_WRITE_CONFIG(dword, u32)
+
-+#ifdef RC32434_PROC_DEBUG
-+static int rc32434_read_proc(char *buf, char **start, off_t fpos,
-+ int length, int *eof, void *data)
++/**
++ * pci_block_user_cfg_access - Block userspace PCI config reads/writes
++ * @dev: pci device struct
++ *
++ * When user access is blocked, any reads or writes to config space will
++ * sleep until access is unblocked again. We don't allow nesting of
++ * block/unblock calls.
++ */
++void pci_block_user_cfg_access(struct pci_dev *dev)
+{
-+ struct net_device *dev = (struct net_device *)data;
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+ int len = 0;
-+
-+ /* print out header */
-+ len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
-+ len += sprintf (buf + len,
-+ "DMA halt count = %10d, DMA run count = %10d\n",
-+ lp->dma_halt_cnt, lp->dma_run_cnt);
-+
-+ if (fpos >= len) {
-+ *start = buf;
-+ *eof = 1;
-+ return 0;
-+ }
-+ *start = buf + fpos;
-+
-+ if ((len -= fpos) > length)
-+ return length;
-+ *eof = 1;
-+
-+ return len;
-+
-+}
-+#endif
++ unsigned long flags;
++ int was_blocked;
+
++ spin_lock_irqsave(&pci_lock, flags);
++ was_blocked = dev->block_ucfg_access;
++ dev->block_ucfg_access = 1;
++ spin_unlock_irqrestore(&pci_lock, flags);
+
-+/*
-+ * Restart the RC32434 ethernet controller.
-+ */
-+static int rc32434_restart(struct net_device *dev)
-+{
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+
-+ /*
-+ * Disable interrupts
-+ */
-+ disable_irq(lp->rx_irq);
-+ disable_irq(lp->tx_irq);
-+#ifdef RC32434_REVISION
-+ disable_irq(lp->ovr_irq);
-+#endif
-+ disable_irq(lp->und_irq);
-+
-+ /* Mask F E bit in Tx DMA */
-+ rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
-+ /* Mask D H E bit in Rx DMA */
-+ rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
-+
-+ rc32434_init(dev);
-+ rc32434_multicast_list(dev);
-+
-+ enable_irq(lp->und_irq);
-+#ifdef RC32434_REVISION
-+ enable_irq(lp->ovr_irq);
-+#endif
-+ enable_irq(lp->tx_irq);
-+ enable_irq(lp->rx_irq);
-+
-+ return 0;
++ /* If we BUG() inside the pci_lock, we're guaranteed to hose
++ * the machine */
++ BUG_ON(was_blocked);
+}
++EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
+
-+int rc32434_init_module(void)
++/**
++ * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
++ * @dev: pci device struct
++ *
++ * This function allows userspace PCI config accesses to resume.
++ */
++void pci_unblock_user_cfg_access(struct pci_dev *dev)
+{
-+#ifdef CONFIG_MACH_ARUBA
-+ if (mips_machtype != MACH_ARUBA_AP70)
-+ return 1;
-+#endif
++ unsigned long flags;
+
-+ printk(KERN_INFO DRIVER_NAME " \n");
-+ return rc32434_probe(0);
-+}
++ spin_lock_irqsave(&pci_lock, flags);
+
-+static int rc32434_probe(int port_num)
-+{
-+ struct rc32434_if_t *bif = &rc32434_iflist[port_num];
-+ struct rc32434_local *lp = NULL;
-+ struct net_device *dev = NULL;
-+ int i, retval,err;
-+
-+ dev = alloc_etherdev(sizeof(struct rc32434_local));
-+ if(!dev) {
-+ ERR("rc32434_eth: alloc_etherdev failed\n");
-+ return -1;
-+ }
-+
-+ SET_MODULE_OWNER(dev);
-+ bif->dev = dev;
++ /* This indicates a problem in the caller, but we don't need
++ * to kill them, unlike a double-block above. */
++ WARN_ON(!dev->block_ucfg_access);
+
-+#ifdef CONFIG_MACH_ARUBA
-+ {
-+ extern char * getenv(char *e);
-+ memcpy(bif->mac_str, getenv("ethaddr"), 17);
-+ }
++ dev->block_ucfg_access = 0;
++ wake_up_all(&pci_ucfg_wait);
++ spin_unlock_irqrestore(&pci_lock, flags);
++}
++EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);
+diff -Nur linux-2.6.21.1/drivers/serial/8250.c linux-2.6.21.1-owrt/drivers/serial/8250.c
+--- linux-2.6.21.1/drivers/serial/8250.c 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/drivers/serial/8250.c 2007-05-23 23:37:11.000000000 +0200
+@@ -1635,7 +1635,7 @@
+ {
+ struct uart_8250_port *up = (struct uart_8250_port *)port;
+ unsigned long flags;
+- unsigned char lsr, iir;
++// unsigned char lsr, iir;
+ int retval;
+
+ up->capabilities = uart_config[up->port.type].flags;
+@@ -1772,6 +1772,8 @@
+
+ serial8250_set_mctrl(&up->port, up->port.mctrl);
+
++// For some reason this test causes problems on the AP6x serial console
++#if 0
+ /*
+ * Do a quick test to see if we receive an
+ * interrupt when we enable the TX irq.
+@@ -1790,7 +1792,8 @@
+ } else {
+ up->bugs &= ~UART_BUG_TXEN;
+ }
+-
+#endif
+
-+ printk("mac: %s\n", bif->mac_str);
-+ if ((retval = parse_mac_addr(dev, bif->mac_str))) {
-+ ERR("MAC address parse failed\n");
-+ free_netdev(dev);
-+ return -1;
-+ }
-+
-+
-+ /* Initialize the device structure. */
-+ if (dev->priv == NULL) {
-+ lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
-+ memset(lp, 0, sizeof(struct rc32434_local));
-+ }
-+ else {
-+ lp = (struct rc32434_local *)dev->priv;
-+ }
-+
-+ lp->rx_irq = bif->rx_dma_irq;
-+ lp->tx_irq = bif->tx_dma_irq;
-+ lp->ovr_irq = bif->rx_ovr_irq;
-+ lp->und_irq = bif->tx_und_irq;
-+
-+ lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
-+
-+ if (!lp->eth_regs) {
-+ ERR("Can't remap eth registers\n");
-+ retval = -ENXIO;
-+ goto probe_err_out;
-+ }
-+
-+ lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
-+
-+ if (!lp->rx_dma_regs) {
-+ ERR("Can't remap Rx DMA registers\n");
-+ retval = -ENXIO;
-+ goto probe_err_out;
-+ }
-+ lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
-+
-+ if (!lp->tx_dma_regs) {
-+ ERR("Can't remap Tx DMA registers\n");
-+ retval = -ENXIO;
-+ goto probe_err_out;
-+ }
-+
-+#ifdef RC32434_PROC_DEBUG
-+ lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
-+ rc32434_read_proc, dev);
-+#endif
-+
-+ lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
-+ if (!lp->td_ring) {
-+ ERR("Can't allocate descriptors\n");
-+ retval = -ENOMEM;
-+ goto probe_err_out;
-+ }
-+
-+ dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
-+
-+ /* now convert TD_RING pointer to KSEG1 */
-+ lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
-+ lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
-+
-+
-+ spin_lock_init(&lp->lock);
-+
-+ dev->base_addr = bif->iobase;
-+ /* just use the rx dma irq */
-+ dev->irq = bif->rx_dma_irq;
-+
-+ dev->priv = lp;
-+
-+ dev->open = rc32434_open;
-+ dev->stop = rc32434_close;
-+ dev->hard_start_xmit = rc32434_send_packet;
-+ dev->get_stats = rc32434_get_stats;
-+ dev->set_multicast_list = &rc32434_multicast_list;
-+ dev->tx_timeout = rc32434_tx_timeout;
-+ dev->watchdog_timeo = RC32434_TX_TIMEOUT;
-+
-+#ifdef CONFIG_IDT_USE_NAPI
-+ dev->poll = rc32434_poll;
-+ dev->weight = bif->weight;
-+ printk("Using NAPI with weight %d\n",dev->weight);
-+#else
-+ lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
-+ tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
-+#endif
-+ lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
-+ tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
-+
-+ if ((err = register_netdev(dev))) {
-+ printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
-+ free_netdev(dev);
-+ retval = -EINVAL;
-+ goto probe_err_out;
-+ }
-+
-+ INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
-+ for (i = 0; i < 6; i++) {
-+ printk("%2.2x", dev->dev_addr[i]);
-+ if (i<5)
-+ printk(":");
-+ }
-+ printk("\n");
-+
-+ return 0;
-+
-+ probe_err_out:
-+ rc32434_cleanup_module();
-+ ERR(" failed. Returns %d\n", retval);
-+ return retval;
-+
-+}
-+
-+
-+static void rc32434_cleanup_module(void)
-+{
-+ int i;
-+
-+ for (i = 0; rc32434_iflist[i].iobase; i++) {
-+ struct rc32434_if_t * bif = &rc32434_iflist[i];
-+ if (bif->dev != NULL) {
-+ struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
-+ if (lp != NULL) {
-+ if (lp->eth_regs)
-+ iounmap((void*)lp->eth_regs);
-+ if (lp->rx_dma_regs)
-+ iounmap((void*)lp->rx_dma_regs);
-+ if (lp->tx_dma_regs)
-+ iounmap((void*)lp->tx_dma_regs);
-+ if (lp->td_ring)
-+ kfree((void*)KSEG0ADDR(lp->td_ring));
-+
-+#ifdef RC32434_PROC_DEBUG
-+ if (lp->ps) {
-+ remove_proc_entry(bif->name, proc_net);
-+ }
-+#endif
-+ kfree(lp);
-+ }
-+
-+ unregister_netdev(bif->dev);
-+ free_netdev(bif->dev);
-+ kfree(bif->dev);
-+ }
-+ }
-+}
-+
-+
-+
-+static int rc32434_open(struct net_device *dev)
-+{
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+
-+ /* Initialize */
-+ if (rc32434_init(dev)) {
-+ ERR("Error: cannot open the Ethernet device\n");
-+ return -EAGAIN;
-+ }
-+
-+ /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
-+ if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
-+ SA_SHIRQ | SA_INTERRUPT,
-+ "rc32434 ethernet Rx", dev)) {
-+ ERR(": unable to get Rx DMA IRQ %d\n",
-+ lp->rx_irq);
-+ return -EAGAIN;
-+ }
-+ if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
-+ SA_SHIRQ | SA_INTERRUPT,
-+ "rc32434 ethernet Tx", dev)) {
-+ ERR(": unable to get Tx DMA IRQ %d\n",
-+ lp->tx_irq);
-+ free_irq(lp->rx_irq, dev);
-+ return -EAGAIN;
-+ }
-+
-+#ifdef RC32434_REVISION
-+ /* Install handler for overrun error. */
-+ if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
-+ SA_SHIRQ | SA_INTERRUPT,
-+ "Ethernet Overflow", dev)) {
-+ ERR(": unable to get OVR IRQ %d\n",
-+ lp->ovr_irq);
-+ free_irq(lp->rx_irq, dev);
-+ free_irq(lp->tx_irq, dev);
-+ return -EAGAIN;
-+ }
-+#endif
-+
-+ /* Install handler for underflow error. */
-+ if (request_irq(lp->und_irq, &rc32434_und_interrupt,
-+ SA_SHIRQ | SA_INTERRUPT,
-+ "Ethernet Underflow", dev)) {
-+ ERR(": unable to get UND IRQ %d\n",
-+ lp->und_irq);
-+ free_irq(lp->rx_irq, dev);
-+ free_irq(lp->tx_irq, dev);
-+#ifdef RC32434_REVISION
-+ free_irq(lp->ovr_irq, dev);
-+#endif
-+ return -EAGAIN;
-+ }
-+
-+
-+ return 0;
-+}
-+
-+
-+
-+
-+static int rc32434_close(struct net_device *dev)
-+{
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+ u32 tmp;
-+
-+ /* Disable interrupts */
-+ disable_irq(lp->rx_irq);
-+ disable_irq(lp->tx_irq);
-+#ifdef RC32434_REVISION
-+ disable_irq(lp->ovr_irq);
-+#endif
-+ disable_irq(lp->und_irq);
-+
-+ tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
-+ tmp = tmp | DMASM_f_m | DMASM_e_m;
-+ rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
-+
-+ tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
-+ tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
-+ rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
-+
-+ free_irq(lp->rx_irq, dev);
-+ free_irq(lp->tx_irq, dev);
-+#ifdef RC32434_REVISION
-+ free_irq(lp->ovr_irq, dev);
-+#endif
-+ free_irq(lp->und_irq, dev);
-+ return 0;
-+}
-+
-+
-+/* transmit packet */
-+static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
-+{
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+ unsigned long flags;
-+ u32 length;
-+ DMAD_t td;
-+
-+
-+ spin_lock_irqsave(&lp->lock, flags);
-+
-+ td = &lp->td_ring[lp->tx_chain_tail];
-+
-+ /* stop queue when full, drop pkts if queue already full */
-+ if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
-+ lp->tx_full = 1;
-+
-+ if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
-+ netif_stop_queue(dev);
-+ }
-+ else {
-+ lp->stats.tx_dropped++;
-+ dev_kfree_skb_any(skb);
-+ spin_unlock_irqrestore(&lp->lock, flags);
-+ return 1;
-+ }
-+ }
-+
-+ lp->tx_count ++;
-+
-+ lp->tx_skb[lp->tx_chain_tail] = skb;
-+
-+ length = skb->len;
-+
-+ /* Setup the transmit descriptor. */
-+ td->ca = CPHYSADDR(skb->data);
-+
-+ if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
-+ if( lp->tx_chain_status == empty ) {
-+ td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
-+ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
-+ rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
-+ lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
-+ }
-+ else {
-+ td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
-+ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
-+ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
-+ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
-+ rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
-+ lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
-+ lp->tx_chain_status = empty;
-+ }
-+ }
-+ else {
-+ if( lp->tx_chain_status == empty ) {
-+ td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
-+ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
-+ lp->tx_chain_status = filled;
-+ }
-+ else {
-+ td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
-+ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
-+ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
-+ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
-+ }
-+ }
-+
-+ dev->trans_start = jiffies;
-+
-+ spin_unlock_irqrestore(&lp->lock, flags);
-+
-+ return 0;
-+}
-+
-+
-+/* Ethernet MII-PHY Handler */
-+static void rc32434_mii_handler(unsigned long data)
-+{
-+ struct net_device *dev = (struct net_device *)data;
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+ unsigned long flags;
-+ unsigned long duplex_status;
-+ int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
-+
-+ spin_lock_irqsave(&lp->lock, flags);
-+
-+ /* Two ports are using the same MII, the difference is the PHY address */
-+ rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
-+ rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
-+ rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
-+ rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
-+ while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
-+
-+ ERR("irq:%x port_addr:%x RDD:%x\n",
-+ lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
-+ duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
-+ if(duplex_status != lp->duplex_mode) {
-+ ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
-+ lp->duplex_mode = duplex_status;
-+ rc32434_restart(dev);
-+ }
-+
-+ lp->mii_phy_timer.expires = jiffies + 10 * HZ;
-+ add_timer(&lp->mii_phy_timer);
-+
-+ spin_unlock_irqrestore(&lp->lock, flags);
-+
-+}
-+
-+#ifdef RC32434_REVISION
-+/* Ethernet Rx Overflow interrupt */
-+static irqreturn_t
-+rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
-+{
-+ struct net_device *dev = (struct net_device *)dev_id;
-+ struct rc32434_local *lp;
-+ unsigned int ovr;
-+ irqreturn_t retval = IRQ_NONE;
-+
-+ ASSERT(dev != NULL);
-+
-+ lp = (struct rc32434_local *)dev->priv;
-+ spin_lock(&lp->lock);
-+ ovr = rc32434_readl(&lp->eth_regs->ethintfc);
-+
-+ if(ovr & ETHINTFC_ovr_m) {
-+ netif_stop_queue(dev);
-+
-+ /* clear OVR bit */
-+ rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
-+
-+ /* Restart interface */
-+ rc32434_restart(dev);
-+ retval = IRQ_HANDLED;
-+ }
-+ spin_unlock(&lp->lock);
-+
-+ return retval;
-+}
-+
-+#endif
-+
-+
-+/* Ethernet Tx Underflow interrupt */
-+static irqreturn_t
-+rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
-+{
-+ struct net_device *dev = (struct net_device *)dev_id;
-+ struct rc32434_local *lp;
-+ unsigned int und;
-+ irqreturn_t retval = IRQ_NONE;
-+
-+ ASSERT(dev != NULL);
-+
-+ lp = (struct rc32434_local *)dev->priv;
-+
-+ spin_lock(&lp->lock);
-+
-+ und = rc32434_readl(&lp->eth_regs->ethintfc);
-+
-+ if(und & ETHINTFC_und_m) {
-+ netif_stop_queue(dev);
-+
-+ rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
-+
-+ /* Restart interface */
-+ rc32434_restart(dev);
-+ retval = IRQ_HANDLED;
-+ }
-+
-+ spin_unlock(&lp->lock);
-+
-+ return retval;
-+}
-+
-+
-+/* Ethernet Rx DMA interrupt */
-+static irqreturn_t
-+rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
-+{
-+ struct net_device *dev = (struct net_device *)dev_id;
-+ struct rc32434_local* lp;
-+ volatile u32 dmas,dmasm;
-+ irqreturn_t retval;
-+
-+ ASSERT(dev != NULL);
-+
-+ lp = (struct rc32434_local *)dev->priv;
-+
-+ spin_lock(&lp->lock);
-+ dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
-+ if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
-+ /* Mask D H E bit in Rx DMA */
-+ dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
-+ rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
-+#ifdef CONFIG_IDT_USE_NAPI
-+ if(netif_rx_schedule_prep(dev))
-+ __netif_rx_schedule(dev);
-+#else
-+ tasklet_hi_schedule(lp->rx_tasklet);
-+#endif
-+
-+ if (dmas & DMAS_e_m)
-+ ERR(": DMA error\n");
-+
-+ retval = IRQ_HANDLED;
-+ }
-+ else
-+ retval = IRQ_NONE;
-+
-+ spin_unlock(&lp->lock);
-+ return retval;
-+}
-+
-+#ifdef CONFIG_IDT_USE_NAPI
-+static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
-+#else
-+static void rc32434_rx_tasklet(unsigned long rx_data_dev)
-+#endif
-+{
-+ struct net_device *dev = (struct net_device *)rx_data_dev;
-+ struct rc32434_local* lp = netdev_priv(dev);
-+ volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
-+ struct sk_buff *skb, *skb_new;
-+ u8* pkt_buf;
-+ u32 devcs, count, pkt_len, pktuncrc_len;
-+ volatile u32 dmas;
-+#ifdef CONFIG_IDT_USE_NAPI
-+ u32 received = 0;
-+ int rx_work_limit = min(*budget,dev->quota);
-+#else
-+ unsigned long flags;
-+ spin_lock_irqsave(&lp->lock, flags);
-+#endif
-+
-+ while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
-+#ifdef CONFIG_IDT_USE_NAPI
-+ if(--rx_work_limit <0)
-+ {
-+ break;
-+ }
-+#endif
-+ /* init the var. used for the later operations within the while loop */
-+ skb_new = NULL;
-+ devcs = rd->devcs;
-+ pkt_len = RCVPKT_LENGTH(devcs);
-+ skb = lp->rx_skb[lp->rx_next_done];
-+
-+ if (count < 64) {
-+ lp->stats.rx_errors++;
-+ lp->stats.rx_dropped++;
-+ }
-+ else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
-+ /* check that this is a whole packet */
-+ /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
-+ lp->stats.rx_errors++;
-+ lp->stats.rx_dropped++;
-+ }
-+ else if ( (devcs & ETHRX_rok_m) ) {
-+
-+ {
-+ /* must be the (first and) last descriptor then */
-+ pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
-+
-+ pktuncrc_len = pkt_len - 4;
-+ /* invalidate the cache */
-+ dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
-+
-+ /* Malloc up new buffer. */
-+ skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
-+
-+ if (skb_new != NULL){
-+ /* Make room */
-+ skb_put(skb, pktuncrc_len);
-+
-+ skb->protocol = eth_type_trans(skb, dev);
-+
-+ /* pass the packet to upper layers */
-+#ifdef CONFIG_IDT_USE_NAPI
-+ netif_receive_skb(skb);
-+#else
-+ netif_rx(skb);
-+#endif
-+
-+ dev->last_rx = jiffies;
-+ lp->stats.rx_packets++;
-+ lp->stats.rx_bytes += pktuncrc_len;
-+
-+ if (IS_RCV_MP(devcs))
-+ lp->stats.multicast++;
-+
-+ /* 16 bit align */
-+ skb_reserve(skb_new, 2);
-+
-+ skb_new->dev = dev;
-+ lp->rx_skb[lp->rx_next_done] = skb_new;
-+ }
-+ else {
-+ ERR("no memory, dropping rx packet.\n");
-+ lp->stats.rx_errors++;
-+ lp->stats.rx_dropped++;
-+ }
-+ }
-+
-+ }
-+ else {
-+ /* This should only happen if we enable accepting broken packets */
-+ lp->stats.rx_errors++;
-+ lp->stats.rx_dropped++;
-+
-+ /* add statistics counters */
-+ if (IS_RCV_CRC_ERR(devcs)) {
-+ DBG(2, "RX CRC error\n");
-+ lp->stats.rx_crc_errors++;
-+ }
-+ else if (IS_RCV_LOR_ERR(devcs)) {
-+ DBG(2, "RX LOR error\n");
-+ lp->stats.rx_length_errors++;
-+ }
-+ else if (IS_RCV_LE_ERR(devcs)) {
-+ DBG(2, "RX LE error\n");
-+ lp->stats.rx_length_errors++;
-+ }
-+ else if (IS_RCV_OVR_ERR(devcs)) {
-+ lp->stats.rx_over_errors++;
-+ }
-+ else if (IS_RCV_CV_ERR(devcs)) {
-+ /* code violation */
-+ DBG(2, "RX CV error\n");
-+ lp->stats.rx_frame_errors++;
-+ }
-+ else if (IS_RCV_CES_ERR(devcs)) {
-+ DBG(2, "RX Preamble error\n");
-+ }
-+ }
-+
-+ rd->devcs = 0;
-+
-+ /* restore descriptor's curr_addr */
-+ if(skb_new)
-+ rd->ca = CPHYSADDR(skb_new->data);
-+ else
-+ rd->ca = CPHYSADDR(skb->data);
-+
-+ rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
-+ lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
-+
-+ lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
-+ rd = &lp->rd_ring[lp->rx_next_done];
-+ rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
-+ }
-+#ifdef CONFIG_IDT_USE_NAPI
-+ dev->quota -= received;
-+ *budget =- received;
-+ if(rx_work_limit < 0)
-+ goto not_done;
-+#endif
-+
-+ dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
-+
-+ if(dmas & DMAS_h_m) {
-+ rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
-+#ifdef RC32434_PROC_DEBUG
-+ lp->dma_halt_cnt++;
-+#endif
-+ rd->devcs = 0;
-+ skb = lp->rx_skb[lp->rx_next_done];
-+ rd->ca = CPHYSADDR(skb->data);
-+ rc32434_chain_rx(lp,rd);
-+ }
-+
-+#ifdef CONFIG_IDT_USE_NAPI
-+ netif_rx_complete(dev);
-+#endif
-+ /* Enable D H E bit in Rx DMA */
-+ rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
-+#ifdef CONFIG_IDT_USE_NAPI
-+ return 0;
-+ not_done:
-+ return 1;
-+#else
-+ spin_unlock_irqrestore(&lp->lock, flags);
-+ return;
-+#endif
-+
-+
-+}
-+
-+
-+
-+/* Ethernet Tx DMA interrupt */
-+static irqreturn_t
-+rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
-+{
-+ struct net_device *dev = (struct net_device *)dev_id;
-+ struct rc32434_local *lp;
-+ volatile u32 dmas,dmasm;
-+ irqreturn_t retval;
-+
-+ ASSERT(dev != NULL);
-+
-+ lp = (struct rc32434_local *)dev->priv;
-+
-+ spin_lock(&lp->lock);
-+
-+ dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
-+
-+ if (dmas & (DMAS_f_m | DMAS_e_m)) {
-+ dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
-+ /* Mask F E bit in Tx DMA */
-+ rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
-+
-+ tasklet_hi_schedule(lp->tx_tasklet);
-+
-+ if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
-+ rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
-+ lp->tx_chain_status = empty;
-+ lp->tx_chain_head = lp->tx_chain_tail;
-+ dev->trans_start = jiffies;
-+ }
-+
-+ if (dmas & DMAS_e_m)
-+ ERR(": DMA error\n");
-+
-+ retval = IRQ_HANDLED;
-+ }
-+ else
-+ retval = IRQ_NONE;
-+
-+ spin_unlock(&lp->lock);
-+
-+ return retval;
-+}
-+
-+
-+static void rc32434_tx_tasklet(unsigned long tx_data_dev)
-+{
-+ struct net_device *dev = (struct net_device *)tx_data_dev;
-+ struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
-+ volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
-+ u32 devcs;
-+ unsigned long flags;
-+ volatile u32 dmas;
-+
-+ spin_lock_irqsave(&lp->lock, flags);
-+
-+ /* process all desc that are done */
-+ while(IS_DMA_FINISHED(td->control)) {
-+ if(lp->tx_full == 1) {
-+ netif_wake_queue(dev);
-+ lp->tx_full = 0;
-+ }
-+
-+ devcs = lp->td_ring[lp->tx_next_done].devcs;
-+ if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
-+ lp->stats.tx_errors++;
-+ lp->stats.tx_dropped++;
-+
-+ /* should never happen */
-+ DBG(1, __FUNCTION__ ": split tx ignored\n");
-+ }
-+ else if (IS_TX_TOK(devcs)) {
-+ lp->stats.tx_packets++;
-+ }
-+ else {
-+ lp->stats.tx_errors++;
-+ lp->stats.tx_dropped++;
-+
-+ /* underflow */
-+ if (IS_TX_UND_ERR(devcs))
-+ lp->stats.tx_fifo_errors++;
-+
-+ /* oversized frame */
-+ if (IS_TX_OF_ERR(devcs))
-+ lp->stats.tx_aborted_errors++;
-+
-+ /* excessive deferrals */
-+ if (IS_TX_ED_ERR(devcs))
-+ lp->stats.tx_carrier_errors++;
-+
-+ /* collisions: medium busy */
-+ if (IS_TX_EC_ERR(devcs))
-+ lp->stats.collisions++;
-+
-+ /* late collision */
-+ if (IS_TX_LC_ERR(devcs))
-+ lp->stats.tx_window_errors++;
-+
-+ }
-+
-+ /* We must always free the original skb */
-+ if (lp->tx_skb[lp->tx_next_done] != NULL) {
-+ dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
-+ lp->tx_skb[lp->tx_next_done] = NULL;
-+ }
-+
-+ lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
-+ lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
-+ lp->td_ring[lp->tx_next_done].link = 0;
-+ lp->td_ring[lp->tx_next_done].ca = 0;
-+ lp->tx_count --;
-+
-+ /* go on to next transmission */
-+ lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
-+ td = &lp->td_ring[lp->tx_next_done];
-+
-+ }
-+
-+ dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
-+ rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
-+
-+ /* Enable F E bit in Tx DMA */
-+ rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
-+ spin_unlock_irqrestore(&lp->lock, flags);
-+
-+}
-+
-+
-+static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
-+{
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+ return &lp->stats;
-+}
-+
-+
-+/*
-+ * Set or clear the multicast filter for this adaptor.
-+ */
-+static void rc32434_multicast_list(struct net_device *dev)
-+{
-+ /* listen to broadcasts always and to treat */
-+ /* IFF bits independantly */
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+ unsigned long flags;
-+ u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
-+
-+ if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
-+ recognise |= ETHARC_pro_m;
-+
-+ if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
-+ recognise |= ETHARC_am_m; /* all multicast & bcast */
-+ else if (dev->mc_count > 0) {
-+ DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
-+ recognise |= ETHARC_am_m; /* for the time being */
-+ }
-+
-+ spin_lock_irqsave(&lp->lock, flags);
-+ rc32434_writel(recognise, &lp->eth_regs->etharc);
-+ spin_unlock_irqrestore(&lp->lock, flags);
-+}
-+
-+
-+static void rc32434_tx_timeout(struct net_device *dev)
-+{
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&lp->lock, flags);
-+ rc32434_restart(dev);
-+ spin_unlock_irqrestore(&lp->lock, flags);
-+
-+}
-+
-+
+ spin_unlock_irqrestore(&up->port.lock, flags);
+
+ /*
+diff -Nur linux-2.6.21.1/drivers/serial/8250.c.orig linux-2.6.21.1-owrt/drivers/serial/8250.c.orig
+--- linux-2.6.21.1/drivers/serial/8250.c.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/drivers/serial/8250.c.orig 2007-04-27 23:49:26.000000000 +0200
+@@ -0,0 +1,2817 @@
+/*
-+ * Initialize the RC32434 ethernet controller.
-+ */
-+static int rc32434_init(struct net_device *dev)
-+{
-+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-+ int i, j;
-+
-+ /* Disable DMA */
-+ rc32434_abort_tx(dev);
-+ rc32434_abort_rx(dev);
-+
-+ /* reset ethernet logic */
-+ rc32434_writel(0, &lp->eth_regs->ethintfc);
-+ while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
-+ dev->trans_start = jiffies;
-+
-+ /* Enable Ethernet Interface */
-+ rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
-+
-+#ifndef CONFIG_IDT_USE_NAPI
-+ tasklet_disable(lp->rx_tasklet);
-+#endif
-+ tasklet_disable(lp->tx_tasklet);
-+
-+ /* Initialize the transmit Descriptors */
-+ for (i = 0; i < RC32434_NUM_TDS; i++) {
-+ lp->td_ring[i].control = DMAD_iof_m;
-+ lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
-+ lp->td_ring[i].ca = 0;
-+ lp->td_ring[i].link = 0;
-+ if (lp->tx_skb[i] != NULL) {
-+ dev_kfree_skb_any(lp->tx_skb[i]);
-+ lp->tx_skb[i] = NULL;
-+ }
-+ }
-+ lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
-+ lp-> tx_chain_status = empty;
-+
-+ /*
-+ * Initialize the receive descriptors so that they
-+ * become a circular linked list, ie. let the last
-+ * descriptor point to the first again.
-+ */
-+ for (i=0; i<RC32434_NUM_RDS; i++) {
-+ struct sk_buff *skb = lp->rx_skb[i];
-+
-+ if (lp->rx_skb[i] == NULL) {
-+ skb = dev_alloc_skb(RC32434_RBSIZE + 2);
-+ if (skb == NULL) {
-+ ERR("No memory in the system\n");
-+ for (j = 0; j < RC32434_NUM_RDS; j ++)
-+ if (lp->rx_skb[j] != NULL)
-+ dev_kfree_skb_any(lp->rx_skb[j]);
-+
-+ return 1;
-+ }
-+ else {
-+ skb->dev = dev;
-+ skb_reserve(skb, 2);
-+ lp->rx_skb[i] = skb;
-+ lp->rd_ring[i].ca = CPHYSADDR(skb->data);
-+
-+ }
-+ }
-+ lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
-+ lp->rd_ring[i].devcs = 0;
-+ lp->rd_ring[i].ca = CPHYSADDR(skb->data);
-+ lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
-+
-+ }
-+ /* loop back */
-+ lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
-+ lp->rx_next_done = 0;
-+
-+ lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
-+ lp->rx_chain_head = 0;
-+ lp->rx_chain_tail = 0;
-+ lp->rx_chain_status = empty;
-+
-+ rc32434_writel(0, &lp->rx_dma_regs->dmas);
-+ /* Start Rx DMA */
-+ rc32434_start_rx(lp, &lp->rd_ring[0]);
-+
-+ /* Enable F E bit in Tx DMA */
-+ rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
-+ /* Enable D H E bit in Rx DMA */
-+ rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
-+
-+ /* Accept only packets destined for this Ethernet device address */
-+ rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
-+
-+ /* Set all Ether station address registers to their initial values */
-+ rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
-+ rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
-+
-+ rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
-+ rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
-+
-+ rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
-+ rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
-+
-+ rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
-+ rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
-+
-+
-+ /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
-+ rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
-+ //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
-+
-+ /* Back to back inter-packet-gap */
-+ rc32434_writel(0x15, &lp->eth_regs->ethipgt);
-+ /* Non - Back to back inter-packet-gap */
-+ rc32434_writel(0x12, &lp->eth_regs->ethipgr);
-+
-+ /* Management Clock Prescaler Divisor */
-+ /* Clock independent setting */
-+ rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
-+ &lp->eth_regs->ethmcp);
-+
-+ /* don't transmit until fifo contains 48b */
-+ rc32434_writel(48, &lp->eth_regs->ethfifott);
-+
-+ rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
-+
-+#ifndef CONFIG_IDT_USE_NAPI
-+ tasklet_enable(lp->rx_tasklet);
-+#endif
-+ tasklet_enable(lp->tx_tasklet);
-+
-+ netif_start_queue(dev);
-+
-+
-+ return 0;
-+
-+}
-+
-+
-+#ifndef MODULE
-+
-+static int __init rc32434_setup(char *options)
-+{
-+ /* no options yet */
-+ return 1;
-+}
-+
-+static int __init rc32434_setup_ethaddr0(char *options)
-+{
-+ memcpy(mac0, options, 17);
-+ mac0[17]= '\0';
-+ return 1;
-+}
-+
-+__setup("rc32434eth=", rc32434_setup);
-+__setup("ethaddr0=", rc32434_setup_ethaddr0);
-+
-+
-+#endif /* MODULE */
-+
-+module_init(rc32434_init_module);
-+module_exit(rc32434_cleanup_module);
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-diff -Nur linux-2.6.17/drivers/net/rc32434_eth.h linux-2.6.17-owrt/drivers/net/rc32434_eth.h
---- linux-2.6.17/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/drivers/net/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,187 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for IDT RC32434 on-chip ethernet controller.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * linux/drivers/char/8250.c
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ * Driver for 8250/16550-type serial ports
+ *
++ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb
++ * Copyright (C) 2001 Russell King.
+ *
-+ * Initial Release
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
+ *
-+ * Aug 2004
++ * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
+ *
-+ * Added NAPI
++ * A note about mapbase / membase
+ *
-+ **************************************************************************
++ * mapbase is the physical address of the IO port.
++ * membase is an 'ioremapped' cookie.
+ */
+
++#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
++#define SUPPORT_SYSRQ
++#endif
+
-+#include <asm/idt-boards/rc32434/rc32434.h>
-+#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
-+#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
-+
-+#define RC32434_DEBUG 2
-+//#define RC32434_PROC_DEBUG
-+#undef RC32434_DEBUG
-+
-+#ifdef RC32434_DEBUG
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/ioport.h>
++#include <linux/init.h>
++#include <linux/console.h>
++#include <linux/sysrq.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/tty.h>
++#include <linux/tty_flip.h>
++#include <linux/serial_reg.h>
++#include <linux/serial_core.h>
++#include <linux/serial.h>
++#include <linux/serial_8250.h>
++#include <linux/nmi.h>
++#include <linux/mutex.h>
+
-+/* use 0 for production, 1 for verification, >2 for debug */
-+static int rc32434_debug = RC32434_DEBUG;
-+#define ASSERT(expr) \
-+ if(!(expr)) { \
-+ printk( "Assertion failed! %s,%s,%s,line=%d\n", \
-+ #expr,__FILE__,__FUNCTION__,__LINE__); }
-+#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
-+#else
-+#define ASSERT(expr) do {} while (0)
-+#define DBG(lvl, format, arg...) do {} while (0)
-+#endif
++#include <asm/io.h>
++#include <asm/irq.h>
+
-+#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
-+#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
-+#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
++#include "8250.h"
+
-+#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
-+#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
-+#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
-+#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
++/*
++ * Configuration:
++ * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
++ * is unsafe when used on edge-triggered interrupts.
++ */
++static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
+
-+#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
-+#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
++static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
+
-+/* the following must be powers of two */
-+#ifdef CONFIG_IDT_USE_NAPI
-+#define RC32434_NUM_RDS 64 /* number of receive descriptors */
-+#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
++/*
++ * Debugging.
++ */
++#if 0
++#define DEBUG_AUTOCONF(fmt...) printk(fmt)
+#else
-+#define RC32434_NUM_RDS 128 /* number of receive descriptors */
-+#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
++#define DEBUG_AUTOCONF(fmt...) do { } while (0)
+#endif
+
-+#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
-+#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
-+#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
-+#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
-+#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
-+
-+#define RC32434_TX_TIMEOUT HZ * 100
-+
-+#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
-+#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
-+
-+enum status { filled, empty};
-+#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
-+#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
++#if 0
++#define DEBUG_INTR(fmt...) printk(fmt)
++#else
++#define DEBUG_INTR(fmt...) do { } while (0)
++#endif
+
++#define PASS_LIMIT 256
+
-+/* Information that need to be kept for each board. */
-+struct rc32434_local {
-+ ETH_t eth_regs;
-+ DMA_Chan_t rx_dma_regs;
-+ DMA_Chan_t tx_dma_regs;
-+ volatile DMAD_t td_ring; /* transmit descriptor ring */
-+ volatile DMAD_t rd_ring; /* receive descriptor ring */
-+
-+ struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
-+ struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
-+
-+#ifndef CONFIG_IDT_USE_NAPI
-+ struct tasklet_struct * rx_tasklet;
-+#endif
-+ struct tasklet_struct * tx_tasklet;
-+
-+ int rx_next_done;
-+ int rx_chain_head;
-+ int rx_chain_tail;
-+ enum status rx_chain_status;
-+
-+ int tx_next_done;
-+ int tx_chain_head;
-+ int tx_chain_tail;
-+ enum status tx_chain_status;
-+ int tx_count;
-+ int tx_full;
-+
-+ struct timer_list mii_phy_timer;
-+ unsigned long duplex_mode;
-+
-+ int rx_irq;
-+ int tx_irq;
-+ int ovr_irq;
-+ int und_irq;
-+
-+ struct net_device_stats stats;
-+ spinlock_t lock;
-+
-+ /* debug /proc entry */
-+ struct proc_dir_entry *ps;
-+ int dma_halt_cnt; int dma_run_cnt;
-+};
++/*
++ * We default to IRQ0 for the "no irq" hack. Some
++ * machine types want others as well - they're free
++ * to redefine this in their header file.
++ */
++#define is_real_interrupt(irq) ((irq) != 0)
+
-+extern unsigned int idt_cpu_freq;
-+
-+/* Index to functions, as function prototypes. */
-+static int rc32434_open(struct net_device *dev);
-+static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
-+static void rc32434_mii_handler(unsigned long data);
-+static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
-+static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
-+static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
-+#ifdef RC32434_REVISION
-+static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
++#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
++#define CONFIG_SERIAL_DETECT_IRQ 1
+#endif
-+static int rc32434_close(struct net_device *dev);
-+static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
-+static void rc32434_multicast_list(struct net_device *dev);
-+static int rc32434_init(struct net_device *dev);
-+static void rc32434_tx_timeout(struct net_device *dev);
-+
-+static void rc32434_tx_tasklet(unsigned long tx_data_dev);
-+#ifdef CONFIG_IDT_USE_NAPI
-+static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
-+#else
-+static void rc32434_rx_tasklet(unsigned long rx_data_dev);
++#ifdef CONFIG_SERIAL_8250_MANY_PORTS
++#define CONFIG_SERIAL_MANY_PORTS 1
+#endif
-+static void rc32434_cleanup_module(void);
-+static int rc32434_probe(int port_num);
-+int rc32434_init_module(void);
+
++/*
++ * HUB6 is always on. This will be removed once the header
++ * files have been cleaned.
++ */
++#define CONFIG_HUB6 1
+
-+static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
-+{
-+ if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
-+ rc32434_writel(0x10, &ch->dmac);
-+
-+ while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
-+ dev->trans_start = jiffies;
-+
-+ rc32434_writel(0, &ch->dmas);
-+ }
-+
-+ rc32434_writel(0, &ch->dmadptr);
-+ rc32434_writel(0, &ch->dmandptr);
-+}
-diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
---- linux-2.6.17/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h 2006-06-18 12:44:28.000000000 +0200
-@@ -218,6 +218,17 @@
- #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
- #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
-
++#include <asm/serial.h>
+
+/*
-+ * Valid machtype for group ARUBA
++ * SERIAL_PORT_DFNS tells us about built-in ports that have no
++ * standard enumeration mechanism. Platforms that can find all
++ * serial ports via mechanisms like ACPI or PCI need not supply it.
+ */
-+#define MACH_GROUP_ARUBA 23
-+#define MACH_ARUBA_UNKNOWN 0
-+#define MACH_ARUBA_AP60 1
-+#define MACH_ARUBA_AP65 2
-+#define MACH_ARUBA_AP70 3
-+#define MACH_ARUBA_AP40 4
++#ifndef SERIAL_PORT_DFNS
++#define SERIAL_PORT_DFNS
++#endif
+
- #define CL_SIZE COMMAND_LINE_SIZE
-
- const char *get_system_type(void);
-diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
---- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/include/asm-mips/cpu.h 2006-06-18 12:45:56.000000000 +0200
-@@ -54,6 +54,9 @@
- #define PRID_IMP_R14000 0x0f00
- #define PRID_IMP_R8000 0x1000
- #define PRID_IMP_PR4450 0x1200
-+#define PRID_IMP_RC32334 0x1800
-+#define PRID_IMP_RC32355 0x1900
-+#define PRID_IMP_RC32365 0x1900
- #define PRID_IMP_R4600 0x2000
- #define PRID_IMP_R4700 0x2100
- #define PRID_IMP_TX39 0x2200
-@@ -200,7 +203,8 @@
- #define CPU_SB1A 62
- #define CPU_74K 63
- #define CPU_R14000 64
--#define CPU_LAST 64
-+#define CPU_RC32300 65
-+#define CPU_LAST 65
-
- /*
- * ISA Level encodings
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,142 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * RC32300 helper routines
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
++static const struct old_serial_port old_serial_port[] = {
++ SERIAL_PORT_DFNS /* defined in asm/serial.h */
++};
++
++#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
++
++#ifdef CONFIG_SERIAL_8250_RSA
++
++#define PORT_RSA_MAX 4
++static unsigned long probe_rsa[PORT_RSA_MAX];
++static unsigned int probe_rsa_count;
++#endif /* CONFIG_SERIAL_8250_RSA */
++
++struct uart_8250_port {
++ struct uart_port port;
++ struct timer_list timer; /* "no irq" timer */
++ struct list_head list; /* ports on this IRQ */
++ unsigned short capabilities; /* port capabilities */
++ unsigned short bugs; /* port bugs */
++ unsigned int tx_loadsz; /* transmit fifo load size */
++ unsigned char acr;
++ unsigned char ier;
++ unsigned char lcr;
++ unsigned char mcr;
++ unsigned char mcr_mask; /* mask of user bits */
++ unsigned char mcr_force; /* mask of forced bits */
++ unsigned char lsr_break_flag;
++
++ /*
++ * We provide a per-port pm hook.
++ */
++ void (*pm)(struct uart_port *port,
++ unsigned int state, unsigned int old);
++};
++
++struct irq_info {
++ spinlock_t lock;
++ struct list_head *head;
++};
++
++static struct irq_info irq_lists[NR_IRQS];
++
++/*
++ * Here we define the default xmit fifo size used for each type of UART.
+ */
++static const struct serial8250_config uart_config[] = {
++ [PORT_UNKNOWN] = {
++ .name = "unknown",
++ .fifo_size = 1,
++ .tx_loadsz = 1,
++ },
++ [PORT_8250] = {
++ .name = "8250",
++ .fifo_size = 1,
++ .tx_loadsz = 1,
++ },
++ [PORT_16450] = {
++ .name = "16450",
++ .fifo_size = 1,
++ .tx_loadsz = 1,
++ },
++ [PORT_16550] = {
++ .name = "16550",
++ .fifo_size = 1,
++ .tx_loadsz = 1,
++ },
++ [PORT_16550A] = {
++ .name = "16550A",
++ .fifo_size = 16,
++ .tx_loadsz = 16,
++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
++ .flags = UART_CAP_FIFO,
++ },
++ [PORT_CIRRUS] = {
++ .name = "Cirrus",
++ .fifo_size = 1,
++ .tx_loadsz = 1,
++ },
++ [PORT_16650] = {
++ .name = "ST16650",
++ .fifo_size = 1,
++ .tx_loadsz = 1,
++ .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
++ },
++ [PORT_16650V2] = {
++ .name = "ST16650V2",
++ .fifo_size = 32,
++ .tx_loadsz = 16,
++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
++ UART_FCR_T_TRIG_00,
++ .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
++ },
++ [PORT_16750] = {
++ .name = "TI16750",
++ .fifo_size = 64,
++ .tx_loadsz = 64,
++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
++ UART_FCR7_64BYTE,
++ .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
++ },
++ [PORT_STARTECH] = {
++ .name = "Startech",
++ .fifo_size = 1,
++ .tx_loadsz = 1,
++ },
++ [PORT_16C950] = {
++ .name = "16C950/954",
++ .fifo_size = 128,
++ .tx_loadsz = 128,
++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
++ .flags = UART_CAP_FIFO,
++ },
++ [PORT_16654] = {
++ .name = "ST16654",
++ .fifo_size = 64,
++ .tx_loadsz = 32,
++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
++ UART_FCR_T_TRIG_10,
++ .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
++ },
++ [PORT_16850] = {
++ .name = "XR16850",
++ .fifo_size = 128,
++ .tx_loadsz = 128,
++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
++ .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
++ },
++ [PORT_RSA] = {
++ .name = "RSA",
++ .fifo_size = 2048,
++ .tx_loadsz = 2048,
++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
++ .flags = UART_CAP_FIFO,
++ },
++ [PORT_NS16550A] = {
++ .name = "NS16550A",
++ .fifo_size = 16,
++ .tx_loadsz = 16,
++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
++ .flags = UART_CAP_FIFO | UART_NATSEMI,
++ },
++ [PORT_XSCALE] = {
++ .name = "XScale",
++ .fifo_size = 32,
++ .tx_loadsz = 32,
++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
++ .flags = UART_CAP_FIFO | UART_CAP_UUE,
++ },
++};
+
-+#ifndef __IDT_RC32300_H__
-+#define __IDT_RC32300_H__
++#ifdef CONFIG_SERIAL_8250_AU1X00
++
++/* Au1x00 UART hardware has a weird register layout */
++static const u8 au_io_in_map[] = {
++ [UART_RX] = 0,
++ [UART_IER] = 2,
++ [UART_IIR] = 3,
++ [UART_LCR] = 5,
++ [UART_MCR] = 6,
++ [UART_LSR] = 7,
++ [UART_MSR] = 8,
++};
+
-+#include <linux/delay.h>
-+#include <asm/io.h>
++static const u8 au_io_out_map[] = {
++ [UART_TX] = 1,
++ [UART_IER] = 2,
++ [UART_FCR] = 4,
++ [UART_LCR] = 5,
++ [UART_MCR] = 6,
++};
++
++/* sane hardware needs no mapping */
++static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
++{
++ if (up->port.iotype != UPIO_AU)
++ return offset;
++ return au_io_in_map[offset];
++}
++
++static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
++{
++ if (up->port.iotype != UPIO_AU)
++ return offset;
++ return au_io_out_map[offset];
++}
++
++#else
++
++/* sane hardware needs no mapping */
++#define map_8250_in_reg(up, offset) (offset)
++#define map_8250_out_reg(up, offset) (offset)
+
++#endif
+
-+/* cpu pipeline flush */
-+static inline void rc32300_sync(void)
++static unsigned int serial_in(struct uart_8250_port *up, int offset)
+{
-+ __asm__ volatile ("sync");
++ unsigned int tmp;
++ offset = map_8250_in_reg(up, offset) << up->port.regshift;
++
++ switch (up->port.iotype) {
++ case UPIO_HUB6:
++ outb(up->port.hub6 - 1 + offset, up->port.iobase);
++ return inb(up->port.iobase + 1);
++
++ case UPIO_MEM:
++ return readb(up->port.membase + offset);
++
++ case UPIO_MEM32:
++ return readl(up->port.membase + offset);
++
++#ifdef CONFIG_SERIAL_8250_AU1X00
++ case UPIO_AU:
++ return __raw_readl(up->port.membase + offset);
++#endif
++
++ case UPIO_TSI:
++ if (offset == UART_IIR) {
++ tmp = readl(up->port.membase + (UART_IIR & ~3));
++ return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
++ } else
++ return readb(up->port.membase + offset);
++
++ default:
++ return inb(up->port.iobase + offset);
++ }
+}
+
-+static inline void rc32300_sync_udelay(int us)
++static void
++serial_out(struct uart_8250_port *up, int offset, int value)
+{
-+ __asm__ volatile ("sync");
-+ udelay(us);
++ offset = map_8250_out_reg(up, offset) << up->port.regshift;
++
++ switch (up->port.iotype) {
++ case UPIO_HUB6:
++ outb(up->port.hub6 - 1 + offset, up->port.iobase);
++ outb(value, up->port.iobase + 1);
++ break;
++
++ case UPIO_MEM:
++ writeb(value, up->port.membase + offset);
++ break;
++
++ case UPIO_MEM32:
++ writel(value, up->port.membase + offset);
++ break;
++
++#ifdef CONFIG_SERIAL_8250_AU1X00
++ case UPIO_AU:
++ __raw_writel(value, up->port.membase + offset);
++ break;
++#endif
++ case UPIO_TSI:
++ if (!((offset == UART_IER) && (value & UART_IER_UUE)))
++ writeb(value, up->port.membase + offset);
++ break;
++
++ default:
++ outb(value, up->port.iobase + offset);
++ }
+}
+
-+static inline void rc32300_sync_delay(int ms)
++static void
++serial_out_sync(struct uart_8250_port *up, int offset, int value)
+{
-+ __asm__ volatile ("sync");
-+ mdelay(ms);
++ switch (up->port.iotype) {
++ case UPIO_MEM:
++ case UPIO_MEM32:
++#ifdef CONFIG_SERIAL_8250_AU1X00
++ case UPIO_AU:
++#endif
++ serial_out(up, offset, value);
++ serial_in(up, UART_LCR); /* safe, no side-effects */
++ break;
++ default:
++ serial_out(up, offset, value);
++ }
+}
+
+/*
-+ * Macros to access internal RC32300 registers. No byte
-+ * swapping should be done when accessing the internal
-+ * registers.
++ * We used to support using pause I/O for certain machines. We
++ * haven't supported this for a while, but just in case it's badly
++ * needed for certain old 386 machines, I've left these #define's
++ * in....
+ */
++#define serial_inp(up, offset) serial_in(up, offset)
++#define serial_outp(up, offset, value) serial_out(up, offset, value)
+
-+static inline u8 rc32300_readb(unsigned long pa)
++/* Uart divisor latch read */
++static inline int _serial_dl_read(struct uart_8250_port *up)
+{
-+ return *((volatile u8 *)KSEG1ADDR(pa));
++ return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
+}
-+static inline u16 rc32300_readw(unsigned long pa)
++
++/* Uart divisor latch write */
++static inline void _serial_dl_write(struct uart_8250_port *up, int value)
+{
-+ return *((volatile u16 *)KSEG1ADDR(pa));
++ serial_outp(up, UART_DLL, value & 0xff);
++ serial_outp(up, UART_DLM, value >> 8 & 0xff);
+}
-+static inline u32 rc32300_readl(unsigned long pa)
++
++#ifdef CONFIG_SERIAL_8250_AU1X00
++/* Au1x00 haven't got a standard divisor latch */
++static int serial_dl_read(struct uart_8250_port *up)
+{
-+ return *((volatile u32 *)KSEG1ADDR(pa));
++ if (up->port.iotype == UPIO_AU)
++ return __raw_readl(up->port.membase + 0x28);
++ else
++ return _serial_dl_read(up);
+}
-+static inline void rc32300_writeb(u8 val, unsigned long pa)
++
++static void serial_dl_write(struct uart_8250_port *up, int value)
+{
-+ *((volatile u8 *)KSEG1ADDR(pa)) = val;
++ if (up->port.iotype == UPIO_AU)
++ __raw_writel(value, up->port.membase + 0x28);
++ else
++ _serial_dl_write(up, value);
+}
-+static inline void rc32300_writew(u16 val, unsigned long pa)
++#else
++#define serial_dl_read(up) _serial_dl_read(up)
++#define serial_dl_write(up, value) _serial_dl_write(up, value)
++#endif
++
++/*
++ * For the 16C950
++ */
++static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
+{
-+ *((volatile u16 *)KSEG1ADDR(pa)) = val;
++ serial_out(up, UART_SCR, offset);
++ serial_out(up, UART_ICR, value);
+}
-+static inline void rc32300_writel(u32 val, unsigned long pa)
++
++static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
+{
-+ *((volatile u32 *)KSEG1ADDR(pa)) = val;
-+}
++ unsigned int value;
+
++ serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
++ serial_out(up, UART_SCR, offset);
++ value = serial_in(up, UART_ICR);
++ serial_icr_write(up, UART_ACR, up->acr);
+
-+#define local_readb __raw_readb
-+#define local_readw __raw_readw
-+#define local_readl __raw_readl
++ return value;
++}
+
-+#define local_writeb __raw_writeb
-+#define local_writew __raw_writew
-+#define local_writel __raw_writel
++/*
++ * FIFO support.
++ */
++static inline void serial8250_clear_fifos(struct uart_8250_port *p)
++{
++ if (p->capabilities & UART_CAP_FIFO) {
++ serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
++ serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
++ UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
++ serial_outp(p, UART_FCR, 0);
++ }
++}
+
++/*
++ * IER sleep support. UARTs which have EFRs need the "extended
++ * capability" bit enabled. Note that on XR16C850s, we need to
++ * reset LCR to write to IER.
++ */
++static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
++{
++ if (p->capabilities & UART_CAP_SLEEP) {
++ if (p->capabilities & UART_CAP_EFR) {
++ serial_outp(p, UART_LCR, 0xBF);
++ serial_outp(p, UART_EFR, UART_EFR_ECB);
++ serial_outp(p, UART_LCR, 0);
++ }
++ serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
++ if (p->capabilities & UART_CAP_EFR) {
++ serial_outp(p, UART_LCR, 0xBF);
++ serial_outp(p, UART_EFR, 0);
++ serial_outp(p, UART_LCR, 0);
++ }
++ }
++}
+
++#ifdef CONFIG_SERIAL_8250_RSA
+/*
-+ * C access to CLZ and CLO instructions
-+ * (count leading zeroes/ones).
++ * Attempts to turn on the RSA FIFO. Returns zero on failure.
++ * We set the port uart clock rate if we succeed.
+ */
-+static inline int rc32300_clz(unsigned long val)
++static int __enable_rsa(struct uart_8250_port *up)
+{
-+ int ret;
-+ __asm__ volatile (
-+ ".set\tnoreorder\n\t"
-+ ".set\tnoat\n\t"
-+ ".set\tmips32\n\t"
-+ "clz\t%0,%1\n\t"
-+ ".set\tmips0\n\t"
-+ ".set\tat\n\t"
-+ ".set\treorder"
-+ : "=r" (ret)
-+ : "r" (val));
-+
-+ return ret;
++ unsigned char mode;
++ int result;
++
++ mode = serial_inp(up, UART_RSA_MSR);
++ result = mode & UART_RSA_MSR_FIFO;
++
++ if (!result) {
++ serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
++ mode = serial_inp(up, UART_RSA_MSR);
++ result = mode & UART_RSA_MSR_FIFO;
++ }
++
++ if (result)
++ up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
++
++ return result;
+}
-+static inline int rc32300_clo(unsigned long val)
++
++static void enable_rsa(struct uart_8250_port *up)
+{
-+ int ret;
-+ __asm__ volatile (
-+ ".set\tnoreorder\n\t"
-+ ".set\tnoat\n\t"
-+ ".set\tmips32\n\t"
-+ "clo\t%0,%1\n\t"
-+ ".set\tmips0\n\t"
-+ ".set\tat\n\t"
-+ ".set\treorder"
-+ : "=r" (ret)
-+ : "r" (val));
-+
-+ return ret;
++ if (up->port.type == PORT_RSA) {
++ if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
++ spin_lock_irq(&up->port.lock);
++ __enable_rsa(up);
++ spin_unlock_irq(&up->port.lock);
++ }
++ if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
++ serial_outp(up, UART_RSA_FRR, 0);
++ }
+}
+
-+#endif // __IDT_RC32300_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,207 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for IDT RC32334 CPU.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
++/*
++ * Attempts to turn off the RSA FIFO. Returns zero on failure.
++ * It is unknown why interrupts were disabled in here. However,
++ * the caller is expected to preserve this behaviour by grabbing
++ * the spinlock before calling this function.
+ */
++static void disable_rsa(struct uart_8250_port *up)
++{
++ unsigned char mode;
++ int result;
+
++ if (up->port.type == PORT_RSA &&
++ up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
++ spin_lock_irq(&up->port.lock);
+
-+#ifndef __IDT_RC32334_H__
-+#define __IDT_RC32334_H__
++ mode = serial_inp(up, UART_RSA_MSR);
++ result = !(mode & UART_RSA_MSR_FIFO);
+
-+#include <linux/delay.h>
-+#include <asm/io.h>
++ if (!result) {
++ serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
++ mode = serial_inp(up, UART_RSA_MSR);
++ result = !(mode & UART_RSA_MSR_FIFO);
++ }
+
-+/* Base address of internal registers */
-+#define RC32334_REG_BASE 0x18000000
-+
-+/* CPU and IP Bus Control */
-+#define CPU_PORT_WIDTH 0xffffe200 // virtual!
-+#define CPU_BTA 0xffffe204 // virtual!
-+#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
-+#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
-+#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
-+#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
-+#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
-+#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
-+#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
-+
-+/* Memory Controller */
-+#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
-+#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
-+#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
-+#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
-+#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
-+#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
-+#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
-+#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
-+#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
-+#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
-+
-+/* PCI Controller */
-+#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
-+#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
-+#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
-+#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
-+#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
-+#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
-+#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
-+#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
-+#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
-+#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
-+#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
-+#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
-+#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
-+#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
-+#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
-+#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
-+#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
-+#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
-+
-+/* Timers */
-+#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
-+#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
-+#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
-+#define TIMER_REG_OFFSET 0x10
-+
-+/* Programmable I/O */
-+#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
-+#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
++ if (result)
++ up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
++ spin_unlock_irq(&up->port.lock);
++ }
++}
++#endif /* CONFIG_SERIAL_8250_RSA */
+
+/*
-+ * DMA
-+ *
-+ * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
-+ *
-+ * DMA0: 18001400
-+ * DMA1: 18001440
-+ * DMA2: 18001900
-+ * DMA3: 18001940
-+ * NB: dma number must be immediate value or variable.
-+ * It MUST NOT be a function since it would get called twice!
++ * This is a quickie test to see how big the FIFO is.
++ * It doesn't work at all the time, more's the pity.
+ */
-+#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
-+
-+#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
-+#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
-+#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
-+
-+#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
-+#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
-+#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
-+#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
-+#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
-+
-+#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
-+
-+/* Expansion Interrupt Controller */
-+#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
-+#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
-+#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
-+#define IC_GROUP_OFFSET 0x10
-+
-+#define NUM_INTR_GROUPS 15
++static int size_fifo(struct uart_8250_port *up)
++{
++ unsigned char old_fcr, old_mcr, old_lcr;
++ unsigned short old_dl;
++ int count;
++
++ old_lcr = serial_inp(up, UART_LCR);
++ serial_outp(up, UART_LCR, 0);
++ old_fcr = serial_inp(up, UART_FCR);
++ old_mcr = serial_inp(up, UART_MCR);
++ serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
++ UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
++ serial_outp(up, UART_MCR, UART_MCR_LOOP);
++ serial_outp(up, UART_LCR, UART_LCR_DLAB);
++ old_dl = serial_dl_read(up);
++ serial_dl_write(up, 0x0001);
++ serial_outp(up, UART_LCR, 0x03);
++ for (count = 0; count < 256; count++)
++ serial_outp(up, UART_TX, count);
++ mdelay(20);/* FIXME - schedule_timeout */
++ for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
++ (count < 256); count++)
++ serial_inp(up, UART_RX);
++ serial_outp(up, UART_FCR, old_fcr);
++ serial_outp(up, UART_MCR, old_mcr);
++ serial_outp(up, UART_LCR, UART_LCR_DLAB);
++ serial_dl_write(up, old_dl);
++ serial_outp(up, UART_LCR, old_lcr);
++
++ return count;
++}
++
+/*
-+ * The IRQ mapping is as follows:
-+ *
-+ * IRQ Mapped To
-+ * --- -------------------
-+ * 0 SW0 (IP0) SW0 intr
-+ * 1 SW1 (IP1) SW1 intr
-+ * 2 Int0 (IP2) board-specific
-+ * 3 Int1 (IP3) board-specific
-+ * 4 Int2 (IP4) board-specific
-+ * - Int3 (IP5) not used, mapped to IRQ's 8 and up
-+ * 6 Int4 (IP6) board-specific
-+ * 7 Int5 (IP7) CP0 Timer
-+ *
-+ * IRQ's 8 and up are all mapped to Int3 (IP5), which
-+ * internally on the RC32334 is routed to the Expansion
-+ * Interrupt Controller.
++ * Read UART ID using the divisor method - set DLL and DLM to zero
++ * and the revision will be in DLL and device type in DLM. We
++ * preserve the device state across this.
+ */
-+#define MIPS_CPU_TIMER_IRQ 7
-+
-+#define GROUP1_IRQ_BASE 8 // bus error
-+#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
-+#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
-+#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
-+#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
-+#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
-+#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
-+#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
-+#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
-+#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
-+#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
-+#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
-+#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
-+#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
-+
-+#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
-+
-+/* 16550 UARTs */
-+#ifdef __MIPSEB__
-+#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
-+#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
-+#else
-+#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
-+#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
-+#endif
++static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
++{
++ unsigned char old_dll, old_dlm, old_lcr;
++ unsigned int id;
+
-+#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
-+#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
-+
-+#define IDT_CLOCK_MULT 2
-+
-+/* NVRAM */
-+#define NVRAM_BASE 0x12000000
-+#define NVRAM_ENVSIZE_OFF 4
-+#define NVRAM_ENVSTART_OFF 0x40
-+
-+/* LCD 4-digit display */
-+#define LCD_CLEAR 0x14000400
-+#define LCD_DIGIT0 0x1400000f
-+#define LCD_DIGIT1 0x14000008
-+#define LCD_DIGIT2 0x14000007
-+#define LCD_DIGIT3 0x14000003
-+
-+/* Interrupts routed on 79S334A board (see rc32334.h) */
-+#define RC32334_SCC8530_IRQ 2
-+#define RC32334_PCI_INTA_IRQ 3
-+#define RC32334_PCI_INTB_IRQ 4
-+#define RC32334_PCI_INTC_IRQ 6
-+#define RC32334_PCI_INTD_IRQ 7
-+
-+#define RAM_SIZE (32*1024*1024)
-+
-+#endif // __IDT_RC32334_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,206 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * DMA controller defines on IDT RC32355
-+ *
-+ * Copyright 2004 IDT Inc.
-+ * Author: Integrated Device Technology Inc. rischelp@idt.com
-+ *
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ * May 2004 rkt
-+ * Initial Release
-+ *
-+ **************************************************************************
-+ */
++ old_lcr = serial_inp(p, UART_LCR);
++ serial_outp(p, UART_LCR, UART_LCR_DLAB);
++
++ old_dll = serial_inp(p, UART_DLL);
++ old_dlm = serial_inp(p, UART_DLM);
++
++ serial_outp(p, UART_DLL, 0);
++ serial_outp(p, UART_DLM, 0);
++
++ id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
+
-+#ifndef BANYAN_DMA_H
-+#define BANYAN_DMA_H
-+#include <asm/idt-boards/rc32300/rc32300.h>
++ serial_outp(p, UART_DLL, old_dll);
++ serial_outp(p, UART_DLM, old_dlm);
++ serial_outp(p, UART_LCR, old_lcr);
++
++ return id;
++}
+
+/*
-+ * An image of one RC32355 dma channel registers
++ * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
++ * When this function is called we know it is at least a StarTech
++ * 16650 V2, but it might be one of several StarTech UARTs, or one of
++ * its clones. (We treat the broken original StarTech 16650 V1 as a
++ * 16550, and why not? Startech doesn't seem to even acknowledge its
++ * existence.)
++ *
++ * What evil have men's minds wrought...
+ */
-+typedef struct {
-+ u32 dmac;
-+ u32 dmas;
-+ u32 dmasm;
-+ u32 dmadptr;
-+ u32 dmandptr;
-+} rc32355_dma_ch_t;
++static void autoconfig_has_efr(struct uart_8250_port *up)
++{
++ unsigned int id1, id2, id3, rev;
++
++ /*
++ * Everything with an EFR has SLEEP
++ */
++ up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
++
++ /*
++ * First we check to see if it's an Oxford Semiconductor UART.
++ *
++ * If we have to do this here because some non-National
++ * Semiconductor clone chips lock up if you try writing to the
++ * LSR register (which serial_icr_read does)
++ */
++
++ /*
++ * Check for Oxford Semiconductor 16C950.
++ *
++ * EFR [4] must be set else this test fails.
++ *
++ * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
++ * claims that it's needed for 952 dual UART's (which are not
++ * recommended for new designs).
++ */
++ up->acr = 0;
++ serial_out(up, UART_LCR, 0xBF);
++ serial_out(up, UART_EFR, UART_EFR_ECB);
++ serial_out(up, UART_LCR, 0x00);
++ id1 = serial_icr_read(up, UART_ID1);
++ id2 = serial_icr_read(up, UART_ID2);
++ id3 = serial_icr_read(up, UART_ID3);
++ rev = serial_icr_read(up, UART_REV);
++
++ DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
++
++ if (id1 == 0x16 && id2 == 0xC9 &&
++ (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
++ up->port.type = PORT_16C950;
++
++ /*
++ * Enable work around for the Oxford Semiconductor 952 rev B
++ * chip which causes it to seriously miscalculate baud rates
++ * when DLL is 0.
++ */
++ if (id3 == 0x52 && rev == 0x01)
++ up->bugs |= UART_BUG_QUOT;
++ return;
++ }
++
++ /*
++ * We check for a XR16C850 by setting DLL and DLM to 0, and then
++ * reading back DLL and DLM. The chip type depends on the DLM
++ * value read back:
++ * 0x10 - XR16C850 and the DLL contains the chip revision.
++ * 0x12 - XR16C2850.
++ * 0x14 - XR16C854.
++ */
++ id1 = autoconfig_read_divisor_id(up);
++ DEBUG_AUTOCONF("850id=%04x ", id1);
++
++ id2 = id1 >> 8;
++ if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
++ up->port.type = PORT_16850;
++ return;
++ }
++
++ /*
++ * It wasn't an XR16C850.
++ *
++ * We distinguish between the '654 and the '650 by counting
++ * how many bytes are in the FIFO. I'm using this for now,
++ * since that's the technique that was sent to me in the
++ * serial driver update, but I'm not convinced this works.
++ * I've had problems doing this in the past. -TYT
++ */
++ if (size_fifo(up) == 64)
++ up->port.type = PORT_16654;
++ else
++ up->port.type = PORT_16650V2;
++}
+
+/*
-+ * An image of all RC32355 dma channel registers
++ * We detected a chip without a FIFO. Only two fall into
++ * this category - the original 8250 and the 16450. The
++ * 16450 has a scratch register (accessible with LCR=0)
+ */
-+typedef struct {
-+ rc32355_dma_ch_t ch[16];
-+} rc32355_dma_regs_t;
++static void autoconfig_8250(struct uart_8250_port *up)
++{
++ unsigned char scratch, status1, status2;
++
++ up->port.type = PORT_8250;
++
++ scratch = serial_in(up, UART_SCR);
++ serial_outp(up, UART_SCR, 0xa5);
++ status1 = serial_in(up, UART_SCR);
++ serial_outp(up, UART_SCR, 0x5a);
++ status2 = serial_in(up, UART_SCR);
++ serial_outp(up, UART_SCR, scratch);
++
++ if (status1 == 0xa5 && status2 == 0x5a)
++ up->port.type = PORT_16450;
++}
++
++static int broken_efr(struct uart_8250_port *up)
++{
++ /*
++ * Exar ST16C2550 "A2" devices incorrectly detect as
++ * having an EFR, and report an ID of 0x0201. See
++ * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
++ */
++ if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
++ return 1;
+
++ return 0;
++}
+
-+#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
++/*
++ * We know that the chip has FIFOs. Does it have an EFR? The
++ * EFR is located in the same register position as the IIR and
++ * we know the top two bits of the IIR are currently set. The
++ * EFR should contain zero. Try to read the EFR.
++ */
++static void autoconfig_16550a(struct uart_8250_port *up)
++{
++ unsigned char status1, status2;
++ unsigned int iersave;
+
++ up->port.type = PORT_16550A;
++ up->capabilities |= UART_CAP_FIFO;
+
-+/* DMAC register layout */
++ /*
++ * Check for presence of the EFR when DLAB is set.
++ * Only ST16C650V1 UARTs pass this test.
++ */
++ serial_outp(up, UART_LCR, UART_LCR_DLAB);
++ if (serial_in(up, UART_EFR) == 0) {
++ serial_outp(up, UART_EFR, 0xA8);
++ if (serial_in(up, UART_EFR) != 0) {
++ DEBUG_AUTOCONF("EFRv1 ");
++ up->port.type = PORT_16650;
++ up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
++ } else {
++ DEBUG_AUTOCONF("Motorola 8xxx DUART ");
++ }
++ serial_outp(up, UART_EFR, 0);
++ return;
++ }
+
-+#define DMAC_RUN 0x1 /* Halts processing when cleared */
-+#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
-+#define DMAC_MODE_MASK 0xC /* DMA operating mode */
++ /*
++ * Maybe it requires 0xbf to be written to the LCR.
++ * (other ST16C650V2 UARTs, TI16C752A, etc)
++ */
++ serial_outp(up, UART_LCR, 0xBF);
++ if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
++ DEBUG_AUTOCONF("EFRv2 ");
++ autoconfig_has_efr(up);
++ return;
++ }
+
-+#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
-+#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
-+#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
++ /*
++ * Check for a National Semiconductor SuperIO chip.
++ * Attempt to switch to bank 2, read the value of the LOOP bit
++ * from EXCR1. Switch back to bank 0, change it in MCR. Then
++ * switch back to bank 2, read it from EXCR1 again and check
++ * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
++ */
++ serial_outp(up, UART_LCR, 0);
++ status1 = serial_in(up, UART_MCR);
++ serial_outp(up, UART_LCR, 0xE0);
++ status2 = serial_in(up, 0x02); /* EXCR1 */
++
++ if (!((status2 ^ status1) & UART_MCR_LOOP)) {
++ serial_outp(up, UART_LCR, 0);
++ serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
++ serial_outp(up, UART_LCR, 0xE0);
++ status2 = serial_in(up, 0x02); /* EXCR1 */
++ serial_outp(up, UART_LCR, 0);
++ serial_outp(up, UART_MCR, status1);
++
++ if ((status2 ^ status1) & UART_MCR_LOOP) {
++ unsigned short quot;
++
++ serial_outp(up, UART_LCR, 0xE0);
++
++ quot = serial_dl_read(up);
++ quot <<= 3;
++
++ status1 = serial_in(up, 0x04); /* EXCR1 */
++ status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
++ status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
++ serial_outp(up, 0x04, status1);
++
++ serial_dl_write(up, quot);
+
-+/* DMAS and DMASM register layout */
++ serial_outp(up, UART_LCR, 0);
+
-+#define DMAS_F 0x01 /* Finished */
-+#define DMAS_D 0x02 /* Done */
-+#define DMAS_C 0x04 /* Chain */
-+#define DMAS_E 0x08 /* Error */
-+#define DMAS_H 0x10 /* Halt */
++ up->port.uartclk = 921600*16;
++ up->port.type = PORT_NS16550A;
++ up->capabilities |= UART_NATSEMI;
++ return;
++ }
++ }
+
-+/* Polling count for DMAS_H bit in DMAS register after halting DMA */
-+#define DMA_HALT_TIMEOUT 500
++ /*
++ * No EFR. Try to detect a TI16750, which only sets bit 5 of
++ * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
++ * Try setting it with and without DLAB set. Cheap clones
++ * set bit 5 without DLAB set.
++ */
++ serial_outp(up, UART_LCR, 0);
++ serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
++ status1 = serial_in(up, UART_IIR) >> 5;
++ serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
++ serial_outp(up, UART_LCR, UART_LCR_DLAB);
++ serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
++ status2 = serial_in(up, UART_IIR) >> 5;
++ serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
++ serial_outp(up, UART_LCR, 0);
++
++ DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
++
++ if (status1 == 6 && status2 == 7) {
++ up->port.type = PORT_16750;
++ up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
++ return;
++ }
+
++ /*
++ * Try writing and reading the UART_IER_UUE bit (b6).
++ * If it works, this is probably one of the Xscale platform's
++ * internal UARTs.
++ * We're going to explicitly set the UUE bit to 0 before
++ * trying to write and read a 1 just to make sure it's not
++ * already a 1 and maybe locked there before we even start start.
++ */
++ iersave = serial_in(up, UART_IER);
++ serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
++ if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
++ /*
++ * OK it's in a known zero state, try writing and reading
++ * without disturbing the current state of the other bits.
++ */
++ serial_outp(up, UART_IER, iersave | UART_IER_UUE);
++ if (serial_in(up, UART_IER) & UART_IER_UUE) {
++ /*
++ * It's an Xscale.
++ * We'll leave the UART_IER_UUE bit set to 1 (enabled).
++ */
++ DEBUG_AUTOCONF("Xscale ");
++ up->port.type = PORT_XSCALE;
++ up->capabilities |= UART_CAP_UUE;
++ return;
++ }
++ } else {
++ /*
++ * If we got here we couldn't force the IER_UUE bit to 0.
++ * Log it and continue.
++ */
++ DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
++ }
++ serial_outp(up, UART_IER, iersave);
++}
+
-+static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
++/*
++ * This routine is called by rs_init() to initialize a specific serial
++ * port. It determines what type of UART chip this serial port is
++ * using: 8250, 16450, 16550, 16550A. The important question is
++ * whether or not this UART is a 16550A or not, since this will
++ * determine whether or not we can use its FIFO features or not.
++ */
++static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
+{
-+ int timeout=1;
-+
-+ if (local_readl(&ch->dmac) & DMAC_RUN) {
-+ local_writel(0, &ch->dmac);
-+ for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
-+ if (local_readl(&ch->dmas) & DMAS_H) {
-+ local_writel(0, &ch->dmas);
++ unsigned char status1, scratch, scratch2, scratch3;
++ unsigned char save_lcr, save_mcr;
++ unsigned long flags;
++
++ if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
++ return;
++
++ DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
++ up->port.line, up->port.iobase, up->port.membase);
++
++ /*
++ * We really do need global IRQs disabled here - we're going to
++ * be frobbing the chips IRQ enable register to see if it exists.
++ */
++ spin_lock_irqsave(&up->port.lock, flags);
++// save_flags(flags); cli();
++
++ up->capabilities = 0;
++ up->bugs = 0;
++
++ if (!(up->port.flags & UPF_BUGGY_UART)) {
++ /*
++ * Do a simple existence test first; if we fail this,
++ * there's no point trying anything else.
++ *
++ * 0x80 is used as a nonsense port to prevent against
++ * false positives due to ISA bus float. The
++ * assumption is that 0x80 is a non-existent port;
++ * which should be safe since include/asm/io.h also
++ * makes this assumption.
++ *
++ * Note: this is safe as long as MCR bit 4 is clear
++ * and the device is in "PC" mode.
++ */
++ scratch = serial_inp(up, UART_IER);
++ serial_outp(up, UART_IER, 0);
++#ifdef __i386__
++ outb(0xff, 0x080);
++#endif
++ /*
++ * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
++ * 16C754B) allow only to modify them if an EFR bit is set.
++ */
++ scratch2 = serial_inp(up, UART_IER) & 0x0f;
++ serial_outp(up, UART_IER, 0x0F);
++#ifdef __i386__
++ outb(0, 0x080);
++#endif
++ scratch3 = serial_inp(up, UART_IER) & 0x0f;
++ serial_outp(up, UART_IER, scratch);
++ if (scratch2 != 0 || scratch3 != 0x0F) {
++ /*
++ * We failed; there's nothing here
++ */
++ DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
++ scratch2, scratch3);
++ goto out;
++ }
++ }
++
++ save_mcr = serial_in(up, UART_MCR);
++ save_lcr = serial_in(up, UART_LCR);
++
++ /*
++ * Check to see if a UART is really there. Certain broken
++ * internal modems based on the Rockwell chipset fail this
++ * test, because they apparently don't implement the loopback
++ * test mode. So this test is skipped on the COM 1 through
++ * COM 4 ports. This *should* be safe, since no board
++ * manufacturer would be stupid enough to design a board
++ * that conflicts with COM 1-4 --- we hope!
++ */
++ if (!(up->port.flags & UPF_SKIP_TEST)) {
++ serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
++ status1 = serial_inp(up, UART_MSR) & 0xF0;
++ serial_outp(up, UART_MCR, save_mcr);
++ if (status1 != 0x90) {
++ DEBUG_AUTOCONF("LOOP test failed (%02x) ",
++ status1);
++ goto out;
++ }
++ }
++
++ /*
++ * We're pretty sure there's a port here. Lets find out what
++ * type of port it is. The IIR top two bits allows us to find
++ * out if it's 8250 or 16450, 16550, 16550A or later. This
++ * determines what we test for next.
++ *
++ * We also initialise the EFR (if any) to zero for later. The
++ * EFR occupies the same register location as the FCR and IIR.
++ */
++ serial_outp(up, UART_LCR, 0xBF);
++ serial_outp(up, UART_EFR, 0);
++ serial_outp(up, UART_LCR, 0);
++
++ serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
++ scratch = serial_in(up, UART_IIR) >> 6;
++
++ DEBUG_AUTOCONF("iir=%d ", scratch);
++
++ switch (scratch) {
++ case 0:
++ autoconfig_8250(up);
++ break;
++ case 1:
++ up->port.type = PORT_UNKNOWN;
++ break;
++ case 2:
++ up->port.type = PORT_16550;
++ break;
++ case 3:
++ autoconfig_16550a(up);
++ break;
++ }
++
++#ifdef CONFIG_SERIAL_8250_RSA
++ /*
++ * Only probe for RSA ports if we got the region.
++ */
++ if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
++ int i;
++
++ for (i = 0 ; i < probe_rsa_count; ++i) {
++ if (probe_rsa[i] == up->port.iobase &&
++ __enable_rsa(up)) {
++ up->port.type = PORT_RSA;
+ break;
+ }
+ }
+ }
++#endif
++
++#ifdef CONFIG_SERIAL_8250_AU1X00
++ /* if access method is AU, it is a 16550 with a quirk */
++ if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
++ up->bugs |= UART_BUG_NOMSR;
++#endif
++
++ serial_outp(up, UART_LCR, save_lcr);
++
++ if (up->capabilities != uart_config[up->port.type].flags) {
++ printk(KERN_WARNING
++ "ttyS%d: detected caps %08x should be %08x\n",
++ up->port.line, up->capabilities,
++ uart_config[up->port.type].flags);
++ }
++
++ up->port.fifosize = uart_config[up->port.type].fifo_size;
++ up->capabilities = uart_config[up->port.type].flags;
++ up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
++
++ if (up->port.type == PORT_UNKNOWN)
++ goto out;
+
-+ return timeout ? 0 : 1;
++ /*
++ * Reset the UART.
++ */
++#ifdef CONFIG_SERIAL_8250_RSA
++ if (up->port.type == PORT_RSA)
++ serial_outp(up, UART_RSA_FRR, 0);
++#endif
++ serial_outp(up, UART_MCR, save_mcr);
++ serial8250_clear_fifos(up);
++ serial_in(up, UART_RX);
++ if (up->capabilities & UART_CAP_UUE)
++ serial_outp(up, UART_IER, UART_IER_UUE);
++ else
++ serial_outp(up, UART_IER, 0);
++
++ out:
++ spin_unlock_irqrestore(&up->port.lock, flags);
++// restore_flags(flags);
++ DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
+}
+
-+static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
++static void autoconfig_irq(struct uart_8250_port *up)
+{
-+ local_writel(0, &ch->dmandptr);
-+ local_writel(dma_addr, &ch->dmadptr);
++ unsigned char save_mcr, save_ier;
++ unsigned char save_ICP = 0;
++ unsigned int ICP = 0;
++ unsigned long irqs;
++ int irq;
++
++ if (up->port.flags & UPF_FOURPORT) {
++ ICP = (up->port.iobase & 0xfe0) | 0x1f;
++ save_ICP = inb_p(ICP);
++ outb_p(0x80, ICP);
++ (void) inb_p(ICP);
++ }
++
++ /* forget possible initially masked and pending IRQ */
++ probe_irq_off(probe_irq_on());
++ save_mcr = serial_inp(up, UART_MCR);
++ save_ier = serial_inp(up, UART_IER);
++ serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
++
++ irqs = probe_irq_on();
++ serial_outp(up, UART_MCR, 0);
++ udelay (10);
++ if (up->port.flags & UPF_FOURPORT) {
++ serial_outp(up, UART_MCR,
++ UART_MCR_DTR | UART_MCR_RTS);
++ } else {
++ serial_outp(up, UART_MCR,
++ UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
++ }
++ serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
++ (void)serial_inp(up, UART_LSR);
++ (void)serial_inp(up, UART_RX);
++ (void)serial_inp(up, UART_IIR);
++ (void)serial_inp(up, UART_MSR);
++ serial_outp(up, UART_TX, 0xFF);
++ udelay (20);
++ irq = probe_irq_off(irqs);
++
++ serial_outp(up, UART_MCR, save_mcr);
++ serial_outp(up, UART_IER, save_ier);
++
++ if (up->port.flags & UPF_FOURPORT)
++ outb_p(save_ICP, ICP);
++
++ up->port.irq = (irq > 0) ? irq : 0;
+}
+
-+static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
++static inline void __stop_tx(struct uart_8250_port *p)
+{
-+ local_writel(dma_addr, &ch->dmandptr);
++ if (p->ier & UART_IER_THRI) {
++ p->ier &= ~UART_IER_THRI;
++ serial_out(p, UART_IER, p->ier);
++ }
+}
+
++static void serial8250_stop_tx(struct uart_port *port)
++{
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++
++ __stop_tx(up);
+
-+/* The following can be used to describe DMA channels 0 to 15, and the */
-+/* sub device's needed to select them in the DMADESC_DS_MASK field */
++ /*
++ * We really want to stop the transmitter from sending.
++ */
++ if (up->port.type == PORT_16C950) {
++ up->acr |= UART_ACR_TXDIS;
++ serial_icr_write(up, UART_ACR, up->acr);
++ }
++}
+
-+#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
++static void transmit_chars(struct uart_8250_port *up);
+
-+#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
-+#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
++static void serial8250_start_tx(struct uart_port *port)
++{
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
+
-+#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
-+#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
++ if (!(up->ier & UART_IER_THRI)) {
++ up->ier |= UART_IER_THRI;
++ serial_out(up, UART_IER, up->ier);
+
-+#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
-+#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
++ if (up->bugs & UART_BUG_TXEN) {
++ unsigned char lsr, iir;
++ lsr = serial_in(up, UART_LSR);
++ iir = serial_in(up, UART_IIR);
++ if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
++ transmit_chars(up);
++ }
++ }
+
-+#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
-+#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
++ /*
++ * Re-enable the transmitter if we disabled it.
++ */
++ if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
++ up->acr &= ~UART_ACR_TXDIS;
++ serial_icr_write(up, UART_ACR, up->acr);
++ }
++}
+
-+/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
-+#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
-+#define DMA_DEV_ATMVCC(entry) 0
++static void serial8250_stop_rx(struct uart_port *port)
++{
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
+
-+#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
-+#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
++ up->ier &= ~UART_IER_RLSI;
++ up->port.read_status_mask &= ~UART_LSR_DR;
++ serial_out(up, UART_IER, up->ier);
++}
+
-+#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
-+#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
++static void serial8250_enable_ms(struct uart_port *port)
++{
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
+
-+#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
-+#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
++ /* no MSR capabilities */
++ if (up->bugs & UART_BUG_NOMSR)
++ return;
+
-+#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
-+#define DMA_DEV_ETHERIN 0 /* Ethernet input */
++ up->ier |= UART_IER_MSI;
++ serial_out(up, UART_IER, up->ier);
++}
+
-+#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
-+#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
++static void
++receive_chars(struct uart_8250_port *up, unsigned int *status)
++{
++ struct tty_struct *tty = up->port.info->tty;
++ unsigned char ch, lsr = *status;
++ int max_count = 256;
++ char flag;
++
++ do {
++ ch = serial_inp(up, UART_RX);
++ flag = TTY_NORMAL;
++ up->port.icount.rx++;
++
++#ifdef CONFIG_SERIAL_8250_CONSOLE
++ /*
++ * Recover the break flag from console xmit
++ */
++ if (up->port.line == up->port.cons->index) {
++ lsr |= up->lsr_break_flag;
++ up->lsr_break_flag = 0;
++ }
++#endif
+
-+#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
-+#define DMA_DEV_TDMIN 0 /* TDM Bus input */
++ if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
++ UART_LSR_FE | UART_LSR_OE))) {
++ /*
++ * For statistics only
++ */
++ if (lsr & UART_LSR_BI) {
++ lsr &= ~(UART_LSR_FE | UART_LSR_PE);
++ up->port.icount.brk++;
++ /*
++ * We do the SysRQ and SAK checking
++ * here because otherwise the break
++ * may get masked by ignore_status_mask
++ * or read_status_mask.
++ */
++ if (uart_handle_break(&up->port))
++ goto ignore_char;
++ } else if (lsr & UART_LSR_PE)
++ up->port.icount.parity++;
++ else if (lsr & UART_LSR_FE)
++ up->port.icount.frame++;
++ if (lsr & UART_LSR_OE)
++ up->port.icount.overrun++;
++
++ /*
++ * Mask off conditions which should be ignored.
++ */
++ lsr &= up->port.read_status_mask;
++
++ if (lsr & UART_LSR_BI) {
++ DEBUG_INTR("handling break....");
++ flag = TTY_BREAK;
++ } else if (lsr & UART_LSR_PE)
++ flag = TTY_PARITY;
++ else if (lsr & UART_LSR_FE)
++ flag = TTY_FRAME;
++ }
++ if (uart_handle_sysrq_char(&up->port, ch))
++ goto ignore_char;
++
++ uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
++
++ ignore_char:
++ lsr = serial_inp(up, UART_LSR);
++ } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
++ spin_unlock(&up->port.lock);
++ tty_flip_buffer_push(tty);
++ spin_lock(&up->port.lock);
++ *status = lsr;
++}
+
-+#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
-+#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
++static void transmit_chars(struct uart_8250_port *up)
++{
++ struct circ_buf *xmit = &up->port.info->xmit;
++ int count;
+
-+#define DMA_CHAN_USBIN 13 /* USB input */
-+#define DMA_DEV_USBIN 0 /* USB input */
++ if (up->port.x_char) {
++ serial_outp(up, UART_TX, up->port.x_char);
++ up->port.icount.tx++;
++ up->port.x_char = 0;
++ return;
++ }
++ if (uart_tx_stopped(&up->port)) {
++ serial8250_stop_tx(&up->port);
++ return;
++ }
++ if (uart_circ_empty(xmit)) {
++ __stop_tx(up);
++ return;
++ }
+
-+#define DMA_CHAN_USBOUT 14 /* USB output */
-+#define DMA_DEV_USBOUT 0 /* USB output */
++ count = up->tx_loadsz;
++ do {
++ serial_out(up, UART_TX, xmit->buf[xmit->tail]);
++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++ up->port.icount.tx++;
++ if (uart_circ_empty(xmit))
++ break;
++ } while (--count > 0);
+
-+#define DMA_CHAN_EXTERN 15 /* External DMA */
-+#define DMA_DEV_EXTERN 0 /* External DMA */
++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++ uart_write_wakeup(&up->port);
+
-+/*
-+ * An RC32355 dma descriptor in system memory
-+ */
-+typedef struct {
-+ u32 cmdstat; /* control and status */
-+ u32 curr_addr; /* current address of data */
-+ u32 devcs; /* peripheral-specific control and status */
-+ u32 link; /* link to next descriptor */
-+} rc32355_dma_desc_t;
-+
-+/* Values for the descriptor cmdstat word */
-+
-+#define DMADESC_F 0x80000000u /* Finished bit */
-+#define DMADESC_D 0x40000000u /* Done bit */
-+#define DMADESC_T 0x20000000u /* Terminated bit */
-+#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
-+#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
-+#define DMADESC_COD 0x04000000u /* Chain On Done */
-+#define DMADESC_COF 0x02000000u /* Chain On Finished */
-+
-+#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
-+#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
-+
-+#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
-+#define DMADESC_DS_SHIFT 20 /* Device Select shift */
-+
-+#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
-+#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
-+
-+#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
-+#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
-+#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
-+#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
-+
-+#define DMA_DEVCMD(devcmd) \
-+ (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
-+#define DMA_DS(ds) \
-+ (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
-+#define DMA_COUNT(count) \
-+ ((count) & DMADESC_COUNT_MASK)
-+
-+#endif /* RC32355_DMA_H */
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,442 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Ethernet registers on IDT RC32355
-+ *
-+ * Copyright 2004 IDT Inc.
-+ * Author: Integrated Device Technology Inc. rischelp@idt.com
-+ *
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ * May 2004 rkt
-+ * Initial Release
-+ *
-+ **************************************************************************
-+ */
++ DEBUG_INTR("THRE...");
+
++ if (uart_circ_empty(xmit))
++ __stop_tx(up);
++}
+
-+#ifndef RC32355_ETHER_H
-+#define RC32355_ETHER_H
++static unsigned int check_modem_status(struct uart_8250_port *up)
++{
++ unsigned int status = serial_in(up, UART_MSR);
+
-+#include <asm/idt-boards/rc32300/rc32355_dma.h>
++ if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
++ up->port.info != NULL) {
++ if (status & UART_MSR_TERI)
++ up->port.icount.rng++;
++ if (status & UART_MSR_DDSR)
++ up->port.icount.dsr++;
++ if (status & UART_MSR_DDCD)
++ uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
++ if (status & UART_MSR_DCTS)
++ uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
+
-+/*
-+ * A partial image of the RC32355 ethernet registers
-+ */
-+typedef struct {
-+ u32 ethintfc;
-+ u32 ethfifott;
-+ u32 etharc;
-+ u32 ethhash0;
-+ u32 ethhash1;
-+ u32 ethfifost;
-+ u32 ethfifos;
-+ u32 ethodeops;
-+ u32 ethis;
-+ u32 ethos;
-+ u32 ethmcp;
-+ u32 _u1;
-+ u32 ethid;
-+ u32 _u2;
-+ u32 _u3;
-+ u32 _u4;
-+ u32 ethod;
-+ u32 _u5;
-+ u32 _u6;
-+ u32 _u7;
-+ u32 ethodeop;
-+ u32 _u8[43];
-+ u32 ethsal0;
-+ u32 ethsah0;
-+ u32 ethsal1;
-+ u32 ethsah1;
-+ u32 ethsal2;
-+ u32 ethsah2;
-+ u32 ethsal3;
-+ u32 ethsah3;
-+ u32 ethrbc;
-+ u32 ethrpc;
-+ u32 ethrupc;
-+ u32 ethrfc;
-+ u32 ethtbc;
-+ u32 ethgpf;
-+ u32 _u9[50];
-+ u32 ethmac1;
-+ u32 ethmac2;
-+ u32 ethipgt;
-+ u32 ethipgr;
-+ u32 ethclrt;
-+ u32 ethmaxf;
-+ u32 _u10;
-+ u32 ethmtest;
-+ u32 miimcfg;
-+ u32 miimcmd;
-+ u32 miimaddr;
-+ u32 miimwtd;
-+ u32 miimrdd;
-+ u32 miimind;
-+ u32 _u11;
-+ u32 _u12;
-+ u32 ethcfsa0;
-+ u32 ethcfsa1;
-+ u32 ethcfsa2;
-+} rc32355_eth_regs_t;
-+
-+#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
-+
-+#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
-+#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
-+#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
-+#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
-+#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
-+#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
-+#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
-+#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
-+#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
-+#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
-+#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
-+#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
-+#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
-+#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
-+
-+/* for n in { 0, 1, 2, 3 } */
-+#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
-+#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
-+
-+#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
-+#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
-+#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
-+#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
-+#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
-+#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
-+#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
-+#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
-+#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
-+#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
-+#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
-+#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
-+#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
-+
-+#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
-+#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
-+#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
-+#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
-+#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
-+#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
-+
-+/* for n in { 0, 1, 2 } */
-+#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
++ wake_up_interruptible(&up->port.info->delta_msr_wait);
++ }
+
++ return status;
++}
+
+/*
-+ * Register Interpretations follow
++ * This handles the interrupt from one port.
+ */
++static inline void
++serial8250_handle_port(struct uart_8250_port *up)
++{
++ unsigned int status;
++ unsigned long flags;
+
-+/******************************************************************************
-+ * ETHINTFC register
-+ *****************************************************************************/
-+
-+#define ETHERINTFC_EN (1<<0)
-+#define ETHERINTFC_ITS (1<<1)
-+#define ETHERINTFC_RES (1<<2)
-+#define ETHERINTFC_RIP (1<<2)
-+#define ETHERINTFC_JAM (1<<3)
-+
-+/******************************************************************************
-+ * ETHFIFOTT register
-+ *****************************************************************************/
-+
-+#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
-+
-+/******************************************************************************
-+ * ETHARC register
-+ *****************************************************************************/
-+
-+#define ETHERARC_PRO (1<<0)
-+#define ETHERARC_AM (1<<1)
-+#define ETHERARC_AFM (1<<2)
-+#define ETHERARC_AB (1<<3)
-+
-+/******************************************************************************
-+ * ETHHASH registers
-+ *****************************************************************************/
-+
-+#define ETHERHASH0(v) (((v)&0xffff)<<0)
-+#define ETHERHASH1(v) (((v)&0xffff)<<0)
-+
-+/******************************************************************************
-+ * ETHSA registers
-+ *****************************************************************************/
-+
-+#define ETHERSAL0(v) (((v)&0xffff)<<0)
-+#define ETHERSAL1(v) (((v)&0xffff)<<0)
-+#define ETHERSAL2(v) (((v)&0xffff)<<0)
-+#define ETHERSAL3(v) (((v)&0xffff)<<0)
-+#define ETHERSAH0(v) (((v)&0xff)<<0)
-+#define ETHERSAH1(v) (((v)&0xff)<<0)
-+#define ETHERSAH2(v) (((v)&0xff)<<0)
-+#define ETHERSAH3(v) (((v)&0xff)<<0)
-+
-+/******************************************************************************
-+ * ETHFIFOST register
-+ *****************************************************************************/
-+
-+#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
-+#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
-+
-+/******************************************************************************
-+ * ETHFIFOS register
-+ *****************************************************************************/
-+
-+#define ETHERFIFOS_IR (1<<0)
-+#define ETHERFIFOS_OR (1<<1)
-+#define ETHERFIFOS_OVR (1<<2)
-+#define ETHERFIFOS_UND (1<<3)
-+
-+/******************************************************************************
-+ * DATA registers
-+ *****************************************************************************/
-+
-+#define ETHERID(v) (((v)&0xffff)<<0)
-+#define ETHEROD(v) (((v)&0xffff)<<0)
-+
-+/******************************************************************************
-+ * ETHODEOPS register
-+ *****************************************************************************/
-+
-+#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
-+
-+/******************************************************************************
-+ * ETHODEOP register
-+ *****************************************************************************/
-+
-+#define ETHERODEOP(v) (((v)&0xffff)<<0)
-+
-+/******************************************************************************
-+ * ETHIS register
-+ *****************************************************************************/
-+
-+#define ETHERIS_EOP (1<<0)
-+#define ETHERIS_ROK (1<<2)
-+#define ETHERIS_FM (1<<3)
-+#define ETHERIS_MP (1<<4)
-+#define ETHERIS_BP (1<<5)
-+#define ETHERIS_VLT (1<<6)
-+#define ETHERIS_CF (1<<7)
-+#define ETHERIS_OVR (1<<8)
-+#define ETHERIS_CRC (1<<9)
-+#define ETHERIS_CV (1<<10)
-+#define ETHERIS_DB (1<<11)
-+#define ETHERIS_LE (1<<12)
-+#define ETHERIS_LOR (1<<13)
-+#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
-+#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
-+
-+/******************************************************************************
-+ * ETHOS register
-+ *****************************************************************************/
-+
-+#define ETHEROS_T (1<<0)
-+#define ETHEROS_TOK (1<<6)
-+#define ETHEROS_MP (1<<7)
-+#define ETHEROS_BP (1<<8)
-+#define ETHEROS_UND (1<<9)
-+#define ETHEROS_OF (1<<10)
-+#define ETHEROS_ED (1<<11)
-+#define ETHEROS_EC (1<<12)
-+#define ETHEROS_LC (1<<13)
-+#define ETHEROS_TD (1<<14)
-+#define ETHEROS_CRC (1<<15)
-+#define ETHEROS_LE (1<<16)
-+#define ETHEROS_CC(v) (((v)&0xf)<<17)
-+#define ETHEROS_PFD (1<<21)
-+
-+/******************************************************************************
-+ * Statistics registers
-+ *****************************************************************************/
-+
-+#define ETHERRBC(v) (((v)&0xffff)<<0)
-+#define ETHERRPC(v) (((v)&0xffff)<<0)
-+#define ETHERRUPC(v) (((v)&0xffff)<<0)
-+#define ETHERRFC(v) (((v)&0xffff)<<0)
-+#define ETHERTBC(v) (((v)&0xffff)<<0)
-+
-+/******************************************************************************
-+ * ETHGPF register
-+ *****************************************************************************/
-+
-+#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
-+
-+/******************************************************************************
-+ * MAC registers
-+ *****************************************************************************/
-+//ETHMAC1
-+#define ETHERMAC1_RE (1<<0)
-+#define ETHERMAC1_PAF (1<<1)
-+#define ETHERMAC1_RFC (1<<2)
-+#define ETHERMAC1_TFC (1<<3)
-+#define ETHERMAC1_LB (1<<4)
-+#define ETHERMAC1_MR (1<<15)
-+
-+//ETHMAC2
-+#define ETHERMAC2_FD (1<<0)
-+#define ETHERMAC2_FLC (1<<1)
-+#define ETHERMAC2_HFE (1<<2)
-+#define ETHERMAC2_DC (1<<3)
-+#define ETHERMAC2_CEN (1<<4)
-+#define ETHERMAC2_PE (1<<5)
-+#define ETHERMAC2_VPE (1<<6)
-+#define ETHERMAC2_APE (1<<7)
-+#define ETHERMAC2_PPE (1<<8)
-+#define ETHERMAC2_LPE (1<<9)
-+#define ETHERMAC2_NB (1<<12)
-+#define ETHERMAC2_BP (1<<13)
-+#define ETHERMAC2_ED (1<<14)
-+
-+//ETHIPGT
-+#define ETHERIPGT(v) (((v)&0x3f)<<0)
-+
-+//ETHIPGR
-+#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
-+#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
-+
-+//ETHCLRT
-+#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
-+#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
-+
-+//ETHMAXF
-+#define ETHERMAXF(v) (((v)&0x3f)<<0)
-+
-+//ETHMTEST
-+#define ETHERMTEST_TB (1<<2)
-+
-+//ETHMCP
-+#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
-+
-+//MIIMCFG
-+#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
-+#define ETHERMIIMCFG_R (1<<15)
-+
-+//MIIMCMD
-+#define ETHERMIIMCMD_RD (1<<0)
-+#define ETHERMIIMCMD_SCN (1<<1)
-+
-+//MIIMADDR
-+#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
-+#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
-+
-+//MIIMWTD
-+#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
-+
-+//MIIMRDD
-+#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
-+
-+//MIIMIND
-+#define ETHERMIIMIND_BSY (1<<0)
-+#define ETHERMIIMIND_SCN (1<<1)
-+#define ETHERMIIMIND_NV (1<<2)
-+
-+//DMA DEVCS IN
-+#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
-+#define ETHERDMA_IN_CES (1<<14)
-+#define ETHERDMA_IN_LOR (1<<13)
-+#define ETHERDMA_IN_LE (1<<12)
-+#define ETHERDMA_IN_DB (1<<11)
-+#define ETHERDMA_IN_CV (1<<10)
-+#define ETHERDMA_IN_CRC (1<<9)
-+#define ETHERDMA_IN_OVR (1<<8)
-+#define ETHERDMA_IN_CF (1<<7)
-+#define ETHERDMA_IN_VLT (1<<6)
-+#define ETHERDMA_IN_BP (1<<5)
-+#define ETHERDMA_IN_MP (1<<4)
-+#define ETHERDMA_IN_FM (1<<3)
-+#define ETHERDMA_IN_ROK (1<<2)
-+#define ETHERDMA_IN_LD (1<<1)
-+#define ETHERDMA_IN_FD (1<<0)
-+
-+//DMA DEVCS OUT
-+#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
-+#define ETHERDMA_OUT_CNT 0x001e0000
-+#define ETHERDMA_OUT_SHFT 17
-+#define ETHERDMA_OUT_LE (1<<16)
-+
-+#define ETHERDMA_OUT_CRC (1<<15)
-+#define ETHERDMA_OUT_TD (1<<14)
-+#define ETHERDMA_OUT_LC (1<<13)
-+#define ETHERDMA_OUT_EC (1<<12)
-+#define ETHERDMA_OUT_ED (1<<11)
-+#define ETHERDMA_OUT_OF (1<<10)
-+#define ETHERDMA_OUT_UND (1<<9)
-+#define ETHERDMA_OUT_BP (1<<8)
-+#define ETHERDMA_OUT_MP (1<<7)
-+#define ETHERDMA_OUT_TOK (1<<6)
-+#define ETHERDMA_OUT_HEN (1<<5)
-+#define ETHERDMA_OUT_CEN (1<<4)
-+#define ETHERDMA_OUT_PEN (1<<3)
-+#define ETHERDMA_OUT_OEN (1<<2)
-+#define ETHERDMA_OUT_LD (1<<1)
-+#define ETHERDMA_OUT_FD (1<<0)
-+
-+#define RCV_ERRS \
-+ (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
-+#define TX_ERRS \
-+ (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
-+ ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
-+
-+#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
-+#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
-+#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
-+#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
-+#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
-+#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
-+#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
-+#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
-+#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
-+#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
-+#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
-+#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
-+ Range */
-+#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
-+#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
-+ received packet */
-+
-+#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
-+#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
-+
-+#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
-+#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
-+ Underflow */
-+#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
-+#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
-+ deferral */
-+#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
-+ collisions */
-+#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
-+#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
-+#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
-+#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
-+
-+#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
-+
-+#endif /* RC32355_ETHER_H */
-+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,177 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for IDT RC32355 CPU.
-+ *
-+ * Copyright 2004 IDT Inc.
-+ * Author: Integrated Device Technology Inc. rischelp@idt.com
-+ *
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ * May 2004 rkt
-+ * Initial Release
-+ *
-+ **************************************************************************
-+ */
++ spin_lock_irqsave(&up->port.lock, flags);
+
++ status = serial_inp(up, UART_LSR);
+
-+#ifndef _RC32355_H_
-+#define _RC32355_H_
++ DEBUG_INTR("status = %x...", status);
+
-+#include <linux/delay.h>
-+#include <asm/io.h>
++ if (status & UART_LSR_DR)
++ receive_chars(up, &status);
++ check_modem_status(up);
++ if (status & UART_LSR_THRE)
++ transmit_chars(up);
++
++ spin_unlock_irqrestore(&up->port.lock, flags);
++}
+
-+/* Base address of internal registers */
-+#define RC32355_REG_BASE 0x18000000
-+
-+/* System ID Registers */
-+#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
-+#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
-+#define CPU_REV (RC32355_REG_BASE + 0x0002c)
-+
-+/* Reset Controller */
-+#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
-+
-+/* Device Controller */
-+#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
-+#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
-+#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
-+#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
-+#define DEV_REG_OFFSET 0x10
-+
-+/* SDRAM Controller */
-+#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
-+#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
-+#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
-+#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
-+#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
-+
-+/* Bus Arbiter */
-+#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
-+#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
-+
-+/* Counters/Timers */
-+#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
-+#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
-+#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
-+#define TIMER_REG_OFFSET 0x0C
-+
-+/* System Integrity */
-+
-+/* Interrupt Controller */
-+#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
-+#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
-+#define IC_GROUP_OFFSET 0x08
-+
-+#define NUM_INTR_GROUPS 5
+/*
-+ * The IRQ mapping is as follows:
++ * This is the serial driver's interrupt routine.
++ *
++ * Arjan thinks the old way was overly complex, so it got simplified.
++ * Alan disagrees, saying that need the complexity to handle the weird
++ * nature of ISA shared interrupts. (This is a special exception.)
+ *
-+ * IRQ Mapped To
-+ * --- -------------------
-+ * 0 SW0 (IP0) SW0 intr
-+ * 1 SW1 (IP1) SW1 intr
-+ * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
-+ * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
-+ * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
-+ * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
-+ * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
-+ * 7 Int5 (IP7) CP0 Timer
++ * In order to handle ISA shared interrupts properly, we need to check
++ * that all ports have been serviced, and therefore the ISA interrupt
++ * line has been de-asserted.
+ *
-+ * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
-+ * internally on the RC32355 is routed to the Expansion
-+ * Interrupt Controller.
++ * This means we need to loop through all ports. checking that they
++ * don't have an interrupt pending.
+ */
-+#define MIPS_CPU_TIMER_IRQ 7
++static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
++{
++ struct irq_info *i = dev_id;
++ struct list_head *l, *end = NULL;
++ int pass_counter = 0, handled = 0;
+
-+#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
-+#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
-+#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
-+#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
-+#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
++ DEBUG_INTR("serial8250_interrupt(%d)...", irq);
+
-+#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
++ spin_lock(&i->lock);
+
-+/* DMA - see rc32355_dma.h for full list of registers */
++ l = i->head;
++ do {
++ struct uart_8250_port *up;
++ unsigned int iir;
+
-+#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
-+#define DMA_CHAN_OFFSET 0x14
++ up = list_entry(l, struct uart_8250_port, list);
+
-+/* GPIO Controller */
++ iir = serial_in(up, UART_IIR);
++ if (!(iir & UART_IIR_NO_INT)) {
++ serial8250_handle_port(up);
+
-+/* TDM Bus */
++ handled = 1;
+
-+/* 16550 UARTs */
-+#ifdef __MIPSEB__
-+#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
-+#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
-+#else
-+#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
-+#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
-+#endif
++ end = NULL;
++ } else if (end == NULL)
++ end = l;
+
-+#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
-+#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
++ l = l->next;
++
++ if (l == i->head && pass_counter++ > PASS_LIMIT) {
++ /* If we hit this, we're dead. */
++ printk(KERN_ERR "serial8250: too much work for "
++ "irq%d\n", irq);
++ break;
++ }
++ } while (l != end);
+
-+/* ATM */
++ spin_unlock(&i->lock);
+
-+/* Ethernet - see rc32355_eth.h for full list of registers */
++ DEBUG_INTR("end.\n");
+
-+#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
++ return IRQ_RETVAL(handled);
++}
+
++/*
++ * To support ISA shared interrupts, we need to have one interrupt
++ * handler that ensures that the IRQ line has been deasserted
++ * before returning. Failing to do this will result in the IRQ
++ * line being stuck active, and, since ISA irqs are edge triggered,
++ * no more IRQs will be seen.
++ */
++static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
++{
++ spin_lock_irq(&i->lock);
+
-+#define IDT_CLOCK_MULT 2
++ if (!list_empty(i->head)) {
++ if (i->head == &up->list)
++ i->head = i->head->next;
++ list_del(&up->list);
++ } else {
++ BUG_ON(i->head != &up->list);
++ i->head = NULL;
++ }
+
-+/* Memory map of 79EB355 board */
++ spin_unlock_irq(&i->lock);
++}
+
-+/* DRAM */
-+#define RAM_BASE 0x00000000
-+#define RAM_SIZE (32*1024*1024)
++static int serial_link_irq_chain(struct uart_8250_port *up)
++{
++ struct irq_info *i = irq_lists + up->port.irq;
++ int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
+
-+/* SRAM (device 1) */
-+#define SRAM_BASE 0x02000000
-+#define SRAM_SIZE 0x00100000
++ spin_lock_irq(&i->lock);
+
-+/* FLASH (device 2) */
-+#define FLASH_BASE 0x0C000000
-+#define FLASH_SIZE 0x00C00000
++ if (i->head) {
++ list_add(&up->list, i->head);
++ spin_unlock_irq(&i->lock);
+
-+/* ATM PHY (device 4) */
-+#define ATM_PHY_BASE 0x14000000
++ ret = 0;
++ } else {
++ INIT_LIST_HEAD(&up->list);
++ i->head = &up->list;
++ spin_unlock_irq(&i->lock);
+
-+/* TDM switch (device 3) */
-+#define TDM_BASE 0x1A000000
++ ret = request_irq(up->port.irq, serial8250_interrupt,
++ irq_flags, "serial", i);
++ if (ret < 0)
++ serial_do_unlink(i, up);
++ }
+
-+/* LCD panel (device 3) */
-+#define LCD_BASE 0x1A002000
++ return ret;
++}
+
-+/* RTC (DS1511W) (device 3) */
-+#define RTC_BASE 0x1A004000
++static void serial_unlink_irq_chain(struct uart_8250_port *up)
++{
++ struct irq_info *i = irq_lists + up->port.irq;
+
-+/* NVRAM (256 bytes internal to the DS1511 RTC) */
-+#define NVRAM_ADDR RTC_BASE + 0x10
-+#define NVRAM_DATA RTC_BASE + 0x13
-+#define NVRAM_ENVSIZE_OFF 4
-+#define NVRAM_ENVSTART_OFF 32
++ BUG_ON(i->head == NULL);
+
-+#endif /* _RC32355_H_ */
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,226 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * RC32365/336 DMA hardware abstraction.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ if (list_empty(i->head))
++ free_irq(up->port.irq, i);
+
-+#ifndef __IDT_RC32365_DMA_H__
-+#define __IDT_RC32365_DMA_H__
++ serial_do_unlink(i, up);
++}
+
-+enum
++/* Base timer interval for polling */
++static inline int poll_timeout(int timeout)
+{
-+ DMA0_PhysicalAddress = 0x18038000,
-+ DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
-+
-+ DMA0_VirtualAddress = 0xb8038000,
-+ DMA_VirtualAddress = DMA0_VirtualAddress, // Default
-+} ;
++ return timeout > 6 ? (timeout / 2 - 2) : 1;
++}
+
+/*
-+ * DMA descriptor (in physical memory).
++ * This function is used to handle ports that do not have an
++ * interrupt. This doesn't work very well for 16450's, but gives
++ * barely passable results for a 16550A. (Although at the expense
++ * of much CPU overhead).
+ */
-+
-+typedef struct DMAD_s
++static void serial8250_timeout(unsigned long data)
+{
-+ u32 control ; // Control. use DMAD_*
-+ u32 ca ; // Current Address.
-+ u32 devcs ; // Device control and status.
-+ u32 link ; // Next descriptor in chain.
-+} volatile *DMAD_t ;
++ struct uart_8250_port *up = (struct uart_8250_port *)data;
++ unsigned int iir;
++
++ iir = serial_in(up, UART_IIR);
++ if (!(iir & UART_IIR_NO_INT))
++ serial8250_handle_port(up);
++ mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
++}
+
-+enum
++static void serial8250_backup_timeout(unsigned long data)
+{
-+ DMAD_size = sizeof (struct DMAD_s),
-+ DMAD_count_b = 0, // in DMAD_t -> control
-+ DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
-+ DMAD_ds_b = 20, // in DMAD_t -> control
-+ DMAD_ds_m = 0x00300000, // in DMAD_t -> control
-+ DMAD_ds_extToMem0_v = 0,
-+ DMAD_ds_memToExt0_v = 1,
-+ DMAD_ds_extToMem1_v = 0,
-+ DMAD_ds_memToExt1_v = 1,
-+ DMAD_ds_ethRcv0_v = 0,
-+ DMAD_ds_ethXmt0_v = 0,
-+ DMAD_ds_ethRcv1_v = 0,
-+ DMAD_ds_ethXmt2_v = 0,
-+ DMAD_ds_memToFifo_v = 0,
-+ DMAD_ds_fifoToMem_v = 0,
-+ DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
-+ DMAD_ds_pciToMem_v = 0,
-+ DMAD_ds_memToPci_v = 0,
-+ DMAD_ds_securityInput_v = 0,
-+ DMAD_ds_securityOutput_v = 0,
-+ DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
-+
-+ DMAD_devcmd_b = 22, // in DMAD_t -> control
-+ DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
-+ DMAD_devcmd_byte_v = 0, //memory-to-memory
-+ DMAD_devcmd_halfword_v = 1, //memory-to-memory
-+ DMAD_devcmd_word_v = 2, //memory-to-memory
-+ DMAD_devcmd_2words_v = 3, //memory-to-memory
-+ DMAD_devcmd_4words_v = 4, //memory-to-memory
-+ DMAD_devcmd_6words_v = 5, //memory-to-memory
-+ DMAD_devcmd_8words_v = 6, //memory-to-memory
-+ DMAD_devcmd_16words_v = 7, //memory-to-memory
-+ DMAD_cof_b = 25, // chain on finished
-+ DMAD_cof_m = 0x02000000, //
-+ DMAD_cod_b = 26, // chain on done
-+ DMAD_cod_m = 0x04000000, //
-+ DMAD_iof_b = 27, // interrupt on finished
-+ DMAD_iof_m = 0x08000000, //
-+ DMAD_iod_b = 28, // interrupt on done
-+ DMAD_iod_m = 0x10000000, //
-+ DMAD_t_b = 29, // terminated
-+ DMAD_t_m = 0x20000000, //
-+ DMAD_d_b = 30, // done
-+ DMAD_d_m = 0x40000000, //
-+ DMAD_f_b = 31, // finished
-+ DMAD_f_m = 0x80000000, //
-+} ;
++ struct uart_8250_port *up = (struct uart_8250_port *)data;
++ unsigned int iir, ier = 0;
+
-+/*
-+ * DMA register (within Internal Register Map).
-+ */
++ /*
++ * Must disable interrupts or else we risk racing with the interrupt
++ * based handler.
++ */
++ if (is_real_interrupt(up->port.irq)) {
++ ier = serial_in(up, UART_IER);
++ serial_out(up, UART_IER, 0);
++ }
+
-+struct DMA_Chan_s
-+{
-+ u32 dmac ; // Control.
-+ u32 dmas ; // Status.
-+ u32 dmasm ; // Mask.
-+ u32 dmadptr ; // Descriptor pointer.
-+ u32 dmandptr ; // Next descriptor pointer.
-+};
++ iir = serial_in(up, UART_IIR);
+
-+typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
++ /*
++ * This should be a safe test for anyone who doesn't trust the
++ * IIR bits on their UART, but it's specifically designed for
++ * the "Diva" UART used on the management processor on many HP
++ * ia64 and parisc boxes.
++ */
++ if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
++ (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
++ (serial_in(up, UART_LSR) & UART_LSR_THRE)) {
++ iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
++ iir |= UART_IIR_THRI;
++ }
+
-+//DMA_Channels use DMACH_count instead
++ if (!(iir & UART_IIR_NO_INT))
++ serial8250_handle_port(up);
+
-+enum
-+{
-+ DMAC_run_b = 0, //
-+ DMAC_run_m = 0x00000001, //
-+ DMAC_dm_b = 1, // done mask
-+ DMAC_dm_m = 0x00000002, //
-+ DMAC_mode_b = 2, //
-+ DMAC_mode_m = 0x0000000c, //
-+ DMAC_mode_auto_v = 0,
-+ DMAC_mode_burst_v = 1,
-+ DMAC_mode_transfer_v = 2, //usually used
-+ DMAC_mode_reserved_v = 3,
-+ DMAC_a_b = 4, //
-+ DMAC_a_m = 0x00000010, //
-+
-+ DMAS_f_b = 0, // finished (sticky)
-+ DMAS_f_m = 0x00000001, //
-+ DMAS_d_b = 1, // done (sticky)
-+ DMAS_d_m = 0x00000002, //
-+ DMAS_c_b = 2, // chain (sticky)
-+ DMAS_c_m = 0x00000004, //
-+ DMAS_e_b = 3, // error (sticky)
-+ DMAS_e_m = 0x00000008, //
-+ DMAS_h_b = 4, // halt (sticky)
-+ DMAS_h_m = 0x00000010, //
-+
-+ DMASM_f_b = 0, // finished (1=mask)
-+ DMASM_f_m = 0x00000001, //
-+ DMASM_d_b = 1, // done (1=mask)
-+ DMASM_d_m = 0x00000002, //
-+ DMASM_c_b = 2, // chain (1=mask)
-+ DMASM_c_m = 0x00000004, //
-+ DMASM_e_b = 3, // error (1=mask)
-+ DMASM_e_m = 0x00000008, //
-+ DMASM_h_b = 4, // halt (1=mask)
-+ DMASM_h_m = 0x00000010, //
-+} ;
++ if (is_real_interrupt(up->port.irq))
++ serial_out(up, UART_IER, ier);
+
-+/*
-+ * DMA channel definitions
-+ */
++ /* Standard timer interval plus 0.2s to keep the port running */
++ mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout) + HZ/5);
++}
+
-+enum
++static unsigned int serial8250_tx_empty(struct uart_port *port)
+{
-+ DMACH_ethRcv0 = 0,
-+ DMACH_ethXmt0 = 1,
-+ DMACH_ethRcv1 = 2,
-+ DMACH_ethXmt2 = 3,
-+ DMACH_pciToMem = 4,
-+ DMACH_memToPci = 5,
-+ DMACH_securityInput = 6,
-+ DMACH_securityOutput = 7,
-+ DMACH_rng = 8,
-+
-+ DMACH_count //must be last
-+};
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++ unsigned long flags;
++ unsigned int ret;
+
++ spin_lock_irqsave(&up->port.lock, flags);
++ ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
++ spin_unlock_irqrestore(&up->port.lock, flags);
+
-+typedef struct DMAC_s
++ return ret;
++}
++
++static unsigned int serial8250_get_mctrl(struct uart_port *port)
+{
-+ struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
-+} volatile *DMA_t ;
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++ unsigned int status;
++ unsigned int ret;
+
++ status = check_modem_status(up);
+
-+/*
-+ * External DMA parameters
-+*/
++ ret = 0;
++ if (status & UART_MSR_DCD)
++ ret |= TIOCM_CAR;
++ if (status & UART_MSR_RI)
++ ret |= TIOCM_RNG;
++ if (status & UART_MSR_DSR)
++ ret |= TIOCM_DSR;
++ if (status & UART_MSR_CTS)
++ ret |= TIOCM_CTS;
++ return ret;
++}
+
-+enum
++static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
-+ DMADEVCMD_ts_b = 0, // ts field in devcmd
-+ DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
-+ DMADEVCMD_ts_byte_v = 0,
-+ DMADEVCMD_ts_halfword_v = 1,
-+ DMADEVCMD_ts_word_v = 2,
-+ DMADEVCMD_ts_2word_v = 3,
-+ DMADEVCMD_ts_4word_v = 4,
-+ DMADEVCMD_ts_6word_v = 5,
-+ DMADEVCMD_ts_8word_v = 6,
-+ DMADEVCMD_ts_16word_v = 7
-+};
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++ unsigned char mcr = 0;
+
++ if (mctrl & TIOCM_RTS)
++ mcr |= UART_MCR_RTS;
++ if (mctrl & TIOCM_DTR)
++ mcr |= UART_MCR_DTR;
++ if (mctrl & TIOCM_OUT1)
++ mcr |= UART_MCR_OUT1;
++ if (mctrl & TIOCM_OUT2)
++ mcr |= UART_MCR_OUT2;
++ if (mctrl & TIOCM_LOOP)
++ mcr |= UART_MCR_LOOP;
+
-+#if 1 // aws - Compatibility.
-+# define EXTDMA_ts_b DMADEVCMD_ts_b
-+# define EXTDMA_ts_m DMADEVCMD_ts_m
-+# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
-+# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
-+# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
-+# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
-+# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
-+# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
-+# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
-+# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
-+#endif // aws - Compatibility.
-+
-+#endif // __IDT_RC32365_DMA_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,86 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * RC32365/336 DMA interface routines.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
+
-+#ifndef __IDT_RC32365_DMA_V_H__
-+#define __IDT_RC32365_DMA_V_H__
++ serial_out(up, UART_MCR, mcr);
++}
++
++static void serial8250_break_ctl(struct uart_port *port, int break_state)
++{
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++ unsigned long flags;
+
++ spin_lock_irqsave(&up->port.lock, flags);
++ if (break_state == -1)
++ up->lcr |= UART_LCR_SBC;
++ else
++ up->lcr &= ~UART_LCR_SBC;
++ serial_out(up, UART_LCR, up->lcr);
++ spin_unlock_irqrestore(&up->port.lock, flags);
++}
+
-+#include <asm/idt-boards/rc32300/rc32300.h>
-+#include <asm/idt-boards/rc32300/rc32365_dma.h>
-+#include <asm/idt-boards/rc32300/rc32365.h>
++#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
+
-+#define DMA_CHAN_OFFSET 0x14
-+#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
-+#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
-+#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
++/*
++ * Wait for transmitter & holding register to empty
++ */
++static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
++{
++ unsigned int status, tmout = 10000;
+
-+#define DMA_COUNT(count) \
-+ ((count) & DMAD_count_m)
++ /* Wait up to 10ms for the character(s) to be sent. */
++ do {
++ status = serial_in(up, UART_LSR);
+
-+#define DMA_HALT_TIMEOUT 500
++ if (status & UART_LSR_BI)
++ up->lsr_break_flag = UART_LSR_BI;
+
-+static inline int rc32365_halt_dma(DMA_Chan_t ch)
-+{
-+ int timeout=1;
-+ if (local_readl(&ch->dmac) & DMAC_run_m) {
-+ local_writel(0, &ch->dmac);
-+
-+ for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
-+ if (local_readl(&ch->dmas) & DMAS_h_m) {
-+ local_writel(0, &ch->dmas);
-+ break;
-+ }
++ if (--tmout == 0)
++ break;
++ udelay(1);
++ } while ((status & bits) != bits);
++
++ /* Wait up to 1s for flow control if necessary */
++ if (up->port.flags & UPF_CONS_FLOW) {
++ tmout = 1000000;
++ while (!(serial_in(up, UART_MSR) & UART_MSR_CTS) && --tmout) {
++ udelay(1);
++ touch_nmi_watchdog();
+ }
++ }
++}
+
++static int serial8250_startup(struct uart_port *port)
++{
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++ unsigned long flags;
++ unsigned char lsr, iir;
++ int retval;
++
++ up->capabilities = uart_config[up->port.type].flags;
++ up->mcr = 0;
++
++ if (up->port.type == PORT_16C950) {
++ /* Wake up and initialize UART */
++ up->acr = 0;
++ serial_outp(up, UART_LCR, 0xBF);
++ serial_outp(up, UART_EFR, UART_EFR_ECB);
++ serial_outp(up, UART_IER, 0);
++ serial_outp(up, UART_LCR, 0);
++ serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
++ serial_outp(up, UART_LCR, 0xBF);
++ serial_outp(up, UART_EFR, UART_EFR_ECB);
++ serial_outp(up, UART_LCR, 0);
+ }
+
-+ return timeout ? 0 : 1;
-+}
++#ifdef CONFIG_SERIAL_8250_RSA
++ /*
++ * If this is an RSA port, see if we can kick it up to the
++ * higher speed clock.
++ */
++ enable_rsa(up);
++#endif
+
++ /*
++ * Clear the FIFO buffers and disable them.
++ * (they will be reenabled in set_termios())
++ */
++ serial8250_clear_fifos(up);
+
-+static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
-+{
-+ local_writel(0, &ch->dmandptr);
-+ local_writel(dma_addr, &ch->dmadptr);
-+}
++ /*
++ * Clear the interrupt registers.
++ */
++ (void) serial_inp(up, UART_LSR);
++ (void) serial_inp(up, UART_RX);
++ (void) serial_inp(up, UART_IIR);
++ (void) serial_inp(up, UART_MSR);
+
-+static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
-+{
-+ local_writel(dma_addr, &ch->dmandptr);
-+}
-+#endif //__IDT_RC32365_DMA_V_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,344 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * RC32365/336 Ethernet hardware abstraction.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ /*
++ * At this point, there's no way the LSR could still be 0xff;
++ * if it is, then bail out, because there's likely no UART
++ * here.
++ */
++ if (!(up->port.flags & UPF_BUGGY_UART) &&
++ (serial_inp(up, UART_LSR) == 0xff)) {
++ printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
++ return -ENODEV;
++ }
+
-+#ifndef __IDT_RC32365_ETH_H__
-+#define __IDT_RC32365_ETH_H__
++ /*
++ * For a XR16C850, we need to set the trigger levels
++ */
++ if (up->port.type == PORT_16850) {
++ unsigned char fctr;
+
-+enum
-+{
-+ ETH0_PhysicalAddress = 0x18058000,
-+ ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
-+ ETH0_VirtualAddress = 0xb8058000,
++ serial_outp(up, UART_LCR, 0xbf);
+
-+ ETH_VirtualAddress = ETH0_VirtualAddress, // Default
++ fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
++ serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
++ serial_outp(up, UART_TRG, UART_TRG_96);
++ serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
++ serial_outp(up, UART_TRG, UART_TRG_96);
+
-+ ETH1_PhysicalAddress = 0x18060000,
-+ ETH1_VirtualAddress = 0xb8060000, // Default
-+} ;
++ serial_outp(up, UART_LCR, 0);
++ }
+
-+typedef struct
-+{
-+ u32 ethintfc ;
-+ u32 ethfifott ;
-+ u32 etharc ;
-+ u32 ethhash0 ;
-+ u32 ethhash1 ;
-+ u32 ethu0 [4] ; // Reserved.
-+ u32 ethpfs ;
-+ u32 ethmcp ;
-+ u32 eth_u1 [10] ; // Reserved.
-+ u32 ethspare ;
-+ u32 eth_u2 [42] ; // Reserved.
-+ u32 ethsal0 ;
-+ u32 ethsah0 ;
-+ u32 ethsal1 ;
-+ u32 ethsah1 ;
-+ u32 ethsal2 ;
-+ u32 ethsah2 ;
-+ u32 ethsal3 ;
-+ u32 ethsah3 ;
-+ u32 ethrbc ;
-+ u32 ethrpc ;
-+ u32 ethrupc ;
-+ u32 ethrfc ;
-+ u32 ethtbc ;
-+ u32 ethgpf ;
-+ u32 eth_u9 [50] ; // Reserved.
-+ u32 ethmac1 ;
-+ u32 ethmac2 ;
-+ u32 ethipgt ;
-+ u32 ethipgr ;
-+ u32 ethclrt ;
-+ u32 ethmaxf ;
-+ u32 eth_u10 ; // Reserved.
-+ u32 ethmtest ;
-+ u32 miimcfg ;
-+ u32 miimcmd ;
-+ u32 miimaddr ;
-+ u32 miimwtd ;
-+ u32 miimrdd ;
-+ u32 miimind ;
-+ u32 eth_u11 ; // Reserved.
-+ u32 eth_u12 ; // Reserved.
-+ u32 ethcfsa0 ;
-+ u32 ethcfsa1 ;
-+ u32 ethcfsa2 ;
-+} volatile *ETH_t;
-+
-+enum
-+{
-+ ETHINTFC_en_b = 0,
-+ ETHINTFC_en_m = 0x00000001,
-+ ETHINTFC_its_b = 1,
-+ ETHINTFC_its_m = 0x00000002,
-+ ETHINTFC_rip_b = 2,
-+ ETHINTFC_rip_m = 0x00000004,
-+ ETHINTFC_jam_b = 3,
-+ ETHINTFC_jam_m = 0x00000008,
-+ ETHINTFC_ovr_b = 4,
-+ ETHINTFC_ovr_m = 0x00000010,
-+ ETHINTFC_und_b = 5,
-+ ETHINTFC_und_m = 0x00000020,
-+
-+ ETHFIFOTT_tth_b = 0,
-+ ETHFIFOTT_tth_m = 0x0000007f,
-+
-+ ETHARC_pro_b = 0,
-+ ETHARC_pro_m = 0x00000001,
-+ ETHARC_am_b = 1,
-+ ETHARC_am_m = 0x00000002,
-+ ETHARC_afm_b = 2,
-+ ETHARC_afm_m = 0x00000004,
-+ ETHARC_ab_b = 3,
-+ ETHARC_ab_m = 0x00000008,
-+
-+ ETHSAL_byte5_b = 0,
-+ ETHSAL_byte5_m = 0x000000ff,
-+ ETHSAL_byte4_b = 8,
-+ ETHSAL_byte4_m = 0x0000ff00,
-+ ETHSAL_byte3_b = 16,
-+ ETHSAL_byte3_m = 0x00ff0000,
-+ ETHSAL_byte2_b = 24,
-+ ETHSAL_byte2_m = 0xff000000,
-+
-+ ETHSAH_byte1_b = 0,
-+ ETHSAH_byte1_m = 0x000000ff,
-+ ETHSAH_byte0_b = 8,
-+ ETHSAH_byte0_m = 0x0000ff00,
-+
-+ ETHGPF_ptv_b = 0,
-+ ETHGPF_ptv_m = 0x0000ffff,
-+
-+ ETHPFS_pfd_b = 0,
-+ ETHPFS_pfd_m = 0x00000001,
-+
-+ ETHCFSA0_cfsa4_b = 0,
-+ ETHCFSA0_cfsa4_m = 0x000000ff,
-+ ETHCFSA0_cfsa5_b = 8,
-+ ETHCFSA0_cfsa5_m = 0x0000ff00,
-+
-+ ETHCFSA1_cfsa2_b = 0,
-+ ETHCFSA1_cfsa2_m = 0x000000ff,
-+ ETHCFSA1_cfsa3_b = 8,
-+ ETHCFSA1_cfsa3_m = 0x0000ff00,
-+
-+ ETHCFSA2_cfsa0_b = 0,
-+ ETHCFSA2_cfsa0_m = 0x000000ff,
-+ ETHCFSA2_cfsa1_b = 8,
-+ ETHCFSA2_cfsa1_m = 0x0000ff00,
-+
-+ ETHMAC1_re_b = 0,
-+ ETHMAC1_re_m = 0x00000001,
-+ ETHMAC1_paf_b = 1,
-+ ETHMAC1_paf_m = 0x00000002,
-+ ETHMAC1_rfc_b = 2,
-+ ETHMAC1_rfc_m = 0x00000004,
-+ ETHMAC1_tfc_b = 3,
-+ ETHMAC1_tfc_m = 0x00000008,
-+ ETHMAC1_lb_b = 4,
-+ ETHMAC1_lb_m = 0x00000010,
-+ ETHMAC1_mr_b = 31,
-+ ETHMAC1_mr_m = 0x80000000,
-+
-+ ETHMAC2_fd_b = 0,
-+ ETHMAC2_fd_m = 0x00000001,
-+ ETHMAC2_flc_b = 1,
-+ ETHMAC2_flc_m = 0x00000002,
-+ ETHMAC2_hfe_b = 2,
-+ ETHMAC2_hfe_m = 0x00000004,
-+ ETHMAC2_dc_b = 3,
-+ ETHMAC2_dc_m = 0x00000008,
-+ ETHMAC2_cen_b = 4,
-+ ETHMAC2_cen_m = 0x00000010,
-+ ETHMAC2_pe_b = 5,
-+ ETHMAC2_pe_m = 0x00000020,
-+ ETHMAC2_vpe_b = 6,
-+ ETHMAC2_vpe_m = 0x00000040,
-+ ETHMAC2_ape_b = 7,
-+ ETHMAC2_ape_m = 0x00000080,
-+ ETHMAC2_ppe_b = 8,
-+ ETHMAC2_ppe_m = 0x00000100,
-+ ETHMAC2_lpe_b = 9,
-+ ETHMAC2_lpe_m = 0x00000200,
-+ ETHMAC2_nb_b = 12,
-+ ETHMAC2_nb_m = 0x00001000,
-+ ETHMAC2_bp_b = 13,
-+ ETHMAC2_bp_m = 0x00002000,
-+ ETHMAC2_ed_b = 14,
-+ ETHMAC2_ed_m = 0x00004000,
-+
-+ ETHIPGT_ipgt_b = 0,
-+ ETHIPGT_ipgt_m = 0x0000007f,
-+
-+ ETHIPGR_ipgr2_b = 0,
-+ ETHIPGR_ipgr2_m = 0x0000007f,
-+ ETHIPGR_ipgr1_b = 8,
-+ ETHIPGR_ipgr1_m = 0x00007f00,
-+
-+ ETHCLRT_maxret_b = 0,
-+ ETHCLRT_maxret_m = 0x0000000f,
-+ ETHCLRT_colwin_b = 8,
-+ ETHCLRT_colwin_m = 0x00003f00,
-+
-+ ETHMAXF_maxf_b = 0,
-+ ETHMAXF_maxf_m = 0x0000ffff,
-+
-+ ETHMTEST_tb_b = 2,
-+ ETHMTEST_tb_m = 0x00000004,
-+
-+ ETHMCP_div_b = 0,
-+ ETHMCP_div_m = 0x000000ff,
-+
-+ MIIMCFG_rsv_b = 0,
-+ MIIMCFG_rsv_m = 0x0000000c,
++ if (is_real_interrupt(up->port.irq)) {
++ /*
++ * Test for UARTs that do not reassert THRE when the
++ * transmitter is idle and the interrupt has already
++ * been cleared. Real 16550s should always reassert
++ * this interrupt whenever the transmitter is idle and
++ * the interrupt is enabled. Delays are necessary to
++ * allow register changes to become visible.
++ */
++ spin_lock_irqsave(&up->port.lock, flags);
++
++ wait_for_xmitr(up, UART_LSR_THRE);
++ serial_out_sync(up, UART_IER, UART_IER_THRI);
++ udelay(1); /* allow THRE to set */
++ serial_in(up, UART_IIR);
++ serial_out(up, UART_IER, 0);
++ serial_out_sync(up, UART_IER, UART_IER_THRI);
++ udelay(1); /* allow a working UART time to re-assert THRE */
++ iir = serial_in(up, UART_IIR);
++ serial_out(up, UART_IER, 0);
++
++ spin_unlock_irqrestore(&up->port.lock, flags);
++
++ /*
++ * If the interrupt is not reasserted, setup a timer to
++ * kick the UART on a regular basis.
++ */
++ if (iir & UART_IIR_NO_INT) {
++ pr_debug("ttyS%d - using backup timer\n", port->line);
++ up->timer.function = serial8250_backup_timeout;
++ up->timer.data = (unsigned long)up;
++ mod_timer(&up->timer, jiffies +
++ poll_timeout(up->port.timeout) + HZ/5);
++ }
++ }
+
-+ MIIMCMD_rd_b = 0,
-+ MIIMCMD_rd_m = 0x00000001,
-+ MIIMCMD_scn_b = 1,
-+ MIIMCMD_scn_m = 0x00000002,
++ /*
++ * If the "interrupt" for this port doesn't correspond with any
++ * hardware interrupt, we use a timer-based system. The original
++ * driver used to do this with IRQ0.
++ */
++ if (!is_real_interrupt(up->port.irq)) {
++ up->timer.data = (unsigned long)up;
++ mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
++ } else {
++ retval = serial_link_irq_chain(up);
++ if (retval)
++ return retval;
++ }
+
-+ MIIMADDR_regaddr_b = 0,
-+ MIIMADDR_regaddr_m = 0x0000001f,
-+ MIIMADDR_phyaddr_b = 8,
-+ MIIMADDR_phyaddr_m = 0x00001f00,
++ /*
++ * Now, initialize the UART
++ */
++ serial_outp(up, UART_LCR, UART_LCR_WLEN8);
+
-+ MIIMWTD_wdata_b = 0,
-+ MIIMWTD_wdata_m = 0x0000ffff,
++ spin_lock_irqsave(&up->port.lock, flags);
++ if (up->port.flags & UPF_FOURPORT) {
++ if (!is_real_interrupt(up->port.irq))
++ up->port.mctrl |= TIOCM_OUT1;
++ } else
++ /*
++ * Most PC uarts need OUT2 raised to enable interrupts.
++ */
++ if (is_real_interrupt(up->port.irq))
++ up->port.mctrl |= TIOCM_OUT2;
+
-+ MIIMRDD_rdata_b = 0,
-+ MIIMRDD_rdata_m = 0x0000ffff,
++ serial8250_set_mctrl(&up->port, up->port.mctrl);
+
-+ MIIMIND_bsy_b = 0,
-+ MIIMIND_bsy_m = 0x00000001,
-+ MIIMIND_scn_b = 1,
-+ MIIMIND_scn_m = 0x00000002,
-+ MIIMIND_nv_b = 2,
-+ MIIMIND_nv_m = 0x00000004,
++ /*
++ * Do a quick test to see if we receive an
++ * interrupt when we enable the TX irq.
++ */
++ serial_outp(up, UART_IER, UART_IER_THRI);
++ lsr = serial_in(up, UART_LSR);
++ iir = serial_in(up, UART_IIR);
++ serial_outp(up, UART_IER, 0);
++
++ if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
++ if (!(up->bugs & UART_BUG_TXEN)) {
++ up->bugs |= UART_BUG_TXEN;
++ pr_debug("ttyS%d - enabling bad tx status workarounds\n",
++ port->line);
++ }
++ } else {
++ up->bugs &= ~UART_BUG_TXEN;
++ }
+
-+} ;
++ spin_unlock_irqrestore(&up->port.lock, flags);
+
-+/*
-+ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
-+ */
-+enum
-+{
-+ ETHRX_fd_b = 0,
-+ ETHRX_fd_m = 0x00000001,
-+ ETHRX_ld_b = 1,
-+ ETHRX_ld_m = 0x00000002,
-+ ETHRX_rok_b = 2,
-+ ETHRX_rok_m = 0x00000004,
-+ ETHRX_fm_b = 3,
-+ ETHRX_fm_m = 0x00000008,
-+ ETHRX_mp_b = 4,
-+ ETHRX_mp_m = 0x00000010,
-+ ETHRX_bp_b = 5,
-+ ETHRX_bp_m = 0x00000020,
-+ ETHRX_vlt_b = 6,
-+ ETHRX_vlt_m = 0x00000040,
-+ ETHRX_cf_b = 7,
-+ ETHRX_cf_m = 0x00000080,
-+ ETHRX_ovr_b = 8,
-+ ETHRX_ovr_m = 0x00000100,
-+ ETHRX_crc_b = 9,
-+ ETHRX_crc_m = 0x00000200,
-+ ETHRX_cv_b = 10,
-+ ETHRX_cv_m = 0x00000400,
-+ ETHRX_db_b = 11,
-+ ETHRX_db_m = 0x00000800,
-+ ETHRX_le_b = 12,
-+ ETHRX_le_m = 0x00001000,
-+ ETHRX_lor_b = 13,
-+ ETHRX_lor_m = 0x00002000,
-+ ETHRX_ces_b = 14,
-+ ETHRX_ces_m = 0x00004000,
-+ ETHRX_length_b = 16,
-+ ETHRX_length_m = 0xffff0000,
-+
-+ ETHTX_fd_b = 0,
-+ ETHTX_fd_m = 0x00000001,
-+ ETHTX_ld_b = 1,
-+ ETHTX_ld_m = 0x00000002,
-+ ETHTX_oen_b = 2,
-+ ETHTX_oen_m = 0x00000004,
-+ ETHTX_pen_b = 3,
-+ ETHTX_pen_m = 0x00000008,
-+ ETHTX_cen_b = 4,
-+ ETHTX_cen_m = 0x00000010,
-+ ETHTX_hen_b = 5,
-+ ETHTX_hen_m = 0x00000020,
-+ ETHTX_tok_b = 6,
-+ ETHTX_tok_m = 0x00000040,
-+ ETHTX_mp_b = 7,
-+ ETHTX_mp_m = 0x00000080,
-+ ETHTX_bp_b = 8,
-+ ETHTX_bp_m = 0x00000100,
-+ ETHTX_und_b = 9,
-+ ETHTX_und_m = 0x00000200,
-+ ETHTX_of_b = 10,
-+ ETHTX_of_m = 0x00000400,
-+ ETHTX_ed_b = 11,
-+ ETHTX_ed_m = 0x00000800,
-+ ETHTX_ec_b = 12,
-+ ETHTX_ec_m = 0x00001000,
-+ ETHTX_lc_b = 13,
-+ ETHTX_lc_m = 0x00002000,
-+ ETHTX_td_b = 14,
-+ ETHTX_td_m = 0x00004000,
-+ ETHTX_crc_b = 15,
-+ ETHTX_crc_m = 0x00008000,
-+ ETHTX_le_b = 16,
-+ ETHTX_le_m = 0x00010000,
-+ ETHTX_cc_b = 17,
-+ ETHTX_cc_m = 0x001E0000,
-+} ;
-+
-+enum
-+{
-+ ETH0_IPABMC_PhysicalAddress = 0x18040010,
-+ ETH0_IPABMC_VirtualAddress = 0xb8040000,
-+ ETH1_IPABMC_PhysicalAddress = 0x18040018,
-+ ETH1_IPABMC_VirtualAddress = 0xb8040018,
-+} ;
++ /*
++ * Finally, enable interrupts. Note: Modem status interrupts
++ * are set via set_termios(), which will be occurring imminently
++ * anyway, so we don't enable them here.
++ */
++ up->ier = UART_IER_RLSI | UART_IER_RDI;
++ serial_outp(up, UART_IER, up->ier);
++
++ if (up->port.flags & UPF_FOURPORT) {
++ unsigned int icp;
++ /*
++ * Enable interrupts on the AST Fourport board
++ */
++ icp = (up->port.iobase & 0xfe0) | 0x01f;
++ outb_p(0x80, icp);
++ (void) inb_p(icp);
++ }
++
++ /*
++ * And clear the interrupt registers again for luck.
++ */
++ (void) serial_inp(up, UART_LSR);
++ (void) serial_inp(up, UART_RX);
++ (void) serial_inp(up, UART_IIR);
++ (void) serial_inp(up, UART_MSR);
+
-+typedef struct
++ return 0;
++}
++
++static void serial8250_shutdown(struct uart_port *port)
+{
-+ u32 ipabmcrx ;
-+ u32 ipabmctx ;
-+}volatile *IPABM_ETH_t;
-+#endif //__IDT_RC32365_ETH_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,72 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * RC32365/336 Ethernet status checking.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++ unsigned long flags;
+
-+#ifndef __IDT_RC32365_ETH_V_H__
-+#define __IDT_RC32365_ETH_V_H__
-+#include <asm/idt-boards/rc32300/rc32365_eth.h>
-+
-+#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
-+#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
-+#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
-+#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
-+#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
-+#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
-+#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
-+#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
-+#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
-+#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
-+#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
-+
-+#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
-+
-+#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
-+#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
-+#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
-+#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
-+#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
-+#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
-+#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
-+#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
-+#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
-+#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
-+#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
-+#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
-+#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
-+#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
-+
-+#endif //__IDT_RC32365_ETH_V_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,181 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * RC32365/336 GPIO hardware abstraction.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ /*
++ * Disable interrupts from this port
++ */
++ up->ier = 0;
++ serial_outp(up, UART_IER, 0);
+
-+#ifndef __IDT_RC32365_GPIO_H__
-+#define __IDT_RC32365_GPIO_H__
++ spin_lock_irqsave(&up->port.lock, flags);
++ if (up->port.flags & UPF_FOURPORT) {
++ /* reset interrupts on the AST Fourport board */
++ inb((up->port.iobase & 0xfe0) | 0x1f);
++ up->port.mctrl |= TIOCM_OUT1;
++ } else
++ up->port.mctrl &= ~TIOCM_OUT2;
+
-+enum
-+{
-+ GPIO0_PhysicalAddress = 0x18048000,
-+ GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
-+
-+ GPIO0_VirtualAddress = 0xb8048000,
-+ GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
-+} ;
++ serial8250_set_mctrl(&up->port, up->port.mctrl);
++ spin_unlock_irqrestore(&up->port.lock, flags);
+
-+typedef struct
-+{
-+ u32 gpiofunc; /* GPIO Function Register
-+ * gpiofunc[x]==0 bit = gpio
-+ * func[x]==1 bit = altfunc
-+ */
-+ u32 gpiocfg; /* GPIO Configuration Register
-+ * gpiocfg[x]==0 bit = input
-+ * gpiocfg[x]==1 bit = output
-+ */
-+ u32 gpiod; /* GPIO Data Register
-+ * gpiod[x] read/write gpio pinX status
-+ */
-+ u32 gpioilevel; /* GPIO Interrupt Status Register
-+ * interrupt level (see gpioistat)
-+ */
-+ u32 gpioistat; /* Gpio Interrupt Status Register
-+ * istat[x] = (gpiod[x] == level[x])
-+ * cleared in ISR (STICKY bits)
-+ */
-+ u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
-+} volatile * GPIO_t ;
-+
-+typedef enum
-+{
-+ GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
-+ GPIO_alt_v = 1, // gpiofunc use pin as alt.
-+ GPIO_input_v = 0, // gpiocfg use pin as input.
-+ GPIO_output_v = 1, // gpiocfg use pin as output.
-+ GPIO_pin0_b = 0,
-+ GPIO_pin0_m = 0x00000001,
-+ GPIO_pin1_b = 1,
-+ GPIO_pin1_m = 0x00000002,
-+ GPIO_pin2_b = 2,
-+ GPIO_pin2_m = 0x00000004,
-+ GPIO_pin3_b = 3,
-+ GPIO_pin3_m = 0x00000008,
-+ GPIO_pin4_b = 4,
-+ GPIO_pin4_m = 0x00000010,
-+ GPIO_pin5_b = 5,
-+ GPIO_pin5_m = 0x00000020,
-+ GPIO_pin6_b = 6,
-+ GPIO_pin6_m = 0x00000040,
-+ GPIO_pin7_b = 7,
-+ GPIO_pin7_m = 0x00000080,
-+ GPIO_pin8_b = 8,
-+ GPIO_pin8_m = 0x00000100,
-+ GPIO_pin9_b = 9,
-+ GPIO_pin9_m = 0x00000200,
-+ GPIO_pin10_b = 10,
-+ GPIO_pin10_m = 0x00000400,
-+ GPIO_pin11_b = 11,
-+ GPIO_pin11_m = 0x00000800,
-+ GPIO_pin12_b = 12,
-+ GPIO_pin12_m = 0x00001000,
-+ GPIO_pin13_b = 13,
-+ GPIO_pin13_m = 0x00002000,
-+ GPIO_pin14_b = 14,
-+ GPIO_pin14_m = 0x00004000,
-+ GPIO_pin15_b = 15,
-+ GPIO_pin15_m = 0x00008000,
-+
-+// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
-+
-+ GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
-+ GPIO_u0sout_m = GPIO_pin0_m,
-+ GPIO_u0sout_cfg_v = GPIO_output_v,
-+
-+ GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
-+ GPIO_u0sinp_m = GPIO_pin1_m,
-+ GPIO_u0sinp_cfg_v = GPIO_input_v,
-+
-+ GPIO_maddr22_b = GPIO_pin2_b, // M&P bus bit 22.
-+ GPIO_maddr22_m = GPIO_pin2_m,
-+ GPIO_maddr22_cfg_v = GPIO_output_v,
-+
-+ GPIO_maddr23_b = GPIO_pin3_b, // M&P bus bit 23.
-+ GPIO_maddr23_m = GPIO_pin3_m,
-+ GPIO_maddr23_cfg_v = GPIO_output_v,
-+
-+ GPIO_maddr24_b = GPIO_pin4_b, // M&P bus bit 24.
-+ GPIO_maddr24_m = GPIO_pin4_m,
-+ GPIO_maddr24_cfg_v = GPIO_output_v,
-+
-+ GPIO_maddr25_b = GPIO_pin5_b, // M&P bus bit 25.
-+ GPIO_maddr25_m = GPIO_pin5_m,
-+ GPIO_maddr25_cfg_v = GPIO_output_v,
-+
-+ GPIO_rngclk_b = GPIO_pin6_b, // reserved.
-+ GPIO_rngclk_m = GPIO_pin6_m,
-+ GPIO_rngclk_cfg_v = GPIO_input_v,
++ /*
++ * Disable break condition and FIFOs
++ */
++ serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
++ serial8250_clear_fifos(up);
+
-+ GPIO_sdckenp_b = GPIO_pin7_b, // reserved.
-+ GPIO_sdckenp_m = GPIO_pin7_m,
-+ GPIO_sdckenp_cfg_v = GPIO_output_v,
++#ifdef CONFIG_SERIAL_8250_RSA
++ /*
++ * Reset the RSA board back to 115kbps compat mode.
++ */
++ disable_rsa(up);
++#endif
+
-+ GPIO_cen1_b = GPIO_pin8_b, // reserved.
-+ GPIO_cen1_m = GPIO_pin8_m,
-+ GPIO_cen1_cfg_v = GPIO_output_v,
++ /*
++ * Read data port to reset things, and then unlink from
++ * the IRQ chain.
++ */
++ (void) serial_in(up, UART_RX);
+
-+ GPIO_cen2_b = GPIO_pin9_b, // reserved.
-+ GPIO_cen2_m = GPIO_pin9_m,
-+ GPIO_cen2_cfg_v = GPIO_output_v,
-+
-+ GPIO_regn_b = GPIO_pin10_b, // reserved.
-+ GPIO_regn_m = GPIO_pin10_m,
-+ GPIO_regn_cfg_v = GPIO_output_v,
-+
-+ GPIO_iordn_b = GPIO_pin11_b, // reserved.
-+ GPIO_iordn_m = GPIO_pin11_m,
-+ GPIO_iordn_cfg_v = GPIO_output_v,
-+
-+ GPIO_iowrn_b = GPIO_pin12_b, // reserved.
-+ GPIO_iowrn_m = GPIO_pin12_m,
-+ GPIO_iowrn_cfg_v = GPIO_output_v,
-+
-+ GPIO_pcireqn2_b = GPIO_pin13_b, // PCI messaging int.
-+ GPIO_pcireqn2_m = GPIO_pin13_m,
-+ GPIO_pcireqn2_cfg_v = GPIO_input_v,
-+
-+ GPIO_pcigntn2_b = GPIO_pin14_b, // PCI messaging int.
-+ GPIO_pcigntn2_m = GPIO_pin14_m,
-+ GPIO_pcigntn2_cfg_v = GPIO_output_v,
-+
-+ GPIO_pcimuintn_b = GPIO_pin15_b, // PCI messaging int.
-+ GPIO_pcimuintn_m = GPIO_pin15_m,
-+ GPIO_pcimuintn_cfg_v= GPIO_output_v,
-+
-+} GPIO_DEFS_t;
-+
-+#endif //__IDT_RC32365_GPIO_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,91 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Routines to set/clear/toggle GPIO on RC32365
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
-+#ifndef __IDT_RC32365_GPIO_V_H__
-+#define __IDT_RC32365_GPIO_V_H__
-+
-+
-+#ifdef _LANGUAGE_ASSEMBLY
-+#define SET_GPIO(pin) \
-+ lui t5,0xb804 ; \
-+ ori t5,t5,0x8000 ; \
-+ lw t4,8(t5) ; \
-+ ori t4,t4,pin ; \
-+ sw t4,8(t5) ;
-+
-+#define CLEAR_GPIO(pin) \
-+ lui t5,0xb804 ; \
-+ ori t5,t5,0x8000 ; \
-+ lw t4,8(t5) ; \
-+ lui t6,0xFFFF; \
-+ ori t6,t6,0xFFFF; \
-+ xori t6,t6,pin ; \
-+ and t4,t6 ; \
-+ sw t4,8(t5) ;
-+
-+#define TOGGLE_GPIO(pin) \
-+ lui t5,0xb804 ; \
-+ ori t5,t5,0x8000 ; \
-+ lw t4,8(t5) ; \
-+ xori t4,t4,pin ; \
-+ sw t4,8(t5) ;
-+
-+#else // !_LANGUAGE_ASSEMBLY
-+#include <asm/rc32300/types.h>
-+#include <asm/rc32300/rc32365_gpio.h>
-+#include <asm/rc32300/rc32365.h>
-+
-+static inline void set_gpio(unsigned long pin)
-+{
-+ idt_gpio->gpiod |= pin;
-+}
-+
-+static inline void clear_gpio(unsigned long pin)
-+{
-+ idt_gpio->gpiod &= ~pin;
++ del_timer_sync(&up->timer);
++ up->timer.function = serial8250_timeout;
++ if (is_real_interrupt(up->port.irq))
++ serial_unlink_irq_chain(up);
+}
-+static inline void toggle_gpio(unsigned long pin)
++
++static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
+{
-+ idt_gpio->gpiod ^= pin;
-+}
-+#define SET_GPIO(pin) set_gpio(pin)
-+#define CLEAR_GPIO(pin) clear_gpio(pin)
-+#define TOGGLE_GPIO(pin) toggle_gpio(pin)
-+#endif // _LANGUAGE_ASSEMBLY
++ unsigned int quot;
++
++ /*
++ * Handle magic divisors for baud rates above baud_base on
++ * SMSC SuperIO chips.
++ */
++ if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
++ baud == (port->uartclk/4))
++ quot = 0x8001;
++ else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
++ baud == (port->uartclk/8))
++ quot = 0x8002;
++ else
++ quot = uart_get_divisor(port, baud);
+
-+#endif //__IDT_RC32365_GPIO_V_H__
++ return quot;
++}
+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,160 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for IDT RC32365 CPU.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++static void
++serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
++ struct ktermios *old)
++{
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++ unsigned char cval, fcr = 0;
++ unsigned long flags;
++ unsigned int baud, quot;
++
++ switch (termios->c_cflag & CSIZE) {
++ case CS5:
++ cval = UART_LCR_WLEN5;
++ break;
++ case CS6:
++ cval = UART_LCR_WLEN6;
++ break;
++ case CS7:
++ cval = UART_LCR_WLEN7;
++ break;
++ default:
++ case CS8:
++ cval = UART_LCR_WLEN8;
++ break;
++ }
+
-+#ifndef __IDT_RC32365_H__
-+#define __IDT_RC32365_H__
++ if (termios->c_cflag & CSTOPB)
++ cval |= UART_LCR_STOP;
++ if (termios->c_cflag & PARENB)
++ cval |= UART_LCR_PARITY;
++ if (!(termios->c_cflag & PARODD))
++ cval |= UART_LCR_EPAR;
++#ifdef CMSPAR
++ if (termios->c_cflag & CMSPAR)
++ cval |= UART_LCR_SPAR;
++#endif
+
-+extern unsigned int cedar_za;
++ /*
++ * Ask the core to calculate the divisor for us.
++ */
++ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
++ quot = serial8250_get_divisor(port, baud);
+
-+/* Base address of internal registers */
-+#define RC32365_REG_BASE 0x18000000
++ /*
++ * Oxford Semi 952 rev B workaround
++ */
++ if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
++ quot ++;
+
-+/* System ID Registers */
-+#define CPU_SYSID (RC32365_REG_BASE + 0x00018)
-+#define CPU_DEVTYPE (RC32365_REG_BASE + 0x0001c)
++ if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
++ if (baud < 2400)
++ fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
++ else
++ fcr = uart_config[up->port.type].fcr;
++ }
+
-+/* Reset Controller */
-+#define RESET_CNTL (RC32365_REG_BASE + 0x08000)
-+#define BOOT_VECTOR (RC32365_REG_BASE + 0x08004)
++ /*
++ * MCR-based auto flow control. When AFE is enabled, RTS will be
++ * deasserted when the receive FIFO contains more characters than
++ * the trigger, or the MCR RTS bit is cleared. In the case where
++ * the remote UART is not using CTS auto flow control, we must
++ * have sufficient FIFO entries for the latency of the remote
++ * UART to respond. IOW, at least 32 bytes of FIFO.
++ */
++ if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
++ up->mcr &= ~UART_MCR_AFE;
++ if (termios->c_cflag & CRTSCTS)
++ up->mcr |= UART_MCR_AFE;
++ }
+
-+/* Device Controller */
-+#define DEV0_BASE (RC32365_REG_BASE + 0x10000)
-+#define DEV0_MASK (RC32365_REG_BASE + 0x10004)
-+#define DEV0_CNTL (RC32365_REG_BASE + 0x10008)
-+#define DEV0_TIMING (RC32365_REG_BASE + 0x1000c)
-+#define DEV_REG_OFFSET 0x10
++ /*
++ * Ok, we're now changing the port state. Do it with
++ * interrupts disabled.
++ */
++ spin_lock_irqsave(&up->port.lock, flags);
+
-+/* SDRAM Controller */
-+#define SDRAM0_BASE (RC32365_REG_BASE + 0x18000)
-+#define SDRAM0_MASK (RC32365_REG_BASE + 0x18004)
-+#define SDRAM1_BASE (RC32365_REG_BASE + 0x18008)
-+#define SDRAM1_MASK (RC32365_REG_BASE + 0x1800c)
-+#define SDRAM_CNTL (RC32365_REG_BASE + 0x18010)
++ /*
++ * Update the per-port timeout.
++ */
++ uart_update_timeout(port, termios->c_cflag, baud);
+
-+/* Counters/Timers */
-+#define TIMER0_COUNT (RC32365_REG_BASE + 0x20000)
-+#define TIMER0_COMPARE (RC32365_REG_BASE + 0x20004)
-+#define TIMER0_CNTL (RC32365_REG_BASE + 0x20008)
-+#define TIMER0_SELECT (RC32365_REG_BASE + 0x2000c)
-+#define TIMER_REG_OFFSET 0x10
++ up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
++ if (termios->c_iflag & INPCK)
++ up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
++ if (termios->c_iflag & (BRKINT | PARMRK))
++ up->port.read_status_mask |= UART_LSR_BI;
+
-+/* System Integrity */
++ /*
++ * Characteres to ignore
++ */
++ up->port.ignore_status_mask = 0;
++ if (termios->c_iflag & IGNPAR)
++ up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
++ if (termios->c_iflag & IGNBRK) {
++ up->port.ignore_status_mask |= UART_LSR_BI;
++ /*
++ * If we're ignoring parity and break indicators,
++ * ignore overruns too (for real raw support).
++ */
++ if (termios->c_iflag & IGNPAR)
++ up->port.ignore_status_mask |= UART_LSR_OE;
++ }
+
-+/* Interrupt Controller */
-+#define IC_GROUP0_PEND (RC32365_REG_BASE + 0x30000)
-+#define IC_GROUP0_TEST (RC32365_REG_BASE + 0x30004)
-+#define IC_GROUP0_MASK (RC32365_REG_BASE + 0x30008)
-+#define IC_GROUP_OFFSET 0x0c
++ /*
++ * ignore all characters if CREAD is not set
++ */
++ if ((termios->c_cflag & CREAD) == 0)
++ up->port.ignore_status_mask |= UART_LSR_DR;
+
-+#define NUM_INTR_GROUPS 5
-+/*
-+ * The IRQ mapping is as follows:
-+ *
-+ * IRQ Mapped To
-+ * --- -------------------
-+ * 0 SW0 (IP0) SW0 intr
-+ * 1 SW1 (IP1) SW1 intr
-+ * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
-+ * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
-+ * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
-+ * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
-+ * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
-+ * 7 Int5 (IP7) CP0 Timer
-+ *
-+ * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
-+ * internally on the RC32365 is routed to the Expansion
-+ * Interrupt Controller.
-+ */
-+#define MIPS_CPU_TIMER_IRQ 7
++ /*
++ * CTS flow control flag and modem status interrupts
++ */
++ up->ier &= ~UART_IER_MSI;
++ if (!(up->bugs & UART_BUG_NOMSR) &&
++ UART_ENABLE_MS(&up->port, termios->c_cflag))
++ up->ier |= UART_IER_MSI;
++ if (up->capabilities & UART_CAP_UUE)
++ up->ier |= UART_IER_UUE | UART_IER_RTOIE;
++
++ serial_out(up, UART_IER, up->ier);
++
++ if (up->capabilities & UART_CAP_EFR) {
++ unsigned char efr = 0;
++ /*
++ * TI16C752/Startech hardware flow control. FIXME:
++ * - TI16C752 requires control thresholds to be set.
++ * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
++ */
++ if (termios->c_cflag & CRTSCTS)
++ efr |= UART_EFR_CTS;
++
++ serial_outp(up, UART_LCR, 0xBF);
++ serial_outp(up, UART_EFR, efr);
++ }
+
-+#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
-+#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
-+#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // RNG, SEC
-+#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
-+#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
++#ifdef CONFIG_ARCH_OMAP15XX
++ /* Workaround to enable 115200 baud on OMAP1510 internal ports */
++ if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
++ if (baud == 115200) {
++ quot = 1;
++ serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
++ } else
++ serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
++ }
++#endif
+
-+#define RC32365_NR_IRQS (GROUP4_IRQ_BASE + 32)
++ if (up->capabilities & UART_NATSEMI) {
++ /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
++ serial_outp(up, UART_LCR, 0xe0);
++ } else {
++ serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
++ }
+
-+/* DMA - see rc32365_dma.h for full list of registers */
++ serial_dl_write(up, quot);
+
-+#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
-+#define DMA_CHAN_OFFSET 0x14
++ /*
++ * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
++ * is written without DLAB set, this mode will be disabled.
++ */
++ if (up->port.type == PORT_16750)
++ serial_outp(up, UART_FCR, fcr);
++
++ serial_outp(up, UART_LCR, cval); /* reset DLAB */
++ up->lcr = cval; /* Save LCR */
++ if (up->port.type != PORT_16750) {
++ if (fcr & UART_FCR_ENABLE_FIFO) {
++ /* emulated UARTs (Lucent Venus 167x) need two steps */
++ serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
++ }
++ serial_outp(up, UART_FCR, fcr); /* set fcr */
++ }
++ serial8250_set_mctrl(&up->port, up->port.mctrl);
++ spin_unlock_irqrestore(&up->port.lock, flags);
++}
+
-+/* GPIO Controller */
-+#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
++static void
++serial8250_pm(struct uart_port *port, unsigned int state,
++ unsigned int oldstate)
++{
++ struct uart_8250_port *p = (struct uart_8250_port *)port;
+
-+/* 16550 UARTs */
-+#ifdef __MIPSEB__
-+#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
-+#else
-+#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
-+#endif
-+#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 0)
++ serial8250_set_sleep(p, state != 0);
+
-+/* Ethernet - see rc32365_eth.h for full list of registers */
++ if (p->pm)
++ p->pm(port, state, oldstate);
++}
+
-+#define RC32365_ETH_BASE (RC32365_REG_BASE + 0x58000)
++/*
++ * Resource handling.
++ */
++static int serial8250_request_std_resource(struct uart_8250_port *up)
++{
++ unsigned int size = 8 << up->port.regshift;
++ int ret = 0;
++
++ switch (up->port.iotype) {
++ case UPIO_AU:
++ size = 0x100000;
++ /* fall thru */
++ case UPIO_TSI:
++ case UPIO_MEM32:
++ case UPIO_MEM:
++ if (!up->port.mapbase)
++ break;
+
-+#define IDT_CLOCK_MULT 2
++ if (!request_mem_region(up->port.mapbase, size, "serial")) {
++ ret = -EBUSY;
++ break;
++ }
+
-+/* FLASH (device 1) */
-+#define FLASH_BASE 0x08000000
-+#define FLASH_SIZE 0x00800000
++ if (up->port.flags & UPF_IOREMAP) {
++ up->port.membase = ioremap(up->port.mapbase, size);
++ if (!up->port.membase) {
++ release_mem_region(up->port.mapbase, size);
++ ret = -ENOMEM;
++ }
++ }
++ break;
+
-+/* LCD 4-digit display (device 2) */
-+#define LCD_DIGIT0 0x0C000003
-+#define LCD_DIGIT1 0x0C000002
-+#define LCD_DIGIT2 0x0C000001
-+#define LCD_DIGIT3 0x0C000000
++ case UPIO_HUB6:
++ case UPIO_PORT:
++ if (!request_region(up->port.iobase, size, "serial"))
++ ret = -EBUSY;
++ break;
++ }
++ return ret;
++}
+
-+/* RTC (DS1553) (device 2) */
-+#define RTC_BASE 0x0c800000
-+/* NVRAM */
-+#define NVRAM_BASE RTC_BASE
-+#define NVRAM_ENVSIZE_OFF 4
-+#define NVRAM_ENVSTART_OFF 32
++static void serial8250_release_std_resource(struct uart_8250_port *up)
++{
++ unsigned int size = 8 << up->port.regshift;
+
-+/* Interrupts routed on 79EB365 board */
-+#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE + 8)
-+#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE + 9)
-+#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
-+#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
++ switch (up->port.iotype) {
++ case UPIO_AU:
++ size = 0x100000;
++ /* fall thru */
++ case UPIO_TSI:
++ case UPIO_MEM32:
++ case UPIO_MEM:
++ if (!up->port.mapbase)
++ break;
+
-+#define RAM_SIZE (32 * 1024 * 1024)
++ if (up->port.flags & UPF_IOREMAP) {
++ iounmap(up->port.membase);
++ up->port.membase = NULL;
++ }
+
-+#endif //__IDT_RC32365_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,515 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Datatype declaration for IDT 79EB365/336 PCI
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ release_mem_region(up->port.mapbase, size);
++ break;
+
-+#ifndef __IDT_RC32365_PCI_H__
-+#define __IDT_RC32365_PCI_H__
++ case UPIO_HUB6:
++ case UPIO_PORT:
++ release_region(up->port.iobase, size);
++ break;
++ }
++}
+
-+enum
++static int serial8250_request_rsa_resource(struct uart_8250_port *up)
+{
-+ PCI0_PhysicalAddress = 0x18068000,
-+ PCI_PhysicalAddress = PCI0_PhysicalAddress,
-+
-+ PCI0_VirtualAddress = 0xb8068000,
-+ PCI_VirtualAddress = PCI0_VirtualAddress,
-+} ;
++ unsigned long start = UART_RSA_BASE << up->port.regshift;
++ unsigned int size = 8 << up->port.regshift;
++ int ret = -EINVAL;
+
-+enum
-+{
-+ PCI_LbaCount = 4, // Local base addresses.
-+} ;
++ switch (up->port.iotype) {
++ case UPIO_HUB6:
++ case UPIO_PORT:
++ start += up->port.iobase;
++ if (request_region(start, size, "serial-rsa"))
++ ret = 0;
++ else
++ ret = -EBUSY;
++ break;
++ }
+
-+typedef struct
-+{
-+ u32 a ; // Address.
-+ u32 c ; // Control.
-+ u32 m ; // mapping.
-+} PCI_Map_s ;
++ return ret;
++}
+
-+typedef struct
++static void serial8250_release_rsa_resource(struct uart_8250_port *up)
+{
-+ u32 pcic ;
-+ u32 pcis ;
-+ u32 pcism ;
-+ u32 pcicfga ;
-+ u32 pcicfgd ;
-+ PCI_Map_s pcilba [PCI_LbaCount] ;
-+ u32 pcidac ;
-+ u32 pcidas ;
-+ u32 pcidasm ;
-+ u32 pcidad ;
-+ u32 pcidma8c ;
-+ u32 pcidma9c ;
-+ u32 pcitc ;
-+} volatile *PCI_t ;
-+
-+// PCI messaging unit.
-+enum
-+{
-+ PCIM_Count = 2,
-+} ;
-+typedef struct
++ unsigned long offset = UART_RSA_BASE << up->port.regshift;
++ unsigned int size = 8 << up->port.regshift;
++
++ switch (up->port.iotype) {
++ case UPIO_HUB6:
++ case UPIO_PORT:
++ release_region(up->port.iobase + offset, size);
++ break;
++ }
++}
++
++static void serial8250_release_port(struct uart_port *port)
+{
-+ u32 pciim [PCIM_Count] ;
-+ u32 pciom [PCIM_Count] ;
-+ u32 pciid ;
-+ u32 pciiic ;
-+ u32 pciiim ;
-+ u32 pciiod ;
-+ u32 pciioic ;
-+ u32 pciioim ;
-+} volatile *PCIM_t ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Control Register
-+ *
-+ ******************************************************************************/
-+enum
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++
++ serial8250_release_std_resource(up);
++ if (up->port.type == PORT_RSA)
++ serial8250_release_rsa_resource(up);
++}
++
++static int serial8250_request_port(struct uart_port *port)
+{
-+ PCIC_en_b = 0,
-+ PCIC_en_m = 0x00000001,
-+ PCIC_tnr_b = 1,
-+ PCIC_tnr_m = 0x00000002,
-+ PCIC_sce_b = 2,
-+ PCIC_sce_m = 0x00000004,
-+ PCIC_ien_b = 3,
-+ PCIC_ien_m = 0x00000008,
-+ PCIC_aaa_b = 4,
-+ PCIC_aaa_m = 0x00000010,
-+ PCIC_eap_b = 5,
-+ PCIC_eap_m = 0x00000020,
-+ PCIC_pcim_b = 6,
-+ PCIC_pcim_m = 0x000001c0,
-+ PCIC_pcim_disabled_v = 0,
-+ PCIC_pcim_tnr_v = 1, // Satellite - target not ready
-+ PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
-+ PCIC_pcim_extern_v = 3, // Host - external arbiter.
-+ PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
-+ PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
-+ PCIC_pcim_reserved6_v = 6,
-+ PCIC_pcim_reserved7_v = 7,
-+ PCIC_igm_b = 9,
-+ PCIC_igm_m = 0x00000200,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Status Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIS_eed_b = 0,
-+ PCIS_eed_m = 0x00000001,
-+ PCIS_wr_b = 1,
-+ PCIS_wr_m = 0x00000002,
-+ PCIS_nmi_b = 2,
-+ PCIS_nmi_m = 0x00000004,
-+ PCIS_ii_b = 3,
-+ PCIS_ii_m = 0x00000008,
-+ PCIS_cwe_b = 4,
-+ PCIS_cwe_m = 0x00000010,
-+ PCIS_cre_b = 5,
-+ PCIS_cre_m = 0x00000020,
-+ PCIS_mdpe_b = 6,
-+ PCIS_mdpe_m = 0x00000040,
-+ PCIS_sta_b = 7,
-+ PCIS_sta_m = 0x00000080,
-+ PCIS_rta_b = 8,
-+ PCIS_rta_m = 0x00000100,
-+ PCIS_rma_b = 9,
-+ PCIS_rma_m = 0x00000200,
-+ PCIS_sse_b = 10,
-+ PCIS_sse_m = 0x00000400,
-+ PCIS_ose_b = 11,
-+ PCIS_ose_m = 0x00000800,
-+ PCIS_pe_b = 12,
-+ PCIS_pe_m = 0x00001000,
-+ PCIS_tae_b = 13,
-+ PCIS_tae_m = 0x00002000,
-+ PCIS_rle_b = 14,
-+ PCIS_rle_m = 0x00004000,
-+ PCIS_bme_b = 15,
-+ PCIS_bme_m = 0x00008000,
-+ PCIS_prd_b = 16,
-+ PCIS_prd_m = 0x00010000,
-+ PCIS_rip_b = 17,
-+ PCIS_rip_m = 0x00020000,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Status Mask Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCISM_eed_b = 0,
-+ PCISM_eed_m = 0x00000001,
-+ PCISM_wr_b = 1,
-+ PCISM_wr_m = 0x00000002,
-+ PCISM_nmi_b = 2,
-+ PCISM_nmi_m = 0x00000004,
-+ PCISM_ii_b = 3,
-+ PCISM_ii_m = 0x00000008,
-+ PCISM_cwe_b = 4,
-+ PCISM_cwe_m = 0x00000010,
-+ PCISM_cre_b = 5,
-+ PCISM_cre_m = 0x00000020,
-+ PCISM_mdpe_b = 6,
-+ PCISM_mdpe_m = 0x00000040,
-+ PCISM_sta_b = 7,
-+ PCISM_sta_m = 0x00000080,
-+ PCISM_rta_b = 8,
-+ PCISM_rta_m = 0x00000100,
-+ PCISM_rma_b = 9,
-+ PCISM_rma_m = 0x00000200,
-+ PCISM_sse_b = 10,
-+ PCISM_sse_m = 0x00000400,
-+ PCISM_ose_b = 11,
-+ PCISM_ose_m = 0x00000800,
-+ PCISM_pe_b = 12,
-+ PCISM_pe_m = 0x00001000,
-+ PCISM_tae_b = 13,
-+ PCISM_tae_m = 0x00002000,
-+ PCISM_rle_b = 14,
-+ PCISM_rle_m = 0x00004000,
-+ PCISM_bme_b = 15,
-+ PCISM_bme_m = 0x00008000,
-+ PCISM_prd_b = 16,
-+ PCISM_prd_m = 0x00010000,
-+ PCISM_rip_b = 17,
-+ PCISM_rip_m = 0x00020000,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Configuration Address Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCICFGA_reg_b = 2,
-+ PCICFGA_reg_m = 0x000000fc,
-+ PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
-+ PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
-+ PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
-+ PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
-+ PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
-+ PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
-+ PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
-+ PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
-+ PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
-+ PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
-+ PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba0m_v = 0x48>>2,
-+ PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba1m_v = 0x50>>2,
-+ PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba2m_v = 0x58>>2,
-+ PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba3m_v = 0x60>>2,
-+ PCICFGA_reg_pmgt_v = 0x64>>2,
-+ PCICFGA_func_b = 8,
-+ PCICFGA_func_m = 0x00000700,
-+ PCICFGA_dev_b = 11,
-+ PCICFGA_dev_m = 0x0000f800,
-+ PCICFGA_dev_internal_v = 0,
-+ PCICFGA_bus_b = 16,
-+ PCICFGA_bus_m = 0x00ff0000,
-+ PCICFGA_bus_type0_v = 0, //local bus
-+ PCICFGA_en_b = 31, // read only
-+ PCICFGA_en_m = 0x80000000,
-+} ;
-+
-+enum {
-+ PCFGID_vendor_b = 0,
-+ PCFGID_vendor_m = 0x0000ffff,
-+ PCFGID_vendor_IDT_v = 0x111d,
-+ PCFGID_device_b = 16,
-+ PCFGID_device_m = 0xffff0000,
-+ PCFGID_device_Acaciade_v = 0x0207,
-+
-+ PCFG04_command_ioena_b = 1,
-+ PCFG04_command_ioena_m = 0x00000001,
-+ PCFG04_command_memena_b = 2,
-+ PCFG04_command_memena_m = 0x00000002,
-+ PCFG04_command_bmena_b = 3,
-+ PCFG04_command_bmena_m = 0x00000004,
-+ PCFG04_command_mwinv_b = 5,
-+ PCFG04_command_mwinv_m = 0x00000010,
-+ PCFG04_command_parena_b = 7,
-+ PCFG04_command_parena_m = 0x00000040,
-+ PCFG04_command_serrena_b = 9,
-+ PCFG04_command_serrena_m = 0x00000100,
-+ PCFG04_command_fastbbena_b = 10,
-+ PCFG04_command_fastbbena_m = 0x00000200,
-+ PCFG04_status_b = 16,
-+ PCFG04_status_m = 0xffff0000,
-+ PCFG04_status_66MHz_b = 21, // 66 MHz enable
-+ PCFG04_status_66MHz_m = 0x00200000,
-+ PCFG04_status_fbb_b = 23,
-+ PCFG04_status_fbb_m = 0x00800000,
-+ PCFG04_status_mdpe_b = 24,
-+ PCFG04_status_mdpe_m = 0x01000000,
-+ PCFG04_status_dst_b = 25,
-+ PCFG04_status_dst_m = 0x06000000,
-+ PCFG04_status_sta_b = 27,
-+ PCFG04_status_sta_m = 0x08000000,
-+ PCFG04_status_rta_b = 28,
-+ PCFG04_status_rta_m = 0x10000000,
-+ PCFG04_status_rma_b = 29,
-+ PCFG04_status_rma_m = 0x20000000,
-+ PCFG04_status_sse_b = 30,
-+ PCFG04_status_sse_m = 0x40000000,
-+ PCFG04_status_pe_b = 31,
-+ PCFG04_status_pe_m = 0x40000000,
-+
-+ PCFG08_revId_b = 0,
-+ PCFG08_revId_m = 0x000000ff,
-+ PCFG08_classCode_b = 0,
-+ PCFG08_classCode_m = 0xffffff00,
-+ PCFG08_classCode_bridge_v = 06,
-+ PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
-+ PCFG0C_cacheline_b = 0,
-+ PCFG0C_cacheline_m = 0x000000ff,
-+ PCFG0C_masterLatency_b = 8,
-+ PCFG0C_masterLatency_m = 0x0000ff00,
-+ PCFG0C_headerType_b = 16,
-+ PCFG0C_headerType_m = 0x00ff0000,
-+ PCFG0C_bist_b = 24,
-+ PCFG0C_bist_m = 0xff000000,
-+
-+ PCIPBA_msi_b = 0,
-+ PCIPBA_msi_m = 0x00000001,
-+ PCIPBA_p_b = 3,
-+ PCIPBA_p_m = 0x00000004,
-+ PCIPBA_baddr_b = 8,
-+ PCIPBA_baddr_m = 0xffffff00,
-+
-+ PCFGSS_vendorId_b = 0,
-+ PCFGSS_vendorId_m = 0x0000ffff,
-+ PCFGSS_id_b = 16,
-+ PCFGSS_id_m = 0xffff0000,
-+
-+ PCFG3C_interruptLine_b = 0,
-+ PCFG3C_interruptLine_m = 0x000000ff,
-+ PCFG3C_interruptPin_b = 8,
-+ PCFG3C_interruptPin_m = 0x0000ff00,
-+ PCFG3C_minGrant_b = 16,
-+ PCFG3C_minGrant_m = 0x00ff0000,
-+ PCFG3C_maxLat_b = 24,
-+ PCFG3C_maxLat_m = 0xff000000,
-+
-+ PCIPBAC_msi_b = 0,
-+ PCIPBAC_msi_m = 0x00000001,
-+ PCIPBAC_p_b = 1,
-+ PCIPBAC_p_m = 0x00000002,
-+ PCIPBAC_size_b = 2,
-+ PCIPBAC_size_m = 0x0000007c,
-+ PCIPBAC_sb_b = 7,
-+ PCIPBAC_sb_m = 0x00000080,
-+ PCIPBAC_pp_b = 8,
-+ PCIPBAC_pp_m = 0x00000100,
-+ PCIPBAC_mr_b = 9,
-+ PCIPBAC_mr_m = 0x00000600,
-+ PCIPBAC_mr_read_v =0, //no prefetching
-+ PCIPBAC_mr_readLine_v =1,
-+ PCIPBAC_mr_readMult_v =2,
-+ PCIPBAC_mrl_b = 11,
-+ PCIPBAC_mrl_m = 0x00000800,
-+ PCIPBAC_mrm_b = 12,
-+ PCIPBAC_mrm_m = 0x00001000,
-+ PCIPBAC_trp_b = 13,
-+ PCIPBAC_trp_m = 0x00002000,
-+
-+ PCFG40_trdyTimeout_b = 0,
-+ PCFG40_trdyTimeout_m = 0x000000ff,
-+ PCFG40_retryLim_b = 8,
-+ PCFG40_retryLim_m = 0x0000ff00,
-+};
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++ int ret = 0;
+
-+/*******************************************************************************
-+ *
-+ * PCI Local Base Address [0|1|2|3] Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
-+ PCILBA_baddr_m = 0xffffff00,
-+} ;
-+/*******************************************************************************
-+ *
-+ * PCI Local Base Address Control Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
-+ PCILBAC_msi_m = 0x00000001,
-+ PCILBAC_msi_mem_v = 0,
-+ PCILBAC_msi_io_v = 1,
-+ PCILBAC_size_b = 2, // In pPci->pcilba[i].c
-+ PCILBAC_size_m = 0x0000007c,
-+ PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
-+ PCILBAC_sb_m = 0x00000080,
-+ PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
-+ PCILBAC_rt_m = 0x00000100,
-+ PCILBAC_rt_noprefetch_v = 0, // mem read
-+ PCILBAC_rt_prefetch_v = 1, // mem readline
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Local Base Address [0|1|2|3] Mapping Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCILBAM_maddr_b = 8,
-+ PCILBAM_maddr_m = 0xffffff00,
-+} ;
++ ret = serial8250_request_std_resource(up);
++ if (ret == 0 && up->port.type == PORT_RSA) {
++ ret = serial8250_request_rsa_resource(up);
++ if (ret < 0)
++ serial8250_release_std_resource(up);
++ }
+
-+/*******************************************************************************
-+ *
-+ * PCI Decoupled Access Control Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIDAC_den_b = 0,
-+ PCIDAC_den_m = 0x00000001,
-+} ;
++ return ret;
++}
+
-+/*******************************************************************************
-+ *
-+ * PCI Decoupled Access Status Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIDAS_d_b = 0,
-+ PCIDAS_d_m = 0x00000001,
-+ PCIDAS_b_b = 1,
-+ PCIDAS_b_m = 0x00000002,
-+ PCIDAS_e_b = 2,
-+ PCIDAS_e_m = 0x00000004,
-+ PCIDAS_ofe_b = 3,
-+ PCIDAS_ofe_m = 0x00000008,
-+ PCIDAS_off_b = 4,
-+ PCIDAS_off_m = 0x00000010,
-+ PCIDAS_ife_b = 5,
-+ PCIDAS_ife_m = 0x00000020,
-+ PCIDAS_iff_b = 6,
-+ PCIDAS_iff_m = 0x00000040,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI DMA Channel 8 Configuration Register
-+ *
-+ ******************************************************************************/
-+enum
++static void serial8250_config_port(struct uart_port *port, int flags)
+{
-+ PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
-+ PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
-+ PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
-+ PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
-+} ;
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
++ int probeflags = PROBE_ANY;
++ int ret;
+
-+/*******************************************************************************
-+ *
-+ * PCI DMA Channel 9 Configuration Register
-+ *
-+ ******************************************************************************/
-+enum
++ /*
++ * Find the region that we can probe for. This in turn
++ * tells us whether we can probe for the type of port.
++ */
++ ret = serial8250_request_std_resource(up);
++ if (ret < 0)
++ return;
++
++ ret = serial8250_request_rsa_resource(up);
++ if (ret < 0)
++ probeflags &= ~PROBE_RSA;
++
++ if (flags & UART_CONFIG_TYPE)
++ autoconfig(up, probeflags);
++ if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
++ autoconfig_irq(up);
++
++ if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
++ serial8250_release_rsa_resource(up);
++ if (up->port.type == PORT_UNKNOWN)
++ serial8250_release_std_resource(up);
++}
++
++static int
++serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
-+ PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
-+ PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
-+} ;
++ if (ser->irq >= NR_IRQS || ser->irq < 0 ||
++ ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
++ ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
++ ser->type == PORT_STARTECH)
++ return -EINVAL;
++ return 0;
++}
+
-+/*******************************************************************************
-+ *
-+ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
-+ PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
-+ // These are for reads (DMA channel 8)
-+ PCIDMAD_devcmd_mr_v = 0, //memory read
-+ PCIDMAD_devcmd_mrl_v = 1, //memory read line
-+ PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
-+ PCIDMAD_devcmd_ior_v = 3, //I/O read
-+ // These are for writes (DMA channel 9)
-+ PCIDMAD_devcmd_mw_v = 0, //memory write
-+ PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
-+ PCIDMAD_devcmd_iow_v = 3, //I/O write
-+
-+ // Swap byte field applies to both DMA channel 8 and 9
-+ PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
-+ PCIDMAD_sb_m = 0x01000000, // swap byte field
-+} ;
++static const char *
++serial8250_type(struct uart_port *port)
++{
++ int type = port->type;
+
++ if (type >= ARRAY_SIZE(uart_config))
++ type = 0;
++ return uart_config[type].name;
++}
+
-+/*******************************************************************************
-+ *
-+ * PCI Target Control Register
-+ *
-+ ******************************************************************************/
-+enum
-+{
-+ PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
-+ PCITC_rtimer_m = 0x000000ff,
-+ PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
-+ PCITC_dtimer_m = 0x0000ff00,
-+ PCITC_rdr_b = 18, // In PCITC_t -> pcitc
-+ PCITC_rdr_m = 0x00040000,
-+ PCITC_ddt_b = 19, // In PCITC_t -> pcitc
-+ PCITC_ddt_m = 0x00080000,
-+} ;
-+/*******************************************************************************
-+ *
-+ * PCI messaging unit [applies to both inbound and outbound registers ]
-+ *
-+ ******************************************************************************/
-+enum
-+{
-+ PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
-+ PCIM_m0_m = 0x00000001, // inbound or outbound message 0
-+ PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
-+ PCIM_m1_m = 0x00000002, // inbound or outbound message 1
-+ PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
-+ PCIM_db_m = 0x00000004, // inbound or outbound doorbell
++static struct uart_ops serial8250_pops = {
++ .tx_empty = serial8250_tx_empty,
++ .set_mctrl = serial8250_set_mctrl,
++ .get_mctrl = serial8250_get_mctrl,
++ .stop_tx = serial8250_stop_tx,
++ .start_tx = serial8250_start_tx,
++ .stop_rx = serial8250_stop_rx,
++ .enable_ms = serial8250_enable_ms,
++ .break_ctl = serial8250_break_ctl,
++ .startup = serial8250_startup,
++ .shutdown = serial8250_shutdown,
++ .set_termios = serial8250_set_termios,
++ .pm = serial8250_pm,
++ .type = serial8250_type,
++ .release_port = serial8250_release_port,
++ .request_port = serial8250_request_port,
++ .config_port = serial8250_config_port,
++ .verify_port = serial8250_verify_port,
+};
+
++static struct uart_8250_port serial8250_ports[UART_NR];
+
-+#endif // __IDT_RC32365_PCI_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,217 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * PCI header values for IDT 79EB365/336
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++static void __init serial8250_isa_init_ports(void)
++{
++ struct uart_8250_port *up;
++ static int first = 1;
++ int i;
+
-+#ifndef __IDT_RC32365_PCI_V_H__
-+#define __IDT_RC32365_PCI_V_H__
-+
-+
-+#define PCI_MSG_VirtualAddress 0xB806C010
-+#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
-+#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
-+
-+#define PCIM_SHFT 0x6
-+#define PCIM_BIT_LEN 0x7
-+#define PCIM_H_EA 0x3
-+#define PCIM_H_IA_FIX 0x4
-+#define PCIM_H_IA_RR 0x5
-+
-+#define PCI_ADDR_START 0x50000000
-+
-+#define CPUTOPCI_MEM_WIN 0x02000000
-+#define CPUTOPCI_IO_WIN 0x00100000
-+#define PCILBA_SIZE_SHFT 2
-+#define PCILBA_SIZE_MASK 0x1F
-+#define SIZE_256MB 0x1C
-+#define SIZE_128MB 0x1B
-+#define SIZE_64MB 0x1A
-+#define SIZE_32MB 0x19
-+#define SIZE_16MB 0x18
-+#define SIZE_4MB 0x16
-+#define SIZE_2MB 0x15
-+#define SIZE_1MB 0x14
-+#define CEDAR_CONFIG0_ADDR 0x80000000
-+#define CEDAR_CONFIG1_ADDR 0x80000004
-+#define CEDAR_CONFIG2_ADDR 0x80000008
-+#define CEDAR_CONFIG3_ADDR 0x8000000C
-+#define CEDAR_CONFIG4_ADDR 0x80000010
-+#define CEDAR_CONFIG5_ADDR 0x80000014
-+#define CEDAR_CONFIG6_ADDR 0x80000018
-+#define CEDAR_CONFIG7_ADDR 0x8000001C
-+#define CEDAR_CONFIG8_ADDR 0x80000020
-+#define CEDAR_CONFIG9_ADDR 0x80000024
-+#define CEDAR_CONFIG10_ADDR 0x80000028
-+#define CEDAR_CONFIG11_ADDR 0x8000002C
-+#define CEDAR_CONFIG12_ADDR 0x80000030
-+#define CEDAR_CONFIG13_ADDR 0x80000034
-+#define CEDAR_CONFIG14_ADDR 0x80000038
-+#define CEDAR_CONFIG15_ADDR 0x8000003C
-+#define CEDAR_CONFIG16_ADDR 0x80000040
-+#define CEDAR_CONFIG17_ADDR 0x80000044
-+#define CEDAR_CONFIG18_ADDR 0x80000048
-+#define CEDAR_CONFIG19_ADDR 0x8000004C
-+#define CEDAR_CONFIG20_ADDR 0x80000050
-+#define CEDAR_CONFIG21_ADDR 0x80000054
-+#define CEDAR_CONFIG22_ADDR 0x80000058
-+#define CEDAR_CONFIG23_ADDR 0x8000005C
-+#define CEDAR_CONFIG24_ADDR 0x80000060
-+#define CEDAR_CONFIG25_ADDR 0x80000064
-+#define CEDAR_CMD (PCFG04_command_ioena_m | \
-+ PCFG04_command_memena_m | \
-+ PCFG04_command_bmena_m | \
-+ PCFG04_command_mwinv_m | \
-+ PCFG04_command_parena_m | \
-+ PCFG04_command_serrena_m )
-+
-+#define CEDAR_STAT (PCFG04_status_mdpe_m | \
-+ PCFG04_status_sta_m | \
-+ PCFG04_status_rta_m | \
-+ PCFG04_status_rma_m | \
-+ PCFG04_status_sse_m | \
-+ PCFG04_status_pe_m)
-+
-+#define CEDAR_CNFG1 ((CEDAR_STAT << 16) | \
-+ CEDAR_CMD)
-+
-+#define CEDAR_REVID 0
-+#define CEDAR_CLASS_CODE 0
-+#define CEDAR_CNFG2 ((CEDAR_CLASS_CODE << 8) | \
-+ CEDAR_REVID)
-+
-+#define CEDAR_CACHE_LINE_SIZE 4
-+#define CEDAR_MASTER_LAT 0x3c
-+#define CEDAR_HEADER_TYPE 0
-+#define CEDAR_BIST 0
-+
-+#define CEDAR_CNFG3 ((CEDAR_BIST << 24) | \
-+ (CEDAR_HEADER_TYPE << 16) | \
-+ (CEDAR_MASTER_LAT << 8) | \
-+ CEDAR_CACHE_LINE_SIZE)
-+
-+#define CEDAR_BAR0 0x00000008 /* 128 MB Memory */
-+#define CEDAR_BAR1 0x18800001 /* 1 MB IO */
-+#define CEDAR_BAR2 0x18000001 /* 2 MB IO window for Cedar
-+ internal Registers */
-+#define CEDAR_BAR3 0x48000008 /* Spare 128 MB Memory */
-+
-+#define CEDAR_CNFG4 CEDAR_BAR0
-+#define CEDAR_CNFG5 CEDAR_BAR1
-+#define CEDAR_CNFG6 CEDAR_BAR2
-+#define CEDAR_CNFG7 CEDAR_BAR3
-+
-+#define CEDAR_SUBSYS_VENDOR_ID 0
-+#define CEDAR_SUBSYSTEM_ID 0
-+#define CEDAR_CNFG8 0
-+#define CEDAR_CNFG9 0
-+#define CEDAR_CNFG10 0
-+#define CEDAR_CNFG11 ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
-+ CEDAR_SUBSYSTEM_ID)
-+#define CEDAR_INT_LINE 1
-+#define CEDAR_INT_PIN 1
-+#define CEDAR_MIN_GNT 8
-+#define CEDAR_MAX_LAT 0x38
-+#define CEDAR_CNFG12 0
-+#define CEDAR_CNFG13 0
-+#define CEDAR_CNFG14 0
-+#define CEDAR_CNFG15 ((CEDAR_MAX_LAT << 24) | \
-+ (CEDAR_MIN_GNT << 16) | \
-+ (CEDAR_INT_PIN << 8) | \
-+ CEDAR_INT_LINE)
-+#define CEDAR_RETRY_LIMIT 0x80
-+#define CEDAR_TRDY_LIMIT 0x80
-+#define CEDAR_CNFG16 ((CEDAR_RETRY_LIMIT << 8) | \
-+ CEDAR_TRDY_LIMIT)
-+#define PCI_PBAxC_R 0x0
-+#define PCI_PBAxC_RL 0x1
-+#define PCI_PBAxC_RM 0x2
-+#define SIZE_SHFT 2
-+#ifdef __MIPSEB__
-+#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
-+ PCIPBAC_pp_m | \
-+ PCIPBAC_sb_m | \
-+ (SIZE_128MB << SIZE_SHFT) | \
-+ PCIPBAC_p_m)
-+#else
++ if (!first)
++ return;
++ first = 0;
+
-+#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
-+ PCIPBAC_pp_m | \
-+ (SIZE_128MB << SIZE_SHFT) | \
-+ PCIPBAC_p_m)
-+#endif
-+#define CEDAR_CNFG17 CEDAR_PBA0C
-+#define CEDAR_PBA0M 0x0
-+#define CEDAR_CNFG18 CEDAR_PBA0M
++ for (i = 0; i < nr_uarts; i++) {
++ struct uart_8250_port *up = &serial8250_ports[i];
+
-+#ifdef __MIPSEB__
-+#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
-+ PCIPBAC_sb_m | \
-+ PCIPBAC_msi_m)
-+#else
-+#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
-+ PCIPBAC_msi_m)
-+#endif
-+#define CEDAR_CNFG19 CEDAR_PBA1C
-+#define CEDAR_PBA1M 0x0
-+#define CEDAR_CNFG20 CEDAR_PBA1M
++ up->port.line = i;
++ spin_lock_init(&up->port.lock);
+
-+#ifdef __MIPSEB__
-+#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
-+ PCIPBAC_sb_m | \
-+ PCIPBAC_msi_m)
-+#else
-+#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
-+ PCIPBAC_msi_m)
-+#endif
++ init_timer(&up->timer);
++ up->timer.function = serial8250_timeout;
+
-+#define CEDAR_CNFG21 CEDAR_PBA2C
-+#define CEDAR_PBA2M 0x18000000
-+#define CEDAR_CNFG22 CEDAR_PBA2M
++ /*
++ * ALPHA_KLUDGE_MCR needs to be killed.
++ */
++ up->mcr_mask = ~ALPHA_KLUDGE_MCR;
++ up->mcr_force = ALPHA_KLUDGE_MCR;
+
-+#ifdef __MIPSEB__
-+#define CEDAR_PBA3C PCIPBAC_sb_m
-+#else
-+#define CEDAR_PBA3C 0
-+#endif
++ up->port.ops = &serial8250_pops;
++ }
+
-+#define CEDAR_CNFG23 CEDAR_PBA3C
-+#define CEDAR_PBA3M 0
-+#define CEDAR_CNFG24 CEDAR_PBA3M
++ for (i = 0, up = serial8250_ports;
++ i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
++ i++, up++) {
++ up->port.iobase = old_serial_port[i].port;
++ up->port.irq = irq_canonicalize(old_serial_port[i].irq);
++ up->port.uartclk = old_serial_port[i].baud_base * 16;
++ up->port.flags = old_serial_port[i].flags;
++ up->port.hub6 = old_serial_port[i].hub6;
++ up->port.membase = old_serial_port[i].iomem_base;
++ up->port.iotype = old_serial_port[i].io_type;
++ up->port.regshift = old_serial_port[i].iomem_reg_shift;
++ if (share_irqs)
++ up->port.flags |= UPF_SHARE_IRQ;
++ }
++}
+
-+#define PCITC_DTIMER_VAL 8
-+#define PCITC_RTIMER_VAL 0x10
++static void __init
++serial8250_register_ports(struct uart_driver *drv, struct device *dev)
++{
++ int i;
+
-+#endif //__IDT_RC32365_PCI_V_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,205 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * DMA register definition
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ serial8250_isa_init_ports();
+
-+#ifndef __IDT_DMA_H__
-+#define __IDT_DMA_H__
++ for (i = 0; i < nr_uarts; i++) {
++ struct uart_8250_port *up = &serial8250_ports[i];
+
-+enum
++ up->port.dev = dev;
++ uart_add_one_port(drv, &up->port);
++ }
++}
++
++#ifdef CONFIG_SERIAL_8250_CONSOLE
++
++static void serial8250_console_putchar(struct uart_port *port, int ch)
+{
-+ DMA0_PhysicalAddress = 0x18040000,
-+ DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
++ struct uart_8250_port *up = (struct uart_8250_port *)port;
+
-+ DMA0_VirtualAddress = 0xb8040000,
-+ DMA_VirtualAddress = DMA0_VirtualAddress, // Default
-+} ;
++ wait_for_xmitr(up, UART_LSR_THRE);
++ serial_out(up, UART_TX, ch);
++}
+
+/*
-+ * DMA descriptor (in physical memory).
++ * Print a string to the serial port trying not to disturb
++ * any possible real use of the port...
++ *
++ * The console_lock must be held when we get here.
+ */
-+
-+typedef struct DMAD_s
++static void
++serial8250_console_write(struct console *co, const char *s, unsigned int count)
+{
-+ u32 control ; // Control. use DMAD_*
-+ u32 ca ; // Current Address.
-+ u32 devcs ; // Device control and status.
-+ u32 link ; // Next descriptor in chain.
-+} volatile *DMAD_t ;
++ struct uart_8250_port *up = &serial8250_ports[co->index];
++ unsigned long flags;
++ unsigned int ier;
++ int locked = 1;
+
-+enum
-+{
-+ DMAD_size = sizeof (struct DMAD_s),
-+ DMAD_count_b = 0, // in DMAD_t -> control
-+ DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
-+ DMAD_ds_b = 20, // in DMAD_t -> control
-+ DMAD_ds_m = 0x00300000, // in DMAD_t -> control
-+ DMAD_ds_ethRcv0_v = 0,
-+ DMAD_ds_ethXmt0_v = 0,
-+ DMAD_ds_memToFifo_v = 0,
-+ DMAD_ds_fifoToMem_v = 0,
-+ DMAD_ds_pciToMem_v = 0,
-+ DMAD_ds_memToPci_v = 0,
-+
-+ DMAD_devcmd_b = 22, // in DMAD_t -> control
-+ DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
-+ DMAD_devcmd_byte_v = 0, //memory-to-memory
-+ DMAD_devcmd_halfword_v = 1, //memory-to-memory
-+ DMAD_devcmd_word_v = 2, //memory-to-memory
-+ DMAD_devcmd_2words_v = 3, //memory-to-memory
-+ DMAD_devcmd_4words_v = 4, //memory-to-memory
-+ DMAD_devcmd_6words_v = 5, //memory-to-memory
-+ DMAD_devcmd_8words_v = 6, //memory-to-memory
-+ DMAD_devcmd_16words_v = 7, //memory-to-memory
-+ DMAD_cof_b = 25, // chain on finished
-+ DMAD_cof_m = 0x02000000, //
-+ DMAD_cod_b = 26, // chain on done
-+ DMAD_cod_m = 0x04000000, //
-+ DMAD_iof_b = 27, // interrupt on finished
-+ DMAD_iof_m = 0x08000000, //
-+ DMAD_iod_b = 28, // interrupt on done
-+ DMAD_iod_m = 0x10000000, //
-+ DMAD_t_b = 29, // terminated
-+ DMAD_t_m = 0x20000000, //
-+ DMAD_d_b = 30, // done
-+ DMAD_d_m = 0x40000000, //
-+ DMAD_f_b = 31, // finished
-+ DMAD_f_m = 0x80000000, //
-+} ;
++ touch_nmi_watchdog();
+
-+/*
-+ * DMA register (within Internal Register Map).
-+ */
++ local_irq_save(flags);
++ if (up->port.sysrq) {
++ /* serial8250_handle_port() already took the lock */
++ locked = 0;
++ } else if (oops_in_progress) {
++ locked = spin_trylock(&up->port.lock);
++ } else
++ spin_lock(&up->port.lock);
+
-+struct DMA_Chan_s
-+{
-+ u32 dmac ; // Control.
-+ u32 dmas ; // Status.
-+ u32 dmasm ; // Mask.
-+ u32 dmadptr ; // Descriptor pointer.
-+ u32 dmandptr ; // Next descriptor pointer.
-+};
++ /*
++ * First save the IER then disable the interrupts
++ */
++ ier = serial_in(up, UART_IER);
+
-+typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
++ if (up->capabilities & UART_CAP_UUE)
++ serial_out(up, UART_IER, UART_IER_UUE);
++ else
++ serial_out(up, UART_IER, 0);
+
-+//DMA_Channels use DMACH_count instead
++ uart_console_write(&up->port, s, count, serial8250_console_putchar);
+
-+enum
-+{
-+ DMAC_run_b = 0, //
-+ DMAC_run_m = 0x00000001, //
-+ DMAC_dm_b = 1, // done mask
-+ DMAC_dm_m = 0x00000002, //
-+ DMAC_mode_b = 2, //
-+ DMAC_mode_m = 0x0000000c, //
-+ DMAC_mode_auto_v = 0,
-+ DMAC_mode_burst_v = 1,
-+ DMAC_mode_transfer_v = 2, //usually used
-+ DMAC_mode_reserved_v = 3,
-+ DMAC_a_b = 4, //
-+ DMAC_a_m = 0x00000010, //
-+
-+ DMAS_f_b = 0, // finished (sticky)
-+ DMAS_f_m = 0x00000001, //
-+ DMAS_d_b = 1, // done (sticky)
-+ DMAS_d_m = 0x00000002, //
-+ DMAS_c_b = 2, // chain (sticky)
-+ DMAS_c_m = 0x00000004, //
-+ DMAS_e_b = 3, // error (sticky)
-+ DMAS_e_m = 0x00000008, //
-+ DMAS_h_b = 4, // halt (sticky)
-+ DMAS_h_m = 0x00000010, //
-+
-+ DMASM_f_b = 0, // finished (1=mask)
-+ DMASM_f_m = 0x00000001, //
-+ DMASM_d_b = 1, // done (1=mask)
-+ DMASM_d_m = 0x00000002, //
-+ DMASM_c_b = 2, // chain (1=mask)
-+ DMASM_c_m = 0x00000004, //
-+ DMASM_e_b = 3, // error (1=mask)
-+ DMASM_e_m = 0x00000008, //
-+ DMASM_h_b = 4, // halt (1=mask)
-+ DMASM_h_m = 0x00000010, //
-+} ;
++ /*
++ * Finally, wait for transmitter to become empty
++ * and restore the IER
++ */
++ wait_for_xmitr(up, BOTH_EMPTY);
++ serial_out(up, UART_IER, ier);
+
-+/*
-+ * DMA channel definitions
-+ */
++ if (locked)
++ spin_unlock(&up->port.lock);
++ local_irq_restore(flags);
++}
+
-+enum
++static int __init serial8250_console_setup(struct console *co, char *options)
+{
-+ DMACH_ethRcv0 = 0,
-+ DMACH_ethXmt0 = 1,
-+ DMACH_memToFifo = 2,
-+ DMACH_fifoToMem = 3,
-+ DMACH_pciToMem = 4,
-+ DMACH_memToPci = 5,
-+
-+ DMACH_count //must be last
-+};
++ struct uart_port *port;
++ int baud = 9600;
++ int bits = 8;
++ int parity = 'n';
++ int flow = 'n';
+
++ /*
++ * Check whether an invalid uart number has been specified, and
++ * if so, search for the first available port that does have
++ * console support.
++ */
++ if (co->index >= nr_uarts)
++ co->index = 0;
++ port = &serial8250_ports[co->index].port;
++ if (!port->iobase && !port->membase)
++ return -ENODEV;
+
-+typedef struct DMAC_s
-+{
-+ struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
-+} volatile *DMA_t ;
++ if (options)
++ uart_parse_options(options, &baud, &parity, &bits, &flow);
+
++ return uart_set_options(port, co, baud, parity, bits, flow);
++}
+
-+/*
-+ * External DMA parameters
-+*/
++static struct uart_driver serial8250_reg;
++static struct console serial8250_console = {
++ .name = "ttyS",
++ .write = serial8250_console_write,
++ .device = uart_console_device,
++ .setup = serial8250_console_setup,
++ .flags = CON_PRINTBUFFER,
++ .index = -1,
++ .data = &serial8250_reg,
++};
+
-+enum
++static int __init serial8250_console_init(void)
+{
-+ DMADEVCMD_ts_b = 0, // ts field in devcmd
-+ DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
-+ DMADEVCMD_ts_byte_v = 0,
-+ DMADEVCMD_ts_halfword_v = 1,
-+ DMADEVCMD_ts_word_v = 2,
-+ DMADEVCMD_ts_2word_v = 3,
-+ DMADEVCMD_ts_4word_v = 4,
-+ DMADEVCMD_ts_6word_v = 5,
-+ DMADEVCMD_ts_8word_v = 6,
-+ DMADEVCMD_ts_16word_v = 7
-+};
++ serial8250_isa_init_ports();
++ register_console(&serial8250_console);
++ return 0;
++}
++console_initcall(serial8250_console_init);
++
++static int __init find_port(struct uart_port *p)
++{
++ int line;
++ struct uart_port *port;
+
++ for (line = 0; line < nr_uarts; line++) {
++ port = &serial8250_ports[line].port;
++ if (uart_match_port(p, port))
++ return line;
++ }
++ return -ENODEV;
++}
+
-+#endif // __IDT_DMA_H__
++int __init serial8250_start_console(struct uart_port *port, char *options)
++{
++ int line;
+
++ line = find_port(port);
++ if (line < 0)
++ return -ENODEV;
+
++ add_preferred_console("ttyS", line, options);
++ printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
++ line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
++ port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
++ (unsigned long) port->iobase, options);
++ if (!(serial8250_console.flags & CON_ENABLED)) {
++ serial8250_console.flags &= ~CON_PRINTBUFFER;
++ register_console(&serial8250_console);
++ }
++ return line;
++}
+
++#define SERIAL8250_CONSOLE &serial8250_console
++#else
++#define SERIAL8250_CONSOLE NULL
++#endif
+
++static struct uart_driver serial8250_reg = {
++ .owner = THIS_MODULE,
++ .driver_name = "serial",
++ .dev_name = "ttyS",
++ .major = TTY_MAJOR,
++ .minor = 64,
++ .nr = UART_NR,
++ .cons = SERIAL8250_CONSOLE,
++};
+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,89 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for DMA controller.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
-+ *
-+ * Initial Release
-+ *
-+ *
++/*
++ * early_serial_setup - early registration for 8250 ports
+ *
-+ **************************************************************************
++ * Setup an 8250 port structure prior to console initialisation. Use
++ * after console initialisation will cause undefined behaviour.
+ */
++int __init early_serial_setup(struct uart_port *port)
++{
++ if (port->line >= ARRAY_SIZE(serial8250_ports))
++ return -ENODEV;
+
-+#ifndef __IDT_DMA_V_H__
-+#define __IDT_DMA_V_H__
-+
-+#include <asm/idt-boards/rc32434/rc32434_dma.h>
-+#include <asm/idt-boards/rc32434/rc32434.h>
-+
-+#define DMA_CHAN_OFFSET 0x14
-+#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
-+#define DMA_COUNT(count) \
-+ ((count) & DMAD_count_m)
-+
-+#define DMA_HALT_TIMEOUT 500
++ serial8250_isa_init_ports();
++ serial8250_ports[port->line].port = *port;
++ serial8250_ports[port->line].port.ops = &serial8250_pops;
++ return 0;
++}
+
++/**
++ * serial8250_suspend_port - suspend one serial port
++ * @line: serial line number
++ *
++ * Suspend one serial port.
++ */
++void serial8250_suspend_port(int line)
++{
++ uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
++}
+
-+static inline int rc32434_halt_dma(DMA_Chan_t ch)
++/**
++ * serial8250_resume_port - resume one serial port
++ * @line: serial line number
++ *
++ * Resume one serial port.
++ */
++void serial8250_resume_port(int line)
+{
-+ int timeout=1;
-+ if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
-+ rc32434_writel(0, &ch->dmac);
-+
-+ for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
-+ if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
-+ rc32434_writel(0, &ch->dmas);
-+ break;
-+ }
-+ }
++ uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
++}
+
++/*
++ * Register a set of serial devices attached to a platform device. The
++ * list is terminated with a zero flags entry, which means we expect
++ * all entries to have at least UPF_BOOT_AUTOCONF set.
++ */
++static int __devinit serial8250_probe(struct platform_device *dev)
++{
++ struct plat_serial8250_port *p = dev->dev.platform_data;
++ struct uart_port port;
++ int ret, i;
++
++ memset(&port, 0, sizeof(struct uart_port));
++
++ for (i = 0; p && p->flags != 0; p++, i++) {
++ port.iobase = p->iobase;
++ port.membase = p->membase;
++ port.irq = p->irq;
++ port.uartclk = p->uartclk;
++ port.regshift = p->regshift;
++ port.iotype = p->iotype;
++ port.flags = p->flags;
++ port.mapbase = p->mapbase;
++ port.hub6 = p->hub6;
++ port.dev = &dev->dev;
++ if (share_irqs)
++ port.flags |= UPF_SHARE_IRQ;
++ ret = serial8250_register_port(&port);
++ if (ret < 0) {
++ dev_err(&dev->dev, "unable to register port at index %d "
++ "(IO%lx MEM%lx IRQ%d): %d\n", i,
++ p->iobase, p->mapbase, p->irq, ret);
++ }
+ }
-+
-+ return timeout ? 0 : 1;
++ return 0;
+}
+
-+static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
++/*
++ * Remove serial ports registered against a platform device.
++ */
++static int __devexit serial8250_remove(struct platform_device *dev)
+{
-+ rc32434_writel(0, &ch->dmandptr);
-+ rc32434_writel(dma_addr, &ch->dmadptr);
-+}
++ int i;
+
-+static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
-+{
-+ rc32434_writel(dma_addr, &ch->dmandptr);
-+}
++ for (i = 0; i < nr_uarts; i++) {
++ struct uart_8250_port *up = &serial8250_ports[i];
+
-+#endif // __IDT_DMA_V_H__
++ if (up->port.dev == &dev->dev)
++ serial8250_unregister_port(i);
++ }
++ return 0;
++}
+
++static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
++{
++ int i;
+
++ for (i = 0; i < UART_NR; i++) {
++ struct uart_8250_port *up = &serial8250_ports[i];
+
++ if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
++ uart_suspend_port(&serial8250_reg, &up->port);
++ }
+
++ return 0;
++}
+
++static int serial8250_resume(struct platform_device *dev)
++{
++ int i;
+
++ for (i = 0; i < UART_NR; i++) {
++ struct uart_8250_port *up = &serial8250_ports[i];
+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,333 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Ethernet register definition
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
++ uart_resume_port(&serial8250_reg, &up->port);
++ }
+
-+#ifndef __IDT_ETH_H__
-+#define __IDT_ETH_H__
++ return 0;
++}
+
++static struct platform_driver serial8250_isa_driver = {
++ .probe = serial8250_probe,
++ .remove = __devexit_p(serial8250_remove),
++ .suspend = serial8250_suspend,
++ .resume = serial8250_resume,
++ .driver = {
++ .name = "serial8250",
++ .owner = THIS_MODULE,
++ },
++};
+
-+enum
-+{
-+ ETH0_PhysicalAddress = 0x18060000,
-+ ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
++/*
++ * This "device" covers _all_ ISA 8250-compatible serial devices listed
++ * in the table in include/asm/serial.h
++ */
++static struct platform_device *serial8250_isa_devs;
+
-+ ETH0_VirtualAddress = 0xb8060000,
-+ ETH_VirtualAddress = ETH0_VirtualAddress, // Default
-+} ;
++/*
++ * serial8250_register_port and serial8250_unregister_port allows for
++ * 16x50 serial ports to be configured at run-time, to support PCMCIA
++ * modems and PCI multiport cards.
++ */
++static DEFINE_MUTEX(serial_mutex);
+
-+typedef struct
-+{
-+ u32 ethintfc ;
-+ u32 ethfifott ;
-+ u32 etharc ;
-+ u32 ethhash0 ;
-+ u32 ethhash1 ;
-+ u32 ethu0 [4] ; // Reserved.
-+ u32 ethpfs ;
-+ u32 ethmcp ;
-+ u32 eth_u1 [10] ; // Reserved.
-+ u32 ethspare ;
-+ u32 eth_u2 [42] ; // Reserved.
-+ u32 ethsal0 ;
-+ u32 ethsah0 ;
-+ u32 ethsal1 ;
-+ u32 ethsah1 ;
-+ u32 ethsal2 ;
-+ u32 ethsah2 ;
-+ u32 ethsal3 ;
-+ u32 ethsah3 ;
-+ u32 ethrbc ;
-+ u32 ethrpc ;
-+ u32 ethrupc ;
-+ u32 ethrfc ;
-+ u32 ethtbc ;
-+ u32 ethgpf ;
-+ u32 eth_u9 [50] ; // Reserved.
-+ u32 ethmac1 ;
-+ u32 ethmac2 ;
-+ u32 ethipgt ;
-+ u32 ethipgr ;
-+ u32 ethclrt ;
-+ u32 ethmaxf ;
-+ u32 eth_u10 ; // Reserved.
-+ u32 ethmtest ;
-+ u32 miimcfg ;
-+ u32 miimcmd ;
-+ u32 miimaddr ;
-+ u32 miimwtd ;
-+ u32 miimrdd ;
-+ u32 miimind ;
-+ u32 eth_u11 ; // Reserved.
-+ u32 eth_u12 ; // Reserved.
-+ u32 ethcfsa0 ;
-+ u32 ethcfsa1 ;
-+ u32 ethcfsa2 ;
-+} volatile *ETH_t;
-+
-+enum
++static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
+{
-+ ETHINTFC_en_b = 0,
-+ ETHINTFC_en_m = 0x00000001,
-+ ETHINTFC_its_b = 1,
-+ ETHINTFC_its_m = 0x00000002,
-+ ETHINTFC_rip_b = 2,
-+ ETHINTFC_rip_m = 0x00000004,
-+ ETHINTFC_jam_b = 3,
-+ ETHINTFC_jam_m = 0x00000008,
-+ ETHINTFC_ovr_b = 4,
-+ ETHINTFC_ovr_m = 0x00000010,
-+ ETHINTFC_und_b = 5,
-+ ETHINTFC_und_m = 0x00000020,
-+
-+ ETHFIFOTT_tth_b = 0,
-+ ETHFIFOTT_tth_m = 0x0000007f,
-+
-+ ETHARC_pro_b = 0,
-+ ETHARC_pro_m = 0x00000001,
-+ ETHARC_am_b = 1,
-+ ETHARC_am_m = 0x00000002,
-+ ETHARC_afm_b = 2,
-+ ETHARC_afm_m = 0x00000004,
-+ ETHARC_ab_b = 3,
-+ ETHARC_ab_m = 0x00000008,
-+
-+ ETHSAL_byte5_b = 0,
-+ ETHSAL_byte5_m = 0x000000ff,
-+ ETHSAL_byte4_b = 8,
-+ ETHSAL_byte4_m = 0x0000ff00,
-+ ETHSAL_byte3_b = 16,
-+ ETHSAL_byte3_m = 0x00ff0000,
-+ ETHSAL_byte2_b = 24,
-+ ETHSAL_byte2_m = 0xff000000,
-+
-+ ETHSAH_byte1_b = 0,
-+ ETHSAH_byte1_m = 0x000000ff,
-+ ETHSAH_byte0_b = 8,
-+ ETHSAH_byte0_m = 0x0000ff00,
-+
-+ ETHGPF_ptv_b = 0,
-+ ETHGPF_ptv_m = 0x0000ffff,
-+
-+ ETHPFS_pfd_b = 0,
-+ ETHPFS_pfd_m = 0x00000001,
-+
-+ ETHCFSA0_cfsa4_b = 0,
-+ ETHCFSA0_cfsa4_m = 0x000000ff,
-+ ETHCFSA0_cfsa5_b = 8,
-+ ETHCFSA0_cfsa5_m = 0x0000ff00,
-+
-+ ETHCFSA1_cfsa2_b = 0,
-+ ETHCFSA1_cfsa2_m = 0x000000ff,
-+ ETHCFSA1_cfsa3_b = 8,
-+ ETHCFSA1_cfsa3_m = 0x0000ff00,
-+
-+ ETHCFSA2_cfsa0_b = 0,
-+ ETHCFSA2_cfsa0_m = 0x000000ff,
-+ ETHCFSA2_cfsa1_b = 8,
-+ ETHCFSA2_cfsa1_m = 0x0000ff00,
-+
-+ ETHMAC1_re_b = 0,
-+ ETHMAC1_re_m = 0x00000001,
-+ ETHMAC1_paf_b = 1,
-+ ETHMAC1_paf_m = 0x00000002,
-+ ETHMAC1_rfc_b = 2,
-+ ETHMAC1_rfc_m = 0x00000004,
-+ ETHMAC1_tfc_b = 3,
-+ ETHMAC1_tfc_m = 0x00000008,
-+ ETHMAC1_lb_b = 4,
-+ ETHMAC1_lb_m = 0x00000010,
-+ ETHMAC1_mr_b = 31,
-+ ETHMAC1_mr_m = 0x80000000,
-+
-+ ETHMAC2_fd_b = 0,
-+ ETHMAC2_fd_m = 0x00000001,
-+ ETHMAC2_flc_b = 1,
-+ ETHMAC2_flc_m = 0x00000002,
-+ ETHMAC2_hfe_b = 2,
-+ ETHMAC2_hfe_m = 0x00000004,
-+ ETHMAC2_dc_b = 3,
-+ ETHMAC2_dc_m = 0x00000008,
-+ ETHMAC2_cen_b = 4,
-+ ETHMAC2_cen_m = 0x00000010,
-+ ETHMAC2_pe_b = 5,
-+ ETHMAC2_pe_m = 0x00000020,
-+ ETHMAC2_vpe_b = 6,
-+ ETHMAC2_vpe_m = 0x00000040,
-+ ETHMAC2_ape_b = 7,
-+ ETHMAC2_ape_m = 0x00000080,
-+ ETHMAC2_ppe_b = 8,
-+ ETHMAC2_ppe_m = 0x00000100,
-+ ETHMAC2_lpe_b = 9,
-+ ETHMAC2_lpe_m = 0x00000200,
-+ ETHMAC2_nb_b = 12,
-+ ETHMAC2_nb_m = 0x00001000,
-+ ETHMAC2_bp_b = 13,
-+ ETHMAC2_bp_m = 0x00002000,
-+ ETHMAC2_ed_b = 14,
-+ ETHMAC2_ed_m = 0x00004000,
-+
-+ ETHIPGT_ipgt_b = 0,
-+ ETHIPGT_ipgt_m = 0x0000007f,
-+
-+ ETHIPGR_ipgr2_b = 0,
-+ ETHIPGR_ipgr2_m = 0x0000007f,
-+ ETHIPGR_ipgr1_b = 8,
-+ ETHIPGR_ipgr1_m = 0x00007f00,
-+
-+ ETHCLRT_maxret_b = 0,
-+ ETHCLRT_maxret_m = 0x0000000f,
-+ ETHCLRT_colwin_b = 8,
-+ ETHCLRT_colwin_m = 0x00003f00,
-+
-+ ETHMAXF_maxf_b = 0,
-+ ETHMAXF_maxf_m = 0x0000ffff,
-+
-+ ETHMTEST_tb_b = 2,
-+ ETHMTEST_tb_m = 0x00000004,
-+
-+ ETHMCP_div_b = 0,
-+ ETHMCP_div_m = 0x000000ff,
-+
-+ MIIMCFG_rsv_b = 0,
-+ MIIMCFG_rsv_m = 0x0000000c,
-+
-+ MIIMCMD_rd_b = 0,
-+ MIIMCMD_rd_m = 0x00000001,
-+ MIIMCMD_scn_b = 1,
-+ MIIMCMD_scn_m = 0x00000002,
-+
-+ MIIMADDR_regaddr_b = 0,
-+ MIIMADDR_regaddr_m = 0x0000001f,
-+ MIIMADDR_phyaddr_b = 8,
-+ MIIMADDR_phyaddr_m = 0x00001f00,
++ int i;
+
-+ MIIMWTD_wdata_b = 0,
-+ MIIMWTD_wdata_m = 0x0000ffff,
++ /*
++ * First, find a port entry which matches.
++ */
++ for (i = 0; i < nr_uarts; i++)
++ if (uart_match_port(&serial8250_ports[i].port, port))
++ return &serial8250_ports[i];
+
-+ MIIMRDD_rdata_b = 0,
-+ MIIMRDD_rdata_m = 0x0000ffff,
++ /*
++ * We didn't find a matching entry, so look for the first
++ * free entry. We look for one which hasn't been previously
++ * used (indicated by zero iobase).
++ */
++ for (i = 0; i < nr_uarts; i++)
++ if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
++ serial8250_ports[i].port.iobase == 0)
++ return &serial8250_ports[i];
+
-+ MIIMIND_bsy_b = 0,
-+ MIIMIND_bsy_m = 0x00000001,
-+ MIIMIND_scn_b = 1,
-+ MIIMIND_scn_m = 0x00000002,
-+ MIIMIND_nv_b = 2,
-+ MIIMIND_nv_m = 0x00000004,
++ /*
++ * That also failed. Last resort is to find any entry which
++ * doesn't have a real port associated with it.
++ */
++ for (i = 0; i < nr_uarts; i++)
++ if (serial8250_ports[i].port.type == PORT_UNKNOWN)
++ return &serial8250_ports[i];
+
-+} ;
++ return NULL;
++}
+
-+/*
-+ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
-+ */
-+enum
-+{
-+ ETHRX_fd_b = 0,
-+ ETHRX_fd_m = 0x00000001,
-+ ETHRX_ld_b = 1,
-+ ETHRX_ld_m = 0x00000002,
-+ ETHRX_rok_b = 2,
-+ ETHRX_rok_m = 0x00000004,
-+ ETHRX_fm_b = 3,
-+ ETHRX_fm_m = 0x00000008,
-+ ETHRX_mp_b = 4,
-+ ETHRX_mp_m = 0x00000010,
-+ ETHRX_bp_b = 5,
-+ ETHRX_bp_m = 0x00000020,
-+ ETHRX_vlt_b = 6,
-+ ETHRX_vlt_m = 0x00000040,
-+ ETHRX_cf_b = 7,
-+ ETHRX_cf_m = 0x00000080,
-+ ETHRX_ovr_b = 8,
-+ ETHRX_ovr_m = 0x00000100,
-+ ETHRX_crc_b = 9,
-+ ETHRX_crc_m = 0x00000200,
-+ ETHRX_cv_b = 10,
-+ ETHRX_cv_m = 0x00000400,
-+ ETHRX_db_b = 11,
-+ ETHRX_db_m = 0x00000800,
-+ ETHRX_le_b = 12,
-+ ETHRX_le_m = 0x00001000,
-+ ETHRX_lor_b = 13,
-+ ETHRX_lor_m = 0x00002000,
-+ ETHRX_ces_b = 14,
-+ ETHRX_ces_m = 0x00004000,
-+ ETHRX_length_b = 16,
-+ ETHRX_length_m = 0xffff0000,
-+
-+ ETHTX_fd_b = 0,
-+ ETHTX_fd_m = 0x00000001,
-+ ETHTX_ld_b = 1,
-+ ETHTX_ld_m = 0x00000002,
-+ ETHTX_oen_b = 2,
-+ ETHTX_oen_m = 0x00000004,
-+ ETHTX_pen_b = 3,
-+ ETHTX_pen_m = 0x00000008,
-+ ETHTX_cen_b = 4,
-+ ETHTX_cen_m = 0x00000010,
-+ ETHTX_hen_b = 5,
-+ ETHTX_hen_m = 0x00000020,
-+ ETHTX_tok_b = 6,
-+ ETHTX_tok_m = 0x00000040,
-+ ETHTX_mp_b = 7,
-+ ETHTX_mp_m = 0x00000080,
-+ ETHTX_bp_b = 8,
-+ ETHTX_bp_m = 0x00000100,
-+ ETHTX_und_b = 9,
-+ ETHTX_und_m = 0x00000200,
-+ ETHTX_of_b = 10,
-+ ETHTX_of_m = 0x00000400,
-+ ETHTX_ed_b = 11,
-+ ETHTX_ed_m = 0x00000800,
-+ ETHTX_ec_b = 12,
-+ ETHTX_ec_m = 0x00001000,
-+ ETHTX_lc_b = 13,
-+ ETHTX_lc_m = 0x00002000,
-+ ETHTX_td_b = 14,
-+ ETHTX_td_m = 0x00004000,
-+ ETHTX_crc_b = 15,
-+ ETHTX_crc_m = 0x00008000,
-+ ETHTX_le_b = 16,
-+ ETHTX_le_m = 0x00010000,
-+ ETHTX_cc_b = 17,
-+ ETHTX_cc_m = 0x001E0000,
-+} ;
-+
-+#endif // __IDT_ETH_H__
-+
-+
-+
-+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,77 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Ethernet register definition
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
++/**
++ * serial8250_register_port - register a serial port
++ * @port: serial port template
+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
++ * Configure the serial port specified by the request. If the
++ * port exists and is in use, it is hung up and unregistered
++ * first.
+ *
-+ * Initial Release
++ * The port is then probed and if necessary the IRQ is autodetected
++ * If this fails an error is returned.
+ *
-+ *
-+ *
-+ **************************************************************************
++ * On success the port is ready to use and the line number is returned.
+ */
++int serial8250_register_port(struct uart_port *port)
++{
++ struct uart_8250_port *uart;
++ int ret = -ENOSPC;
++
++ if (port->uartclk == 0)
++ return -EINVAL;
++
++ mutex_lock(&serial_mutex);
++
++ uart = serial8250_find_match_or_unused(port);
++ if (uart) {
++ uart_remove_one_port(&serial8250_reg, &uart->port);
++
++ uart->port.iobase = port->iobase;
++ uart->port.membase = port->membase;
++ uart->port.irq = port->irq;
++ uart->port.uartclk = port->uartclk;
++ uart->port.fifosize = port->fifosize;
++ uart->port.regshift = port->regshift;
++ uart->port.iotype = port->iotype;
++ uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
++ uart->port.mapbase = port->mapbase;
++ if (port->dev)
++ uart->port.dev = port->dev;
++
++ ret = uart_add_one_port(&serial8250_reg, &uart->port);
++ if (ret == 0)
++ ret = uart->port.line;
++ }
++ mutex_unlock(&serial_mutex);
+
-+#ifndef __IDT_ETH_V_H__
-+#define __IDT_ETH_V_H__
-+
-+#include <asm/idt-boards/rc32434/rc32434_eth.h>
-+
-+#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
-+#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
-+#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
-+#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
-+#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
-+#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
-+#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
-+#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
-+#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
-+#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
-+#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
-+
-+#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
-+
-+#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
-+#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
-+#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
-+#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
-+#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
-+#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
-+#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
-+#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
-+#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
-+#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
-+#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
-+#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
-+#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
-+#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
-+#endif // __IDT_ETH_V_H__
-+
-+
-+
-+
-+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,167 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * GPIO register definition
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
-+ *
-+ * Initial Release
-+ *
-+ *
++ return ret;
++}
++EXPORT_SYMBOL(serial8250_register_port);
++
++/**
++ * serial8250_unregister_port - remove a 16x50 serial port at runtime
++ * @line: serial line number
+ *
-+ **************************************************************************
++ * Remove one serial port. This may not be called from interrupt
++ * context. We hand the port back to the our control.
+ */
++void serial8250_unregister_port(int line)
++{
++ struct uart_8250_port *uart = &serial8250_ports[line];
++
++ mutex_lock(&serial_mutex);
++ uart_remove_one_port(&serial8250_reg, &uart->port);
++ if (serial8250_isa_devs) {
++ uart->port.flags &= ~UPF_BOOT_AUTOCONF;
++ uart->port.type = PORT_UNKNOWN;
++ uart->port.dev = &serial8250_isa_devs->dev;
++ uart_add_one_port(&serial8250_reg, &uart->port);
++ } else {
++ uart->port.dev = NULL;
++ }
++ mutex_unlock(&serial_mutex);
++}
++EXPORT_SYMBOL(serial8250_unregister_port);
+
-+#ifndef __IDT_GPIO_H__
-+#define __IDT_GPIO_H__
-+
-+enum
++static int __init serial8250_init(void)
+{
-+ GPIO0_PhysicalAddress = 0x18050000,
-+ GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
++ int ret, i;
+
-+ GPIO0_VirtualAddress = 0xb8050000,
-+ GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
-+} ;
++ if (nr_uarts > UART_NR)
++ nr_uarts = UART_NR;
+
-+typedef struct
-+{
-+ u32 gpiofunc; /* GPIO Function Register
-+ * gpiofunc[x]==0 bit = gpio
-+ * func[x]==1 bit = altfunc
-+ */
-+ u32 gpiocfg; /* GPIO Configuration Register
-+ * gpiocfg[x]==0 bit = input
-+ * gpiocfg[x]==1 bit = output
-+ */
-+ u32 gpiod; /* GPIO Data Register
-+ * gpiod[x] read/write gpio pinX status
-+ */
-+ u32 gpioilevel; /* GPIO Interrupt Status Register
-+ * interrupt level (see gpioistat)
-+ */
-+ u32 gpioistat; /* Gpio Interrupt Status Register
-+ * istat[x] = (gpiod[x] == level[x])
-+ * cleared in ISR (STICKY bits)
-+ */
-+ u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
-+} volatile * GPIO_t ;
-+
-+typedef enum
-+{
-+ GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
-+ GPIO_alt_v = 1, // gpiofunc use pin as alt.
-+ GPIO_input_v = 0, // gpiocfg use pin as input.
-+ GPIO_output_v = 1, // gpiocfg use pin as output.
-+ GPIO_pin0_b = 0,
-+ GPIO_pin0_m = 0x00000001,
-+ GPIO_pin1_b = 1,
-+ GPIO_pin1_m = 0x00000002,
-+ GPIO_pin2_b = 2,
-+ GPIO_pin2_m = 0x00000004,
-+ GPIO_pin3_b = 3,
-+ GPIO_pin3_m = 0x00000008,
-+ GPIO_pin4_b = 4,
-+ GPIO_pin4_m = 0x00000010,
-+ GPIO_pin5_b = 5,
-+ GPIO_pin5_m = 0x00000020,
-+ GPIO_pin6_b = 6,
-+ GPIO_pin6_m = 0x00000040,
-+ GPIO_pin7_b = 7,
-+ GPIO_pin7_m = 0x00000080,
-+ GPIO_pin8_b = 8,
-+ GPIO_pin8_m = 0x00000100,
-+ GPIO_pin9_b = 9,
-+ GPIO_pin9_m = 0x00000200,
-+ GPIO_pin10_b = 10,
-+ GPIO_pin10_m = 0x00000400,
-+ GPIO_pin11_b = 11,
-+ GPIO_pin11_m = 0x00000800,
-+ GPIO_pin12_b = 12,
-+ GPIO_pin12_m = 0x00001000,
-+ GPIO_pin13_b = 13,
-+ GPIO_pin13_m = 0x00002000,
-+
-+// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
-+
-+ GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
-+ GPIO_u0sout_m = GPIO_pin0_m,
-+ GPIO_u0sout_cfg_v = GPIO_output_v,
-+ GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
-+ GPIO_u0sinp_m = GPIO_pin1_m,
-+ GPIO_u0sinp_cfg_v = GPIO_input_v,
-+ GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
-+ GPIO_u0rtsn_m = GPIO_pin2_m,
-+ GPIO_u0rtsn_cfg_v = GPIO_output_v,
-+ GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
-+ GPIO_u0ctsn_m = GPIO_pin3_m,
-+ GPIO_u0ctsn_cfg_v = GPIO_input_v,
-+
-+ GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
-+ GPIO_maddr22_m = GPIO_pin4_m,
-+ GPIO_maddr22_cfg_v = GPIO_output_v,
-+
-+ GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
-+ GPIO_maddr23_m = GPIO_pin5_m,
-+ GPIO_maddr23_cfg_v = GPIO_output_v,
-+
-+ GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
-+ GPIO_maddr24_m = GPIO_pin6_m,
-+ GPIO_maddr24_cfg_v = GPIO_output_v,
-+
-+ GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
-+ GPIO_maddr25_m = GPIO_pin7_m,
-+ GPIO_maddr25_cfg_v = GPIO_output_v,
-+
-+ GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
-+ GPIO_cpudmadebug_m = GPIO_pin8_m,
-+ GPIO_cpudmadebug_cfg_v = GPIO_output_v,
-+
-+ GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
-+ GPIO_pcireq4_m = GPIO_pin9_m,
-+ GPIO_pcireq4_cfg_v = GPIO_input_v,
-+
-+ GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
-+ GPIO_pcigrant4_m = GPIO_pin10_m,
-+ GPIO_pcigrant4_cfg_v = GPIO_output_v,
-+
-+ GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
-+ GPIO_pcireq5_m = GPIO_pin11_m,
-+ GPIO_pcireq5_cfg_v = GPIO_input_v,
-+
-+ GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
-+ GPIO_pcigrant5_m = GPIO_pin12_m,
-+ GPIO_pcigrant5_cfg_v = GPIO_output_v,
-+
-+ GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
-+ GPIO_pcimuintn_m = GPIO_pin13_m,
-+ GPIO_pcimuintn_cfg_v = GPIO_output_v,
-+
-+} GPIO_DEFS_t;
-+
-+#endif // __IDT_GPIO_H__
-+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,199 @@
-+ /**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for IDT RC32434 CPU
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
++ "%d ports, IRQ sharing %sabled\n", nr_uarts,
++ share_irqs ? "en" : "dis");
+
-+#ifndef _RC32434_H_
-+#define _RC32434_H_
++ for (i = 0; i < NR_IRQS; i++)
++ spin_lock_init(&irq_lists[i].lock);
+
-+#include <linux/config.h>
-+#include <linux/delay.h>
-+#include <asm/io.h>
-+#include <asm/idt-boards/rc32434/rc32434_timer.h>
++ ret = uart_register_driver(&serial8250_reg);
++ if (ret)
++ goto out;
+
-+#define RC32434_REG_BASE 0x18000000
++ serial8250_isa_devs = platform_device_alloc("serial8250",
++ PLAT8250_DEV_LEGACY);
++ if (!serial8250_isa_devs) {
++ ret = -ENOMEM;
++ goto unreg_uart_drv;
++ }
+
++ ret = platform_device_add(serial8250_isa_devs);
++ if (ret)
++ goto put_dev;
+
-+#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
-+#define idt_timer ((volatile TIM_t) TIM0_VirtualAddress)
-+#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
++ serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
+
-+#define IDT_CLOCK_MULT 2
-+#define MIPS_CPU_TIMER_IRQ 7
-+/* Interrupt Controller */
-+#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
-+#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
-+#define IC_GROUP_OFFSET 0x0C
-+#define RTC_BASE 0xBA001FF0
++ ret = platform_driver_register(&serial8250_isa_driver);
++ if (ret == 0)
++ goto out;
+
-+#define NUM_INTR_GROUPS 5
-+/* 16550 UARTs */
++ platform_device_del(serial8250_isa_devs);
++ put_dev:
++ platform_device_put(serial8250_isa_devs);
++ unreg_uart_drv:
++ uart_unregister_driver(&serial8250_reg);
++ out:
++ return ret;
++}
+
-+#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
-+#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
-+#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
-+#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
-+#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
++static void __exit serial8250_exit(void)
++{
++ struct platform_device *isa_dev = serial8250_isa_devs;
+
-+#ifdef __MIPSEB__
++ /*
++ * This tells serial8250_unregister_port() not to re-register
++ * the ports (thereby making serial8250_isa_driver permanently
++ * in use.)
++ */
++ serial8250_isa_devs = NULL;
+
-+#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
-+#define EB434_UART1_BASE (0x19800003)
++ platform_driver_unregister(&serial8250_isa_driver);
++ platform_device_unregister(isa_dev);
+
-+#else
++ uart_unregister_driver(&serial8250_reg);
++}
+
-+#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
-+#define EB434_UART1_BASE (0x19800000)
++module_init(serial8250_init);
++module_exit(serial8250_exit);
+
-+#endif
++EXPORT_SYMBOL(serial8250_suspend_port);
++EXPORT_SYMBOL(serial8250_resume_port);
+
-+#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
-+#define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
+
-+#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
++module_param(share_irqs, uint, 0644);
++MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
++ " (unsafe)");
+
-+/* cpu pipeline flush */
-+static inline void rc32434_sync(void)
-+{
-+ __asm__ volatile ("sync");
-+}
++module_param(nr_uarts, uint, 0644);
++MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
+
-+static inline void rc32434_sync_udelay(int us)
-+{
-+ __asm__ volatile ("sync");
-+ udelay(us);
-+}
++#ifdef CONFIG_SERIAL_8250_RSA
++module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
++MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
++#endif
++MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
+diff -Nur linux-2.6.21.1/drivers/usb/host/ehci.h linux-2.6.21.1-owrt/drivers/usb/host/ehci.h
+--- linux-2.6.21.1/drivers/usb/host/ehci.h 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/drivers/usb/host/ehci.h 2007-05-23 23:37:18.000000000 +0200
+@@ -87,6 +87,7 @@
+ struct dma_pool *sitd_pool; /* sitd per split iso urb */
+
+ struct timer_list watchdog;
++ struct timer_list softirq;
+ unsigned long actions;
+ unsigned stamp;
+ unsigned long next_statechange;
+diff -Nur linux-2.6.21.1/drivers/usb/host/ehci-hcd.c linux-2.6.21.1-owrt/drivers/usb/host/ehci-hcd.c
+--- linux-2.6.21.1/drivers/usb/host/ehci-hcd.c 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/drivers/usb/host/ehci-hcd.c 2007-05-23 23:37:18.000000000 +0200
+@@ -118,6 +118,7 @@
+ #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
+ #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
+ #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
++#define EHCI_SOFTIRQ (HZ/400)
+
+ /* Initial IRQ latency: faster than hw default */
+ static int log2_irq_thresh = 0; // 0 to 6
+@@ -273,6 +274,16 @@
+ #include "ehci-sched.c"
+
+ /*-------------------------------------------------------------------------*/
++static irqreturn_t ehci_irq (struct usb_hcd *hcd);
+
-+static inline void rc32434_sync_delay(int ms)
++static void ehci_softirq (unsigned long param)
+{
-+ __asm__ volatile ("sync");
-+ mdelay(ms);
-+}
-+
-+
++ struct ehci_hcd *ehci = (struct ehci_hcd *) param;
+
++ if (ehci_irq(ehci_to_hcd(ehci)) != IRQ_NONE)
++ set_bit(HCD_FLAG_SAW_IRQ, &(ehci_to_hcd(ehci))->flags);
++ mod_timer (&ehci->softirq, jiffies + EHCI_SOFTIRQ);
++}
+
+ static void ehci_watchdog (unsigned long param)
+ {
+@@ -289,6 +300,10 @@
+ COUNT (ehci->stats.lost_iaa);
+ ehci_writel(ehci, STS_IAA, &ehci->regs->status);
+ ehci->reclaim_ready = 1;
++ if (!timer_pending(&ehci->softirq)) {
++ ehci_info(ehci, "switching to softirq\n");
++ mod_timer (&ehci->softirq, jiffies + EHCI_SOFTIRQ);
++ }
+ }
+ }
+
+@@ -396,6 +411,7 @@
+
+ /* no more interrupts ... */
+ del_timer_sync (&ehci->watchdog);
++ del_timer_sync (&ehci->softirq);
+
+ spin_lock_irq(&ehci->lock);
+ if (HC_IS_RUNNING (hcd->state))
+@@ -444,6 +460,10 @@
+ ehci->watchdog.function = ehci_watchdog;
+ ehci->watchdog.data = (unsigned long) ehci;
+
++ init_timer(&ehci->softirq);
++ ehci->softirq.function = ehci_softirq;
++ ehci->softirq.data = (unsigned long) ehci;
++
+ /*
+ * hw default: 1K periodic list heads, one per frame.
+ * periodic_size can shrink by USBCMD update if hcc_params allows.
+diff -Nur linux-2.6.21.1/drivers/usb/host/ehci-hcd.c.orig linux-2.6.21.1-owrt/drivers/usb/host/ehci-hcd.c.orig
+--- linux-2.6.21.1/drivers/usb/host/ehci-hcd.c.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/drivers/usb/host/ehci-hcd.c.orig 2007-04-27 23:49:26.000000000 +0200
+@@ -0,0 +1,1008 @@
+/*
-+ * Macros to access internal RC32434 registers. No byte
-+ * swapping should be done when accessing the internal
-+ * registers.
++ * Copyright (c) 2000-2004 by David Brownell
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software Foundation,
++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
-+#define rc32434_readb __raw_readb
-+#define rc32434_readw __raw_readw
-+#define rc32434_readl __raw_readl
-+
-+#define rc32434_writeb __raw_writeb
-+#define rc32434_writew __raw_writew
-+#define rc32434_writel __raw_writel
++#include <linux/module.h>
++#include <linux/pci.h>
++#include <linux/dmapool.h>
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/ioport.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/smp_lock.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/timer.h>
++#include <linux/list.h>
++#include <linux/interrupt.h>
++#include <linux/reboot.h>
++#include <linux/usb.h>
++#include <linux/moduleparam.h>
++#include <linux/dma-mapping.h>
+
-+#if 0
-+static inline u8 rc32434_readb(unsigned long pa)
-+{
-+ return *((volatile u8 *)KSEG1ADDR(pa));
-+}
-+static inline u16 rc32434_readw(unsigned long pa)
-+{
-+ return *((volatile u16 *)KSEG1ADDR(pa));
-+}
-+static inline u32 rc32434_readl(unsigned long pa)
-+{
-+ return *((volatile u32 *)KSEG1ADDR(pa));
-+}
-+static inline void rc32434_writeb(u8 val, unsigned long pa)
-+{
-+ *((volatile u8 *)KSEG1ADDR(pa)) = val;
-+}
-+static inline void rc32434_writew(u16 val, unsigned long pa)
-+{
-+ *((volatile u16 *)KSEG1ADDR(pa)) = val;
-+}
-+static inline void rc32434_writel(u32 val, unsigned long pa)
-+{
-+ *((volatile u32 *)KSEG1ADDR(pa)) = val;
-+}
++#include "../core/hcd.h"
+
++#include <asm/byteorder.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/system.h>
++#include <asm/unaligned.h>
++#ifdef CONFIG_PPC_PS3
++#include <asm/firmware.h>
+#endif
+
+
++/*-------------------------------------------------------------------------*/
++
+/*
-+ * C access to CLZ and CLO instructions
-+ * (count leading zeroes/ones).
++ * EHCI hc_driver implementation ... experimental, incomplete.
++ * Based on the final 1.0 register interface specification.
++ *
++ * USB 2.0 shows up in upcoming www.pcmcia.org technology.
++ * First was PCMCIA, like ISA; then CardBus, which is PCI.
++ * Next comes "CardBay", using USB 2.0 signals.
++ *
++ * Contains additional contributions by Brad Hards, Rory Bolt, and others.
++ * Special thanks to Intel and VIA for providing host controllers to
++ * test this driver on, and Cypress (including In-System Design) for
++ * providing early devices for those host controllers to talk to!
++ *
++ * HISTORY:
++ *
++ * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
++ * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
++ * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
++ * <sojkam@centrum.cz>, updates by DB).
++ *
++ * 2002-11-29 Correct handling for hw async_next register.
++ * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
++ * only scheduling is different, no arbitrary limitations.
++ * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
++ * clean up HC run state handshaking.
++ * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
++ * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
++ * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
++ * 2002-05-07 Some error path cleanups to report better errors; wmb();
++ * use non-CVS version id; better iso bandwidth claim.
++ * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
++ * errors in submit path. Bugfixes to interrupt scheduling/processing.
++ * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
++ * more checking to generic hcd framework (db). Make it work with
++ * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
++ * 2002-01-14 Minor cleanup; version synch.
++ * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
++ * 2002-01-04 Control/Bulk queuing behaves.
++ *
++ * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
++ * 2001-June Works with usb-storage and NEC EHCI on 2.4
+ */
-+static inline int rc32434_clz(unsigned long val)
-+{
-+ int ret;
-+ __asm__ volatile (
-+ ".set\tnoreorder\n\t"
-+ ".set\tnoat\n\t"
-+ ".set\tmips32\n\t"
-+ "clz\t%0,%1\n\t"
-+ ".set\tmips0\n\t"
-+ ".set\tat\n\t"
-+ ".set\treorder"
-+ : "=r" (ret)
-+ : "r" (val));
+
-+ return ret;
-+}
-+static inline int rc32434_clo(unsigned long val)
-+{
-+ int ret;
-+ __asm__ volatile (
-+ ".set\tnoreorder\n\t"
-+ ".set\tnoat\n\t"
-+ ".set\tmips32\n\t"
-+ "clo\t%0,%1\n\t"
-+ ".set\tmips0\n\t"
-+ ".set\tat\n\t"
-+ ".set\treorder"
-+ : "=r" (ret)
-+ : "r" (val));
++#define DRIVER_VERSION "10 Dec 2004"
++#define DRIVER_AUTHOR "David Brownell"
++#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
++
++static const char hcd_name [] = "ehci_hcd";
+
-+ return ret;
-+}
-+#endif /* _RC32434_H_ */
+
++#undef EHCI_VERBOSE_DEBUG
++#undef EHCI_URB_TRACE
+
++#ifdef DEBUG
++#define EHCI_STATS
++#endif
+
++/* magic numbers that can affect system performance */
++#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
++#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
++#define EHCI_TUNE_RL_TT 0
++#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
++#define EHCI_TUNE_MULT_TT 1
++#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
+
++#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
++#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
++#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
++#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
+
++/* Initial IRQ latency: faster than hw default */
++static int log2_irq_thresh = 0; // 0 to 6
++module_param (log2_irq_thresh, int, S_IRUGO);
++MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
+
++/* initial park setting: slower than hw default */
++static unsigned park = 0;
++module_param (park, uint, S_IRUGO);
++MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
+
++/* for flakey hardware, ignore overcurrent indicators */
++static int ignore_oc = 0;
++module_param (ignore_oc, bool, S_IRUGO);
++MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
+
++#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
+
++/*-------------------------------------------------------------------------*/
+
++#include "ehci.h"
++#include "ehci-dbg.c"
+
++/*-------------------------------------------------------------------------*/
+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,90 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * System Integrity register definition
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb
++/*
++ * handshake - spin reading hc until handshake completes or fails
++ * @ptr: address of hc register to be read
++ * @mask: bits to look at in result of read
++ * @done: value of those bits when handshake succeeds
++ * @usec: timeout in microseconds
+ *
-+ * Initial Release
++ * Returns negative errno, or zero on success
+ *
-+ *
++ * Success happens when the "mask" bits have the specified value (hardware
++ * handshake done). There are two failure modes: "usec" have passed (major
++ * hardware flakeout), or the register reads as all-ones (hardware removed).
+ *
-+ **************************************************************************
++ * That last failure should_only happen in cases like physical cardbus eject
++ * before driver shutdown. But it also seems to be caused by bugs in cardbus
++ * bridge shutdown: shutting down the bridge before the devices using it.
+ */
++static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
++ u32 mask, u32 done, int usec)
++{
++ u32 result;
++
++ do {
++ result = ehci_readl(ehci, ptr);
++ if (result == ~(u32)0) /* card removed */
++ return -ENODEV;
++ result &= mask;
++ if (result == done)
++ return 0;
++ udelay (1);
++ usec--;
++ } while (usec > 0);
++ return -ETIMEDOUT;
++}
+
-+#ifndef __IDT_INTEG_H__
-+#define __IDT_INTEG_H__
-+
-+enum
++/* force HC to halt state from unknown (EHCI spec section 2.3) */
++static int ehci_halt (struct ehci_hcd *ehci)
+{
-+ INTEG0_PhysicalAddress = 0x18030000,
-+ INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
++ u32 temp = ehci_readl(ehci, &ehci->regs->status);
+
-+ INTEG0_VirtualAddress = 0xB8030000,
-+ INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
-+} ;
++ /* disable any irqs left enabled by previous code */
++ ehci_writel(ehci, 0, &ehci->regs->intr_enable);
+
-+// if you are looking for CEA, try rst.h
-+typedef struct
-+{
-+ u32 filler [0xc] ; // 0x30 bytes unused.
-+ u32 errcs ; // sticky use ERRCS_
-+ u32 wtcount ; // Watchdog timer count reg.
-+ u32 wtcompare ; // Watchdog timer timeout value.
-+ u32 wtc ; // Watchdog timer control. use WTC_
-+} volatile *INTEG_t ;
-+
-+enum
-+{
-+ ERRCS_wto_b = 0, // In INTEG_t -> errcs
-+ ERRCS_wto_m = 0x00000001,
-+ ERRCS_wne_b = 1, // In INTEG_t -> errcs
-+ ERRCS_wne_m = 0x00000002,
-+ ERRCS_ucw_b = 2, // In INTEG_t -> errcs
-+ ERRCS_ucw_m = 0x00000004,
-+ ERRCS_ucr_b = 3, // In INTEG_t -> errcs
-+ ERRCS_ucr_m = 0x00000008,
-+ ERRCS_upw_b = 4, // In INTEG_t -> errcs
-+ ERRCS_upw_m = 0x00000010,
-+ ERRCS_upr_b = 5, // In INTEG_t -> errcs
-+ ERRCS_upr_m = 0x00000020,
-+ ERRCS_udw_b = 6, // In INTEG_t -> errcs
-+ ERRCS_udw_m = 0x00000040,
-+ ERRCS_udr_b = 7, // In INTEG_t -> errcs
-+ ERRCS_udr_m = 0x00000080,
-+ ERRCS_sae_b = 8, // In INTEG_t -> errcs
-+ ERRCS_sae_m = 0x00000100,
-+ ERRCS_wre_b = 9, // In INTEG_t -> errcs
-+ ERRCS_wre_m = 0x00000200,
-+
-+ WTC_en_b = 0, // In INTEG_t -> wtc
-+ WTC_en_m = 0x00000001,
-+ WTC_to_b = 1, // In INTEG_t -> wtc
-+ WTC_to_m = 0x00000002,
-+} ;
-+
-+#endif // __IDT_INTEG_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,174 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Interrupt Controller register definition.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ if ((temp & STS_HALT) != 0)
++ return 0;
+
-+#ifndef __IDT_INT_H__
-+#define __IDT_INT_H__
++ temp = ehci_readl(ehci, &ehci->regs->command);
++ temp &= ~CMD_RUN;
++ ehci_writel(ehci, temp, &ehci->regs->command);
++ return handshake (ehci, &ehci->regs->status,
++ STS_HALT, STS_HALT, 16 * 125);
++}
+
-+enum
++/* put TDI/ARC silicon into EHCI mode */
++static void tdi_reset (struct ehci_hcd *ehci)
+{
-+ INT0_PhysicalAddress = 0x18038000,
-+ INT_PhysicalAddress = INT0_PhysicalAddress, // Default
++ u32 __iomem *reg_ptr;
++ u32 tmp;
+
-+ INT0_VirtualAddress = 0xB8038000,
-+ INT_VirtualAddress = INT0_VirtualAddress, // Default
-+} ;
++ reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68);
++ tmp = ehci_readl(ehci, reg_ptr);
++ tmp |= 0x3;
++ ehci_writel(ehci, tmp, reg_ptr);
++}
+
-+struct INT_s
++/* reset a non-running (STS_HALT == 1) controller */
++static int ehci_reset (struct ehci_hcd *ehci)
+{
-+ u32 ipend ; //Pending interrupts. use INT?_
-+ u32 itest ; //Test bits. use INT?_
-+ u32 imask ; //Interrupt disabled when set. use INT?_
-+} ;
++ int retval;
++ u32 command = ehci_readl(ehci, &ehci->regs->command);
+
-+enum
-+{
-+ IPEND2 = 0, // HW 2 interrupt to core. use INT2_
-+ IPEND3 = 1, // HW 3 interrupt to core. use INT3_
-+ IPEND4 = 2, // HW 4 interrupt to core. use INT4_
-+ IPEND5 = 3, // HW 5 interrupt to core. use INT5_
-+ IPEND6 = 4, // HW 6 interrupt to core. use INT6_
-+
-+ IPEND_count, // must be last (used in loops)
-+ IPEND_min = IPEND2 // min IPEND (used in loops)
-+};
++ command |= CMD_RESET;
++ dbg_cmd (ehci, "reset", command);
++ ehci_writel(ehci, command, &ehci->regs->command);
++ ehci_to_hcd(ehci)->state = HC_STATE_HALT;
++ ehci->next_statechange = jiffies;
++ retval = handshake (ehci, &ehci->regs->command,
++ CMD_RESET, 0, 250 * 1000);
+
-+typedef struct INTC_s
-+{
-+ struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
-+ u32 nmips ; // use NMIPS_
-+} volatile *INT_t ;
++ if (retval)
++ return retval;
+
-+enum
-+{
-+ INT2_timer0_b = 0,
-+ INT2_timer0_m = 0x00000001,
-+ INT2_timer1_b = 1,
-+ INT2_timer1_m = 0x00000002,
-+ INT2_timer2_b = 2,
-+ INT2_timer2_m = 0x00000004,
-+ INT2_refresh_b = 3,
-+ INT2_refresh_m = 0x00000008,
-+ INT2_watchdogTimeout_b = 4,
-+ INT2_watchdogTimeout_m = 0x00000010,
-+ INT2_undecodedCpuWrite_b = 5,
-+ INT2_undecodedCpuWrite_m = 0x00000020,
-+ INT2_undecodedCpuRead_b = 6,
-+ INT2_undecodedCpuRead_m = 0x00000040,
-+ INT2_undecodedPciWrite_b = 7,
-+ INT2_undecodedPciWrite_m = 0x00000080,
-+ INT2_undecodedPciRead_b = 8,
-+ INT2_undecodedPciRead_m = 0x00000100,
-+ INT2_undecodedDmaWrite_b = 9,
-+ INT2_undecodedDmaWrite_m = 0x00000200,
-+ INT2_undecodedDmaRead_b = 10,
-+ INT2_undecodedDmaRead_m = 0x00000400,
-+ INT2_ipBusSlaveAckError_b = 11,
-+ INT2_ipBusSlaveAckError_m = 0x00000800,
-+
-+ INT3_dmaChannel0_b = 0,
-+ INT3_dmaChannel0_m = 0x00000001,
-+ INT3_dmaChannel1_b = 1,
-+ INT3_dmaChannel1_m = 0x00000002,
-+ INT3_dmaChannel2_b = 2,
-+ INT3_dmaChannel2_m = 0x00000004,
-+ INT3_dmaChannel3_b = 3,
-+ INT3_dmaChannel3_m = 0x00000008,
-+ INT3_dmaChannel4_b = 4,
-+ INT3_dmaChannel4_m = 0x00000010,
-+ INT3_dmaChannel5_b = 5,
-+ INT3_dmaChannel5_m = 0x00000020,
-+
-+ INT5_uartGeneral0_b = 0,
-+ INT5_uartGeneral0_m = 0x00000001,
-+ INT5_uartTxrdy0_b = 1,
-+ INT5_uartTxrdy0_m = 0x00000002,
-+ INT5_uartRxrdy0_b = 2,
-+ INT5_uartRxrdy0_m = 0x00000004,
-+ INT5_pci_b = 3,
-+ INT5_pci_m = 0x00000008,
-+ INT5_pciDecoupled_b = 4,
-+ INT5_pciDecoupled_m = 0x00000010,
-+ INT5_spi_b = 5,
-+ INT5_spi_m = 0x00000020,
-+ INT5_deviceDecoupled_b = 6,
-+ INT5_deviceDecoupled_m = 0x00000040,
-+ INT5_eth0Ovr_b = 9,
-+ INT5_eth0Ovr_m = 0x00000200,
-+ INT5_eth0Und_b = 10,
-+ INT5_eth0Und_m = 0x00000400,
-+ INT5_eth0Pfd_b = 11,
-+ INT5_eth0Pfd_m = 0x00000800,
-+ INT5_nvram_b = 12,
-+ INT5_nvram_m = 0x00001000,
-+
-+ INT6_gpio0_b = 0,
-+ INT6_gpio0_m = 0x00000001,
-+ INT6_gpio1_b = 1,
-+ INT6_gpio1_m = 0x00000002,
-+ INT6_gpio2_b = 2,
-+ INT6_gpio2_m = 0x00000004,
-+ INT6_gpio3_b = 3,
-+ INT6_gpio3_m = 0x00000008,
-+ INT6_gpio4_b = 4,
-+ INT6_gpio4_m = 0x00000010,
-+ INT6_gpio5_b = 5,
-+ INT6_gpio5_m = 0x00000020,
-+ INT6_gpio6_b = 6,
-+ INT6_gpio6_m = 0x00000040,
-+ INT6_gpio7_b = 7,
-+ INT6_gpio7_m = 0x00000080,
-+ INT6_gpio8_b = 8,
-+ INT6_gpio8_m = 0x00000100,
-+ INT6_gpio9_b = 9,
-+ INT6_gpio9_m = 0x00000200,
-+ INT6_gpio10_b = 10,
-+ INT6_gpio10_m = 0x00000400,
-+ INT6_gpio11_b = 11,
-+ INT6_gpio11_m = 0x00000800,
-+ INT6_gpio12_b = 12,
-+ INT6_gpio12_m = 0x00001000,
-+ INT6_gpio13_b = 13,
-+ INT6_gpio13_m = 0x00002000,
-+
-+ NMIPS_gpio_b = 0,
-+ NMIPS_gpio_m = 0x00000001,
-+} ;
-+
-+#endif // __IDT_INT_H__
-+
-+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,111 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * IP Arbiter register definitions
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt,neb
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ if (ehci_is_TDI(ehci))
++ tdi_reset (ehci);
+
-+#ifndef __IDT_IPARB_H__
-+#define __IDT_IPARB_H__
++ return retval;
++}
+
-+enum
++/* idle the controller (from running) */
++static void ehci_quiesce (struct ehci_hcd *ehci)
+{
-+ IPARB0_PhysicalAddress = 0x18048000,
-+ IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
++ u32 temp;
+
-+ IPARB0_VirtualAddress = 0xB8048000,
-+ IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
-+} ;
++#ifdef DEBUG
++ if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
++ BUG ();
++#endif
+
-+enum
-+{
-+ IPABMXC_ethernet0Receive = 0,
-+ IPABMXC_ethernet0Transmit = 1,
-+ IPABMXC_memoryToHoldFifo = 2,
-+ IPABMXC_holdFifoToMemory = 3,
-+ IPABMXC_pciToMemory = 4,
-+ IPABMXC_memoryToPci = 5,
-+ IPABMXC_pciTarget = 6,
-+ IPABMXC_pciTargetStart = 7,
-+ IPABMXC_cpuToIpBus = 8,
-+
-+ IPABMXC_Count, // Must be last in list !
-+ IPABMXC_Min = IPABMXC_ethernet0Receive,
-+
-+ IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
-+} ;
-+
-+typedef struct
-+{
-+ u32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
-+ u32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
-+ u32 ipac ; // use IPAC_
-+ u32 ipaitcc; // use IPAITCC_
-+ u32 ipaspare ;
-+} volatile * IPARB_t ;
-+
-+enum
-+{
-+ IPAC_dp_b = 0,
-+ IPAC_dp_m = 0x00000001,
-+ IPAC_dep_b = 1,
-+ IPAC_dep_m = 0x00000002,
-+ IPAC_drm_b = 2,
-+ IPAC_drm_m = 0x00000004,
-+ IPAC_dwm_b = 3,
-+ IPAC_dwm_m = 0x00000008,
-+ IPAC_msk_b = 4,
-+ IPAC_msk_m = 0x00000010,
-+
-+ IPAPC_ptc_b = 0,
-+ IPAPC_ptc_m = 0x00003fff,
-+ IPAPC_mf_b = 14,
-+ IPAPC_mf_m = 0x00004000,
-+ IPAPC_cptc_b = 16,
-+ IPAPC_cptc_m = 0x3fff0000,
-+
-+ IPAITCC_itcc = 0,
-+ IPAITCC_itcc, = 0x000001ff,
-+
-+ IPABMC_mtc_b = 0,
-+ IPABMC_mtc_m = 0x00000fff,
-+ IPABMC_p_b = 12,
-+ IPABMC_p_m = 0x00003000,
-+ IPABMC_msk_b = 14,
-+ IPABMC_msk_m = 0x00004000,
-+ IPABMC_cmtc_b = 16,
-+ IPABMC_cmtc_m = 0x0fff0000,
-+};
++ /* wait for any schedule enables/disables to take effect */
++ temp = ehci_readl(ehci, &ehci->regs->command) << 10;
++ temp &= STS_ASS | STS_PSS;
++ if (handshake (ehci, &ehci->regs->status, STS_ASS | STS_PSS,
++ temp, 16 * 125) != 0) {
++ ehci_to_hcd(ehci)->state = HC_STATE_HALT;
++ return;
++ }
+
-+#endif // __IDT_IPARB_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,695 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * PCI register definitio
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ /* then disable anything that's still active */
++ temp = ehci_readl(ehci, &ehci->regs->command);
++ temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
++ ehci_writel(ehci, temp, &ehci->regs->command);
+
-+#ifndef __IDT_PCI_H__
-+#define __IDT_PCI_H__
++ /* hardware can take 16 microframes to turn off ... */
++ if (handshake (ehci, &ehci->regs->status, STS_ASS | STS_PSS,
++ 0, 16 * 125) != 0) {
++ ehci_to_hcd(ehci)->state = HC_STATE_HALT;
++ return;
++ }
++}
+
-+enum
-+{
-+ PCI0_PhysicalAddress = 0x18080000,
-+ PCI_PhysicalAddress = PCI0_PhysicalAddress,
++/*-------------------------------------------------------------------------*/
+
-+ PCI0_VirtualAddress = 0xB8080000,
-+ PCI_VirtualAddress = PCI0_VirtualAddress,
-+} ;
++static void ehci_work(struct ehci_hcd *ehci);
+
-+enum
-+{
-+ PCI_LbaCount = 4, // Local base addresses.
-+} ;
++#include "ehci-hub.c"
++#include "ehci-mem.c"
++#include "ehci-q.c"
++#include "ehci-sched.c"
+
-+typedef struct
-+{
-+ u32 a ; // Address.
-+ u32 c ; // Control.
-+ u32 m ; // mapping.
-+} PCI_Map_s ;
++/*-------------------------------------------------------------------------*/
+
-+typedef struct
++static void ehci_watchdog (unsigned long param)
+{
-+ u32 pcic ;
-+ u32 pcis ;
-+ u32 pcism ;
-+ u32 pcicfga ;
-+ u32 pcicfgd ;
-+ PCI_Map_s pcilba [PCI_LbaCount] ;
-+ u32 pcidac ;
-+ u32 pcidas ;
-+ u32 pcidasm ;
-+ u32 pcidad ;
-+ u32 pcidma8c ;
-+ u32 pcidma9c ;
-+ u32 pcitc ;
-+} volatile *PCI_t ;
-+
-+// PCI messaging unit.
-+enum
-+{
-+ PCIM_Count = 2,
-+} ;
-+typedef struct
++ struct ehci_hcd *ehci = (struct ehci_hcd *) param;
++ unsigned long flags;
++
++ spin_lock_irqsave (&ehci->lock, flags);
++
++ /* lost IAA irqs wedge things badly; seen with a vt8235 */
++ if (ehci->reclaim) {
++ u32 status = ehci_readl(ehci, &ehci->regs->status);
++ if (status & STS_IAA) {
++ ehci_vdbg (ehci, "lost IAA\n");
++ COUNT (ehci->stats.lost_iaa);
++ ehci_writel(ehci, STS_IAA, &ehci->regs->status);
++ ehci->reclaim_ready = 1;
++ }
++ }
++
++ /* stop async processing after it's idled a bit */
++ if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
++ start_unlink_async (ehci, ehci->async);
++
++ /* ehci could run by timer, without IRQs ... */
++ ehci_work (ehci);
++
++ spin_unlock_irqrestore (&ehci->lock, flags);
++}
++
++/* On some systems, leaving remote wakeup enabled prevents system shutdown.
++ * The firmware seems to think that powering off is a wakeup event!
++ * This routine turns off remote wakeup and everything else, on all ports.
++ */
++static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
+{
-+ u32 pciim [PCIM_Count] ;
-+ u32 pciom [PCIM_Count] ;
-+ u32 pciid ;
-+ u32 pciiic ;
-+ u32 pciiim ;
-+ u32 pciiod ;
-+ u32 pciioic ;
-+ u32 pciioim ;
-+} volatile *PCIM_t ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Control Register
-+ *
-+ ******************************************************************************/
-+enum
++ int port = HCS_N_PORTS(ehci->hcs_params);
++
++ while (port--)
++ ehci_writel(ehci, PORT_RWC_BITS,
++ &ehci->regs->port_status[port]);
++}
++
++/* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
++ * This forcibly disables dma and IRQs, helping kexec and other cases
++ * where the next system software may expect clean state.
++ */
++static void
++ehci_shutdown (struct usb_hcd *hcd)
+{
-+ PCIC_en_b = 0,
-+ PCIC_en_m = 0x00000001,
-+ PCIC_tnr_b = 1,
-+ PCIC_tnr_m = 0x00000002,
-+ PCIC_sce_b = 2,
-+ PCIC_sce_m = 0x00000004,
-+ PCIC_ien_b = 3,
-+ PCIC_ien_m = 0x00000008,
-+ PCIC_aaa_b = 4,
-+ PCIC_aaa_m = 0x00000010,
-+ PCIC_eap_b = 5,
-+ PCIC_eap_m = 0x00000020,
-+ PCIC_pcim_b = 6,
-+ PCIC_pcim_m = 0x000001c0,
-+ PCIC_pcim_disabled_v = 0,
-+ PCIC_pcim_tnr_v = 1, // Satellite - target not ready
-+ PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
-+ PCIC_pcim_extern_v = 3, // Host - external arbiter.
-+ PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
-+ PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
-+ PCIC_pcim_reserved6_v = 6,
-+ PCIC_pcim_reserved7_v = 7,
-+ PCIC_igm_b = 9,
-+ PCIC_igm_m = 0x00000200,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Status Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIS_eed_b = 0,
-+ PCIS_eed_m = 0x00000001,
-+ PCIS_wr_b = 1,
-+ PCIS_wr_m = 0x00000002,
-+ PCIS_nmi_b = 2,
-+ PCIS_nmi_m = 0x00000004,
-+ PCIS_ii_b = 3,
-+ PCIS_ii_m = 0x00000008,
-+ PCIS_cwe_b = 4,
-+ PCIS_cwe_m = 0x00000010,
-+ PCIS_cre_b = 5,
-+ PCIS_cre_m = 0x00000020,
-+ PCIS_mdpe_b = 6,
-+ PCIS_mdpe_m = 0x00000040,
-+ PCIS_sta_b = 7,
-+ PCIS_sta_m = 0x00000080,
-+ PCIS_rta_b = 8,
-+ PCIS_rta_m = 0x00000100,
-+ PCIS_rma_b = 9,
-+ PCIS_rma_m = 0x00000200,
-+ PCIS_sse_b = 10,
-+ PCIS_sse_m = 0x00000400,
-+ PCIS_ose_b = 11,
-+ PCIS_ose_m = 0x00000800,
-+ PCIS_pe_b = 12,
-+ PCIS_pe_m = 0x00001000,
-+ PCIS_tae_b = 13,
-+ PCIS_tae_m = 0x00002000,
-+ PCIS_rle_b = 14,
-+ PCIS_rle_m = 0x00004000,
-+ PCIS_bme_b = 15,
-+ PCIS_bme_m = 0x00008000,
-+ PCIS_prd_b = 16,
-+ PCIS_prd_m = 0x00010000,
-+ PCIS_rip_b = 17,
-+ PCIS_rip_m = 0x00020000,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Status Mask Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCISM_eed_b = 0,
-+ PCISM_eed_m = 0x00000001,
-+ PCISM_wr_b = 1,
-+ PCISM_wr_m = 0x00000002,
-+ PCISM_nmi_b = 2,
-+ PCISM_nmi_m = 0x00000004,
-+ PCISM_ii_b = 3,
-+ PCISM_ii_m = 0x00000008,
-+ PCISM_cwe_b = 4,
-+ PCISM_cwe_m = 0x00000010,
-+ PCISM_cre_b = 5,
-+ PCISM_cre_m = 0x00000020,
-+ PCISM_mdpe_b = 6,
-+ PCISM_mdpe_m = 0x00000040,
-+ PCISM_sta_b = 7,
-+ PCISM_sta_m = 0x00000080,
-+ PCISM_rta_b = 8,
-+ PCISM_rta_m = 0x00000100,
-+ PCISM_rma_b = 9,
-+ PCISM_rma_m = 0x00000200,
-+ PCISM_sse_b = 10,
-+ PCISM_sse_m = 0x00000400,
-+ PCISM_ose_b = 11,
-+ PCISM_ose_m = 0x00000800,
-+ PCISM_pe_b = 12,
-+ PCISM_pe_m = 0x00001000,
-+ PCISM_tae_b = 13,
-+ PCISM_tae_m = 0x00002000,
-+ PCISM_rle_b = 14,
-+ PCISM_rle_m = 0x00004000,
-+ PCISM_bme_b = 15,
-+ PCISM_bme_m = 0x00008000,
-+ PCISM_prd_b = 16,
-+ PCISM_prd_m = 0x00010000,
-+ PCISM_rip_b = 17,
-+ PCISM_rip_m = 0x00020000,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Configuration Address Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCICFGA_reg_b = 2,
-+ PCICFGA_reg_m = 0x000000fc,
-+ PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
-+ PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
-+ PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
-+ PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
-+ PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
-+ PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
-+ PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
-+ PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
-+ PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
-+ PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
-+ PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba0m_v = 0x48>>2,
-+ PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba1m_v = 0x50>>2,
-+ PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba2m_v = 0x58>>2,
-+ PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba3m_v = 0x60>>2,
-+ PCICFGA_reg_pmgt_v = 0x64>>2,
-+ PCICFGA_func_b = 8,
-+ PCICFGA_func_m = 0x00000700,
-+ PCICFGA_dev_b = 11,
-+ PCICFGA_dev_m = 0x0000f800,
-+ PCICFGA_dev_internal_v = 0,
-+ PCICFGA_bus_b = 16,
-+ PCICFGA_bus_m = 0x00ff0000,
-+ PCICFGA_bus_type0_v = 0, //local bus
-+ PCICFGA_en_b = 31, // read only
-+ PCICFGA_en_m = 0x80000000,
-+} ;
-+
-+enum {
-+ PCFGID_vendor_b = 0,
-+ PCFGID_vendor_m = 0x0000ffff,
-+ PCFGID_vendor_IDT_v = 0x111d,
-+ PCFGID_device_b = 16,
-+ PCFGID_device_m = 0xffff0000,
-+ PCFGID_device_Korinade_v = 0x0214,
-+
-+ PCFG04_command_ioena_b = 1,
-+ PCFG04_command_ioena_m = 0x00000001,
-+ PCFG04_command_memena_b = 2,
-+ PCFG04_command_memena_m = 0x00000002,
-+ PCFG04_command_bmena_b = 3,
-+ PCFG04_command_bmena_m = 0x00000004,
-+ PCFG04_command_mwinv_b = 5,
-+ PCFG04_command_mwinv_m = 0x00000010,
-+ PCFG04_command_parena_b = 7,
-+ PCFG04_command_parena_m = 0x00000040,
-+ PCFG04_command_serrena_b = 9,
-+ PCFG04_command_serrena_m = 0x00000100,
-+ PCFG04_command_fastbbena_b = 10,
-+ PCFG04_command_fastbbena_m = 0x00000200,
-+ PCFG04_status_b = 16,
-+ PCFG04_status_m = 0xffff0000,
-+ PCFG04_status_66MHz_b = 21, // 66 MHz enable
-+ PCFG04_status_66MHz_m = 0x00200000,
-+ PCFG04_status_fbb_b = 23,
-+ PCFG04_status_fbb_m = 0x00800000,
-+ PCFG04_status_mdpe_b = 24,
-+ PCFG04_status_mdpe_m = 0x01000000,
-+ PCFG04_status_dst_b = 25,
-+ PCFG04_status_dst_m = 0x06000000,
-+ PCFG04_status_sta_b = 27,
-+ PCFG04_status_sta_m = 0x08000000,
-+ PCFG04_status_rta_b = 28,
-+ PCFG04_status_rta_m = 0x10000000,
-+ PCFG04_status_rma_b = 29,
-+ PCFG04_status_rma_m = 0x20000000,
-+ PCFG04_status_sse_b = 30,
-+ PCFG04_status_sse_m = 0x40000000,
-+ PCFG04_status_pe_b = 31,
-+ PCFG04_status_pe_m = 0x40000000,
-+
-+ PCFG08_revId_b = 0,
-+ PCFG08_revId_m = 0x000000ff,
-+ PCFG08_classCode_b = 0,
-+ PCFG08_classCode_m = 0xffffff00,
-+ PCFG08_classCode_bridge_v = 06,
-+ PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
-+ PCFG0C_cacheline_b = 0,
-+ PCFG0C_cacheline_m = 0x000000ff,
-+ PCFG0C_masterLatency_b = 8,
-+ PCFG0C_masterLatency_m = 0x0000ff00,
-+ PCFG0C_headerType_b = 16,
-+ PCFG0C_headerType_m = 0x00ff0000,
-+ PCFG0C_bist_b = 24,
-+ PCFG0C_bist_m = 0xff000000,
-+
-+ PCIPBA_msi_b = 0,
-+ PCIPBA_msi_m = 0x00000001,
-+ PCIPBA_p_b = 3,
-+ PCIPBA_p_m = 0x00000004,
-+ PCIPBA_baddr_b = 8,
-+ PCIPBA_baddr_m = 0xffffff00,
-+
-+ PCFGSS_vendorId_b = 0,
-+ PCFGSS_vendorId_m = 0x0000ffff,
-+ PCFGSS_id_b = 16,
-+ PCFGSS_id_m = 0xffff0000,
-+
-+ PCFG3C_interruptLine_b = 0,
-+ PCFG3C_interruptLine_m = 0x000000ff,
-+ PCFG3C_interruptPin_b = 8,
-+ PCFG3C_interruptPin_m = 0x0000ff00,
-+ PCFG3C_minGrant_b = 16,
-+ PCFG3C_minGrant_m = 0x00ff0000,
-+ PCFG3C_maxLat_b = 24,
-+ PCFG3C_maxLat_m = 0xff000000,
-+
-+ PCIPBAC_msi_b = 0,
-+ PCIPBAC_msi_m = 0x00000001,
-+ PCIPBAC_p_b = 1,
-+ PCIPBAC_p_m = 0x00000002,
-+ PCIPBAC_size_b = 2,
-+ PCIPBAC_size_m = 0x0000007c,
-+ PCIPBAC_sb_b = 7,
-+ PCIPBAC_sb_m = 0x00000080,
-+ PCIPBAC_pp_b = 8,
-+ PCIPBAC_pp_m = 0x00000100,
-+ PCIPBAC_mr_b = 9,
-+ PCIPBAC_mr_m = 0x00000600,
-+ PCIPBAC_mr_read_v =0, //no prefetching
-+ PCIPBAC_mr_readLine_v =1,
-+ PCIPBAC_mr_readMult_v =2,
-+ PCIPBAC_mrl_b = 11,
-+ PCIPBAC_mrl_m = 0x00000800,
-+ PCIPBAC_mrm_b = 12,
-+ PCIPBAC_mrm_m = 0x00001000,
-+ PCIPBAC_trp_b = 13,
-+ PCIPBAC_trp_m = 0x00002000,
-+
-+ PCFG40_trdyTimeout_b = 0,
-+ PCFG40_trdyTimeout_m = 0x000000ff,
-+ PCFG40_retryLim_b = 8,
-+ PCFG40_retryLim_m = 0x0000ff00,
-+};
++ struct ehci_hcd *ehci;
+
-+/*******************************************************************************
-+ *
-+ * PCI Local Base Address [0|1|2|3] Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
-+ PCILBA_baddr_m = 0xffffff00,
-+} ;
-+/*******************************************************************************
-+ *
-+ * PCI Local Base Address Control Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
-+ PCILBAC_msi_m = 0x00000001,
-+ PCILBAC_msi_mem_v = 0,
-+ PCILBAC_msi_io_v = 1,
-+ PCILBAC_size_b = 2, // In pPci->pcilba[i].c
-+ PCILBAC_size_m = 0x0000007c,
-+ PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
-+ PCILBAC_sb_m = 0x00000080,
-+ PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
-+ PCILBAC_rt_m = 0x00000100,
-+ PCILBAC_rt_noprefetch_v = 0, // mem read
-+ PCILBAC_rt_prefetch_v = 1, // mem readline
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Local Base Address [0|1|2|3] Mapping Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCILBAM_maddr_b = 8,
-+ PCILBAM_maddr_m = 0xffffff00,
-+} ;
++ ehci = hcd_to_ehci (hcd);
++ (void) ehci_halt (ehci);
++ ehci_turn_off_all_ports(ehci);
+
-+/*******************************************************************************
-+ *
-+ * PCI Decoupled Access Control Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIDAC_den_b = 0,
-+ PCIDAC_den_m = 0x00000001,
-+} ;
++ /* make BIOS/etc use companion controller during reboot */
++ ehci_writel(ehci, 0, &ehci->regs->configured_flag);
+
-+/*******************************************************************************
-+ *
-+ * PCI Decoupled Access Status Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIDAS_d_b = 0,
-+ PCIDAS_d_m = 0x00000001,
-+ PCIDAS_b_b = 1,
-+ PCIDAS_b_m = 0x00000002,
-+ PCIDAS_e_b = 2,
-+ PCIDAS_e_m = 0x00000004,
-+ PCIDAS_ofe_b = 3,
-+ PCIDAS_ofe_m = 0x00000008,
-+ PCIDAS_off_b = 4,
-+ PCIDAS_off_m = 0x00000010,
-+ PCIDAS_ife_b = 5,
-+ PCIDAS_ife_m = 0x00000020,
-+ PCIDAS_iff_b = 6,
-+ PCIDAS_iff_m = 0x00000040,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI DMA Channel 8 Configuration Register
-+ *
-+ ******************************************************************************/
-+enum
-+{
-+ PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
-+ PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
-+ PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
-+ PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
-+} ;
++ /* unblock posted writes */
++ ehci_readl(ehci, &ehci->regs->configured_flag);
++}
+
-+/*******************************************************************************
-+ *
-+ * PCI DMA Channel 9 Configuration Register
-+ *
-+ ******************************************************************************/
-+enum
++static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
+{
-+ PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
-+ PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
-+} ;
++ unsigned port;
+
-+/*******************************************************************************
-+ *
-+ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
-+ PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
-+ // These are for reads (DMA channel 8)
-+ PCIDMAD_devcmd_mr_v = 0, //memory read
-+ PCIDMAD_devcmd_mrl_v = 1, //memory read line
-+ PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
-+ PCIDMAD_devcmd_ior_v = 3, //I/O read
-+ // These are for writes (DMA channel 9)
-+ PCIDMAD_devcmd_mw_v = 0, //memory write
-+ PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
-+ PCIDMAD_devcmd_iow_v = 3, //I/O write
-+
-+ // Swap byte field applies to both DMA channel 8 and 9
-+ PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
-+ PCIDMAD_sb_m = 0x01000000, // swap byte field
-+} ;
-+
-+
-+/*******************************************************************************
-+ *
-+ * PCI Target Control Register
-+ *
-+ ******************************************************************************/
-+enum
++ if (!HCS_PPC (ehci->hcs_params))
++ return;
++
++ ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
++ for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
++ (void) ehci_hub_control(ehci_to_hcd(ehci),
++ is_on ? SetPortFeature : ClearPortFeature,
++ USB_PORT_FEAT_POWER,
++ port--, NULL, 0);
++ msleep(20);
++}
++
++/*-------------------------------------------------------------------------*/
++
++/*
++ * ehci_work is called from some interrupts, timers, and so on.
++ * it calls driver completion functions, after dropping ehci->lock.
++ */
++static void ehci_work (struct ehci_hcd *ehci)
+{
-+ PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
-+ PCITC_rtimer_m = 0x000000ff,
-+ PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
-+ PCITC_dtimer_m = 0x0000ff00,
-+ PCITC_rdr_b = 18, // In PCITC_t -> pcitc
-+ PCITC_rdr_m = 0x00040000,
-+ PCITC_ddt_b = 19, // In PCITC_t -> pcitc
-+ PCITC_ddt_m = 0x00080000,
-+} ;
-+/*******************************************************************************
-+ *
-+ * PCI messaging unit [applies to both inbound and outbound registers ]
-+ *
-+ ******************************************************************************/
-+enum
++ timer_action_done (ehci, TIMER_IO_WATCHDOG);
++ if (ehci->reclaim_ready)
++ end_unlink_async (ehci);
++
++ /* another CPU may drop ehci->lock during a schedule scan while
++ * it reports urb completions. this flag guards against bogus
++ * attempts at re-entrant schedule scanning.
++ */
++ if (ehci->scanning)
++ return;
++ ehci->scanning = 1;
++ scan_async (ehci);
++ if (ehci->next_uframe != -1)
++ scan_periodic (ehci);
++ ehci->scanning = 0;
++
++ /* the IO watchdog guards against hardware or driver bugs that
++ * misplace IRQs, and should let us run completely without IRQs.
++ * such lossage has been observed on both VT6202 and VT8235.
++ */
++ if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
++ (ehci->async->qh_next.ptr != NULL ||
++ ehci->periodic_sched != 0))
++ timer_action (ehci, TIMER_IO_WATCHDOG);
++}
++
++static void ehci_stop (struct usb_hcd *hcd)
+{
-+ PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
-+ PCIM_m0_m = 0x00000001, // inbound or outbound message 0
-+ PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
-+ PCIM_m1_m = 0x00000002, // inbound or outbound message 1
-+ PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
-+ PCIM_db_m = 0x00000004, // inbound or outbound doorbell
-+};
++ struct ehci_hcd *ehci = hcd_to_ehci (hcd);
+
++ ehci_dbg (ehci, "stop\n");
+
++ /* Turn off port power on all root hub ports. */
++ ehci_port_power (ehci, 0);
+
++ /* no more interrupts ... */
++ del_timer_sync (&ehci->watchdog);
+
++ spin_lock_irq(&ehci->lock);
++ if (HC_IS_RUNNING (hcd->state))
++ ehci_quiesce (ehci);
+
++ ehci_reset (ehci);
++ ehci_writel(ehci, 0, &ehci->regs->intr_enable);
++ spin_unlock_irq(&ehci->lock);
+
-+#define PCI_MSG_VirtualAddress 0xB8088010
-+#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
-+#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
++ /* let companion controllers work when we aren't */
++ ehci_writel(ehci, 0, &ehci->regs->configured_flag);
+
-+#define PCIM_SHFT 0x6
-+#define PCIM_BIT_LEN 0x7
-+#define PCIM_H_EA 0x3
-+#define PCIM_H_IA_FIX 0x4
-+#define PCIM_H_IA_RR 0x5
-+#if 0
-+#define PCI_ADDR_START 0x13000000
-+#endif
++ remove_companion_file(ehci);
++ remove_debug_files (ehci);
+
-+#define PCI_ADDR_START 0x50000000
-+
-+#define CPUTOPCI_MEM_WIN 0x02000000
-+#define CPUTOPCI_IO_WIN 0x00100000
-+#define PCILBA_SIZE_SHFT 2
-+#define PCILBA_SIZE_MASK 0x1F
-+#define SIZE_256MB 0x1C
-+#define SIZE_128MB 0x1B
-+#define SIZE_64MB 0x1A
-+#define SIZE_32MB 0x19
-+#define SIZE_16MB 0x18
-+#define SIZE_4MB 0x16
-+#define SIZE_2MB 0x15
-+#define SIZE_1MB 0x14
-+#define KORINA_CONFIG0_ADDR 0x80000000
-+#define KORINA_CONFIG1_ADDR 0x80000004
-+#define KORINA_CONFIG2_ADDR 0x80000008
-+#define KORINA_CONFIG3_ADDR 0x8000000C
-+#define KORINA_CONFIG4_ADDR 0x80000010
-+#define KORINA_CONFIG5_ADDR 0x80000014
-+#define KORINA_CONFIG6_ADDR 0x80000018
-+#define KORINA_CONFIG7_ADDR 0x8000001C
-+#define KORINA_CONFIG8_ADDR 0x80000020
-+#define KORINA_CONFIG9_ADDR 0x80000024
-+#define KORINA_CONFIG10_ADDR 0x80000028
-+#define KORINA_CONFIG11_ADDR 0x8000002C
-+#define KORINA_CONFIG12_ADDR 0x80000030
-+#define KORINA_CONFIG13_ADDR 0x80000034
-+#define KORINA_CONFIG14_ADDR 0x80000038
-+#define KORINA_CONFIG15_ADDR 0x8000003C
-+#define KORINA_CONFIG16_ADDR 0x80000040
-+#define KORINA_CONFIG17_ADDR 0x80000044
-+#define KORINA_CONFIG18_ADDR 0x80000048
-+#define KORINA_CONFIG19_ADDR 0x8000004C
-+#define KORINA_CONFIG20_ADDR 0x80000050
-+#define KORINA_CONFIG21_ADDR 0x80000054
-+#define KORINA_CONFIG22_ADDR 0x80000058
-+#define KORINA_CONFIG23_ADDR 0x8000005C
-+#define KORINA_CONFIG24_ADDR 0x80000060
-+#define KORINA_CONFIG25_ADDR 0x80000064
-+#define KORINA_CMD (PCFG04_command_ioena_m | \
-+ PCFG04_command_memena_m | \
-+ PCFG04_command_bmena_m | \
-+ PCFG04_command_mwinv_m | \
-+ PCFG04_command_parena_m | \
-+ PCFG04_command_serrena_m )
-+
-+#define KORINA_STAT (PCFG04_status_mdpe_m | \
-+ PCFG04_status_sta_m | \
-+ PCFG04_status_rta_m | \
-+ PCFG04_status_rma_m | \
-+ PCFG04_status_sse_m | \
-+ PCFG04_status_pe_m)
-+
-+#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
-+
-+#define KORINA_REVID 0
-+#define KORINA_CLASS_CODE 0
-+#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
-+ KORINA_REVID)
-+
-+#define KORINA_CACHE_LINE_SIZE 4
-+#define KORINA_MASTER_LAT 0x3c
-+#define KORINA_HEADER_TYPE 0
-+#define KORINA_BIST 0
-+
-+#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
-+ (KORINA_HEADER_TYPE<<16) | \
-+ (KORINA_MASTER_LAT<<8) | \
-+ KORINA_CACHE_LINE_SIZE )
-+
-+#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
-+#define KORINA_BAR1 0x18800001 /* 1 MB IO */
-+#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
-+ internal Registers */
-+#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
-+
-+#define KORINA_CNFG4 KORINA_BAR0
-+#define KORINA_CNFG5 KORINA_BAR1
-+#define KORINA_CNFG6 KORINA_BAR2
-+#define KORINA_CNFG7 KORINA_BAR3
-+
-+#define KORINA_SUBSYS_VENDOR_ID 0x011d
-+#define KORINA_SUBSYSTEM_ID 0x0214
-+#define KORINA_CNFG8 0
-+#define KORINA_CNFG9 0
-+#define KORINA_CNFG10 0
-+#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
-+ KORINA_SUBSYSTEM_ID)
-+#define KORINA_INT_LINE 1
-+#define KORINA_INT_PIN 1
-+#define KORINA_MIN_GNT 8
-+#define KORINA_MAX_LAT 0x38
-+#define KORINA_CNFG12 0
-+#define KORINA_CNFG13 0
-+#define KORINA_CNFG14 0
-+#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
-+ (KORINA_MIN_GNT<<16) | \
-+ (KORINA_INT_PIN<<8) | \
-+ KORINA_INT_LINE)
-+#define KORINA_RETRY_LIMIT 0x80
-+#define KORINA_TRDY_LIMIT 0x80
-+#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
-+ KORINA_TRDY_LIMIT)
-+#define PCI_PBAxC_R 0x0
-+#define PCI_PBAxC_RL 0x1
-+#define PCI_PBAxC_RM 0x2
-+#define SIZE_SHFT 2
-+
-+#if defined(__MIPSEB__)
-+#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
-+ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
-+ PCIPBAC_pp_m | \
-+ (SIZE_128MB<<SIZE_SHFT) | \
-+ PCIPBAC_p_m)
-+#else
-+#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
-+ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
-+ PCIPBAC_pp_m | \
-+ (SIZE_128MB<<SIZE_SHFT) | \
-+ PCIPBAC_p_m)
-+#endif
-+#define KORINA_CNFG17 KORINA_PBA0C
-+#define KORINA_PBA0M 0x0
-+#define KORINA_CNFG18 KORINA_PBA0M
++ /* root hub is shut down separately (first, when possible) */
++ spin_lock_irq (&ehci->lock);
++ if (ehci->async)
++ ehci_work (ehci);
++ spin_unlock_irq (&ehci->lock);
++ ehci_mem_cleanup (ehci);
+
-+#if defined(__MIPSEB__)
-+#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
-+ PCIPBAC_msi_m)
-+#else
-+#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
-+ PCIPBAC_msi_m)
++#ifdef EHCI_STATS
++ ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
++ ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
++ ehci->stats.lost_iaa);
++ ehci_dbg (ehci, "complete %ld unlink %ld\n",
++ ehci->stats.complete, ehci->stats.unlink);
+#endif
-+#define KORINA_CNFG19 KORINA_PBA1C
-+#define KORINA_PBA1M 0x0
-+#define KORINA_CNFG20 KORINA_PBA1M
+
-+#if defined(__MIPSEB__)
-+#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
-+ PCIPBAC_msi_m)
-+#else
-+#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
-+ PCIPBAC_msi_m)
-+#endif
-+#define KORINA_CNFG21 KORINA_PBA2C
-+#define KORINA_PBA2M 0x18000000
-+#define KORINA_CNFG22 KORINA_PBA2M
-+#define KORINA_PBA3C 0
-+#define KORINA_CNFG23 KORINA_PBA3C
-+#define KORINA_PBA3M 0
-+#define KORINA_CNFG24 KORINA_PBA3M
++ dbg_status (ehci, "ehci_stop completed",
++ ehci_readl(ehci, &ehci->regs->status));
++}
+
++/* one-time init, only for memory state */
++static int ehci_init(struct usb_hcd *hcd)
++{
++ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
++ u32 temp;
++ int retval;
++ u32 hcc_params;
+
++ spin_lock_init(&ehci->lock);
+
-+#define PCITC_DTIMER_VAL 8
-+#define PCITC_RTIMER_VAL 0x10
++ init_timer(&ehci->watchdog);
++ ehci->watchdog.function = ehci_watchdog;
++ ehci->watchdog.data = (unsigned long) ehci;
+
++ /*
++ * hw default: 1K periodic list heads, one per frame.
++ * periodic_size can shrink by USBCMD update if hcc_params allows.
++ */
++ ehci->periodic_size = DEFAULT_I_TDPS;
++ if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
++ return retval;
+
++ /* controllers may cache some of the periodic schedule ... */
++ hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
++ if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
++ ehci->i_thresh = 8;
++ else // N microframes cached
++ ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
+
++ ehci->reclaim = NULL;
++ ehci->reclaim_ready = 0;
++ ehci->next_uframe = -1;
+
-+#endif // __IDT_PCI_H__
++ /*
++ * dedicate a qh for the async ring head, since we couldn't unlink
++ * a 'real' qh without stopping the async schedule [4.8]. use it
++ * as the 'reclamation list head' too.
++ * its dummy is used in hw_alt_next of many tds, to prevent the qh
++ * from automatically advancing to the next td after short reads.
++ */
++ ehci->async->qh_next.qh = NULL;
++ ehci->async->hw_next = QH_NEXT(ehci->async->qh_dma);
++ ehci->async->hw_info1 = cpu_to_le32(QH_HEAD);
++ ehci->async->hw_token = cpu_to_le32(QTD_STS_HALT);
++ ehci->async->hw_qtd_next = EHCI_LIST_END;
++ ehci->async->qh_state = QH_STATE_LINKED;
++ ehci->async->hw_alt_next = QTD_NEXT(ehci->async->dummy->qtd_dma);
++
++ /* clear interrupt enables, set irq latency */
++ if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
++ log2_irq_thresh = 0;
++ temp = 1 << (16 + log2_irq_thresh);
++ if (HCC_CANPARK(hcc_params)) {
++ /* HW default park == 3, on hardware that supports it (like
++ * NVidia and ALI silicon), maximizes throughput on the async
++ * schedule by avoiding QH fetches between transfers.
++ *
++ * With fast usb storage devices and NForce2, "park" seems to
++ * make problems: throughput reduction (!), data errors...
++ */
++ if (park) {
++ park = min(park, (unsigned) 3);
++ temp |= CMD_PARK;
++ temp |= park << 8;
++ }
++ ehci_dbg(ehci, "park %d\n", park);
++ }
++ if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
++ /* periodic schedule size can be smaller than default */
++ temp &= ~(3 << 2);
++ temp |= (EHCI_TUNE_FLS << 2);
++ switch (EHCI_TUNE_FLS) {
++ case 0: ehci->periodic_size = 1024; break;
++ case 1: ehci->periodic_size = 512; break;
++ case 2: ehci->periodic_size = 256; break;
++ default: BUG();
++ }
++ }
++ ehci->command = temp;
+
++ return 0;
++}
+
++/* start HC running; it's halted, ehci_init() has been run (once) */
++static int ehci_run (struct usb_hcd *hcd)
++{
++ struct ehci_hcd *ehci = hcd_to_ehci (hcd);
++ int retval;
++ u32 temp;
++ u32 hcc_params;
+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,119 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Reset register definitions.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ hcd->uses_new_polling = 1;
++ hcd->poll_rh = 0;
+
-+#ifndef __IDT_RST_H__
-+#define __IDT_RST_H__
++ /* EHCI spec section 4.1 */
++ if ((retval = ehci_reset(ehci)) != 0) {
++ ehci_mem_cleanup(ehci);
++ return retval;
++ }
++ ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
++ ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
+
-+enum
-+{
-+ RST0_PhysicalAddress = 0x18000000,
-+ RST_PhysicalAddress = RST0_PhysicalAddress, // Default
++ /*
++ * hcc_params controls whether ehci->regs->segment must (!!!)
++ * be used; it constrains QH/ITD/SITD and QTD locations.
++ * pci_pool consistent memory always uses segment zero.
++ * streaming mappings for I/O buffers, like pci_map_single(),
++ * can return segments above 4GB, if the device allows.
++ *
++ * NOTE: the dma mask is visible through dma_supported(), so
++ * drivers can pass this info along ... like NETIF_F_HIGHDMA,
++ * Scsi_Host.highmem_io, and so forth. It's readonly to all
++ * host side drivers though.
++ */
++ hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
++ if (HCC_64BIT_ADDR(hcc_params)) {
++ ehci_writel(ehci, 0, &ehci->regs->segment);
++#if 0
++// this is deeply broken on almost all architectures
++ if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK))
++ ehci_info(ehci, "enabled 64bit DMA\n");
++#endif
++ }
+
-+ RST0_VirtualAddress = 0xb8000000,
-+ RST_VirtualAddress = RST0_VirtualAddress, // Default
-+} ;
+
-+typedef struct RST_s
-+{
-+ u32 filler [0x0006] ;
-+ u32 sysid ;
-+ u32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
-+ u32 reset ;
-+ u32 bcv ;
-+ u32 cea ;
-+} volatile * RST_t ;
-+
-+enum
-+{
-+ SYSID_rev_b = 0,
-+ SYSID_rev_m = 0x000000ff,
-+ SYSID_imp_b = 8,
-+ SYSID_imp_m = 0x000fff00,
-+ SYSID_vendor_b = 8,
-+ SYSID_vendor_m = 0xfff00000,
-+
-+ BCV_pll_b = 0,
-+ BCV_pll_m = 0x0000000f,
-+ BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
-+ BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
-+ BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
-+ BCV_pll_SlowMul5_v = 0x3, // PCLK=5*CLK.
-+ BCV_pll_Mul5_v = 0x4, // PCLK=5*CLK.
-+ BCV_pll_SlowMul6_v = 0x5, // PCLK=6*CLK.
-+ BCV_pll_Mul6_v = 0x6, // PCLK=6*CLK.
-+ BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
-+ BCV_pll_Mul10_v = 0x8, // PCLK=10*CLK.
-+ BCV_pll_Res9_v = 0x9,
-+ BCV_pll_Res10_v = 0xa,
-+ BCV_pll_Res11_v = 0xb,
-+ BCV_pll_Res12_v = 0xc,
-+ BCV_pll_Res13_v = 0xd,
-+ BCV_pll_Res14_v = 0xe,
-+ BCV_pll_Res15_v = 0xf,
-+ BCV_clkDiv_b = 4,
-+ BCV_clkDiv_m = 0x00000030,
-+ BCV_clkDiv_Div1_v = 0x0,
-+ BCV_clkDiv_Div2_v = 0x1,
-+ BCV_clkDiv_Div4_v = 0x2,
-+ BCV_clkDiv_Res3_v = 0x3,
-+ BCV_bigEndian_b = 6,
-+ BCV_bigEndian_m = 0x00000040,
-+ BCV_resetFast_b = 7,
-+ BCV_resetFast_m = 0x00000080,
-+ BCV_pciMode_b = 8,
-+ BCV_pciMode_m = 0x00000700,
-+ BCV_pciMode_disabled_v = 0, // PCI is disabled.
-+ BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
-+ BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
-+ BCV_pciMode_external_v = 3, // host, external arbiter.
-+ BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
-+ BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
-+ BCV_pciMode_res6_v = 6,
-+ BCV_pciMode_res7_v = 7,
-+ BCV_watchDisable_b = 11,
-+ BCV_watchDisable_m = 0x00000800,
-+ BCV_res12_b = 12,
-+ BCV_res12_m = 0x00001000,
-+ BCV_res13_b = 13,
-+ BCV_res13_m = 0x00002000,
-+ BCV_res14_b = 14,
-+ BCV_res14_m = 0x00004000,
-+ BCV_res15_b = 15,
-+ BCV_res15_m = 0x00008000,
-+} ;
-+#endif // __IDT_RST_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,120 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Serial Peripheral Interface register definitions.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ // Philips, Intel, and maybe others need CMD_RUN before the
++ // root hub will detect new devices (why?); NEC doesn't
++ ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
++ ehci->command |= CMD_RUN;
++ ehci_writel(ehci, ehci->command, &ehci->regs->command);
++ dbg_cmd (ehci, "init", ehci->command);
+
-+#ifndef __IDT_SPI_H__
-+#define __IDT_SPI_H__
++ /*
++ * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
++ * are explicitly handed to companion controller(s), so no TT is
++ * involved with the root hub. (Except where one is integrated,
++ * and there's no companion controller unless maybe for USB OTG.)
++ */
++ hcd->state = HC_STATE_RUNNING;
++ ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
++ ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
++
++ temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
++ ehci_info (ehci,
++ "USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
++ ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
++ temp >> 8, temp & 0xff, DRIVER_VERSION,
++ ignore_oc ? ", overcurrent ignored" : "");
++
++ ehci_writel(ehci, INTR_MASK,
++ &ehci->regs->intr_enable); /* Turn On Interrupts */
++
++ /* GRR this is run-once init(), being done every time the HC starts.
++ * So long as they're part of class devices, we can't do it init()
++ * since the class device isn't created that early.
++ */
++ create_debug_files(ehci);
++ create_companion_file(ehci);
+
-+enum
-+{
-+ SPI0_PhysicalAddress = 0x18070000,
-+ SPI_PhysicalAddress = SPI0_PhysicalAddress,
++ return 0;
++}
+
-+ SPI0_VirtualAddress = 0xB8070000,
-+ SPI_VirtualAddress = SPI0_VirtualAddress,
-+} ;
++/*-------------------------------------------------------------------------*/
+
-+typedef struct
++static irqreturn_t ehci_irq (struct usb_hcd *hcd)
+{
-+ u32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
-+ u32 spc ; // spi control reg use SPC_
-+ u32 sps ; // spi status reg use SPS_
-+ u32 spd ; // spi data reg use SPD_
-+ u32 siofunc ; // serial IO function use SIOFUNC_
-+ u32 siocfg ; // serial IO config use SIOCFG_
-+ u32 siod; // serial IO data use SIOD_
-+} volatile *SPI_t ;
-+
-+enum
-+{
-+ SPCP_div_b = 0,
-+ SPCP_div_m = 0x000000ff,
-+ SPC_spr_b = 0,
-+ SPC_spr_m = 0x00000003,
-+ SPC_spr_div2_v = 0,
-+ SPC_spr_div4_v = 1,
-+ SPC_spr_div16_v = 2,
-+ SPC_spr_div32_v = 3,
-+ SPC_cpha_b = 2,
-+ SPC_cpha_m = 0x00000004,
-+ SPC_cpol_b = 3,
-+ SPC_cpol_m = 0x00000008,
-+ SPC_mstr_b = 4,
-+ SPC_mstr_m = 0x00000010,
-+ SPC_spe_b = 6,
-+ SPC_spe_m = 0x00000040,
-+ SPC_spie_b = 7,
-+ SPC_spie_m = 0x00000080,
-+
-+ SPS_modf_b = 4,
-+ SPS_modf_m = 0x00000010,
-+ SPS_wcol_b = 6,
-+ SPS_wcol_m = 0x00000040,
-+ SPS_spif_b = 7,
-+ SPS_spif_m = 0x00000070,
-+
-+ SPD_data_b = 0,
-+ SPD_data_m = 0x000000ff,
-+
-+ SIOFUNC_sdo_b = 0,
-+ SIOFUNC_sdo_m = 0x00000001,
-+ SIOFUNC_sdi_b = 1,
-+ SIOFUNC_sdi_m = 0x00000002,
-+ SIOFUNC_sck_b = 2,
-+ SIOFUNC_sck_m = 0x00000004,
-+ SIOFUNC_pci_b = 3,
-+ SIOFUNC_pci_m = 0x00000008,
-+
-+ SIOCFG_sdo_b = 0,
-+ SIOCFG_sdo_m = 0x00000001,
-+ SIOCFG_sdi_b = 1,
-+ SIOCFG_sdi_m = 0x00000002,
-+ SIOCFG_sck_b = 2,
-+ SIOCFG_sck_m = 0x00000004,
-+ SIOCFG_pci_b = 3,
-+ SIOCFG_pci_m = 0x00000008,
-+
-+ SIOD_sdo_b = 0,
-+ SIOD_sdo_m = 0x00000001,
-+ SIOD_sdi_b = 1,
-+ SIOD_sdi_m = 0x00000002,
-+ SIOD_sck_b = 2,
-+ SIOD_sck_m = 0x00000004,
-+ SIOD_pci_b = 3,
-+ SIOD_pci_m = 0x00000008,
-+} ;
-+#endif // __IDT_SPI_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,91 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for timer registers
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt,neb.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ struct ehci_hcd *ehci = hcd_to_ehci (hcd);
++ u32 status, pcd_status = 0;
++ int bh;
+
-+#ifndef __IDT_TIM_H__
-+#define __IDT_TIM_H__
++ spin_lock (&ehci->lock);
+
-+enum
-+{
-+ TIM0_PhysicalAddress = 0x18028000,
-+ TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
++ status = ehci_readl(ehci, &ehci->regs->status);
+
-+ TIM0_VirtualAddress = 0xb8028000,
-+ TIM_VirtualAddress = TIM0_VirtualAddress, // Default
-+} ;
++ /* e.g. cardbus physical eject */
++ if (status == ~(u32) 0) {
++ ehci_dbg (ehci, "device removed\n");
++ goto dead;
++ }
+
-+enum
-+{
-+ TIM_Count = 3,
-+} ;
++ status &= INTR_MASK;
++ if (!status) { /* irq sharing? */
++ spin_unlock(&ehci->lock);
++ return IRQ_NONE;
++ }
+
-+struct TIM_CNTR_s
-+{
-+ u32 count ;
-+ u32 compare ;
-+ u32 ctc ; //use CTC_
-+} ;
++ /* clear (just) interrupts */
++ ehci_writel(ehci, status, &ehci->regs->status);
++ ehci_readl(ehci, &ehci->regs->command); /* unblock posted write */
++ bh = 0;
+
-+typedef struct TIM_s
-+{
-+ struct TIM_CNTR_s tim [TIM_Count] ;
-+ u32 rcount ; //use RCOUNT_
-+ u32 rcompare ; //use RCOMPARE_
-+ u32 rtc ; //use RTC_
-+} volatile * TIM_t ;
++#ifdef EHCI_VERBOSE_DEBUG
++ /* unrequested/ignored: Frame List Rollover */
++ dbg_status (ehci, "irq", status);
++#endif
+
-+enum
-+{
-+ CTC_en_b = 0,
-+ CTC_en_m = 0x00000001,
-+ CTC_to_b = 1,
-+ CTC_to_m = 0x00000002,
-+
-+ RCOUNT_count_b = 0,
-+ RCOUNT_count_m = 0x0000ffff,
-+ RCOMPARE_compare_b = 0,
-+ RCOMPARE_compare_m = 0x0000ffff,
-+ RTC_ce_b = 0,
-+ RTC_ce_m = 0x00000001,
-+ RTC_to_b = 1,
-+ RTC_to_m = 0x00000002,
-+ RTC_rqe_b = 2,
-+ RTC_rqe_m = 0x00000004,
-+
-+} ;
-+#endif // __IDT_TIM_H__
-+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,189 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * UART register definitions
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
++ /* INT, ERR, and IAA interrupt rates can be throttled */
++
++ /* normal [4.15.1.2] or error [4.15.1.1] completion */
++ if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
++ if (likely ((status & STS_ERR) == 0))
++ COUNT (ehci->stats.normal);
++ else
++ COUNT (ehci->stats.error);
++ bh = 1;
++ }
++
++ /* complete the unlinking of some qh [4.15.2.3] */
++ if (status & STS_IAA) {
++ COUNT (ehci->stats.reclaim);
++ ehci->reclaim_ready = 1;
++ bh = 1;
++ }
++
++ /* remote wakeup [4.3.1] */
++ if (status & STS_PCD) {
++ unsigned i = HCS_N_PORTS (ehci->hcs_params);
++ pcd_status = status;
++
++ /* resume root hub? */
++ if (!(ehci_readl(ehci, &ehci->regs->command) & CMD_RUN))
++ usb_hcd_resume_root_hub(hcd);
++
++ while (i--) {
++ int pstatus = ehci_readl(ehci,
++ &ehci->regs->port_status [i]);
++
++ if (pstatus & PORT_OWNER)
++ continue;
++ if (!(pstatus & PORT_RESUME)
++ || ehci->reset_done [i] != 0)
++ continue;
++
++ /* start 20 msec resume signaling from this port,
++ * and make khubd collect PORT_STAT_C_SUSPEND to
++ * stop that signaling.
++ */
++ ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
++ ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
++ mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
++ }
++ }
++
++ /* PCI errors [4.15.2.4] */
++ if (unlikely ((status & STS_FATAL) != 0)) {
++ /* bogus "fatal" IRQs appear on some chips... why? */
++ status = ehci_readl(ehci, &ehci->regs->status);
++ dbg_cmd (ehci, "fatal", ehci_readl(ehci,
++ &ehci->regs->command));
++ dbg_status (ehci, "fatal", status);
++ if (status & STS_HALT) {
++ ehci_err (ehci, "fatal error\n");
++dead:
++ ehci_reset (ehci);
++ ehci_writel(ehci, 0, &ehci->regs->configured_flag);
++ /* generic layer kills/unlinks all urbs, then
++ * uses ehci_stop to clean up the rest
++ */
++ bh = 1;
++ }
++ }
++
++ if (bh)
++ ehci_work (ehci);
++ spin_unlock (&ehci->lock);
++ if (pcd_status & STS_PCD)
++ usb_hcd_poll_rh_status(hcd);
++ return IRQ_HANDLED;
++}
++
++/*-------------------------------------------------------------------------*/
++
++/*
++ * non-error returns are a promise to giveback() the urb later
++ * we drop ownership so next owner (or urb unlink) can get it
+ *
-+ * Initial Release
++ * urb + dev is in hcd.self.controller.urb_list
++ * we're queueing TDs onto software and hardware lists
+ *
-+ *
++ * hcd-specific init for hcpriv hasn't been done yet
+ *
-+ **************************************************************************
++ * NOTE: control, bulk, and interrupt share the same code to append TDs
++ * to a (possibly active) QH, and the same QH scanning code.
+ */
++static int ehci_urb_enqueue (
++ struct usb_hcd *hcd,
++ struct usb_host_endpoint *ep,
++ struct urb *urb,
++ gfp_t mem_flags
++) {
++ struct ehci_hcd *ehci = hcd_to_ehci (hcd);
++ struct list_head qtd_list;
++
++ INIT_LIST_HEAD (&qtd_list);
++
++ switch (usb_pipetype (urb->pipe)) {
++ // case PIPE_CONTROL:
++ // case PIPE_BULK:
++ default:
++ if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
++ return -ENOMEM;
++ return submit_async (ehci, ep, urb, &qtd_list, mem_flags);
++
++ case PIPE_INTERRUPT:
++ if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
++ return -ENOMEM;
++ return intr_submit (ehci, ep, urb, &qtd_list, mem_flags);
++
++ case PIPE_ISOCHRONOUS:
++ if (urb->dev->speed == USB_SPEED_HIGH)
++ return itd_submit (ehci, urb, mem_flags);
++ else
++ return sitd_submit (ehci, urb, mem_flags);
++ }
++}
+
-+#ifndef __IDT_UART_H__
-+#define __IDT_UART_H__
-+
-+enum
++static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
+{
-+ UART0_PhysicalAddress = 0x1c000000,
-+ UART_PhysicalAddress = UART0_PhysicalAddress, // Default
++ /* if we need to use IAA and it's busy, defer */
++ if (qh->qh_state == QH_STATE_LINKED
++ && ehci->reclaim
++ && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) {
++ struct ehci_qh *last;
+
-+ UART0_VirtualAddress = 0xbc000000,
-+ UART_VirtualAddress = UART0_VirtualAddress, // Default
-+} ;
++ for (last = ehci->reclaim;
++ last->reclaim;
++ last = last->reclaim)
++ continue;
++ qh->qh_state = QH_STATE_UNLINK_WAIT;
++ last->reclaim = qh;
+
-+/*
-+ * Register definitions are in bytes so we can handle endian problems.
++ /* bypass IAA if the hc can't care */
++ } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim)
++ end_unlink_async (ehci);
++
++ /* something else might have unlinked the qh by now */
++ if (qh->qh_state == QH_STATE_LINKED)
++ start_unlink_async (ehci, qh);
++}
++
++/* remove from hardware lists
++ * completions normally happen asynchronously
+ */
+
-+typedef struct UART_s
++static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
+{
-+ union
-+ {
-+ u32 const uartrb ; // 0x00 - DLAB=0, read.
-+ u32 uartth ; // 0x00 - DLAB=0, write.
-+ u32 uartdll ; // 0x00 - DLAB=1, read/write.
-+ } ;
++ struct ehci_hcd *ehci = hcd_to_ehci (hcd);
++ struct ehci_qh *qh;
++ unsigned long flags;
+
-+ union
-+ {
-+ u32 uartie ; // 0x04 - DLAB=0, read/write.
-+ u32 uartdlh ; // 0x04 - DLAB=1, read/write.
-+ } ;
-+ union
-+ {
-+ u32 const uartii ; // 0x08 - DLAB=0, read.
-+ u32 uartfc ; // 0x08 - DLAB=0, write.
-+ } ;
++ spin_lock_irqsave (&ehci->lock, flags);
++ switch (usb_pipetype (urb->pipe)) {
++ // case PIPE_CONTROL:
++ // case PIPE_BULK:
++ default:
++ qh = (struct ehci_qh *) urb->hcpriv;
++ if (!qh)
++ break;
++ unlink_async (ehci, qh);
++ break;
+
-+ u32 uartlc ; // 0x0c
-+ u32 uartmc ; // 0x10
-+ u32 uartls ; // 0x14
-+ u32 uartms ; // 0x18
-+ u32 uarts ; // 0x1c
-+} volatile *UART_t ;
++ case PIPE_INTERRUPT:
++ qh = (struct ehci_qh *) urb->hcpriv;
++ if (!qh)
++ break;
++ switch (qh->qh_state) {
++ case QH_STATE_LINKED:
++ intr_deschedule (ehci, qh);
++ /* FALL THROUGH */
++ case QH_STATE_IDLE:
++ qh_completions (ehci, qh);
++ break;
++ default:
++ ehci_dbg (ehci, "bogus qh %p state %d\n",
++ qh, qh->qh_state);
++ goto done;
++ }
+
-+// Reset registers.
-+typedef u32 volatile *UARTRR_t ;
++ /* reschedule QH iff another request is queued */
++ if (!list_empty (&qh->qtd_list)
++ && HC_IS_RUNNING (hcd->state)) {
++ int status;
+
-+enum
-+{
-+ UARTIE_rda_b = 0,
-+ UARTIE_rda_m = 0x00000001,
-+ UARTIE_the_b = 1,
-+ UARTIE_the_m = 0x00000002,
-+ UARTIE_rls_b = 2,
-+ UARTIE_rls_m = 0x00000004,
-+ UARTIE_ems_b = 3,
-+ UARTIE_ems_m = 0x00000008,
-+
-+ UARTII_pi_b = 0,
-+ UARTII_pi_m = 0x00000001,
-+ UARTII_iid_b = 1,
-+ UARTII_iid_m = 0x0000000e,
-+ UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
-+ UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
-+ UARTII_iid_rda_v = 2, // Receive data available
-+ UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
-+ UARTII_iid_res4_v = 4, // reserved.
-+ UARTII_iid_res5_v = 5, // reserved.
-+ UARTII_iid_cto_v = 6, // Character timeout.
-+ UARTII_iid_res7_v = 7, // reserved.
-+
-+ UARTFC_en_b = 0,
-+ UARTFC_en_m = 0x00000001,
-+ UARTFC_rr_b = 1,
-+ UARTFC_rr_m = 0x00000002,
-+ UARTFC_tr_b = 2,
-+ UARTFC_tr_m = 0x00000004,
-+ UARTFC_dms_b = 3,
-+ UARTFC_dms_m = 0x00000008,
-+ UARTFC_rt_b = 6,
-+ UARTFC_rt_m = 0x000000c0,
-+ UARTFC_rt_1Byte_v = 0,
-+ UARTFC_rt_4Byte_v = 1,
-+ UARTFC_rt_8Byte_v = 2,
-+ UARTFC_rt_14Byte_v = 3,
-+
-+ UARTLC_wls_b = 0,
-+ UARTLC_wls_m = 0x00000003,
-+ UARTLC_wls_5Bits_v = 0,
-+ UARTLC_wls_6Bits_v = 1,
-+ UARTLC_wls_7Bits_v = 2,
-+ UARTLC_wls_8Bits_v = 3,
-+ UARTLC_stb_b = 2,
-+ UARTLC_stb_m = 0x00000004,
-+ UARTLC_pen_b = 3,
-+ UARTLC_pen_m = 0x00000008,
-+ UARTLC_eps_b = 4,
-+ UARTLC_eps_m = 0x00000010,
-+ UARTLC_sp_b = 5,
-+ UARTLC_sp_m = 0x00000020,
-+ UARTLC_sb_b = 6,
-+ UARTLC_sb_m = 0x00000040,
-+ UARTLC_dlab_b = 7,
-+ UARTLC_dlab_m = 0x00000080,
-+
-+ UARTMC_dtr_b = 0,
-+ UARTMC_dtr_m = 0x00000001,
-+ UARTMC_rts_b = 1,
-+ UARTMC_rts_m = 0x00000002,
-+ UARTMC_o1_b = 2,
-+ UARTMC_o1_m = 0x00000004,
-+ UARTMC_o2_b = 3,
-+ UARTMC_o2_m = 0x00000008,
-+ UARTMC_lp_b = 4,
-+ UARTMC_lp_m = 0x00000010,
-+
-+ UARTLS_dr_b = 0,
-+ UARTLS_dr_m = 0x00000001,
-+ UARTLS_oe_b = 1,
-+ UARTLS_oe_m = 0x00000002,
-+ UARTLS_pe_b = 2,
-+ UARTLS_pe_m = 0x00000004,
-+ UARTLS_fe_b = 3,
-+ UARTLS_fe_m = 0x00000008,
-+ UARTLS_bi_b = 4,
-+ UARTLS_bi_m = 0x00000010,
-+ UARTLS_thr_b = 5,
-+ UARTLS_thr_m = 0x00000020,
-+ UARTLS_te_b = 6,
-+ UARTLS_te_m = 0x00000040,
-+ UARTLS_rfe_b = 7,
-+ UARTLS_rfe_m = 0x00000080,
-+
-+ UARTMS_dcts_b = 0,
-+ UARTMS_dcts_m = 0x00000001,
-+ UARTMS_ddsr_b = 1,
-+ UARTMS_ddsr_m = 0x00000002,
-+ UARTMS_teri_b = 2,
-+ UARTMS_teri_m = 0x00000004,
-+ UARTMS_ddcd_b = 3,
-+ UARTMS_ddcd_m = 0x00000008,
-+ UARTMS_cts_b = 4,
-+ UARTMS_cts_m = 0x00000010,
-+ UARTMS_dsr_b = 5,
-+ UARTMS_dsr_m = 0x00000020,
-+ UARTMS_ri_b = 6,
-+ UARTMS_ri_m = 0x00000040,
-+ UARTMS_dcd_b = 7,
-+ UARTMS_dcd_m = 0x00000080,
-+} ;
-+
-+#endif // __IDT_UART_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,231 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Register definitions for IDT RC32438 DMA.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
-+#ifndef __IDT_RC32438_DMA_H__
-+#define __IDT_RC32438_DMA_H__
-+enum
-+{
-+ DMA0_PhysicalAddress = 0x18040000,
-+ DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
++ status = qh_schedule (ehci, qh);
++ spin_unlock_irqrestore (&ehci->lock, flags);
+
-+ DMA0_VirtualAddress = 0xb8040000,
-+ DMA_VirtualAddress = DMA0_VirtualAddress, // Default
-+} ;
++ if (status != 0) {
++ // shouldn't happen often, but ...
++ // FIXME kill those tds' urbs
++ err ("can't reschedule qh %p, err %d",
++ qh, status);
++ }
++ return status;
++ }
++ break;
+
-+/*
-+ * DMA descriptor (in physical memory).
-+ */
++ case PIPE_ISOCHRONOUS:
++ // itd or sitd ...
+
-+typedef struct DMAD_s
-+{
-+ u32 control ; // Control. use DMAD_*
-+ u32 ca ; // Current Address.
-+ u32 devcs ; // Device control and status.
-+ u32 link ; // Next descriptor in chain.
-+} volatile *DMAD_t ;
++ // wait till next completion, do it then.
++ // completion irqs can wait up to 1024 msec,
++ break;
++ }
++done:
++ spin_unlock_irqrestore (&ehci->lock, flags);
++ return 0;
++}
+
-+enum
-+{
-+ DMAD_size = sizeof (struct DMAD_s),
-+ DMAD_count_b = 0, // in DMAD_t -> control
-+ DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
-+ DMAD_ds_b = 20, // in DMAD_t -> control
-+ DMAD_ds_m = 0x00300000, // in DMAD_t -> control
-+ DMAD_ds_extToMem0_v = 0,
-+ DMAD_ds_memToExt0_v = 1,
-+ DMAD_ds_extToMem1_v = 0,
-+ DMAD_ds_memToExt1_v = 1,
-+ DMAD_ds_ethRcv0_v = 0,
-+ DMAD_ds_ethXmt0_v = 0,
-+ DMAD_ds_ethRcv1_v = 0,
-+ DMAD_ds_ethXmt2_v = 0,
-+ DMAD_ds_memToFifo_v = 0,
-+ DMAD_ds_fifoToMem_v = 0,
-+ DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
-+ DMAD_ds_pciToMem_v = 0,
-+ DMAD_ds_memToPci_v = 0,
-+ DMAD_ds_securityInput_v = 0,
-+ DMAD_ds_securityOutput_v = 0,
-+ DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
-+
-+ DMAD_devcmd_b = 22, // in DMAD_t -> control
-+ DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
-+ DMAD_devcmd_byte_v = 0, //memory-to-memory
-+ DMAD_devcmd_halfword_v = 1, //memory-to-memory
-+ DMAD_devcmd_word_v = 2, //memory-to-memory
-+ DMAD_devcmd_2words_v = 3, //memory-to-memory
-+ DMAD_devcmd_4words_v = 4, //memory-to-memory
-+ DMAD_devcmd_6words_v = 5, //memory-to-memory
-+ DMAD_devcmd_8words_v = 6, //memory-to-memory
-+ DMAD_devcmd_16words_v = 7, //memory-to-memory
-+ DMAD_cof_b = 25, // chain on finished
-+ DMAD_cof_m = 0x02000000, //
-+ DMAD_cod_b = 26, // chain on done
-+ DMAD_cod_m = 0x04000000, //
-+ DMAD_iof_b = 27, // interrupt on finished
-+ DMAD_iof_m = 0x08000000, //
-+ DMAD_iod_b = 28, // interrupt on done
-+ DMAD_iod_m = 0x10000000, //
-+ DMAD_t_b = 29, // terminated
-+ DMAD_t_m = 0x20000000, //
-+ DMAD_d_b = 30, // done
-+ DMAD_d_m = 0x40000000, //
-+ DMAD_f_b = 31, // finished
-+ DMAD_f_m = 0x80000000, //
-+} ;
++/*-------------------------------------------------------------------------*/
+
-+/*
-+ * DMA register (within Internal Register Map).
-+ */
++// bulk qh holds the data toggle
+
-+struct DMA_Chan_s
++static void
++ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
+{
-+ u32 dmac ; // Control.
-+ u32 dmas ; // Status.
-+ u32 dmasm ; // Mask.
-+ u32 dmadptr ; // Descriptor pointer.
-+ u32 dmandptr ; // Next descriptor pointer.
-+};
++ struct ehci_hcd *ehci = hcd_to_ehci (hcd);
++ unsigned long flags;
++ struct ehci_qh *qh, *tmp;
+
-+typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
++ /* ASSERT: any requests/urbs are being unlinked */
++ /* ASSERT: nobody can be submitting urbs for this any more */
+
-+//DMA_Channels use DMACH_count instead
++rescan:
++ spin_lock_irqsave (&ehci->lock, flags);
++ qh = ep->hcpriv;
++ if (!qh)
++ goto done;
+
-+enum
-+{
-+ DMAC_run_b = 0, //
-+ DMAC_run_m = 0x00000001, //
-+ DMAC_dm_b = 1, // done mask
-+ DMAC_dm_m = 0x00000002, //
-+ DMAC_mode_b = 2, //
-+ DMAC_mode_m = 0x0000000c, //
-+ DMAC_mode_auto_v = 0,
-+ DMAC_mode_burst_v = 1,
-+ DMAC_mode_transfer_v = 2, //usually used
-+ DMAC_mode_reserved_v = 3,
-+ DMAC_a_b = 4, //
-+ DMAC_a_m = 0x00000010, //
-+
-+ DMAS_f_b = 0, // finished (sticky)
-+ DMAS_f_m = 0x00000001, //
-+ DMAS_d_b = 1, // done (sticky)
-+ DMAS_d_m = 0x00000002, //
-+ DMAS_c_b = 2, // chain (sticky)
-+ DMAS_c_m = 0x00000004, //
-+ DMAS_e_b = 3, // error (sticky)
-+ DMAS_e_m = 0x00000008, //
-+ DMAS_h_b = 4, // halt (sticky)
-+ DMAS_h_m = 0x00000010, //
-+
-+ DMASM_f_b = 0, // finished (1=mask)
-+ DMASM_f_m = 0x00000001, //
-+ DMASM_d_b = 1, // done (1=mask)
-+ DMASM_d_m = 0x00000002, //
-+ DMASM_c_b = 2, // chain (1=mask)
-+ DMASM_c_m = 0x00000004, //
-+ DMASM_e_b = 3, // error (1=mask)
-+ DMASM_e_m = 0x00000008, //
-+ DMASM_h_b = 4, // halt (1=mask)
-+ DMASM_h_m = 0x00000010, //
-+} ;
++ /* endpoints can be iso streams. for now, we don't
++ * accelerate iso completions ... so spin a while.
++ */
++ if (qh->hw_info1 == 0) {
++ ehci_vdbg (ehci, "iso delay\n");
++ goto idle_timeout;
++ }
+
-+/*
-+ * DMA channel definitions
-+ */
++ if (!HC_IS_RUNNING (hcd->state))
++ qh->qh_state = QH_STATE_IDLE;
++ switch (qh->qh_state) {
++ case QH_STATE_LINKED:
++ for (tmp = ehci->async->qh_next.qh;
++ tmp && tmp != qh;
++ tmp = tmp->qh_next.qh)
++ continue;
++ /* periodic qh self-unlinks on empty */
++ if (!tmp)
++ goto nogood;
++ unlink_async (ehci, qh);
++ /* FALL THROUGH */
++ case QH_STATE_UNLINK: /* wait for hw to finish? */
++idle_timeout:
++ spin_unlock_irqrestore (&ehci->lock, flags);
++ schedule_timeout_uninterruptible(1);
++ goto rescan;
++ case QH_STATE_IDLE: /* fully unlinked */
++ if (list_empty (&qh->qtd_list)) {
++ qh_put (qh);
++ break;
++ }
++ /* else FALL THROUGH */
++ default:
++nogood:
++ /* caller was supposed to have unlinked any requests;
++ * that's not our job. just leak this memory.
++ */
++ ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
++ qh, ep->desc.bEndpointAddress, qh->qh_state,
++ list_empty (&qh->qtd_list) ? "" : "(has tds)");
++ break;
++ }
++ ep->hcpriv = NULL;
++done:
++ spin_unlock_irqrestore (&ehci->lock, flags);
++ return;
++}
+
-+enum
++static int ehci_get_frame (struct usb_hcd *hcd)
+{
-+ DMACH_extToMem0 = 0,
-+ DMACH_memToExt0 = 0,
-+ DMACH_extToMem1 = 1,
-+ DMACH_memToExt1 = 1,
-+ DMACH_ethRcv0 = 2,
-+ DMACH_ethXmt0 = 3,
-+ DMACH_ethRcv1 = 4,
-+ DMACH_ethXmt2 = 5,
-+ DMACH_memToFifo = 6,
-+ DMACH_fifoToMem = 7,
-+ DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
-+ DMACH_pciToMem = 8,
-+ DMACH_memToPci = 9,
-+ DMACH_securityInput = 10,
-+ DMACH_securityOutput = 11,
-+ DMACH_rng_se = 12, //randomNumberGenerator on SE
-+
-+ DMACH_count //must be last
-+};
++ struct ehci_hcd *ehci = hcd_to_ehci (hcd);
++ return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
++ ehci->periodic_size;
++}
+
++/*-------------------------------------------------------------------------*/
+
-+typedef struct DMAC_s
-+{
-+ struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
-+} volatile *DMA_t ;
++#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
+
++MODULE_DESCRIPTION (DRIVER_INFO);
++MODULE_AUTHOR (DRIVER_AUTHOR);
++MODULE_LICENSE ("GPL");
+
-+/*
-+ * External DMA parameters
-+*/
++#ifdef CONFIG_PCI
++#include "ehci-pci.c"
++#define PCI_DRIVER ehci_pci_driver
++#endif
++
++#ifdef CONFIG_MPC834x
++#include "ehci-fsl.c"
++#define PLATFORM_DRIVER ehci_fsl_driver
++#endif
++
++#ifdef CONFIG_SOC_AU1200
++#include "ehci-au1xxx.c"
++#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
++#endif
++
++#ifdef CONFIG_PPC_PS3
++#include "ehci-ps3.c"
++#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_sb_driver
++#endif
++
++#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
++ !defined(PS3_SYSTEM_BUS_DRIVER)
++#error "missing bus glue for ehci-hcd"
++#endif
+
-+enum
++static int __init ehci_hcd_init(void)
+{
-+ DMADEVCMD_ts_b = 0, // ts field in devcmd
-+ DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
-+ DMADEVCMD_ts_byte_v = 0,
-+ DMADEVCMD_ts_halfword_v = 1,
-+ DMADEVCMD_ts_word_v = 2,
-+ DMADEVCMD_ts_2word_v = 3,
-+ DMADEVCMD_ts_4word_v = 4,
-+ DMADEVCMD_ts_6word_v = 5,
-+ DMADEVCMD_ts_8word_v = 6,
-+ DMADEVCMD_ts_16word_v = 7
-+};
++ int retval = 0;
+
++ pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
++ hcd_name,
++ sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
++ sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
+
-+#if 1 // aws - Compatibility.
-+# define EXTDMA_ts_b DMADEVCMD_ts_b
-+# define EXTDMA_ts_m DMADEVCMD_ts_m
-+# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
-+# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
-+# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
-+# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
-+# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
-+# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
-+# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
-+# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
-+#endif // aws - Compatibility.
-+
-+#endif //__IDT_RC32438_DMA_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,82 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * DMA operations for IDT RC32438.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
++#ifdef PLATFORM_DRIVER
++ retval = platform_driver_register(&PLATFORM_DRIVER);
++ if (retval < 0)
++ return retval;
++#endif
++
++#ifdef PCI_DRIVER
++ retval = pci_register_driver(&PCI_DRIVER);
++ if (retval < 0) {
++#ifdef PLATFORM_DRIVER
++ platform_driver_unregister(&PLATFORM_DRIVER);
++#endif
++ return retval;
++ }
++#endif
++
++#ifdef PS3_SYSTEM_BUS_DRIVER
++ if (firmware_has_feature(FW_FEATURE_PS3_LV1)) {
++ retval = ps3_system_bus_driver_register(
++ &PS3_SYSTEM_BUS_DRIVER);
++ if (retval < 0) {
++#ifdef PLATFORM_DRIVER
++ platform_driver_unregister(&PLATFORM_DRIVER);
++#endif
++#ifdef PCI_DRIVER
++ pci_unregister_driver(&PCI_DRIVER);
++#endif
++ return retval;
++ }
++ }
++#endif
++
++ return retval;
++}
++module_init(ehci_hcd_init);
++
++static void __exit ehci_hcd_cleanup(void)
++{
++#ifdef PLATFORM_DRIVER
++ platform_driver_unregister(&PLATFORM_DRIVER);
++#endif
++#ifdef PCI_DRIVER
++ pci_unregister_driver(&PCI_DRIVER);
++#endif
++#ifdef PS3_SYSTEM_BUS_DRIVER
++ if (firmware_has_feature(FW_FEATURE_PS3_LV1))
++ ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
++#endif
++}
++module_exit(ehci_hcd_cleanup);
++
+diff -Nur linux-2.6.21.1/drivers/usb/host/ehci.h.orig linux-2.6.21.1-owrt/drivers/usb/host/ehci.h.orig
+--- linux-2.6.21.1/drivers/usb/host/ehci.h.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/drivers/usb/host/ehci.h.orig 2007-04-27 23:49:26.000000000 +0200
+@@ -0,0 +1,707 @@
++/*
++ * Copyright (c) 2001-2002 by David Brownell
+ *
-+ * Initial Release
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
+ *
-+ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
+ *
-+ **************************************************************************
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software Foundation,
++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
-+#ifndef __IDT_RC32438_DMA_V_H__
-+#define __IDT_RC32438_DMA_V_H__
-+#include <asm/idt-boards/rc32438/rc32438_dma.h>
++#ifndef __LINUX_EHCI_HCD_H
++#define __LINUX_EHCI_HCD_H
+
-+#define DMA_CHAN_OFFSET 0x14
-+#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
-+#define DMA_COUNT(count) \
-+ ((count) & DMAD_count_m)
++/* definitions used for the EHCI driver */
+
-+#define DMA_HALT_TIMEOUT 500
++/* statistics can be kept for for tuning/monitoring */
++struct ehci_stats {
++ /* irq usage */
++ unsigned long normal;
++ unsigned long error;
++ unsigned long reclaim;
++ unsigned long lost_iaa;
+
++ /* termination of urbs from core */
++ unsigned long complete;
++ unsigned long unlink;
++};
+
-+static inline int rc32438_halt_dma(DMA_Chan_t ch)
-+{
-+ int timeout=1;
-+ if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
-+ rc32438_writel(0, &ch->dmac);
-+
-+ for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
-+ if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
-+ rc32438_writel(0, &ch->dmas);
-+ break;
-+ }
-+ }
++/* ehci_hcd->lock guards shared data against other CPUs:
++ * ehci_hcd: async, reclaim, periodic (and shadow), ...
++ * usb_host_endpoint: hcpriv
++ * ehci_qh: qh_next, qtd_list
++ * ehci_qtd: qtd_list
++ *
++ * Also, hold this lock when talking to HC registers or
++ * when updating hw_* fields in shared qh/qtd/... structures.
++ */
+
-+ }
-+
-+ return timeout ? 0 : 1;
-+}
++#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
++
++struct ehci_hcd { /* one per controller */
++ /* glue to PCI and HCD framework */
++ struct ehci_caps __iomem *caps;
++ struct ehci_regs __iomem *regs;
++ struct ehci_dbg_port __iomem *debug;
++
++ __u32 hcs_params; /* cached register copy */
++ spinlock_t lock;
++
++ /* async schedule support */
++ struct ehci_qh *async;
++ struct ehci_qh *reclaim;
++ unsigned reclaim_ready : 1;
++ unsigned scanning : 1;
++
++ /* periodic schedule support */
++#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
++ unsigned periodic_size;
++ __le32 *periodic; /* hw periodic table */
++ dma_addr_t periodic_dma;
++ unsigned i_thresh; /* uframes HC might cache */
++
++ union ehci_shadow *pshadow; /* mirror hw periodic table */
++ int next_uframe; /* scan periodic, start here */
++ unsigned periodic_sched; /* periodic activity count */
++
++ /* per root hub port */
++ unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
++ /* bit vectors (one bit per port) */
++ unsigned long bus_suspended; /* which ports were
++ already suspended at the start of a bus suspend */
++ unsigned long companion_ports; /* which ports are
++ dedicated to the companion controller */
++
++ /* per-HC memory pools (could be per-bus, but ...) */
++ struct dma_pool *qh_pool; /* qh per active urb */
++ struct dma_pool *qtd_pool; /* one or more per qh */
++ struct dma_pool *itd_pool; /* itd per iso urb */
++ struct dma_pool *sitd_pool; /* sitd per split iso urb */
++
++ struct timer_list watchdog;
++ unsigned long actions;
++ unsigned stamp;
++ unsigned long next_statechange;
++ u32 command;
++
++ /* SILICON QUIRKS */
++ unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */
++ unsigned no_selective_suspend:1;
++ unsigned has_fsl_port_bug:1; /* FreeScale */
++ unsigned big_endian_mmio:1;
++
++ u8 sbrn; /* packed release number */
++
++ /* irq statistics */
++#ifdef EHCI_STATS
++ struct ehci_stats stats;
++# define COUNT(x) do { (x)++; } while (0)
++#else
++# define COUNT(x) do {} while (0)
++#endif
++};
+
++/* convert between an HCD pointer and the corresponding EHCI_HCD */
++static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
++{
++ return (struct ehci_hcd *) (hcd->hcd_priv);
++}
++static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
++{
++ return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
++}
+
+
++enum ehci_timer_action {
++ TIMER_IO_WATCHDOG,
++ TIMER_IAA_WATCHDOG,
++ TIMER_ASYNC_SHRINK,
++ TIMER_ASYNC_OFF,
++};
+
-+static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
++static inline void
++timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
+{
-+ rc32438_writel(0, &ch->dmandptr);
-+ rc32438_writel(dma_addr, &ch->dmadptr);
++ clear_bit (action, &ehci->actions);
+}
+
-+static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
++static inline void
++timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
+{
-+ rc32438_writel(dma_addr, &ch->dmandptr);
-+}
-+#endif //__IDT_RC32438_DMA_V_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,328 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for IDT EB438 ethernet
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
++ if (!test_and_set_bit (action, &ehci->actions)) {
++ unsigned long t;
++
++ switch (action) {
++ case TIMER_IAA_WATCHDOG:
++ t = EHCI_IAA_JIFFIES;
++ break;
++ case TIMER_IO_WATCHDOG:
++ t = EHCI_IO_JIFFIES;
++ break;
++ case TIMER_ASYNC_OFF:
++ t = EHCI_ASYNC_JIFFIES;
++ break;
++ // case TIMER_ASYNC_SHRINK:
++ default:
++ t = EHCI_SHRINK_JIFFIES;
++ break;
++ }
++ t += jiffies;
++ // all timings except IAA watchdog can be overridden.
++ // async queue SHRINK often precedes IAA. while it's ready
++ // to go OFF neither can matter, and afterwards the IO
++ // watchdog stops unless there's still periodic traffic.
++ if (action != TIMER_IAA_WATCHDOG
++ && t > ehci->watchdog.expires
++ && timer_pending (&ehci->watchdog))
++ return;
++ mod_timer (&ehci->watchdog, t);
++ }
++}
+
-+#ifndef __IDT_RC32438_ETH_H__
-+#define __IDT_RC32438_ETH_H__
-+enum
-+{
-+ ETH0_PhysicalAddress = 0x18058000,
-+ ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
++/*-------------------------------------------------------------------------*/
+
-+ ETH0_VirtualAddress = 0xb8058000,
-+ ETH_VirtualAddress = ETH0_VirtualAddress, // Default
-+ ETH1_PhysicalAddress = 0x18060000,
-+ ETH1_VirtualAddress = 0xb8060000, // Default
-+} ;
++/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
+
-+typedef struct
-+{
-+ u32 ethintfc ;
-+ u32 ethfifott ;
-+ u32 etharc ;
-+ u32 ethhash0 ;
-+ u32 ethhash1 ;
-+ u32 ethu0 [4] ; // Reserved.
-+ u32 ethpfs ;
-+ u32 ethmcp ;
-+ u32 eth_u1 [10] ; // Reserved.
-+ u32 ethspare ;
-+ u32 eth_u2 [42] ; // Reserved.
-+ u32 ethsal0 ;
-+ u32 ethsah0 ;
-+ u32 ethsal1 ;
-+ u32 ethsah1 ;
-+ u32 ethsal2 ;
-+ u32 ethsah2 ;
-+ u32 ethsal3 ;
-+ u32 ethsah3 ;
-+ u32 ethrbc ;
-+ u32 ethrpc ;
-+ u32 ethrupc ;
-+ u32 ethrfc ;
-+ u32 ethtbc ;
-+ u32 ethgpf ;
-+ u32 eth_u9 [50] ; // Reserved.
-+ u32 ethmac1 ;
-+ u32 ethmac2 ;
-+ u32 ethipgt ;
-+ u32 ethipgr ;
-+ u32 ethclrt ;
-+ u32 ethmaxf ;
-+ u32 eth_u10 ; // Reserved.
-+ u32 ethmtest ;
-+ u32 miimcfg ;
-+ u32 miimcmd ;
-+ u32 miimaddr ;
-+ u32 miimwtd ;
-+ u32 miimrdd ;
-+ u32 miimind ;
-+ u32 eth_u11 ; // Reserved.
-+ u32 eth_u12 ; // Reserved.
-+ u32 ethcfsa0 ;
-+ u32 ethcfsa1 ;
-+ u32 ethcfsa2 ;
-+} volatile *ETH_t;
-+
-+enum
-+{
-+ ETHINTFC_en_b = 0,
-+ ETHINTFC_en_m = 0x00000001,
-+ ETHINTFC_its_b = 1,
-+ ETHINTFC_its_m = 0x00000002,
-+ ETHINTFC_rip_b = 2,
-+ ETHINTFC_rip_m = 0x00000004,
-+ ETHINTFC_jam_b = 3,
-+ ETHINTFC_jam_m = 0x00000008,
-+ ETHINTFC_ovr_b = 4,
-+ ETHINTFC_ovr_m = 0x00000010,
-+ ETHINTFC_und_b = 5,
-+ ETHINTFC_und_m = 0x00000020,
-+
-+ ETHFIFOTT_tth_b = 0,
-+ ETHFIFOTT_tth_m = 0x0000007f,
-+
-+ ETHARC_pro_b = 0,
-+ ETHARC_pro_m = 0x00000001,
-+ ETHARC_am_b = 1,
-+ ETHARC_am_m = 0x00000002,
-+ ETHARC_afm_b = 2,
-+ ETHARC_afm_m = 0x00000004,
-+ ETHARC_ab_b = 3,
-+ ETHARC_ab_m = 0x00000008,
-+
-+ ETHSAL_byte5_b = 0,
-+ ETHSAL_byte5_m = 0x000000ff,
-+ ETHSAL_byte4_b = 8,
-+ ETHSAL_byte4_m = 0x0000ff00,
-+ ETHSAL_byte3_b = 16,
-+ ETHSAL_byte3_m = 0x00ff0000,
-+ ETHSAL_byte2_b = 24,
-+ ETHSAL_byte2_m = 0xff000000,
-+
-+ ETHSAH_byte1_b = 0,
-+ ETHSAH_byte1_m = 0x000000ff,
-+ ETHSAH_byte0_b = 8,
-+ ETHSAH_byte0_m = 0x0000ff00,
-+
-+ ETHGPF_ptv_b = 0,
-+ ETHGPF_ptv_m = 0x0000ffff,
-+
-+ ETHPFS_pfd_b = 0,
-+ ETHPFS_pfd_m = 0x00000001,
-+
-+ ETHCFSA0_cfsa4_b = 0,
-+ ETHCFSA0_cfsa4_m = 0x000000ff,
-+ ETHCFSA0_cfsa5_b = 8,
-+ ETHCFSA0_cfsa5_m = 0x0000ff00,
-+
-+ ETHCFSA1_cfsa2_b = 0,
-+ ETHCFSA1_cfsa2_m = 0x000000ff,
-+ ETHCFSA1_cfsa3_b = 8,
-+ ETHCFSA1_cfsa3_m = 0x0000ff00,
-+
-+ ETHCFSA2_cfsa0_b = 0,
-+ ETHCFSA2_cfsa0_m = 0x000000ff,
-+ ETHCFSA2_cfsa1_b = 8,
-+ ETHCFSA2_cfsa1_m = 0x0000ff00,
-+
-+ ETHMAC1_re_b = 0,
-+ ETHMAC1_re_m = 0x00000001,
-+ ETHMAC1_paf_b = 1,
-+ ETHMAC1_paf_m = 0x00000002,
-+ ETHMAC1_rfc_b = 2,
-+ ETHMAC1_rfc_m = 0x00000004,
-+ ETHMAC1_tfc_b = 3,
-+ ETHMAC1_tfc_m = 0x00000008,
-+ ETHMAC1_lb_b = 4,
-+ ETHMAC1_lb_m = 0x00000010,
-+ ETHMAC1_mr_b = 31,
-+ ETHMAC1_mr_m = 0x80000000,
-+
-+ ETHMAC2_fd_b = 0,
-+ ETHMAC2_fd_m = 0x00000001,
-+ ETHMAC2_flc_b = 1,
-+ ETHMAC2_flc_m = 0x00000002,
-+ ETHMAC2_hfe_b = 2,
-+ ETHMAC2_hfe_m = 0x00000004,
-+ ETHMAC2_dc_b = 3,
-+ ETHMAC2_dc_m = 0x00000008,
-+ ETHMAC2_cen_b = 4,
-+ ETHMAC2_cen_m = 0x00000010,
-+ ETHMAC2_pe_b = 5,
-+ ETHMAC2_pe_m = 0x00000020,
-+ ETHMAC2_vpe_b = 6,
-+ ETHMAC2_vpe_m = 0x00000040,
-+ ETHMAC2_ape_b = 7,
-+ ETHMAC2_ape_m = 0x00000080,
-+ ETHMAC2_ppe_b = 8,
-+ ETHMAC2_ppe_m = 0x00000100,
-+ ETHMAC2_lpe_b = 9,
-+ ETHMAC2_lpe_m = 0x00000200,
-+ ETHMAC2_nb_b = 12,
-+ ETHMAC2_nb_m = 0x00001000,
-+ ETHMAC2_bp_b = 13,
-+ ETHMAC2_bp_m = 0x00002000,
-+ ETHMAC2_ed_b = 14,
-+ ETHMAC2_ed_m = 0x00004000,
-+
-+ ETHIPGT_ipgt_b = 0,
-+ ETHIPGT_ipgt_m = 0x0000007f,
-+
-+ ETHIPGR_ipgr2_b = 0,
-+ ETHIPGR_ipgr2_m = 0x0000007f,
-+ ETHIPGR_ipgr1_b = 8,
-+ ETHIPGR_ipgr1_m = 0x00007f00,
-+
-+ ETHCLRT_maxret_b = 0,
-+ ETHCLRT_maxret_m = 0x0000000f,
-+ ETHCLRT_colwin_b = 8,
-+ ETHCLRT_colwin_m = 0x00003f00,
-+
-+ ETHMAXF_maxf_b = 0,
-+ ETHMAXF_maxf_m = 0x0000ffff,
-+
-+ ETHMTEST_tb_b = 2,
-+ ETHMTEST_tb_m = 0x00000004,
-+
-+ ETHMCP_div_b = 0,
-+ ETHMCP_div_m = 0x000000ff,
-+
-+ MIIMCFG_rsv_b = 0,
-+ MIIMCFG_rsv_m = 0x0000000c,
++/* Section 2.2 Host Controller Capability Registers */
++struct ehci_caps {
++ /* these fields are specified as 8 and 16 bit registers,
++ * but some hosts can't perform 8 or 16 bit PCI accesses.
++ */
++ u32 hc_capbase;
++#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
++#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
++ u32 hcs_params; /* HCSPARAMS - offset 0x4 */
++#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
++#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
++#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
++#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
++#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
++#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
++#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
++
++ u32 hcc_params; /* HCCPARAMS - offset 0x8 */
++#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
++#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
++#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
++#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
++#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
++#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
++ u8 portroute [8]; /* nibbles for routing - offset 0xC */
++} __attribute__ ((packed));
++
++
++/* Section 2.3 Host Controller Operational Registers */
++struct ehci_regs {
++
++ /* USBCMD: offset 0x00 */
++ u32 command;
++/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
++#define CMD_PARK (1<<11) /* enable "park" on async qh */
++#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
++#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
++#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
++#define CMD_ASE (1<<5) /* async schedule enable */
++#define CMD_PSE (1<<4) /* periodic schedule enable */
++/* 3:2 is periodic frame list size */
++#define CMD_RESET (1<<1) /* reset HC not bus */
++#define CMD_RUN (1<<0) /* start/stop HC */
++
++ /* USBSTS: offset 0x04 */
++ u32 status;
++#define STS_ASS (1<<15) /* Async Schedule Status */
++#define STS_PSS (1<<14) /* Periodic Schedule Status */
++#define STS_RECL (1<<13) /* Reclamation */
++#define STS_HALT (1<<12) /* Not running (any reason) */
++/* some bits reserved */
++ /* these STS_* flags are also intr_enable bits (USBINTR) */
++#define STS_IAA (1<<5) /* Interrupted on async advance */
++#define STS_FATAL (1<<4) /* such as some PCI access errors */
++#define STS_FLR (1<<3) /* frame list rolled over */
++#define STS_PCD (1<<2) /* port change detect */
++#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
++#define STS_INT (1<<0) /* "normal" completion (short, ...) */
++
++ /* USBINTR: offset 0x08 */
++ u32 intr_enable;
++
++ /* FRINDEX: offset 0x0C */
++ u32 frame_index; /* current microframe number */
++ /* CTRLDSSEGMENT: offset 0x10 */
++ u32 segment; /* address bits 63:32 if needed */
++ /* PERIODICLISTBASE: offset 0x14 */
++ u32 frame_list; /* points to periodic list */
++ /* ASYNCLISTADDR: offset 0x18 */
++ u32 async_next; /* address of next async queue head */
++
++ u32 reserved [9];
++
++ /* CONFIGFLAG: offset 0x40 */
++ u32 configured_flag;
++#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
++
++ /* PORTSC: offset 0x44 */
++ u32 port_status [0]; /* up to N_PORTS */
++/* 31:23 reserved */
++#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
++#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
++#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
++/* 19:16 for port testing */
++#define PORT_LED_OFF (0<<14)
++#define PORT_LED_AMBER (1<<14)
++#define PORT_LED_GREEN (2<<14)
++#define PORT_LED_MASK (3<<14)
++#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
++#define PORT_POWER (1<<12) /* true: has power (see PPC) */
++#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
++/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
++/* 9 reserved */
++#define PORT_RESET (1<<8) /* reset port */
++#define PORT_SUSPEND (1<<7) /* suspend port */
++#define PORT_RESUME (1<<6) /* resume it */
++#define PORT_OCC (1<<5) /* over current change */
++#define PORT_OC (1<<4) /* over current active */
++#define PORT_PEC (1<<3) /* port enable change */
++#define PORT_PE (1<<2) /* port enable */
++#define PORT_CSC (1<<1) /* connect status change */
++#define PORT_CONNECT (1<<0) /* device connected */
++#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
++} __attribute__ ((packed));
++
++/* Appendix C, Debug port ... intended for use with special "debug devices"
++ * that can help if there's no serial console. (nonstandard enumeration.)
++ */
++struct ehci_dbg_port {
++ u32 control;
++#define DBGP_OWNER (1<<30)
++#define DBGP_ENABLED (1<<28)
++#define DBGP_DONE (1<<16)
++#define DBGP_INUSE (1<<10)
++#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
++# define DBGP_ERR_BAD 1
++# define DBGP_ERR_SIGNAL 2
++#define DBGP_ERROR (1<<6)
++#define DBGP_GO (1<<5)
++#define DBGP_OUT (1<<4)
++#define DBGP_LEN(x) (((x)>>0)&0x0f)
++ u32 pids;
++#define DBGP_PID_GET(x) (((x)>>16)&0xff)
++#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok))
++ u32 data03;
++ u32 data47;
++ u32 address;
++#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep))
++} __attribute__ ((packed));
++
++/*-------------------------------------------------------------------------*/
++
++#define QTD_NEXT(dma) cpu_to_le32((u32)dma)
+
-+ MIIMCMD_rd_b = 0,
-+ MIIMCMD_rd_m = 0x00000001,
-+ MIIMCMD_scn_b = 1,
-+ MIIMCMD_scn_m = 0x00000002,
++/*
++ * EHCI Specification 0.95 Section 3.5
++ * QTD: describe data transfer components (buffer, direction, ...)
++ * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
++ *
++ * These are associated only with "QH" (Queue Head) structures,
++ * used with control, bulk, and interrupt transfers.
++ */
++struct ehci_qtd {
++ /* first part defined by EHCI spec */
++ __le32 hw_next; /* see EHCI 3.5.1 */
++ __le32 hw_alt_next; /* see EHCI 3.5.2 */
++ __le32 hw_token; /* see EHCI 3.5.3 */
++#define QTD_TOGGLE (1 << 31) /* data toggle */
++#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
++#define QTD_IOC (1 << 15) /* interrupt on complete */
++#define QTD_CERR(tok) (((tok)>>10) & 0x3)
++#define QTD_PID(tok) (((tok)>>8) & 0x3)
++#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
++#define QTD_STS_HALT (1 << 6) /* halted on error */
++#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
++#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
++#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
++#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
++#define QTD_STS_STS (1 << 1) /* split transaction state */
++#define QTD_STS_PING (1 << 0) /* issue PING? */
++ __le32 hw_buf [5]; /* see EHCI 3.5.4 */
++ __le32 hw_buf_hi [5]; /* Appendix B */
++
++ /* the rest is HCD-private */
++ dma_addr_t qtd_dma; /* qtd address */
++ struct list_head qtd_list; /* sw qtd list */
++ struct urb *urb; /* qtd's urb */
++ size_t length; /* length of buffer */
++} __attribute__ ((aligned (32)));
++
++/* mask NakCnt+T in qh->hw_alt_next */
++#define QTD_MASK __constant_cpu_to_le32 (~0x1f)
++
++#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
++
++/*-------------------------------------------------------------------------*/
++
++/* type tag from {qh,itd,sitd,fstn}->hw_next */
++#define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
++
++/* values for that type tag */
++#define Q_TYPE_ITD __constant_cpu_to_le32 (0 << 1)
++#define Q_TYPE_QH __constant_cpu_to_le32 (1 << 1)
++#define Q_TYPE_SITD __constant_cpu_to_le32 (2 << 1)
++#define Q_TYPE_FSTN __constant_cpu_to_le32 (3 << 1)
++
++/* next async queue entry, or pointer to interrupt/periodic QH */
++#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
++
++/* for periodic/async schedules and qtd lists, mark end of list */
++#define EHCI_LIST_END __constant_cpu_to_le32(1) /* "null pointer" to hw */
+
-+ MIIMADDR_regaddr_b = 0,
-+ MIIMADDR_regaddr_m = 0x0000001f,
-+ MIIMADDR_phyaddr_b = 8,
-+ MIIMADDR_phyaddr_m = 0x00001f00,
++/*
++ * Entries in periodic shadow table are pointers to one of four kinds
++ * of data structure. That's dictated by the hardware; a type tag is
++ * encoded in the low bits of the hardware's periodic schedule. Use
++ * Q_NEXT_TYPE to get the tag.
++ *
++ * For entries in the async schedule, the type tag always says "qh".
++ */
++union ehci_shadow {
++ struct ehci_qh *qh; /* Q_TYPE_QH */
++ struct ehci_itd *itd; /* Q_TYPE_ITD */
++ struct ehci_sitd *sitd; /* Q_TYPE_SITD */
++ struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
++ __le32 *hw_next; /* (all types) */
++ void *ptr;
++};
+
-+ MIIMWTD_wdata_b = 0,
-+ MIIMWTD_wdata_m = 0x0000ffff,
++/*-------------------------------------------------------------------------*/
+
-+ MIIMRDD_rdata_b = 0,
-+ MIIMRDD_rdata_m = 0x0000ffff,
++/*
++ * EHCI Specification 0.95 Section 3.6
++ * QH: describes control/bulk/interrupt endpoints
++ * See Fig 3-7 "Queue Head Structure Layout".
++ *
++ * These appear in both the async and (for interrupt) periodic schedules.
++ */
+
-+ MIIMIND_bsy_b = 0,
-+ MIIMIND_bsy_m = 0x00000001,
-+ MIIMIND_scn_b = 1,
-+ MIIMIND_scn_m = 0x00000002,
-+ MIIMIND_nv_b = 2,
-+ MIIMIND_nv_m = 0x00000004,
++struct ehci_qh {
++ /* first part defined by EHCI spec */
++ __le32 hw_next; /* see EHCI 3.6.1 */
++ __le32 hw_info1; /* see EHCI 3.6.2 */
++#define QH_HEAD 0x00008000
++ __le32 hw_info2; /* see EHCI 3.6.2 */
++#define QH_SMASK 0x000000ff
++#define QH_CMASK 0x0000ff00
++#define QH_HUBADDR 0x007f0000
++#define QH_HUBPORT 0x3f800000
++#define QH_MULT 0xc0000000
++ __le32 hw_current; /* qtd list - see EHCI 3.6.4 */
++
++ /* qtd overlay (hardware parts of a struct ehci_qtd) */
++ __le32 hw_qtd_next;
++ __le32 hw_alt_next;
++ __le32 hw_token;
++ __le32 hw_buf [5];
++ __le32 hw_buf_hi [5];
++
++ /* the rest is HCD-private */
++ dma_addr_t qh_dma; /* address of qh */
++ union ehci_shadow qh_next; /* ptr to qh; or periodic */
++ struct list_head qtd_list; /* sw qtd list */
++ struct ehci_qtd *dummy;
++ struct ehci_qh *reclaim; /* next to reclaim */
++
++ struct ehci_hcd *ehci;
++ struct kref kref;
++ unsigned stamp;
++
++ u8 qh_state;
++#define QH_STATE_LINKED 1 /* HC sees this */
++#define QH_STATE_UNLINK 2 /* HC may still see this */
++#define QH_STATE_IDLE 3 /* HC doesn't see this */
++#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
++#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
++
++ /* periodic schedule info */
++ u8 usecs; /* intr bandwidth */
++ u8 gap_uf; /* uframes split/csplit gap */
++ u8 c_usecs; /* ... split completion bw */
++ u16 tt_usecs; /* tt downstream bandwidth */
++ unsigned short period; /* polling interval */
++ unsigned short start; /* where polling starts */
++#define NO_FRAME ((unsigned short)~0) /* pick new start */
++ struct usb_device *dev; /* access to TT */
++} __attribute__ ((aligned (32)));
++
++/*-------------------------------------------------------------------------*/
++
++/* description of one iso transaction (up to 3 KB data if highspeed) */
++struct ehci_iso_packet {
++ /* These will be copied to iTD when scheduling */
++ u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
++ __le32 transaction; /* itd->hw_transaction[i] |= */
++ u8 cross; /* buf crosses pages */
++ /* for full speed OUT splits */
++ u32 buf1;
++};
+
-+} ;
++/* temporary schedule data for packets from iso urbs (both speeds)
++ * each packet is one logical usb transaction to the device (not TT),
++ * beginning at stream->next_uframe
++ */
++struct ehci_iso_sched {
++ struct list_head td_list;
++ unsigned span;
++ struct ehci_iso_packet packet [0];
++};
+
+/*
-+ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
-+ */
-+enum
-+{
-+ ETHRX_fd_b = 0,
-+ ETHRX_fd_m = 0x00000001,
-+ ETHRX_ld_b = 1,
-+ ETHRX_ld_m = 0x00000002,
-+ ETHRX_rok_b = 2,
-+ ETHRX_rok_m = 0x00000004,
-+ ETHRX_fm_b = 3,
-+ ETHRX_fm_m = 0x00000008,
-+ ETHRX_mp_b = 4,
-+ ETHRX_mp_m = 0x00000010,
-+ ETHRX_bp_b = 5,
-+ ETHRX_bp_m = 0x00000020,
-+ ETHRX_vlt_b = 6,
-+ ETHRX_vlt_m = 0x00000040,
-+ ETHRX_cf_b = 7,
-+ ETHRX_cf_m = 0x00000080,
-+ ETHRX_ovr_b = 8,
-+ ETHRX_ovr_m = 0x00000100,
-+ ETHRX_crc_b = 9,
-+ ETHRX_crc_m = 0x00000200,
-+ ETHRX_cv_b = 10,
-+ ETHRX_cv_m = 0x00000400,
-+ ETHRX_db_b = 11,
-+ ETHRX_db_m = 0x00000800,
-+ ETHRX_le_b = 12,
-+ ETHRX_le_m = 0x00001000,
-+ ETHRX_lor_b = 13,
-+ ETHRX_lor_m = 0x00002000,
-+ ETHRX_ces_b = 14,
-+ ETHRX_ces_m = 0x00004000,
-+ ETHRX_length_b = 16,
-+ ETHRX_length_m = 0xffff0000,
-+
-+ ETHTX_fd_b = 0,
-+ ETHTX_fd_m = 0x00000001,
-+ ETHTX_ld_b = 1,
-+ ETHTX_ld_m = 0x00000002,
-+ ETHTX_oen_b = 2,
-+ ETHTX_oen_m = 0x00000004,
-+ ETHTX_pen_b = 3,
-+ ETHTX_pen_m = 0x00000008,
-+ ETHTX_cen_b = 4,
-+ ETHTX_cen_m = 0x00000010,
-+ ETHTX_hen_b = 5,
-+ ETHTX_hen_m = 0x00000020,
-+ ETHTX_tok_b = 6,
-+ ETHTX_tok_m = 0x00000040,
-+ ETHTX_mp_b = 7,
-+ ETHTX_mp_m = 0x00000080,
-+ ETHTX_bp_b = 8,
-+ ETHTX_bp_m = 0x00000100,
-+ ETHTX_und_b = 9,
-+ ETHTX_und_m = 0x00000200,
-+ ETHTX_of_b = 10,
-+ ETHTX_of_m = 0x00000400,
-+ ETHTX_ed_b = 11,
-+ ETHTX_ed_m = 0x00000800,
-+ ETHTX_ec_b = 12,
-+ ETHTX_ec_m = 0x00001000,
-+ ETHTX_lc_b = 13,
-+ ETHTX_lc_m = 0x00002000,
-+ ETHTX_td_b = 14,
-+ ETHTX_td_m = 0x00004000,
-+ ETHTX_crc_b = 15,
-+ ETHTX_crc_m = 0x00008000,
-+ ETHTX_le_b = 16,
-+ ETHTX_le_m = 0x00010000,
-+ ETHTX_cc_b = 17,
-+ ETHTX_cc_m = 0x001E0000,
-+} ;
-+#endif //__IDT_RC32438_ETH_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,72 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * macros for IDT EB438 ethernet
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
++ * ehci_iso_stream - groups all (s)itds for this endpoint.
++ * acts like a qh would, if EHCI had them for ISO.
+ */
++struct ehci_iso_stream {
++ /* first two fields match QH, but info1 == 0 */
++ __le32 hw_next;
++ __le32 hw_info1;
++
++ u32 refcount;
++ u8 bEndpointAddress;
++ u8 highspeed;
++ u16 depth; /* depth in uframes */
++ struct list_head td_list; /* queued itds/sitds */
++ struct list_head free_list; /* list of unused itds/sitds */
++ struct usb_device *udev;
++ struct usb_host_endpoint *ep;
++
++ /* output of (re)scheduling */
++ unsigned long start; /* jiffies */
++ unsigned long rescheduled;
++ int next_uframe;
++ __le32 splits;
++
++ /* the rest is derived from the endpoint descriptor,
++ * trusting urb->interval == f(epdesc->bInterval) and
++ * including the extra info for hw_bufp[0..2]
++ */
++ u8 interval;
++ u8 usecs, c_usecs;
++ u16 tt_usecs;
++ u16 maxp;
++ u16 raw_mask;
++ unsigned bandwidth;
++
++ /* This is used to initialize iTD's hw_bufp fields */
++ __le32 buf0;
++ __le32 buf1;
++ __le32 buf2;
++
++ /* this is used to initialize sITD's tt info */
++ __le32 address;
++};
+
-+#ifndef __IDT_RC32438_ETH_V_H__
-+#define __IDT_RC32438_ETH_V_H__
-+#include <asm/idt-boards/rc32438/rc32438_eth.h>
-+
-+#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
-+#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
-+#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
-+#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
-+#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
-+#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
-+#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
-+#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
-+#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
-+#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
-+#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
-+
-+#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
-+
-+#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
-+#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
-+#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
-+#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
-+#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
-+#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
-+#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
-+#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
-+#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
-+#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
-+#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
-+#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
-+#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
-+#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
-+
-+#endif //__IDT_RC32438_ETH_V_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,257 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for IDT RC32438 GPIO.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
++/*-------------------------------------------------------------------------*/
++
++/*
++ * EHCI Specification 0.95 Section 3.3
++ * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
+ *
-+ **************************************************************************
++ * Schedule records for high speed iso xfers
+ */
-+#ifndef __IDT_RC32438_GPIO_H__
-+#define __IDT_RC32438_GPIO_H__
-+enum
-+{
-+ GPIO0_PhysicalAddress = 0x18048000,
-+ GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
++struct ehci_itd {
++ /* first part defined by EHCI spec */
++ __le32 hw_next; /* see EHCI 3.3.1 */
++ __le32 hw_transaction [8]; /* see EHCI 3.3.2 */
++#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
++#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
++#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
++#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
++#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
++#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
++
++#define ITD_ACTIVE __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
++
++ __le32 hw_bufp [7]; /* see EHCI 3.3.3 */
++ __le32 hw_bufp_hi [7]; /* Appendix B */
++
++ /* the rest is HCD-private */
++ dma_addr_t itd_dma; /* for this itd */
++ union ehci_shadow itd_next; /* ptr to periodic q entry */
++
++ struct urb *urb;
++ struct ehci_iso_stream *stream; /* endpoint's queue */
++ struct list_head itd_list; /* list of stream's itds */
++
++ /* any/all hw_transactions here may be used by that urb */
++ unsigned frame; /* where scheduled */
++ unsigned pg;
++ unsigned index[8]; /* in urb->iso_frame_desc */
++ u8 usecs[8];
++} __attribute__ ((aligned (32)));
++
++/*-------------------------------------------------------------------------*/
+
-+ GPIO0_VirtualAddress = 0xb8048000,
-+ GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
-+} ;
++/*
++ * EHCI Specification 0.95 Section 3.4
++ * siTD, aka split-transaction isochronous Transfer Descriptor
++ * ... describe full speed iso xfers through TT in hubs
++ * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
++ */
++struct ehci_sitd {
++ /* first part defined by EHCI spec */
++ __le32 hw_next;
++/* uses bit field macros above - see EHCI 0.95 Table 3-8 */
++ __le32 hw_fullspeed_ep; /* EHCI table 3-9 */
++ __le32 hw_uframe; /* EHCI table 3-10 */
++ __le32 hw_results; /* EHCI table 3-11 */
++#define SITD_IOC (1 << 31) /* interrupt on completion */
++#define SITD_PAGE (1 << 30) /* buffer 0/1 */
++#define SITD_LENGTH(x) (0x3ff & ((x)>>16))
++#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
++#define SITD_STS_ERR (1 << 6) /* error from TT */
++#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
++#define SITD_STS_BABBLE (1 << 4) /* device was babbling */
++#define SITD_STS_XACT (1 << 3) /* illegal IN response */
++#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
++#define SITD_STS_STS (1 << 1) /* split transaction state */
++
++#define SITD_ACTIVE __constant_cpu_to_le32(SITD_STS_ACTIVE)
++
++ __le32 hw_buf [2]; /* EHCI table 3-12 */
++ __le32 hw_backpointer; /* EHCI table 3-13 */
++ __le32 hw_buf_hi [2]; /* Appendix B */
++
++ /* the rest is HCD-private */
++ dma_addr_t sitd_dma;
++ union ehci_shadow sitd_next; /* ptr to periodic q entry */
++
++ struct urb *urb;
++ struct ehci_iso_stream *stream; /* endpoint's queue */
++ struct list_head sitd_list; /* list of stream's sitds */
++ unsigned frame;
++ unsigned index;
++} __attribute__ ((aligned (32)));
++
++/*-------------------------------------------------------------------------*/
+
-+typedef struct
-+{
-+ u32 gpiofunc; /* GPIO Function Register
-+ * gpiofunc[x]==0 bit = gpio
-+ * func[x]==1 bit = altfunc
-+ */
-+ u32 gpiocfg; /* GPIO Configuration Register
-+ * gpiocfg[x]==0 bit = input
-+ * gpiocfg[x]==1 bit = output
-+ */
-+ u32 gpiod; /* GPIO Data Register
-+ * gpiod[x] read/write gpio pinX status
-+ */
-+ u32 gpioilevel; /* GPIO Interrupt Status Register
-+ * interrupt level (see gpioistat)
-+ */
-+ u32 gpioistat; /* Gpio Interrupt Status Register
-+ * istat[x] = (gpiod[x] == level[x])
-+ * cleared in ISR (STICKY bits)
-+ */
-+ u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
-+} volatile * GPIO_t ;
-+
-+typedef enum
-+{
-+ GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
-+ GPIO_alt_v = 1, // gpiofunc use pin as alt.
-+ GPIO_input_v = 0, // gpiocfg use pin as input.
-+ GPIO_output_v = 1, // gpiocfg use pin as output.
-+ GPIO_pin0_b = 0,
-+ GPIO_pin0_m = 0x00000001,
-+ GPIO_pin1_b = 1,
-+ GPIO_pin1_m = 0x00000002,
-+ GPIO_pin2_b = 2,
-+ GPIO_pin2_m = 0x00000004,
-+ GPIO_pin3_b = 3,
-+ GPIO_pin3_m = 0x00000008,
-+ GPIO_pin4_b = 4,
-+ GPIO_pin4_m = 0x00000010,
-+ GPIO_pin5_b = 5,
-+ GPIO_pin5_m = 0x00000020,
-+ GPIO_pin6_b = 6,
-+ GPIO_pin6_m = 0x00000040,
-+ GPIO_pin7_b = 7,
-+ GPIO_pin7_m = 0x00000080,
-+ GPIO_pin8_b = 8,
-+ GPIO_pin8_m = 0x00000100,
-+ GPIO_pin9_b = 9,
-+ GPIO_pin9_m = 0x00000200,
-+ GPIO_pin10_b = 10,
-+ GPIO_pin10_m = 0x00000400,
-+ GPIO_pin11_b = 11,
-+ GPIO_pin11_m = 0x00000800,
-+ GPIO_pin12_b = 12,
-+ GPIO_pin12_m = 0x00001000,
-+ GPIO_pin13_b = 13,
-+ GPIO_pin13_m = 0x00002000,
-+ GPIO_pin14_b = 14,
-+ GPIO_pin14_m = 0x00004000,
-+ GPIO_pin15_b = 15,
-+ GPIO_pin15_m = 0x00008000,
-+ GPIO_pin16_b = 16,
-+ GPIO_pin16_m = 0x00010000,
-+ GPIO_pin17_b = 17,
-+ GPIO_pin17_m = 0x00020000,
-+ GPIO_pin18_b = 18,
-+ GPIO_pin18_m = 0x00040000,
-+ GPIO_pin19_b = 19,
-+ GPIO_pin19_m = 0x00080000,
-+ GPIO_pin20_b = 20,
-+ GPIO_pin20_m = 0x00100000,
-+ GPIO_pin21_b = 21,
-+ GPIO_pin21_m = 0x00200000,
-+ GPIO_pin22_b = 22,
-+ GPIO_pin22_m = 0x00400000,
-+ GPIO_pin23_b = 23,
-+ GPIO_pin23_m = 0x00800000,
-+ GPIO_pin24_b = 24,
-+ GPIO_pin24_m = 0x01000000,
-+ GPIO_pin25_b = 25,
-+ GPIO_pin25_m = 0x02000000,
-+ GPIO_pin26_b = 26,
-+ GPIO_pin26_m = 0x04000000,
-+ GPIO_pin27_b = 27,
-+ GPIO_pin27_m = 0x08000000,
-+ GPIO_pin28_b = 28,
-+ GPIO_pin28_m = 0x10000000,
-+ GPIO_pin29_b = 29,
-+ GPIO_pin29_m = 0x20000000,
-+ GPIO_pin30_b = 30,
-+ GPIO_pin30_m = 0x40000000,
-+ GPIO_pin31_b = 31,
-+ GPIO_pin31_m = 0x80000000,
-+
-+// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
-+
-+ GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
-+ GPIO_u0sout_m = GPIO_pin0_m,
-+ GPIO_u0sout_cfg_v = GPIO_output_v,
-+ GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
-+ GPIO_u0sinp_m = GPIO_pin1_m,
-+ GPIO_u0sinp_cfg_v = GPIO_input_v,
-+ GPIO_u0rin_b = GPIO_pin2_b, // UART 0 ring indic.
-+ GPIO_u0rin_m = GPIO_pin2_m,
-+ GPIO_u0rin_cfg_v = GPIO_input_v,
-+ GPIO_u0dcdn_b = GPIO_pin3_b, // UART 0 data carr.det.
-+ GPIO_u0dcdn_m = GPIO_pin3_m,
-+ GPIO_u0dcdn_cfg_v = GPIO_input_v,
-+ GPIO_u0dtrn_b = GPIO_pin4_b, // UART 0 data term rdy.
-+ GPIO_u0dtrn_m = GPIO_pin4_m,
-+ GPIO_u0dtrn_cfg_v = GPIO_output_v,
-+ GPIO_u0dsrn_b = GPIO_pin5_b, // UART 0 data set rdy.
-+ GPIO_u0dsrn_m = GPIO_pin5_m,
-+ GPIO_u0dsrn_cfg_v = GPIO_input_v,
-+ GPIO_u0rtsn_b = GPIO_pin6_b, // UART 0 req. to send.
-+ GPIO_u0rtsn_m = GPIO_pin6_m,
-+ GPIO_u0rtsn_cfg_v = GPIO_output_v,
-+ GPIO_u0ctsn_b = GPIO_pin7_b, // UART 0 clear to send.
-+ GPIO_u0ctsn_m = GPIO_pin7_m,
-+ GPIO_u0ctsn_cfg_v = GPIO_input_v,
-+
-+ GPIO_u1sout_b = GPIO_pin8_b, // UART 1 serial out.
-+ GPIO_u1sout_m = GPIO_pin8_m,
-+ GPIO_u1sout_cfg_v = GPIO_output_v,
-+ GPIO_u1sinp_b = GPIO_pin9_b, // UART 1 serial in.
-+ GPIO_u1sinp_m = GPIO_pin9_m,
-+ GPIO_u1sinp_cfg_v = GPIO_input_v,
-+ GPIO_u1dtrn_b = GPIO_pin10_b, // UART 1 data term rdy.
-+ GPIO_u1dtrn_m = GPIO_pin10_m,
-+ GPIO_u1dtrn_cfg_v = GPIO_output_v,
-+ GPIO_u1dsrn_b = GPIO_pin11_b, // UART 1 data set rdy.
-+ GPIO_u1dsrn_m = GPIO_pin11_m,
-+ GPIO_u1dsrn_cfg_v = GPIO_input_v,
-+ GPIO_u1rtsn_b = GPIO_pin12_b, // UART 1 req. to send.
-+ GPIO_u1rtsn_m = GPIO_pin12_m,
-+ GPIO_u1rtsn_cfg_v = GPIO_output_v,
-+ GPIO_u1ctsn_b = GPIO_pin13_b, // UART 1 clear to send.
-+ GPIO_u1ctsn_m = GPIO_pin13_m,
-+ GPIO_u1ctsn_cfg_v = GPIO_input_v,
-+
-+ GPIO_dmareqn0_b = GPIO_pin14_b, // Ext. DMA 0 request
-+ GPIO_dmareqn0_m = GPIO_pin14_m,
-+ GPIO_dmareqn0_cfg_v = GPIO_input_v,
-+
-+ GPIO_dmareqn1_b = GPIO_pin15_b, // Ext. DMA 1 request
-+ GPIO_dmareqn1_m = GPIO_pin15_m,
-+ GPIO_dmareqn1_cfg_v = GPIO_input_v,
-+
-+ GPIO_dmadonen0_b = GPIO_pin16_b, // Ext. DMA 0 done
-+ GPIO_dmadonen0_m = GPIO_pin16_m,
-+ GPIO_dmadonen0_cfg_v = GPIO_input_v,
-+
-+ GPIO_dmadonen1_b = GPIO_pin17_b, // Ext. DMA 1 done
-+ GPIO_dmadonen1_m = GPIO_pin17_m,
-+ GPIO_dmadonen1_cfg_v = GPIO_input_v,
-+
-+ GPIO_dmafinn0_b = GPIO_pin18_b, // Ext. DMA 0 finished
-+ GPIO_dmafinn0_m = GPIO_pin18_m,
-+ GPIO_dmafinn0_cfg_v = GPIO_output_v,
-+
-+ GPIO_dmafinn1_b = GPIO_pin19_b, // Ext. DMA 1 finished
-+ GPIO_dmafinn1_m = GPIO_pin19_m,
-+ GPIO_dmafinn1_cfg_v = GPIO_output_v,
-+
-+ GPIO_maddr22_b = GPIO_pin20_b, // M&P bus bit 22.
-+ GPIO_maddr22_m = GPIO_pin20_m,
-+ GPIO_maddr22_cfg_v = GPIO_output_v,
-+
-+ GPIO_maddr23_b = GPIO_pin21_b, // M&P bus bit 23.
-+ GPIO_maddr23_m = GPIO_pin21_m,
-+ GPIO_maddr23_cfg_v = GPIO_output_v,
-+
-+ GPIO_maddr24_b = GPIO_pin22_b, // M&P bus bit 24.
-+ GPIO_maddr24_m = GPIO_pin22_m,
-+ GPIO_maddr24_cfg_v = GPIO_output_v,
-+
-+ GPIO_maddr25_b = GPIO_pin23_b, // M&P bus bit 25.
-+ GPIO_maddr25_m = GPIO_pin23_m,
-+ GPIO_maddr25_cfg_v = GPIO_output_v,
-+
-+ GPIO_afspare6_b = GPIO_pin24_b, // reserved.
-+ GPIO_afspare6_m = GPIO_pin24_m,
-+ GPIO_afspare6_cfg_v = GPIO_input_v,
-+ GPIO_afspare5_b = GPIO_pin25_b, // reserved.
-+ GPIO_afspare5_m = GPIO_pin25_m,
-+ GPIO_afspare5_cfg_v = GPIO_input_v,
-+ GPIO_afspare4_b = GPIO_pin26_b, // reserved.
-+ GPIO_afspare4_m = GPIO_pin26_m,
-+ GPIO_afspare4_cfg_v = GPIO_input_v,
-+ GPIO_afspare3_b = GPIO_pin27_b, // reserved.
-+ GPIO_afspare3_m = GPIO_pin27_m,
-+ GPIO_afspare3_cfg_v = GPIO_input_v,
-+ GPIO_afspare2_b = GPIO_pin28_b, // reserved.
-+ GPIO_afspare2_m = GPIO_pin28_m,
-+ GPIO_afspare2_cfg_v = GPIO_input_v,
-+ GPIO_afspare1_b = GPIO_pin29_b, // reserved.
-+ GPIO_afspare1_m = GPIO_pin29_m,
-+ GPIO_afspare1_cfg_v = GPIO_input_v,
-+
-+ GPIO_pcimuintn_b = GPIO_pin30_b, // PCI messaging int.
-+ GPIO_pcimuintn_m = GPIO_pin30_m,
-+ GPIO_pcimuintn_cfg_v = GPIO_output_v,
-+
-+ GPIO_rngclk_b = GPIO_pin31_b, // RNG external clock
-+ GPIO_rngclk_m = GPIO_pin31_m,
-+ GPIO_rncclk_cfg_v = GPIO_input_v,
-+} GPIO_DEFS_t;
-+
-+#endif //__IDT_RC32438_GPIO_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,152 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for IDT RC32438 CPU.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
++/*
++ * EHCI Specification 0.96 Section 3.7
++ * Periodic Frame Span Traversal Node (FSTN)
+ *
-+ **************************************************************************
++ * Manages split interrupt transactions (using TT) that span frame boundaries
++ * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
++ * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
++ * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
+ */
++struct ehci_fstn {
++ __le32 hw_next; /* any periodic q entry */
++ __le32 hw_prev; /* qh or EHCI_LIST_END */
+
-+#ifndef __IDT_RC32438_H__
-+#define __IDT_RC32438_H__
-+#include <linux/config.h>
-+#include <linux/delay.h>
-+#include <asm/io.h>
-+#include <asm/idt-boards/rc32438/rc32438_timer.h>
++ /* the rest is HCD-private */
++ dma_addr_t fstn_dma;
++ union ehci_shadow fstn_next; /* ptr to periodic q entry */
++} __attribute__ ((aligned (32)));
+
-+#define RC32438_REG_BASE 0x18000000
++/*-------------------------------------------------------------------------*/
+
-+#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
-+#define idttimer ((volatile TIM_t) TIM0_VirtualAddress)
-+#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
++#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
+
-+#define IDT_CLOCK_MULT 2
-+#define MIPS_CPU_TIMER_IRQ 7
-+/* Interrupt Controller */
-+#define IC_GROUP0_PEND (RC32438_REG_BASE + 0x38000)
-+#define IC_GROUP0_MASK (RC32438_REG_BASE + 0x38008)
-+#define IC_GROUP_OFFSET 0x0C
-+#define RTC_BASE 0xAC0801FF0
++/*
++ * Some EHCI controllers have a Transaction Translator built into the
++ * root hub. This is a non-standard feature. Each controller will need
++ * to add code to the following inline functions, and call them as
++ * needed (mostly in root hub code).
++ */
+
-+#define NUM_INTR_GROUPS 5
-+/* 16550 UARTs */
++#define ehci_is_TDI(e) ((e)->is_tdi_rh_tt)
+
-+#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
-+#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
-+#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
-+#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
-+#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
++/* Returns the speed of a device attached to a port on the root hub. */
++static inline unsigned int
++ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
++{
++ if (ehci_is_TDI(ehci)) {
++ switch ((portsc>>26)&3) {
++ case 0:
++ return 0;
++ case 1:
++ return (1<<USB_PORT_FEAT_LOWSPEED);
++ case 2:
++ default:
++ return (1<<USB_PORT_FEAT_HIGHSPEED);
++ }
++ }
++ return (1<<USB_PORT_FEAT_HIGHSPEED);
++}
+
-+#ifdef __MIPSEB__
-+#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
-+#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
+#else
-+#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
-+#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
++
++#define ehci_is_TDI(e) (0)
++
++#define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
+#endif
+
-+#define RC32438_UART0_IRQ GROUP3_IRQ_BASE + 0
-+#define RC32438_UART1_IRQ GROUP3_IRQ_BASE + 3
++/*-------------------------------------------------------------------------*/
+
-+#define RC32438_NR_IRQS (GROUP4_IRQ_BASE + 32)
++#ifdef CONFIG_PPC_83xx
++/* Some Freescale processors have an erratum in which the TT
++ * port number in the queue head was 0..N-1 instead of 1..N.
++ */
++#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
++#else
++#define ehci_has_fsl_portno_bug(e) (0)
++#endif
+
++/*
++ * While most USB host controllers implement their registers in
++ * little-endian format, a minority (celleb companion chip) implement
++ * them in big endian format.
++ *
++ * This attempts to support either format at compile time without a
++ * runtime penalty, or both formats with the additional overhead
++ * of checking a flag bit.
++ */
+
++#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
++#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
++#else
++#define ehci_big_endian_mmio(e) 0
++#endif
+
-+/* cpu pipeline flush */
-+static inline void rc32438_sync(void)
++static inline unsigned int ehci_readl (const struct ehci_hcd *ehci,
++ __u32 __iomem * regs)
+{
-+ __asm__ volatile ("sync");
++#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
++ return ehci_big_endian_mmio(ehci) ?
++ readl_be(regs) :
++ readl(regs);
++#else
++ return readl(regs);
++#endif
+}
+
-+static inline void rc32438_sync_udelay(int us)
++static inline void ehci_writel (const struct ehci_hcd *ehci,
++ const unsigned int val, __u32 __iomem *regs)
+{
-+ __asm__ volatile ("sync");
-+ udelay(us);
++#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
++ ehci_big_endian_mmio(ehci) ?
++ writel_be(val, regs) :
++ writel(val, regs);
++#else
++ writel(val, regs);
++#endif
+}
+
-+static inline void rc32438_sync_delay(int ms)
-+{
-+ __asm__ volatile ("sync");
-+ mdelay(ms);
-+}
++/*-------------------------------------------------------------------------*/
++
++#ifndef DEBUG
++#define STUB_DEBUG_FILES
++#endif /* DEBUG */
++
++/*-------------------------------------------------------------------------*/
++
++#endif /* __LINUX_EHCI_HCD_H */
+diff -Nur linux-2.6.21.1/include/asm-mips/bootinfo.h linux-2.6.21.1-owrt/include/asm-mips/bootinfo.h
+--- linux-2.6.21.1/include/asm-mips/bootinfo.h 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/include/asm-mips/bootinfo.h 2007-05-23 23:34:01.000000000 +0200
+@@ -213,6 +213,17 @@
+ #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
+ #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
+
+
+/*
-+ * Macros to access internal RC32438 registers. No byte
-+ * swapping should be done when accessing the internal
-+ * registers.
++ * Valid machtype for group ARUBA
+ */
++#define MACH_GROUP_ARUBA 23
++#define MACH_ARUBA_UNKNOWN 0
++#define MACH_ARUBA_AP60 1
++#define MACH_ARUBA_AP65 2
++#define MACH_ARUBA_AP70 3
++#define MACH_ARUBA_AP40 4
+
-+#define rc32438_readb __raw_readb
-+#define rc32438_readw __raw_readw
-+#define rc32438_readl __raw_readl
-+
-+#define rc32438_writeb __raw_writeb
-+#define rc32438_writew __raw_writew
-+#define rc32438_writel __raw_writel
+ #define CL_SIZE COMMAND_LINE_SIZE
+
+ const char *get_system_type(void);
+diff -Nur linux-2.6.21.1/include/asm-mips/cpu.h linux-2.6.21.1-owrt/include/asm-mips/cpu.h
+--- linux-2.6.21.1/include/asm-mips/cpu.h 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/include/asm-mips/cpu.h 2007-05-23 23:34:01.000000000 +0200
+@@ -54,6 +54,9 @@
+ #define PRID_IMP_R14000 0x0f00
+ #define PRID_IMP_R8000 0x1000
+ #define PRID_IMP_PR4450 0x1200
++#define PRID_IMP_RC32334 0x1800
++#define PRID_IMP_RC32355 0x1900
++#define PRID_IMP_RC32365 0x1900
+ #define PRID_IMP_R4600 0x2000
+ #define PRID_IMP_R4700 0x2100
+ #define PRID_IMP_TX39 0x2200
+@@ -200,7 +203,8 @@
+ #define CPU_SB1A 62
+ #define CPU_74K 63
+ #define CPU_R14000 64
+-#define CPU_LAST 64
++#define CPU_RC32300 65
++#define CPU_LAST 65
+
+ /*
+ * ISA Level encodings
+diff -Nur linux-2.6.21.1/include/asm-mips/mach-generic/irq.h linux-2.6.21.1-owrt/include/asm-mips/mach-generic/irq.h
+--- linux-2.6.21.1/include/asm-mips/mach-generic/irq.h 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/include/asm-mips/mach-generic/irq.h 2007-05-23 23:35:55.000000000 +0200
+@@ -9,7 +9,7 @@
+ #define __ASM_MACH_GENERIC_IRQ_H
+
+ #ifndef NR_IRQS
+-#define NR_IRQS 128
++#define NR_IRQS 256
+ #endif
+
+ #ifdef CONFIG_I8259
+diff -Nur linux-2.6.21.1/include/linux/kernel.h linux-2.6.21.1-owrt/include/linux/kernel.h
+--- linux-2.6.21.1/include/linux/kernel.h 2007-04-27 23:49:26.000000000 +0200
++++ linux-2.6.21.1-owrt/include/linux/kernel.h 2007-05-23 23:34:01.000000000 +0200
+@@ -334,6 +334,7 @@
+ };
+
+ /* Force a compilation error if condition is true */
++extern void BUILD_BUG(void);
+ #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+
+ /* Force a compilation error if condition is true, but also produce a
+diff -Nur linux-2.6.21.1/include/linux/kernel.h.orig linux-2.6.21.1-owrt/include/linux/kernel.h.orig
+--- linux-2.6.21.1/include/linux/kernel.h.orig 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/include/linux/kernel.h.orig 2007-04-27 23:49:26.000000000 +0200
+@@ -0,0 +1,355 @@
++#ifndef _LINUX_KERNEL_H
++#define _LINUX_KERNEL_H
+
+/*
-+ * C access to CLZ and CLO instructions
-+ * (count leading zeroes/ones).
++ * 'kernel.h' contains some often-used function prototypes etc
+ */
-+static inline int rc32438_clz(unsigned long val)
-+{
-+ int ret;
-+ __asm__ volatile (
-+ ".set\tnoreorder\n\t"
-+ ".set\tnoat\n\t"
-+ ".set\tmips32\n\t"
-+ "clz\t%0,%1\n\t"
-+ ".set\tmips0\n\t"
-+ ".set\tat\n\t"
-+ ".set\treorder"
-+ : "=r" (ret)
-+ : "r" (val));
+
-+ return ret;
-+}
-+static inline int rc32438_clo(unsigned long val)
-+{
-+ int ret;
-+ __asm__ volatile (
-+ ".set\tnoreorder\n\t"
-+ ".set\tnoat\n\t"
-+ ".set\tmips32\n\t"
-+ "clo\t%0,%1\n\t"
-+ ".set\tmips0\n\t"
-+ ".set\tat\n\t"
-+ ".set\treorder"
-+ : "=r" (ret)
-+ : "r" (val));
++#ifdef __KERNEL__
+
-+ return ret;
-+}
-+#endif //__IDT_RC32438_H__
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,510 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for IDT RC32438 PCI.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
++#include <stdarg.h>
++#include <linux/linkage.h>
++#include <linux/stddef.h>
++#include <linux/types.h>
++#include <linux/compiler.h>
++#include <linux/bitops.h>
++#include <linux/log2.h>
++#include <asm/byteorder.h>
++#include <asm/bug.h>
++
++extern const char linux_banner[];
++extern const char linux_proc_banner[];
++
++#define INT_MAX ((int)(~0U>>1))
++#define INT_MIN (-INT_MAX - 1)
++#define UINT_MAX (~0U)
++#define LONG_MAX ((long)(~0UL>>1))
++#define LONG_MIN (-LONG_MAX - 1)
++#define ULONG_MAX (~0UL)
++#define LLONG_MAX ((long long)(~0ULL>>1))
++#define LLONG_MIN (-LLONG_MAX - 1)
++#define ULLONG_MAX (~0ULL)
++
++#define STACK_MAGIC 0xdeadbeef
++
++#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1)
++#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
++
++#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
++#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
++#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
++#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
++
++#define KERN_EMERG "<0>" /* system is unusable */
++#define KERN_ALERT "<1>" /* action must be taken immediately */
++#define KERN_CRIT "<2>" /* critical conditions */
++#define KERN_ERR "<3>" /* error conditions */
++#define KERN_WARNING "<4>" /* warning conditions */
++#define KERN_NOTICE "<5>" /* normal but significant condition */
++#define KERN_INFO "<6>" /* informational */
++#define KERN_DEBUG "<7>" /* debug-level messages */
++
++extern int console_printk[];
++
++#define console_loglevel (console_printk[0])
++#define default_message_loglevel (console_printk[1])
++#define minimum_console_loglevel (console_printk[2])
++#define default_console_loglevel (console_printk[3])
++
++struct completion;
++struct pt_regs;
++struct user;
++
++/**
++ * might_sleep - annotation for functions that can sleep
++ *
++ * this macro will print a stack trace if it is executed in an atomic
++ * context (spinlock, irq-handler, ...).
++ *
++ * This is a useful debugging help to be able to catch problems early and not
++ * be bitten later when the calling function happens to sleep when it is not
++ * supposed to.
+ */
++#ifdef CONFIG_PREEMPT_VOLUNTARY
++extern int cond_resched(void);
++# define might_resched() cond_resched()
++#else
++# define might_resched() do { } while (0)
++#endif
+
-+enum
-+{
-+ PCI0_PhysicalAddress = 0x18080000,
-+ PCI_PhysicalAddress = PCI0_PhysicalAddress,
++#ifdef CONFIG_DEBUG_SPINLOCK_SLEEP
++ void __might_sleep(char *file, int line);
++# define might_sleep() \
++ do { __might_sleep(__FILE__, __LINE__); might_resched(); } while (0)
++#else
++# define might_sleep() do { might_resched(); } while (0)
++#endif
+
-+ PCI0_VirtualAddress = 0xb8080000,
-+ PCI_VirtualAddress = PCI0_VirtualAddress,
-+} ;
++#define might_sleep_if(cond) do { if (cond) might_sleep(); } while (0)
++
++#define abs(x) ({ \
++ int __x = (x); \
++ (__x < 0) ? -__x : __x; \
++ })
++
++extern struct atomic_notifier_head panic_notifier_list;
++extern long (*panic_blink)(long time);
++NORET_TYPE void panic(const char * fmt, ...)
++ __attribute__ ((NORET_AND format (printf, 1, 2)));
++extern void oops_enter(void);
++extern void oops_exit(void);
++extern int oops_may_print(void);
++fastcall NORET_TYPE void do_exit(long error_code)
++ ATTRIB_NORET;
++NORET_TYPE void complete_and_exit(struct completion *, long)
++ ATTRIB_NORET;
++extern unsigned long simple_strtoul(const char *,char **,unsigned int);
++extern long simple_strtol(const char *,char **,unsigned int);
++extern unsigned long long simple_strtoull(const char *,char **,unsigned int);
++extern long long simple_strtoll(const char *,char **,unsigned int);
++extern int sprintf(char * buf, const char * fmt, ...)
++ __attribute__ ((format (printf, 2, 3)));
++extern int vsprintf(char *buf, const char *, va_list)
++ __attribute__ ((format (printf, 2, 0)));
++extern int snprintf(char * buf, size_t size, const char * fmt, ...)
++ __attribute__ ((format (printf, 3, 4)));
++extern int vsnprintf(char *buf, size_t size, const char *fmt, va_list args)
++ __attribute__ ((format (printf, 3, 0)));
++extern int scnprintf(char * buf, size_t size, const char * fmt, ...)
++ __attribute__ ((format (printf, 3, 4)));
++extern int vscnprintf(char *buf, size_t size, const char *fmt, va_list args)
++ __attribute__ ((format (printf, 3, 0)));
++extern char *kasprintf(gfp_t gfp, const char *fmt, ...)
++ __attribute__ ((format (printf, 2, 3)));
++
++extern int sscanf(const char *, const char *, ...)
++ __attribute__ ((format (scanf, 2, 3)));
++extern int vsscanf(const char *, const char *, va_list)
++ __attribute__ ((format (scanf, 2, 0)));
++
++extern int get_option(char **str, int *pint);
++extern char *get_options(const char *str, int nints, int *ints);
++extern unsigned long long memparse(char *ptr, char **retptr);
++
++extern int core_kernel_text(unsigned long addr);
++extern int __kernel_text_address(unsigned long addr);
++extern int kernel_text_address(unsigned long addr);
++struct pid;
++extern struct pid *session_of_pgrp(struct pid *pgrp);
++
++extern void dump_thread(struct pt_regs *regs, struct user *dump);
++
++#ifdef CONFIG_PRINTK
++asmlinkage int vprintk(const char *fmt, va_list args)
++ __attribute__ ((format (printf, 1, 0)));
++asmlinkage int printk(const char * fmt, ...)
++ __attribute__ ((format (printf, 1, 2)));
++#else
++static inline int vprintk(const char *s, va_list args)
++ __attribute__ ((format (printf, 1, 0)));
++static inline int vprintk(const char *s, va_list args) { return 0; }
++static inline int printk(const char *s, ...)
++ __attribute__ ((format (printf, 1, 2)));
++static inline int printk(const char *s, ...) { return 0; }
++#endif
+
-+enum
-+{
-+ PCI_LbaCount = 4, // Local base addresses.
-+} ;
++unsigned long int_sqrt(unsigned long);
+
-+typedef struct
-+{
-+ u32 a ; // Address.
-+ u32 c ; // Control.
-+ u32 m ; // mapping.
-+} PCI_Map_s ;
++extern int printk_ratelimit(void);
++extern int __printk_ratelimit(int ratelimit_jiffies, int ratelimit_burst);
++extern bool printk_timed_ratelimit(unsigned long *caller_jiffies,
++ unsigned int interval_msec);
+
-+typedef struct
++static inline void console_silent(void)
+{
-+ u32 pcic ;
-+ u32 pcis ;
-+ u32 pcism ;
-+ u32 pcicfga ;
-+ u32 pcicfgd ;
-+ PCI_Map_s pcilba [PCI_LbaCount] ;
-+ u32 pcidac ;
-+ u32 pcidas ;
-+ u32 pcidasm ;
-+ u32 pcidad ;
-+ u32 pcidma8c ;
-+ u32 pcidma9c ;
-+ u32 pcitc ;
-+} volatile *PCI_t ;
-+
-+// PCI messaging unit.
-+enum
-+{
-+ PCIM_Count = 2,
-+} ;
-+typedef struct
++ console_loglevel = 0;
++}
++
++static inline void console_verbose(void)
+{
-+ u32 pciim [PCIM_Count] ;
-+ u32 pciom [PCIM_Count] ;
-+ u32 pciid ;
-+ u32 pciiic ;
-+ u32 pciiim ;
-+ u32 pciiod ;
-+ u32 pciioic ;
-+ u32 pciioim ;
-+} volatile *PCIM_t ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Control Register
-+ *
-+ ******************************************************************************/
-+enum
++ if (console_loglevel)
++ console_loglevel = 15;
++}
++
++extern void bust_spinlocks(int yes);
++extern void wake_up_klogd(void);
++extern int oops_in_progress; /* If set, an oops, panic(), BUG() or die() is in progress */
++extern int panic_timeout;
++extern int panic_on_oops;
++extern int panic_on_unrecovered_nmi;
++extern int tainted;
++extern const char *print_tainted(void);
++extern void add_taint(unsigned);
++
++/* Values used for system_state */
++extern enum system_states {
++ SYSTEM_BOOTING,
++ SYSTEM_RUNNING,
++ SYSTEM_HALT,
++ SYSTEM_POWER_OFF,
++ SYSTEM_RESTART,
++ SYSTEM_SUSPEND_DISK,
++} system_state;
++
++#define TAINT_PROPRIETARY_MODULE (1<<0)
++#define TAINT_FORCED_MODULE (1<<1)
++#define TAINT_UNSAFE_SMP (1<<2)
++#define TAINT_FORCED_RMMOD (1<<3)
++#define TAINT_MACHINE_CHECK (1<<4)
++#define TAINT_BAD_PAGE (1<<5)
++#define TAINT_USER (1<<6)
++
++extern void dump_stack(void);
++
++#ifdef DEBUG
++/* If you are writing a driver, please use dev_dbg instead */
++#define pr_debug(fmt,arg...) \
++ printk(KERN_DEBUG fmt,##arg)
++#else
++static inline int __attribute__ ((format (printf, 1, 2))) pr_debug(const char * fmt, ...)
+{
-+ PCIC_en_b = 0,
-+ PCIC_en_m = 0x00000001,
-+ PCIC_tnr_b = 1,
-+ PCIC_tnr_m = 0x00000002,
-+ PCIC_sce_b = 2,
-+ PCIC_sce_m = 0x00000004,
-+ PCIC_ien_b = 3,
-+ PCIC_ien_m = 0x00000008,
-+ PCIC_aaa_b = 4,
-+ PCIC_aaa_m = 0x00000010,
-+ PCIC_eap_b = 5,
-+ PCIC_eap_m = 0x00000020,
-+ PCIC_pcim_b = 6,
-+ PCIC_pcim_m = 0x000001c0,
-+ PCIC_pcim_disabled_v = 0,
-+ PCIC_pcim_tnr_v = 1, // Satellite - target not ready
-+ PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
-+ PCIC_pcim_extern_v = 3, // Host - external arbiter.
-+ PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
-+ PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
-+ PCIC_pcim_reserved6_v = 6,
-+ PCIC_pcim_reserved7_v = 7,
-+ PCIC_igm_b = 9,
-+ PCIC_igm_m = 0x00000200,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Status Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIS_eed_b = 0,
-+ PCIS_eed_m = 0x00000001,
-+ PCIS_wr_b = 1,
-+ PCIS_wr_m = 0x00000002,
-+ PCIS_nmi_b = 2,
-+ PCIS_nmi_m = 0x00000004,
-+ PCIS_ii_b = 3,
-+ PCIS_ii_m = 0x00000008,
-+ PCIS_cwe_b = 4,
-+ PCIS_cwe_m = 0x00000010,
-+ PCIS_cre_b = 5,
-+ PCIS_cre_m = 0x00000020,
-+ PCIS_mdpe_b = 6,
-+ PCIS_mdpe_m = 0x00000040,
-+ PCIS_sta_b = 7,
-+ PCIS_sta_m = 0x00000080,
-+ PCIS_rta_b = 8,
-+ PCIS_rta_m = 0x00000100,
-+ PCIS_rma_b = 9,
-+ PCIS_rma_m = 0x00000200,
-+ PCIS_sse_b = 10,
-+ PCIS_sse_m = 0x00000400,
-+ PCIS_ose_b = 11,
-+ PCIS_ose_m = 0x00000800,
-+ PCIS_pe_b = 12,
-+ PCIS_pe_m = 0x00001000,
-+ PCIS_tae_b = 13,
-+ PCIS_tae_m = 0x00002000,
-+ PCIS_rle_b = 14,
-+ PCIS_rle_m = 0x00004000,
-+ PCIS_bme_b = 15,
-+ PCIS_bme_m = 0x00008000,
-+ PCIS_prd_b = 16,
-+ PCIS_prd_m = 0x00010000,
-+ PCIS_rip_b = 17,
-+ PCIS_rip_m = 0x00020000,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Status Mask Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCISM_eed_b = 0,
-+ PCISM_eed_m = 0x00000001,
-+ PCISM_wr_b = 1,
-+ PCISM_wr_m = 0x00000002,
-+ PCISM_nmi_b = 2,
-+ PCISM_nmi_m = 0x00000004,
-+ PCISM_ii_b = 3,
-+ PCISM_ii_m = 0x00000008,
-+ PCISM_cwe_b = 4,
-+ PCISM_cwe_m = 0x00000010,
-+ PCISM_cre_b = 5,
-+ PCISM_cre_m = 0x00000020,
-+ PCISM_mdpe_b = 6,
-+ PCISM_mdpe_m = 0x00000040,
-+ PCISM_sta_b = 7,
-+ PCISM_sta_m = 0x00000080,
-+ PCISM_rta_b = 8,
-+ PCISM_rta_m = 0x00000100,
-+ PCISM_rma_b = 9,
-+ PCISM_rma_m = 0x00000200,
-+ PCISM_sse_b = 10,
-+ PCISM_sse_m = 0x00000400,
-+ PCISM_ose_b = 11,
-+ PCISM_ose_m = 0x00000800,
-+ PCISM_pe_b = 12,
-+ PCISM_pe_m = 0x00001000,
-+ PCISM_tae_b = 13,
-+ PCISM_tae_m = 0x00002000,
-+ PCISM_rle_b = 14,
-+ PCISM_rle_m = 0x00004000,
-+ PCISM_bme_b = 15,
-+ PCISM_bme_m = 0x00008000,
-+ PCISM_prd_b = 16,
-+ PCISM_prd_m = 0x00010000,
-+ PCISM_rip_b = 17,
-+ PCISM_rip_m = 0x00020000,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Configuration Address Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCICFGA_reg_b = 2,
-+ PCICFGA_reg_m = 0x000000fc,
-+ PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
-+ PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
-+ PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
-+ PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
-+ PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
-+ PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
-+ PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
-+ PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
-+ PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
-+ PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
-+ PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba0m_v = 0x48>>2,
-+ PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba1m_v = 0x50>>2,
-+ PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba2m_v = 0x58>>2,
-+ PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
-+ PCICFGA_reg_pba3m_v = 0x60>>2,
-+ PCICFGA_reg_pmgt_v = 0x64>>2,
-+ PCICFGA_func_b = 8,
-+ PCICFGA_func_m = 0x00000700,
-+ PCICFGA_dev_b = 11,
-+ PCICFGA_dev_m = 0x0000f800,
-+ PCICFGA_dev_internal_v = 0,
-+ PCICFGA_bus_b = 16,
-+ PCICFGA_bus_m = 0x00ff0000,
-+ PCICFGA_bus_type0_v = 0, //local bus
-+ PCICFGA_en_b = 31, // read only
-+ PCICFGA_en_m = 0x80000000,
-+} ;
-+
-+enum {
-+ PCFGID_vendor_b = 0,
-+ PCFGID_vendor_m = 0x0000ffff,
-+ PCFGID_vendor_IDT_v = 0x111d,
-+ PCFGID_device_b = 16,
-+ PCFGID_device_m = 0xffff0000,
-+ PCFGID_device_Acaciade_v = 0x0207,
-+
-+ PCFG04_command_ioena_b = 1,
-+ PCFG04_command_ioena_m = 0x00000001,
-+ PCFG04_command_memena_b = 2,
-+ PCFG04_command_memena_m = 0x00000002,
-+ PCFG04_command_bmena_b = 3,
-+ PCFG04_command_bmena_m = 0x00000004,
-+ PCFG04_command_mwinv_b = 5,
-+ PCFG04_command_mwinv_m = 0x00000010,
-+ PCFG04_command_parena_b = 7,
-+ PCFG04_command_parena_m = 0x00000040,
-+ PCFG04_command_serrena_b = 9,
-+ PCFG04_command_serrena_m = 0x00000100,
-+ PCFG04_command_fastbbena_b = 10,
-+ PCFG04_command_fastbbena_m = 0x00000200,
-+ PCFG04_status_b = 16,
-+ PCFG04_status_m = 0xffff0000,
-+ PCFG04_status_66MHz_b = 21, // 66 MHz enable
-+ PCFG04_status_66MHz_m = 0x00200000,
-+ PCFG04_status_fbb_b = 23,
-+ PCFG04_status_fbb_m = 0x00800000,
-+ PCFG04_status_mdpe_b = 24,
-+ PCFG04_status_mdpe_m = 0x01000000,
-+ PCFG04_status_dst_b = 25,
-+ PCFG04_status_dst_m = 0x06000000,
-+ PCFG04_status_sta_b = 27,
-+ PCFG04_status_sta_m = 0x08000000,
-+ PCFG04_status_rta_b = 28,
-+ PCFG04_status_rta_m = 0x10000000,
-+ PCFG04_status_rma_b = 29,
-+ PCFG04_status_rma_m = 0x20000000,
-+ PCFG04_status_sse_b = 30,
-+ PCFG04_status_sse_m = 0x40000000,
-+ PCFG04_status_pe_b = 31,
-+ PCFG04_status_pe_m = 0x40000000,
-+
-+ PCFG08_revId_b = 0,
-+ PCFG08_revId_m = 0x000000ff,
-+ PCFG08_classCode_b = 0,
-+ PCFG08_classCode_m = 0xffffff00,
-+ PCFG08_classCode_bridge_v = 06,
-+ PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
-+ PCFG0C_cacheline_b = 0,
-+ PCFG0C_cacheline_m = 0x000000ff,
-+ PCFG0C_masterLatency_b = 8,
-+ PCFG0C_masterLatency_m = 0x0000ff00,
-+ PCFG0C_headerType_b = 16,
-+ PCFG0C_headerType_m = 0x00ff0000,
-+ PCFG0C_bist_b = 24,
-+ PCFG0C_bist_m = 0xff000000,
-+
-+ PCIPBA_msi_b = 0,
-+ PCIPBA_msi_m = 0x00000001,
-+ PCIPBA_p_b = 3,
-+ PCIPBA_p_m = 0x00000004,
-+ PCIPBA_baddr_b = 8,
-+ PCIPBA_baddr_m = 0xffffff00,
-+
-+ PCFGSS_vendorId_b = 0,
-+ PCFGSS_vendorId_m = 0x0000ffff,
-+ PCFGSS_id_b = 16,
-+ PCFGSS_id_m = 0xffff0000,
-+
-+ PCFG3C_interruptLine_b = 0,
-+ PCFG3C_interruptLine_m = 0x000000ff,
-+ PCFG3C_interruptPin_b = 8,
-+ PCFG3C_interruptPin_m = 0x0000ff00,
-+ PCFG3C_minGrant_b = 16,
-+ PCFG3C_minGrant_m = 0x00ff0000,
-+ PCFG3C_maxLat_b = 24,
-+ PCFG3C_maxLat_m = 0xff000000,
-+
-+ PCIPBAC_msi_b = 0,
-+ PCIPBAC_msi_m = 0x00000001,
-+ PCIPBAC_p_b = 1,
-+ PCIPBAC_p_m = 0x00000002,
-+ PCIPBAC_size_b = 2,
-+ PCIPBAC_size_m = 0x0000007c,
-+ PCIPBAC_sb_b = 7,
-+ PCIPBAC_sb_m = 0x00000080,
-+ PCIPBAC_pp_b = 8,
-+ PCIPBAC_pp_m = 0x00000100,
-+ PCIPBAC_mr_b = 9,
-+ PCIPBAC_mr_m = 0x00000600,
-+ PCIPBAC_mr_read_v =0, //no prefetching
-+ PCIPBAC_mr_readLine_v =1,
-+ PCIPBAC_mr_readMult_v =2,
-+ PCIPBAC_mrl_b = 11,
-+ PCIPBAC_mrl_m = 0x00000800,
-+ PCIPBAC_mrm_b = 12,
-+ PCIPBAC_mrm_m = 0x00001000,
-+ PCIPBAC_trp_b = 13,
-+ PCIPBAC_trp_m = 0x00002000,
-+
-+ PCFG40_trdyTimeout_b = 0,
-+ PCFG40_trdyTimeout_m = 0x000000ff,
-+ PCFG40_retryLim_b = 8,
-+ PCFG40_retryLim_m = 0x0000ff00,
-+};
++ return 0;
++}
++#endif
+
-+/*******************************************************************************
-+ *
-+ * PCI Local Base Address [0|1|2|3] Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
-+ PCILBA_baddr_m = 0xffffff00,
-+} ;
-+/*******************************************************************************
-+ *
-+ * PCI Local Base Address Control Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
-+ PCILBAC_msi_m = 0x00000001,
-+ PCILBAC_msi_mem_v = 0,
-+ PCILBAC_msi_io_v = 1,
-+ PCILBAC_size_b = 2, // In pPci->pcilba[i].c
-+ PCILBAC_size_m = 0x0000007c,
-+ PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
-+ PCILBAC_sb_m = 0x00000080,
-+ PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
-+ PCILBAC_rt_m = 0x00000100,
-+ PCILBAC_rt_noprefetch_v = 0, // mem read
-+ PCILBAC_rt_prefetch_v = 1, // mem readline
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI Local Base Address [0|1|2|3] Mapping Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCILBAM_maddr_b = 8,
-+ PCILBAM_maddr_m = 0xffffff00,
-+} ;
++#define pr_info(fmt,arg...) \
++ printk(KERN_INFO fmt,##arg)
+
-+/*******************************************************************************
-+ *
-+ * PCI Decoupled Access Control Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIDAC_den_b = 0,
-+ PCIDAC_den_m = 0x00000001,
-+} ;
++/*
++ * Display an IP address in readable format.
++ */
+
-+/*******************************************************************************
-+ *
-+ * PCI Decoupled Access Status Register
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIDAS_d_b = 0,
-+ PCIDAS_d_m = 0x00000001,
-+ PCIDAS_b_b = 1,
-+ PCIDAS_b_m = 0x00000002,
-+ PCIDAS_e_b = 2,
-+ PCIDAS_e_m = 0x00000004,
-+ PCIDAS_ofe_b = 3,
-+ PCIDAS_ofe_m = 0x00000008,
-+ PCIDAS_off_b = 4,
-+ PCIDAS_off_m = 0x00000010,
-+ PCIDAS_ife_b = 5,
-+ PCIDAS_ife_m = 0x00000020,
-+ PCIDAS_iff_b = 6,
-+ PCIDAS_iff_m = 0x00000040,
-+} ;
-+
-+/*******************************************************************************
-+ *
-+ * PCI DMA Channel 8 Configuration Register
-+ *
-+ ******************************************************************************/
-+enum
-+{
-+ PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
-+ PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
-+ PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
-+ PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
-+} ;
++#define NIPQUAD(addr) \
++ ((unsigned char *)&addr)[0], \
++ ((unsigned char *)&addr)[1], \
++ ((unsigned char *)&addr)[2], \
++ ((unsigned char *)&addr)[3]
++#define NIPQUAD_FMT "%u.%u.%u.%u"
++
++#define NIP6(addr) \
++ ntohs((addr).s6_addr16[0]), \
++ ntohs((addr).s6_addr16[1]), \
++ ntohs((addr).s6_addr16[2]), \
++ ntohs((addr).s6_addr16[3]), \
++ ntohs((addr).s6_addr16[4]), \
++ ntohs((addr).s6_addr16[5]), \
++ ntohs((addr).s6_addr16[6]), \
++ ntohs((addr).s6_addr16[7])
++#define NIP6_FMT "%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x"
++#define NIP6_SEQFMT "%04x%04x%04x%04x%04x%04x%04x%04x"
++
++#if defined(__LITTLE_ENDIAN)
++#define HIPQUAD(addr) \
++ ((unsigned char *)&addr)[3], \
++ ((unsigned char *)&addr)[2], \
++ ((unsigned char *)&addr)[1], \
++ ((unsigned char *)&addr)[0]
++#elif defined(__BIG_ENDIAN)
++#define HIPQUAD NIPQUAD
++#else
++#error "Please fix asm/byteorder.h"
++#endif /* __LITTLE_ENDIAN */
+
-+/*******************************************************************************
-+ *
-+ * PCI DMA Channel 9 Configuration Register
-+ *
-+ ******************************************************************************/
-+enum
-+{
-+ PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
-+ PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
-+} ;
++/*
++ * min()/max() macros that also do
++ * strict type-checking.. See the
++ * "unnecessary" pointer comparison.
++ */
++#define min(x,y) ({ \
++ typeof(x) _x = (x); \
++ typeof(y) _y = (y); \
++ (void) (&_x == &_y); \
++ _x < _y ? _x : _y; })
++
++#define max(x,y) ({ \
++ typeof(x) _x = (x); \
++ typeof(y) _y = (y); \
++ (void) (&_x == &_y); \
++ _x > _y ? _x : _y; })
+
-+/*******************************************************************************
-+ *
-+ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
-+ *
-+ ******************************************************************************/
-+enum {
-+ PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
-+ PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
-+ // These are for reads (DMA channel 8)
-+ PCIDMAD_devcmd_mr_v = 0, //memory read
-+ PCIDMAD_devcmd_mrl_v = 1, //memory read line
-+ PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
-+ PCIDMAD_devcmd_ior_v = 3, //I/O read
-+ // These are for writes (DMA channel 9)
-+ PCIDMAD_devcmd_mw_v = 0, //memory write
-+ PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
-+ PCIDMAD_devcmd_iow_v = 3, //I/O write
-+
-+ // Swap byte field applies to both DMA channel 8 and 9
-+ PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
-+ PCIDMAD_sb_m = 0x01000000, // swap byte field
-+} ;
-+
-+
-+/*******************************************************************************
-+ *
-+ * PCI Target Control Register
-+ *
-+ ******************************************************************************/
-+enum
-+{
-+ PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
-+ PCITC_rtimer_m = 0x000000ff,
-+ PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
-+ PCITC_dtimer_m = 0x0000ff00,
-+ PCITC_rdr_b = 18, // In PCITC_t -> pcitc
-+ PCITC_rdr_m = 0x00040000,
-+ PCITC_ddt_b = 19, // In PCITC_t -> pcitc
-+ PCITC_ddt_m = 0x00080000,
-+} ;
-+/*******************************************************************************
-+ *
-+ * PCI messaging unit [applies to both inbound and outbound registers ]
++/*
++ * ..and if you can't take the strict
++ * types, you can specify one yourself.
+ *
-+ ******************************************************************************/
-+enum
-+{
-+ PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
-+ PCIM_m0_m = 0x00000001, // inbound or outbound message 0
-+ PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
-+ PCIM_m1_m = 0x00000002, // inbound or outbound message 1
-+ PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
-+ PCIM_db_m = 0x00000004, // inbound or outbound doorbell
-+};
++ * Or not use min/max at all, of course.
++ */
++#define min_t(type,x,y) \
++ ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
++#define max_t(type,x,y) \
++ ({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,190 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Definitions for IDT RC32438 PCI setup.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik
-+ *
-+ * Initial Release
-+ *
-+ *
++
++/**
++ * container_of - cast a member of a structure out to the containing structure
++ * @ptr: the pointer to the member.
++ * @type: the type of the container struct this is embedded in.
++ * @member: the name of the member within the struct.
+ *
-+ **************************************************************************
+ */
++#define container_of(ptr, type, member) ({ \
++ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
++ (type *)( (char *)__mptr - offsetof(type,member) );})
+
-+#define PCI_MSG_VirtualAddress 0xB8088010
-+#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
-+#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
-+
-+#define PCIM_SHFT 0x6
-+#define PCIM_BIT_LEN 0x7
-+#define PCIM_H_EA 0x3
-+#define PCIM_H_IA_FIX 0x4
-+#define PCIM_H_IA_RR 0x5
-+
-+#define PCI_ADDR_START 0x50000000
-+
-+#define CPUTOPCI_MEM_WIN 0x02000000
-+#define CPUTOPCI_IO_WIN 0x00100000
-+#define PCILBA_SIZE_SHFT 2
-+#define PCILBA_SIZE_MASK 0x1F
-+#define SIZE_256MB 0x1C
-+#define SIZE_128MB 0x1B
-+#define SIZE_64MB 0x1A
-+#define SIZE_32MB 0x19
-+#define SIZE_16MB 0x18
-+#define SIZE_4MB 0x16
-+#define SIZE_2MB 0x15
-+#define SIZE_1MB 0x14
-+#define ACACIA_CONFIG0_ADDR 0x80000000
-+#define ACACIA_CONFIG1_ADDR 0x80000004
-+#define ACACIA_CONFIG2_ADDR 0x80000008
-+#define ACACIA_CONFIG3_ADDR 0x8000000C
-+#define ACACIA_CONFIG4_ADDR 0x80000010
-+#define ACACIA_CONFIG5_ADDR 0x80000014
-+#define ACACIA_CONFIG6_ADDR 0x80000018
-+#define ACACIA_CONFIG7_ADDR 0x8000001C
-+#define ACACIA_CONFIG8_ADDR 0x80000020
-+#define ACACIA_CONFIG9_ADDR 0x80000024
-+#define ACACIA_CONFIG10_ADDR 0x80000028
-+#define ACACIA_CONFIG11_ADDR 0x8000002C
-+#define ACACIA_CONFIG12_ADDR 0x80000030
-+#define ACACIA_CONFIG13_ADDR 0x80000034
-+#define ACACIA_CONFIG14_ADDR 0x80000038
-+#define ACACIA_CONFIG15_ADDR 0x8000003C
-+#define ACACIA_CONFIG16_ADDR 0x80000040
-+#define ACACIA_CONFIG17_ADDR 0x80000044
-+#define ACACIA_CONFIG18_ADDR 0x80000048
-+#define ACACIA_CONFIG19_ADDR 0x8000004C
-+#define ACACIA_CONFIG20_ADDR 0x80000050
-+#define ACACIA_CONFIG21_ADDR 0x80000054
-+#define ACACIA_CONFIG22_ADDR 0x80000058
-+#define ACACIA_CONFIG23_ADDR 0x8000005C
-+#define ACACIA_CONFIG24_ADDR 0x80000060
-+#define ACACIA_CONFIG25_ADDR 0x80000064
-+#define ACACIA_CMD (PCFG04_command_ioena_m | \
-+ PCFG04_command_memena_m | \
-+ PCFG04_command_bmena_m | \
-+ PCFG04_command_mwinv_m | \
-+ PCFG04_command_parena_m | \
-+ PCFG04_command_serrena_m )
-+
-+#define ACACIA_STAT (PCFG04_status_mdpe_m | \
-+ PCFG04_status_sta_m | \
-+ PCFG04_status_rta_m | \
-+ PCFG04_status_rma_m | \
-+ PCFG04_status_sse_m | \
-+ PCFG04_status_pe_m)
-+
-+#define ACACIA_CNFG1 ((ACACIA_STAT<<16)|ACACIA_CMD)
-+
-+#define ACACIA_REVID 0
-+#define ACACIA_CLASS_CODE 0
-+#define ACACIA_CNFG2 ((ACACIA_CLASS_CODE<<8) | \
-+ ACACIA_REVID)
-+
-+#define ACACIA_CACHE_LINE_SIZE 4
-+#define ACACIA_MASTER_LAT 0x3c
-+#define ACACIA_HEADER_TYPE 0
-+#define ACACIA_BIST 0
-+
-+#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
-+ (ACACIA_HEADER_TYPE<<16) | \
-+ (ACACIA_MASTER_LAT<<8) | \
-+ ACACIA_CACHE_LINE_SIZE )
-+
-+#define ACACIA_BAR0 0x00000008 /* 128 MB Memory */
-+#define ACACIA_BAR1 0x18800001 /* 1 MB IO */
-+#define ACACIA_BAR2 0x18000001 /* 2 MB IO window for Acacia
-+ internal Registers */
-+#define ACACIA_BAR3 0x48000008 /* Spare 128 MB Memory */
-+
-+#define ACACIA_CNFG4 ACACIA_BAR0
-+#define ACACIA_CNFG5 ACACIA_BAR1
-+#define ACACIA_CNFG6 ACACIA_BAR2
-+#define ACACIA_CNFG7 ACACIA_BAR3
-+
-+#define ACACIA_SUBSYS_VENDOR_ID 0
-+#define ACACIA_SUBSYSTEM_ID 0
-+#define ACACIA_CNFG8 0
-+#define ACACIA_CNFG9 0
-+#define ACACIA_CNFG10 0
-+#define ACACIA_CNFG11 ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
-+ ACACIA_SUBSYSTEM_ID)
-+#define ACACIA_INT_LINE 1
-+#define ACACIA_INT_PIN 1
-+#define ACACIA_MIN_GNT 8
-+#define ACACIA_MAX_LAT 0x38
-+#define ACACIA_CNFG12 0
-+#define ACACIA_CNFG13 0
-+#define ACACIA_CNFG14 0
-+#define ACACIA_CNFG15 ((ACACIA_MAX_LAT<<24) | \
-+ (ACACIA_MIN_GNT<<16) | \
-+ (ACACIA_INT_PIN<<8) | \
-+ ACACIA_INT_LINE)
-+#define ACACIA_RETRY_LIMIT 0x80
-+#define ACACIA_TRDY_LIMIT 0x80
-+#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
-+ ACACIA_TRDY_LIMIT)
-+#define PCI_PBAxC_R 0x0
-+#define PCI_PBAxC_RL 0x1
-+#define PCI_PBAxC_RM 0x2
-+#define SIZE_SHFT 2
-+
-+#define ACACIA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
-+ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
-+ PCIPBAC_pp_m | \
-+ (SIZE_128MB<<SIZE_SHFT) | \
-+ PCIPBAC_p_m)
-+
-+#define ACACIA_CNFG17 ACACIA_PBA0C
-+#define ACACIA_PBA0M 0x0
-+#define ACACIA_CNFG18 ACACIA_PBA0M
-+
-+#define ACACIA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
-+ PCIPBAC_msi_m)
-+
-+#define ACACIA_CNFG19 ACACIA_PBA1C
-+#define ACACIA_PBA1M 0x0
-+#define ACACIA_CNFG20 ACACIA_PBA1M
-+
-+#define ACACIA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
-+ PCIPBAC_msi_m)
-+
-+#define ACACIA_CNFG21 ACACIA_PBA2C
-+#define ACACIA_PBA2M 0x18000000
-+#define ACACIA_CNFG22 ACACIA_PBA2M
-+#define ACACIA_PBA3C 0
-+#define ACACIA_CNFG23 ACACIA_PBA3C
-+#define ACACIA_PBA3M 0
-+#define ACACIA_CNFG24 ACACIA_PBA3M
-+
-+
-+
-+#define PCITC_DTIMER_VAL 8
-+#define PCITC_RTIMER_VAL 0x10
-+
-diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
---- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 2006-06-18 12:44:28.000000000 +0200
-@@ -0,0 +1,91 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Timer register definition IDT RC32438 CPU.
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 P. Sadik.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
++/*
++ * Check at compile time that something is of a particular type.
++ * Always evaluates to 1 so you may use it easily in comparisons.
+ */
-+
-+#ifndef __IDT_RC32438_TIM_H__
-+#define __IDT_RC32438_TIM_H__
++#define typecheck(type,x) \
++({ type __dummy; \
++ typeof(x) __dummy2; \
++ (void)(&__dummy == &__dummy2); \
++ 1; \
++})
+
-+enum
-+{
-+ TIM0_PhysicalAddress = 0x18028000,
-+ TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
++/*
++ * Check at compile time that 'function' is a certain type, or is a pointer
++ * to that type (needs to use typedef for the function type.)
++ */
++#define typecheck_fn(type,function) \
++({ typeof(type) __tmp = function; \
++ (void)__tmp; \
++})
++
++struct sysinfo;
++extern int do_sysinfo(struct sysinfo *info);
++
++#endif /* __KERNEL__ */
++
++#define SI_LOAD_SHIFT 16
++struct sysinfo {
++ long uptime; /* Seconds since boot */
++ unsigned long loads[3]; /* 1, 5, and 15 minute load averages */
++ unsigned long totalram; /* Total usable main memory size */
++ unsigned long freeram; /* Available memory size */
++ unsigned long sharedram; /* Amount of shared memory */
++ unsigned long bufferram; /* Memory used by buffers */
++ unsigned long totalswap; /* Total swap space size */
++ unsigned long freeswap; /* swap space still available */
++ unsigned short procs; /* Number of current processes */
++ unsigned short pad; /* explicit padding for m68k */
++ unsigned long totalhigh; /* Total high memory size */
++ unsigned long freehigh; /* Available high memory size */
++ unsigned int mem_unit; /* Memory unit size in bytes */
++ char _f[20-2*sizeof(long)-sizeof(int)]; /* Padding: libc5 uses this.. */
++};
+
-+ TIM0_VirtualAddress = 0xb8028000,
-+ TIM_VirtualAddress = TIM0_VirtualAddress, // Default
-+} ;
++/* Force a compilation error if condition is true */
++#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+
-+enum
-+{
-+ TIM_Count = 3,
-+} ;
++/* Force a compilation error if condition is true, but also produce a
++ result (of value 0 and type size_t), so the expression can be used
++ e.g. in a structure initializer (or where-ever else comma expressions
++ aren't permitted). */
++#define BUILD_BUG_ON_ZERO(e) (sizeof(char[1 - 2 * !!(e)]) - 1)
+
-+struct TIM_CNTR_s
-+{
-+ u32 count ;
-+ u32 compare ;
-+ u32 ctc ; //use CTC_
-+} ;
++/* Trap pasters of __FUNCTION__ at compile-time */
++#define __FUNCTION__ (__func__)
+
-+typedef struct TIM_s
-+{
-+ struct TIM_CNTR_s tim [TIM_Count] ;
-+ u32 rcount ; //use RCOUNT_
-+ u32 rcompare ; //use RCOMPARE_
-+ u32 rtc ; //use RTC_
-+} volatile * TIM_t ;
++/* This helps us to avoid #ifdef CONFIG_NUMA */
++#ifdef CONFIG_NUMA
++#define NUMA_BUILD 1
++#else
++#define NUMA_BUILD 0
++#endif
+
-+enum
-+{
-+ CTC_en_b = 0,
-+ CTC_en_m = 0x00000001,
-+ CTC_to_b = 1,
-+ CTC_to_m = 0x00000002,
-+
-+ RCOUNT_count_b = 0,
-+ RCOUNT_count_m = 0x0000ffff,
-+ RCOMPARE_compare_b = 0,
-+ RCOMPARE_compare_m = 0x0000ffff,
-+ RTC_ce_b = 0,
-+ RTC_ce_m = 0x00000001,
-+ RTC_to_b = 1,
-+ RTC_to_m = 0x00000002,
-+ RTC_rqe_b = 2,
-+ RTC_rqe_m = 0x00000004,
-+
-+} ;
-+#endif //__IDT_RC32438_TIM_H__
-+
-diff -Nur linux-2.6.17/include/asm-mips/mach-generic/irq.h linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h
---- linux-2.6.17/include/asm-mips/mach-generic/irq.h 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h 2006-06-18 12:44:28.000000000 +0200
-@@ -8,6 +8,6 @@
- #ifndef __ASM_MACH_GENERIC_IRQ_H
- #define __ASM_MACH_GENERIC_IRQ_H
-
--#define NR_IRQS 128
-+#define NR_IRQS 256
-
- #endif /* __ASM_MACH_GENERIC_IRQ_H */
-diff -Nur linux-2.6.17/include/linux/kernel.h linux-2.6.17-owrt/include/linux/kernel.h
---- linux-2.6.17/include/linux/kernel.h 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/include/linux/kernel.h 2006-06-18 12:44:28.000000000 +0200
-@@ -329,6 +329,7 @@
- };
-
- /* Force a compilation error if condition is true */
-+extern void BUILD_BUG(void);
- #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
-
- /* Trap pasters of __FUNCTION__ at compile-time */
++#endif
projects / openwrt.git / blobdiff