ar71xx: define NAND controller base address and register size for AR934X/QCA955x

[openwrt.git] / target / linux / ar71xx / patches-3.3 / 601-MIPS-ath79-add-more-register-defines.patch

diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
index 7166475..8a11a70 100644 (file)
--- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
@@ -20,7 +20,7 @@
  
  #define AR71XX_PCI_MEM_BASE   0x10000000
  #define AR71XX_PCI_MEM_SIZE   0x07000000
-@@ -82,11 +88,15 @@
+@@ -82,17 +88,23 @@
  
  #define AR933X_UART_BASE      (AR71XX_APB_BASE + 0x00020000)
  #define AR933X_UART_SIZE      0x14
@@ -36,16 +36,26 @@
  #define AR934X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
  #define AR934X_WMAC_SIZE      0x20000
  #define AR934X_EHCI_BASE      0x1b000000
-@@ -110,6 +120,8 @@
+ #define AR934X_EHCI_SIZE      0x200
+ #define AR934X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE      0x1000
++#define AR934X_NFC_BASE               0x1b000200
++#define AR934X_NFC_SIZE               0xb8
+ 
+ #define QCA955X_PCI_MEM_BASE0 0x10000000
+ #define QCA955X_PCI_MEM_BASE1 0x12000000
+@@ -112,6 +124,10 @@
  #define QCA955X_EHCI0_BASE    0x1b000000
  #define QCA955X_EHCI1_BASE    0x1b400000
- #define QCA955X_EHCI_SIZE     0x1000
+ #define QCA955X_EHCI_SIZE     0x200
 +#define QCA955X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
 +#define QCA955X_GMAC_SIZE     0x40
++#define QCA955X_NFC_BASE      0x1b000200
++#define QCA955X_NFC_SIZE      0xb8
  
  /*
   * DDR_CTRL block
-@@ -165,6 +177,9 @@
+@@ -167,6 +183,9 @@
  #define AR71XX_AHB_DIV_SHIFT          20
  #define AR71XX_AHB_DIV_MASK           0x7
  
@@ -55,7 +65,7 @@
  #define AR724X_PLL_REG_CPU_CONFIG     0x00
  #define AR724X_PLL_REG_PCIE_CONFIG    0x18
  
-@@ -177,6 +192,8 @@
+@@ -179,6 +198,8 @@
  #define AR724X_DDR_DIV_SHIFT          22
  #define AR724X_DDR_DIV_MASK           0x3
  
@@ -64,7 +74,7 @@
  #define AR913X_PLL_REG_CPU_CONFIG     0x00
  #define AR913X_PLL_REG_ETH_CONFIG     0x04
  #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
-@@ -189,6 +206,9 @@
+@@ -191,6 +212,9 @@
  #define AR913X_AHB_DIV_SHIFT          19
  #define AR913X_AHB_DIV_MASK           0x1
  
@@ -74,15 +84,25 @@
  #define AR933X_PLL_CPU_CONFIG_REG     0x00
  #define AR933X_PLL_CLOCK_CTRL_REG     0x08
  
-@@ -210,6 +230,7 @@
+@@ -212,6 +236,8 @@
  #define AR934X_PLL_CPU_CONFIG_REG             0x00
  #define AR934X_PLL_DDR_CONFIG_REG             0x04
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG               0x08
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG   0x24
 +#define AR934X_PLL_ETH_XMII_CONTROL_REG               0x2c
  
  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
-@@ -368,16 +389,50 @@
+@@ -244,6 +270,8 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL        BIT(21)
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL        BIT(24)
+ 
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL  BIT(6)
++
+ #define QCA955X_PLL_CPU_CONFIG_REG            0x00
+ #define QCA955X_PLL_DDR_CONFIG_REG            0x04
+ #define QCA955X_PLL_CLK_CTRL_REG              0x08
+@@ -370,16 +398,50 @@
  #define AR913X_RESET_USB_HOST         BIT(5)
  #define AR913X_RESET_USB_PHY          BIT(4)
  
@@ -133,7 +153,7 @@
  #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)
-@@ -518,6 +573,14 @@
+@@ -520,6 +582,14 @@
  #define AR71XX_GPIO_REG_INT_ENABLE    0x24
  #define AR71XX_GPIO_REG_FUNC          0x28
  
@@ -148,9 +168,9 @@
  #define AR71XX_GPIO_COUNT             16
  #define AR724X_GPIO_COUNT             18
  #define AR913X_GPIO_COUNT             22
-@@ -525,4 +588,133 @@
- #define AR934X_GPIO_COUNT             23
- #define QCA955X_GPIO_COUNT            24
+@@ -548,4 +618,133 @@
+ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
+ #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  
 +#define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
 +#define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)