/*
- * OHCI HCD (Host Controller Driver) for USB.
+ * ADM5120 HCD (Host Controller Driver) for USB
*
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci.h
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
*
- * This file is licenced under the GPL.
*/
/*
dma_addr_t dma; /* addr of ED */
struct td *dummy; /* next TD to activate */
- struct urb_priv *urb_active; /* active URB */
- struct list_head urb_pending; /* pending URBs */
-
- struct list_head ed_list; /* list of all EDs*/
- struct list_head rm_list; /* for remove list */
+ struct list_head urb_list; /* list of our URBs */
/* host's view of schedule */
struct ed *ed_next; /* on schedule list */
struct ed *ed_prev; /* for non-interrupt EDs */
struct ed *ed_rm_next; /* on rm list */
+ struct list_head td_list; /* "shadow list" of our TDs */
/* create --> IDLE --> OPER --> ... --> IDLE --> destroy
* usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
*/
- u8 state;
-#define ED_NEW 0x00 /* just allocated */
-#define ED_IDLE 0x01 /* linked into HC, but not running */
-#define ED_OPER 0x02 /* linked into HC and running */
-#define ED_UNLINK 0x03 /* being unlinked from HC */
+ u8 state; /* ED_{IDLE,UNLINK,OPER} */
+#define ED_IDLE 0x00 /* NOT linked to HC */
+#define ED_UNLINK 0x01 /* being unlinked from hc */
+#define ED_OPER 0x02 /* IS linked to hc */
u8 type; /* PIPE_{BULK,...} */
#define TD_DP_SHIFT 21 /* direction/pid */
#define TD_DP_MASK 0x3
#define TD_DP (TD_DP_MASK << TD_DP_SHIFT)
+#define TD_DP_GET (((x) >> TD_DP_SHIFT) & TD_DP_MASK)
#define TD_DP_SETUP (0x0 << TD_DP_SHIFT) /* SETUP pid */
#define TD_DP_OUT (0x1 << TD_DP_SHIFT) /* OUT pid */
#define TD_DP_IN (0x2 << TD_DP_SHIFT) /* IN pid */
-#define TD_DP_GET(x) (((x) >> TD_DP_SHIFT) & TD_DP_MASK)
#define TD_ISI_SHIFT 8 /* Interrupt Service Interval */
#define TD_ISI_MASK 0x3f
#define TD_ISI_GET(x) (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK)
/* rest are purely for the driver's use */
__u8 index;
-/* struct ed *ed;*/
+ struct ed *ed;
+ struct td *td_hash; /* dma-->td hashtable */
+ struct td *next_dl_td;
struct urb *urb;
dma_addr_t td_dma; /* addr of this TD */
dma_addr_t data_dma; /* addr of data it points to */
+ struct list_head td_list; /* "shadow list", TDs on same ED */
+
+ u32 flags;
+#define TD_FLAG_DONE (1 << 17) /* retired to done list */
+#define TD_FLAG_ISO (1 << 16) /* copy of ED_ISO */
} __attribute__ ((aligned(TD_ALIGN))); /* c/b/i need 16; only iso needs 32 */
/*
/* map OHCI TD status codes (CC) to errno values */
-static const int cc_to_error [16] = {
+static const int cc_to_error[16] = {
/* No Error */ 0,
/* CRC Error */ -EILSEQ,
/* Bit Stuff */ -EPROTO,
*/
#define ADMHC_INTR_SOFI (1 << 4) /* start of frame */
#define ADMHC_INTR_RESI (1 << 5) /* resume detected */
+#define ADMHC_INTR_6 (1 << 6) /* unknown */
+#define ADMHC_INTR_7 (1 << 7) /* unknown */
#define ADMHC_INTR_BABI (1 << 8) /* babble detected */
#define ADMHC_INTR_INSM (1 << 9) /* root hub status change */
#define ADMHC_INTR_SO (1 << 10) /* scheduling overrun */
/* hcd-private per-urb state */
struct urb_priv {
struct ed *ed;
- struct urb *urb;
struct list_head pending; /* URBs on the same ED */
u32 td_cnt; /* # tds in this request */
* hcd adds to schedule for a live hc any time, but removals finish
* only at the start of the next frame.
*/
+
struct ed *ed_head;
struct ed *ed_tails[4];
struct ed *ed_rm_list; /* to be removed */
+
struct ed *periodic[NUM_INTS]; /* shadow int_table */
#if 0 /* TODO: remove? */
* other external transceivers should be software-transparent
*/
struct otg_transceiver *transceiver;
+ void (*start_hnp)(struct admhcd *ahcd);
#endif
/*
struct dma_pool *td_cache;
struct dma_pool *ed_cache;
struct td *td_hash[TD_HASH_SIZE];
+ struct list_head pending;
/*
* driver state
#define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */
#define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */
#define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/
- // there are also chip quirks/bugs in init logic
+ /* there are also chip quirks/bugs in init logic */
+
+#ifdef DEBUG
+ struct dentry *debug_dir;
+ struct dentry *debug_async;
+ struct dentry *debug_periodic;
+ struct dentry *debug_registers;
+#endif
};
/* convert between an hcd pointer and the corresponding ahcd_hcd */
#define STUB_DEBUG_FILES
#endif /* DEBUG */
-#define admhc_dbg(ahcd, fmt, args...) \
- printk(KERN_DEBUG "adm5120-hcd: " fmt , ## args )
+#ifdef DEBUG
+# define admhc_dbg(ahcd, fmt, args...) \
+ printk(KERN_DEBUG "adm5120-hcd: " fmt, ## args)
+#else
+# define admhc_dbg(ahcd, fmt, args...) do { } while (0)
+#endif
+
#define admhc_err(ahcd, fmt, args...) \
- printk(KERN_ERR "adm5120-hcd: " fmt , ## args )
-#define ahcd_info(ahcd, fmt, args...) \
- printk(KERN_INFO "adm5120-hcd: " fmt , ## args )
+ printk(KERN_ERR "adm5120-hcd: " fmt, ## args)
+#define admhc_info(ahcd, fmt, args...) \
+ printk(KERN_INFO "adm5120-hcd: " fmt, ## args)
#define admhc_warn(ahcd, fmt, args...) \
- printk(KERN_WARNING "adm5120-hcd: " fmt , ## args )
+ printk(KERN_WARNING "adm5120-hcd: " fmt, ## args)
#ifdef ADMHC_VERBOSE_DEBUG
# define admhc_vdbg admhc_dbg
* Big-endian read/write functions are arch-specific.
* Other arches can be added if/when they're needed.
*
- * REVISIT: arch/powerpc now has readl/writel_be, so the
- * definition below can die once the STB04xxx support is
- * finally ported over.
*/
-#if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
-#define readl_be(addr) in_be32((__force unsigned *)addr)
-#define writel_be(val, addr) out_be32((__force unsigned *)addr, val)
-#endif
-
static inline unsigned int admhc_readl(const struct admhcd *ahcd,
__hc32 __iomem *regs)
{
#endif
}
+static inline void admhc_writel_flush(const struct admhcd *ahcd)
+{
+#if 0
+ /* TODO: remove? */
+ (void) admhc_readl(ahcd, &ahcd->regs->gencontrol);
+#endif
+}
+
+
/*-------------------------------------------------------------------------*/
/* cpu to ahcd */
admhcd_to_hcd(ahcd)->state = HC_STATE_HALT;
}
-#define FI 0x2edf /* 12000 bits per frame (-1) */
-#define FSLDP(fi) (0x7fff & ((6 * ((fi) - 1200)) / 7))
-#define FIT ADMHC_SFI_FIT
-#define LSTHRESH 0x628 /* lowspeed bit threshold */
+#define FI 0x2edf /* 12000 bits per frame (-1) */
+#define FSLDP(fi) (0x7fff & ((6 * ((fi) - 1200)) / 7))
+#define FIT ADMHC_SFI_FIT
+#define LSTHRESH 0x628 /* lowspeed bit threshold */
static inline void periodic_reinit(struct admhcd *ahcd)
{
+#if 0
+ u32 fi = ahcd->fminterval & ADMHC_SFI_FI_MASK;
+ u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
+
+ /* TODO: adjust FSLargestDataPacket value too? */
+ admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
+ &ahcd->regs->fminterval);
+#else
u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
/* TODO: adjust FSLargestDataPacket value too? */
admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
&ahcd->regs->fminterval);
+#endif
}
-static inline u32 admhc_get_rhdesc(struct admhcd *ahcd)
+static inline u32 admhc_read_rhdesc(struct admhcd *ahcd)
{
return admhc_readl(ahcd, &ahcd->regs->rhdesc);
}
-static inline u32 admhc_get_portstatus(struct admhcd *ahcd, int port)
+static inline u32 admhc_read_portstatus(struct admhcd *ahcd, int port)
{
return admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
}
+static inline void admhc_write_portstatus(struct admhcd *ahcd, int port,
+ u32 value)
+{
+ admhc_writel(ahcd, value, &ahcd->regs->portstatus[port]);
+}
+
static inline void roothub_write_status(struct admhcd *ahcd, u32 value)
{
/* FIXME: read-only bits must be masked out */
t |= ADMHC_HC_DMAE;
admhc_writel(ahcd, t, &ahcd->regs->host_control);
- admhc_vdbg(ahcd,"DMA enabled\n");
+ admhc_vdbg(ahcd, "DMA enabled\n");
}
static inline void admhc_dma_disable(struct admhcd *ahcd)
t &= ~ADMHC_HC_DMAE;
admhc_writel(ahcd, t, &ahcd->regs->host_control);
- admhc_vdbg(ahcd,"DMA disabled\n");
+ admhc_vdbg(ahcd, "DMA disabled\n");
}
projects / 15.05 / openwrt.git / blobdiff