target/linux/xburst/patches-2.6.37/200-udc.patch

   1 From f39709ba061049463b1a607369e476512da9ec5b Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 24 Apr 2010 12:18:46 +0200
   4 Subject: [PATCH 02/23] Add jz4740 udc driver
   5
   6 ---
   7  drivers/usb/gadget/Kconfig        |   14 +
   8  drivers/usb/gadget/Makefile       |    1 +
   9  drivers/usb/gadget/gadget_chips.h |    9 +
  10  drivers/usb/gadget/jz4740_udc.c   | 2378 +++++++++++++++++++++++++++++++++++++
  11  drivers/usb/gadget/jz4740_udc.h   |  101 ++
  12  5 files changed, 2503 insertions(+), 0 deletions(-)
  13  create mode 100644 drivers/usb/gadget/jz4740_udc.c
  14  create mode 100644 drivers/usb/gadget/jz4740_udc.h
  15
  16 --- a/drivers/usb/gadget/Kconfig
  17 +++ b/drivers/usb/gadget/Kconfig
  18 @@ -121,11 +121,25 @@ choice
  19  #
  20  # Integrated controllers
  21  #
  22 +config USB_GADGET_JZ4740
  23 +       boolean "JZ4740 UDC"
  24 +       depends on MACH_JZ4740
  25 +       select USB_GADGET_SELECTED
  26 +       select USB_GADGET_DUALSPEED
  27 +       help
  28 +          Select this to support the Ingenic JZ4740 processor
  29 +           high speed USB device controller.
  30 +
  31 +config USB_JZ4740
  32 +       tristate
  33 +       depends on USB_GADGET_JZ4740
  34 +       default USB_GADGET
  35
  36  config USB_GADGET_AT91
  37         boolean "Atmel AT91 USB Device Port"
  38         depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9 && !ARCH_AT91SAM9G45
  39         select USB_GADGET_SELECTED
  40 +
  41         help
  42            Many Atmel AT91 processors (such as the AT91RM2000) have a
  43            full speed USB Device Port with support for five configurable
  44 --- a/drivers/usb/gadget/Makefile
  45 +++ b/drivers/usb/gadget/Makefile
  46 @@ -24,6 +24,7 @@ obj-$(CONFIG_USB_FSL_QE)      += fsl_qe_udc.o
  47  obj-$(CONFIG_USB_CI13XXX)      += ci13xxx_udc.o
  48  obj-$(CONFIG_USB_S3C_HSOTG)    += s3c-hsotg.o
  49  obj-$(CONFIG_USB_LANGWELL)     += langwell_udc.o
  50 +obj-$(CONFIG_USB_JZ4740)       += jz4740_udc.o
  51
  52  #
  53  # USB gadget drivers
  54 --- a/drivers/usb/gadget/gadget_chips.h
  55 +++ b/drivers/usb/gadget/gadget_chips.h
  56 @@ -15,6 +15,12 @@
  57  #ifndef __GADGET_CHIPS_H
  58  #define __GADGET_CHIPS_H
  59
  60 +#ifdef CONFIG_USB_GADGET_JZ4740
  61 +#define        gadget_is_jz4740(g)     !strcmp("ingenic_hsusb", (g)->name)
  62 +#else
  63 +#define        gadget_is_jz4740(g)     0
  64 +#endif
  65 +
  66  #ifdef CONFIG_USB_GADGET_NET2280
  67  #define        gadget_is_net2280(g)    !strcmp("net2280", (g)->name)
  68  #else
  69 @@ -200,6 +206,9 @@ static inline int usb_gadget_controller_
  70                 return 0x25;
  71         else if (gadget_is_s3c_hsotg(gadget))
  72                 return 0x26;
  73 +       else if (gadget_is_jz4740(gadget))
  74 +               return 0x27;
  75 +
  76         return -ENOENT;
  77  }
  78
  79 --- /dev/null
  80 +++ b/drivers/usb/gadget/jz4740_udc.c
  81 @@ -0,0 +1,2378 @@
  82 +/*
  83 + * linux/drivers/usb/gadget/jz4740_udc.c
  84 + *
  85 + * Ingenic JZ4740 on-chip high speed USB device controller
  86 + *
  87 + * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
  88 + * Author: <jlwei@ingenic.cn>
  89 + *
  90 + * This program is free software; you can redistribute it and/or modify
  91 + * it under the terms of the GNU General Public License as published by
  92 + * the Free Software Foundation; either version 2 of the License, or
  93 + * (at your option) any later version.
  94 + */
  95 +
  96 +/*
  97 + * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
  98 + *
  99 + *  - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
 100 + *  - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
 101 + */
 102 +
 103 +#include <linux/kernel.h>
 104 +#include <linux/module.h>
 105 +#include <linux/platform_device.h>
 106 +#include <linux/delay.h>
 107 +#include <linux/ioport.h>
 108 +#include <linux/slab.h>
 109 +#include <linux/errno.h>
 110 +#include <linux/init.h>
 111 +#include <linux/list.h>
 112 +#include <linux/interrupt.h>
 113 +#include <linux/proc_fs.h>
 114 +#include <linux/usb.h>
 115 +#include <linux/usb/gadget.h>
 116 +#include <linux/clk.h>
 117 +
 118 +#include <asm/byteorder.h>
 119 +#include <asm/io.h>
 120 +#include <asm/irq.h>
 121 +#include <asm/system.h>
 122 +#include <asm/mach-jz4740/clock.h>
 123 +
 124 +#include "jz4740_udc.h"
 125 +
 126 +#define JZ_REG_UDC_FADDR       0x00 /* Function Address 8-bit */
 127 +#define JZ_REG_UDC_POWER       0x01 /* Power Management 8-bit */
 128 +#define JZ_REG_UDC_INTRIN      0x02 /* Interrupt IN 16-bit */
 129 +#define JZ_REG_UDC_INTROUT     0x04 /* Interrupt OUT 16-bit */
 130 +#define JZ_REG_UDC_INTRINE     0x06 /* Intr IN enable 16-bit */
 131 +#define JZ_REG_UDC_INTROUTE    0x08 /* Intr OUT enable 16-bit */
 132 +#define JZ_REG_UDC_INTRUSB     0x0a /* Interrupt USB 8-bit */
 133 +#define JZ_REG_UDC_INTRUSBE    0x0b /* Interrupt USB Enable 8-bit */
 134 +#define JZ_REG_UDC_FRAME       0x0c /* Frame number 16-bit */
 135 +#define JZ_REG_UDC_INDEX       0x0e /* Index register 8-bit */
 136 +#define JZ_REG_UDC_TESTMODE    0x0f /* USB test mode 8-bit */
 137 +
 138 +#define JZ_REG_UDC_CSR0                0x12 /* EP0 CSR 8-bit */
 139 +#define JZ_REG_UDC_INMAXP      0x10 /* EP1-2 IN Max Pkt Size 16-bit */
 140 +#define JZ_REG_UDC_INCSR       0x12 /* EP1-2 IN CSR LSB 8/16bit */
 141 +#define JZ_REG_UDC_INCSRH      0x13 /* EP1-2 IN CSR MSB 8-bit */
 142 +#define JZ_REG_UDC_OUTMAXP     0x14 /* EP1 OUT Max Pkt Size 16-bit */
 143 +#define JZ_REG_UDC_OUTCSR      0x16 /* EP1 OUT CSR LSB 8/16bit */
 144 +#define JZ_REG_UDC_OUTCSRH     0x17 /* EP1 OUT CSR MSB 8-bit */
 145 +#define JZ_REG_UDC_OUTCOUNT    0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
 146 +
 147 +#define JZ_REG_UDC_EP_FIFO(x)  (4 * (x) + 0x20)
 148 +
 149 +#define JZ_REG_UDC_EPINFO      0x78 /* Endpoint information */
 150 +#define JZ_REG_UDC_RAMINFO     0x79 /* RAM information */
 151 +
 152 +#define JZ_REG_UDC_INTR                0x200 /* DMA pending interrupts */
 153 +#define JZ_REG_UDC_CNTL1       0x204 /* DMA channel 1 control */
 154 +#define JZ_REG_UDC_ADDR1       0x208 /* DMA channel 1 AHB memory addr */
 155 +#define JZ_REG_UDC_COUNT1      0x20c /* DMA channel 1 byte count */
 156 +#define JZ_REG_UDC_CNTL2       0x214 /* DMA channel 2 control */
 157 +#define JZ_REG_UDC_ADDR2       0x218 /* DMA channel 2 AHB memory addr */
 158 +#define JZ_REG_UDC_COUNT2      0x21c /* DMA channel 2 byte count */
 159 +
 160 +/* Power register bit masks */
 161 +#define USB_POWER_SUSPENDM     0x01
 162 +#define USB_POWER_RESUME       0x04
 163 +#define USB_POWER_HSMODE       0x10
 164 +#define USB_POWER_HSENAB       0x20
 165 +#define USB_POWER_SOFTCONN     0x40
 166 +
 167 +/* Interrupt register bit masks */
 168 +#define USB_INTR_SUSPEND       0x01
 169 +#define USB_INTR_RESUME                0x02
 170 +#define USB_INTR_RESET         0x04
 171 +
 172 +#define USB_INTR_EP0           0x0001
 173 +#define USB_INTR_INEP1         0x0002
 174 +#define USB_INTR_INEP2         0x0004
 175 +#define USB_INTR_OUTEP1                0x0002
 176 +
 177 +/* CSR0 bit masks */
 178 +#define USB_CSR0_OUTPKTRDY     0x01
 179 +#define USB_CSR0_INPKTRDY      0x02
 180 +#define USB_CSR0_SENTSTALL     0x04
 181 +#define USB_CSR0_DATAEND       0x08
 182 +#define USB_CSR0_SETUPEND      0x10
 183 +#define USB_CSR0_SENDSTALL     0x20
 184 +#define USB_CSR0_SVDOUTPKTRDY  0x40
 185 +#define USB_CSR0_SVDSETUPEND   0x80
 186 +
 187 +/* Endpoint CSR register bits */
 188 +#define USB_INCSRH_AUTOSET     0x80
 189 +#define USB_INCSRH_ISO         0x40
 190 +#define USB_INCSRH_MODE                0x20
 191 +#define USB_INCSRH_DMAREQENAB  0x10
 192 +#define USB_INCSRH_DMAREQMODE  0x04
 193 +#define USB_INCSR_CDT          0x40
 194 +#define USB_INCSR_SENTSTALL    0x20
 195 +#define USB_INCSR_SENDSTALL    0x10
 196 +#define USB_INCSR_FF           0x08
 197 +#define USB_INCSR_UNDERRUN     0x04
 198 +#define USB_INCSR_FFNOTEMPT    0x02
 199 +#define USB_INCSR_INPKTRDY     0x01
 200 +#define USB_OUTCSRH_AUTOCLR    0x80
 201 +#define USB_OUTCSRH_ISO                0x40
 202 +#define USB_OUTCSRH_DMAREQENAB 0x20
 203 +#define USB_OUTCSRH_DNYT       0x10
 204 +#define USB_OUTCSRH_DMAREQMODE 0x08
 205 +#define USB_OUTCSR_CDT         0x80
 206 +#define USB_OUTCSR_SENTSTALL   0x40
 207 +#define USB_OUTCSR_SENDSTALL   0x20
 208 +#define USB_OUTCSR_FF          0x10
 209 +#define USB_OUTCSR_DATAERR     0x08
 210 +#define USB_OUTCSR_OVERRUN     0x04
 211 +#define USB_OUTCSR_FFFULL      0x02
 212 +#define USB_OUTCSR_OUTPKTRDY   0x01
 213 +
 214 +/* DMA control bits */
 215 +#define USB_CNTL_ENA           0x01
 216 +#define USB_CNTL_DIR_IN                0x02
 217 +#define USB_CNTL_MODE_1                0x04
 218 +#define USB_CNTL_INTR_EN       0x08
 219 +#define USB_CNTL_EP(n)         ((n) << 4)
 220 +#define USB_CNTL_BURST_0       (0 << 9)
 221 +#define USB_CNTL_BURST_4       (1 << 9)
 222 +#define USB_CNTL_BURST_8       (2 << 9)
 223 +#define USB_CNTL_BURST_16      (3 << 9)
 224 +
 225 +
 226 +#ifndef DEBUG
 227 +# define DEBUG(fmt,args...) do {} while(0)
 228 +#endif
 229 +#ifndef DEBUG_EP0
 230 +# define NO_STATES
 231 +# define DEBUG_EP0(fmt,args...) do {} while(0)
 232 +#endif
 233 +#ifndef DEBUG_SETUP
 234 +# define DEBUG_SETUP(fmt,args...) do {} while(0)
 235 +#endif
 236 +
 237 +static unsigned int use_dma = 0;   /* 1: use DMA, 0: use PIO */
 238 +
 239 +module_param(use_dma, int, 0);
 240 +MODULE_PARM_DESC(use_dma, "DMA mode enable flag");
 241 +
 242 +static struct jz4740_udc jz4740_udc_controller;
 243 +
 244 +/*
 245 + * Local declarations.
 246 + */
 247 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
 248 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
 249 +
 250 +static void done(struct jz4740_ep *ep, struct jz4740_request *req,
 251 +                int status);
 252 +static void pio_irq_enable(struct jz4740_ep *ep);
 253 +static void pio_irq_disable(struct jz4740_ep *ep);
 254 +static void stop_activity(struct jz4740_udc *dev,
 255 +                         struct usb_gadget_driver *driver);
 256 +static void nuke(struct jz4740_ep *ep, int status);
 257 +static void flush(struct jz4740_ep *ep);
 258 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
 259 +
 260 +/*-------------------------------------------------------------------------*/
 261 +
 262 +/* inline functions of register read/write/set/clear  */
 263 +
 264 +static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
 265 +{
 266 +       return readb(udc->base + reg);
 267 +}
 268 +
 269 +static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
 270 +{
 271 +       return readw(udc->base + reg);
 272 +}
 273 +
 274 +static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
 275 +{
 276 +       return readl(udc->base + reg);
 277 +}
 278 +
 279 +static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
 280 +{
 281 +       writeb(val, udc->base + reg);
 282 +}
 283 +
 284 +static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
 285 +{
 286 +       writew(val, udc->base + reg);
 287 +}
 288 +
 289 +static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
 290 +{
 291 +       writel(val, udc->base + reg);
 292 +}
 293 +
 294 +static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
 295 +{
 296 +       usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
 297 +}
 298 +
 299 +static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask)
 300 +{
 301 +       usb_writew(udc, reg, usb_readw(udc, reg) | mask);
 302 +}
 303 +
 304 +static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
 305 +{
 306 +       usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
 307 +}
 308 +
 309 +static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
 310 +{
 311 +       usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
 312 +}
 313 +
 314 +/*-------------------------------------------------------------------------*/
 315 +
 316 +static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
 317 +{
 318 +       usb_writeb(udc, JZ_REG_UDC_INDEX, index);
 319 +}
 320 +
 321 +static inline void jz_udc_select_ep(struct jz4740_ep *ep)
 322 +{
 323 +       jz_udc_set_index(ep->dev, ep_index(ep));
 324 +}
 325 +
 326 +static inline int write_packet(struct jz4740_ep *ep,
 327 +                                  struct jz4740_request *req, unsigned int count)
 328 +{
 329 +       uint8_t *buf;
 330 +       unsigned int length, nlong, nbyte;
 331 +       void __iomem *fifo = ep->dev->base + ep->fifo;
 332 +
 333 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 334 +
 335 +       buf = req->req.buf + req->req.actual;
 336 +       prefetch(buf);
 337 +
 338 +       length = req->req.length - req->req.actual;
 339 +       if (length > count)
 340 +               length = count;
 341 +       req->req.actual += length;
 342 +
 343 +       DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo);
 344 +
 345 +       nlong = length >> 2;
 346 +       nbyte = length & 0x3;
 347 +       while (nlong--) {
 348 +               writel(*((uint32_t *)buf), fifo);
 349 +               buf += 4;
 350 +       }
 351 +       while (nbyte--)
 352 +               writeb(*buf++, fifo);
 353 +
 354 +       return length;
 355 +}
 356 +
 357 +static int read_packet(struct jz4740_ep *ep,
 358 +                                 struct jz4740_request *req, unsigned int count)
 359 +{
 360 +       uint8_t *buf;
 361 +       unsigned int length, nlong, nbyte;
 362 +       void __iomem *fifo = ep->dev->base + ep->fifo;
 363 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 364 +
 365 +       buf = req->req.buf + req->req.actual;
 366 +       prefetchw(buf);
 367 +
 368 +       length = req->req.length - req->req.actual;
 369 +       if (length > count)
 370 +               length = count;
 371 +       req->req.actual += length;
 372 +
 373 +       DEBUG("Read %d, fifo %x\n", length, ep->fifo);
 374 +       nlong = length >> 2;
 375 +       nbyte = length & 0x3;
 376 +       while (nlong--) {
 377 +               *((uint32_t *)buf) = readl(fifo);
 378 +               buf += 4;
 379 +       }
 380 +       while (nbyte--)
 381 +               *buf++ = readb(fifo);
 382 +
 383 +       return length;
 384 +}
 385 +
 386 +/*-------------------------------------------------------------------------*/
 387 +
 388 +/*
 389 + *     udc_disable - disable USB device controller
 390 + */
 391 +static void udc_disable(struct jz4740_udc *dev)
 392 +{
 393 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 394 +
 395 +       udc_set_address(dev, 0);
 396 +
 397 +       /* Disable interrupts */
 398 +       usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
 399 +       usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
 400 +       usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
 401 +
 402 +       /* Disable DMA */
 403 +       usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
 404 +       usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
 405 +
 406 +       /* Disconnect from usb */
 407 +       usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
 408 +
 409 +       /* Disable the USB PHY */
 410 +       clk_disable(dev->clk);
 411 +
 412 +       dev->ep0state = WAIT_FOR_SETUP;
 413 +       dev->gadget.speed = USB_SPEED_UNKNOWN;
 414 +
 415 +       return;
 416 +}
 417 +
 418 +/*
 419 + *     udc_reinit - initialize software state
 420 + */
 421 +static void udc_reinit(struct jz4740_udc *dev)
 422 +{
 423 +       int i;
 424 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 425 +
 426 +       /* device/ep0 records init */
 427 +       INIT_LIST_HEAD(&dev->gadget.ep_list);
 428 +       INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
 429 +       dev->ep0state = WAIT_FOR_SETUP;
 430 +
 431 +       for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
 432 +               struct jz4740_ep *ep = &dev->ep[i];
 433 +
 434 +               if (i != 0)
 435 +                       list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
 436 +
 437 +               INIT_LIST_HEAD(&ep->queue);
 438 +               ep->desc = 0;
 439 +               ep->stopped = 0;
 440 +       }
 441 +}
 442 +
 443 +/* until it's enabled, this UDC should be completely invisible
 444 + * to any USB host.
 445 + */
 446 +static void udc_enable(struct jz4740_udc *dev)
 447 +{
 448 +       int i;
 449 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 450 +
 451 +       /* UDC state is incorrect - Added by River */
 452 +       if (dev->state != UDC_STATE_ENABLE) {
 453 +               return;
 454 +       }
 455 +
 456 +       dev->gadget.speed = USB_SPEED_UNKNOWN;
 457 +
 458 +       /* Flush FIFO for each */
 459 +       for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
 460 +               struct jz4740_ep *ep = &dev->ep[i];
 461 +
 462 +               jz_udc_set_index(dev, ep_index(ep));
 463 +               flush(ep);
 464 +       }
 465 +
 466 +       /* Set this bit to allow the UDC entering low-power mode when
 467 +        * there are no actions on the USB bus.
 468 +        * UDC still works during this bit was set.
 469 +        */
 470 +       jz4740_clock_udc_enable_auto_suspend();
 471 +
 472 +       /* Enable the USB PHY */
 473 +       clk_enable(dev->clk);
 474 +
 475 +       /* Disable interrupts */
 476 +/*     usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
 477 +       usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
 478 +       usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
 479 +
 480 +       /* Enable interrupts */
 481 +       usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
 482 +       usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
 483 +       /* Don't enable rest of the interrupts */
 484 +       /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
 485 +          usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
 486 +
 487 +       /* Enable SUSPEND */
 488 +       /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
 489 +
 490 +       /* Enable HS Mode */
 491 +       usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
 492 +
 493 +       /* Let host detect UDC:
 494 +        * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
 495 +        * transistor on and pull the USBDP pin HIGH.
 496 +        */
 497 +       usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
 498 +
 499 +       return;
 500 +}
 501 +
 502 +/*-------------------------------------------------------------------------*/
 503 +
 504 +/* keeping it simple:
 505 + * - one bus driver, initted first;
 506 + * - one function driver, initted second
 507 + */
 508 +
 509 +/*
 510 + * Register entry point for the peripheral controller driver.
 511 + */
 512 +
 513 +int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
 514 +               int (*bind)(struct usb_gadget *))
 515 +{
 516 +       struct jz4740_udc *dev = &jz4740_udc_controller;
 517 +       int retval;
 518 +
 519 +       if (!driver || !bind)
 520 +               return -EINVAL;
 521 +
 522 +       if (!dev)
 523 +               return -ENODEV;
 524 +
 525 +       if (dev->driver)
 526 +               return -EBUSY;
 527 +
 528 +       /* hook up the driver */
 529 +       dev->driver = driver;
 530 +       dev->gadget.dev.driver = &driver->driver;
 531 +
 532 +       retval = bind(&dev->gadget);
 533 +       if (retval) {
 534 +               DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
 535 +                           driver->driver.name, retval);
 536 +               dev->driver = 0;
 537 +               return retval;
 538 +       }
 539 +
 540 +       /* then enable host detection and ep0; and we're ready
 541 +        * for set_configuration as well as eventual disconnect.
 542 +        */
 543 +       udc_enable(dev);
 544 +
 545 +       DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
 546 +             driver->driver.name);
 547 +
 548 +       return 0;
 549 +}
 550 +EXPORT_SYMBOL(usb_gadget_probe_driver);
 551 +
 552 +static void stop_activity(struct jz4740_udc *dev,
 553 +                         struct usb_gadget_driver *driver)
 554 +{
 555 +       int i;
 556 +
 557 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 558 +
 559 +       /* don't disconnect drivers more than once */
 560 +       if (dev->gadget.speed == USB_SPEED_UNKNOWN)
 561 +               driver = 0;
 562 +       dev->gadget.speed = USB_SPEED_UNKNOWN;
 563 +
 564 +       /* prevent new request submissions, kill any outstanding requests  */
 565 +       for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
 566 +               struct jz4740_ep *ep = &dev->ep[i];
 567 +
 568 +               ep->stopped = 1;
 569 +
 570 +               jz_udc_set_index(dev, ep_index(ep));
 571 +               nuke(ep, -ESHUTDOWN);
 572 +       }
 573 +
 574 +       /* report disconnect; the driver is already quiesced */
 575 +       if (driver) {
 576 +               spin_unlock(&dev->lock);
 577 +               driver->disconnect(&dev->gadget);
 578 +               spin_lock(&dev->lock);
 579 +       }
 580 +
 581 +       /* re-init driver-visible data structures */
 582 +       udc_reinit(dev);
 583 +}
 584 +
 585 +
 586 +/*
 587 + * Unregister entry point for the peripheral controller driver.
 588 + */
 589 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
 590 +{
 591 +       struct jz4740_udc *dev = &jz4740_udc_controller;
 592 +       unsigned long flags;
 593 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 594 +
 595 +       if (!dev)
 596 +               return -ENODEV;
 597 +       if (!driver || driver != dev->driver)
 598 +               return -EINVAL;
 599 +       if (!driver->unbind)
 600 +               return -EBUSY;
 601 +
 602 +       spin_lock_irqsave(&dev->lock, flags);
 603 +       dev->driver = 0;
 604 +       stop_activity(dev, driver);
 605 +       spin_unlock_irqrestore(&dev->lock, flags);
 606 +
 607 +       driver->unbind(&dev->gadget);
 608 +
 609 +       udc_disable(dev);
 610 +
 611 +       DEBUG("unregistered driver '%s'\n", driver->driver.name);
 612 +
 613 +       return 0;
 614 +}
 615 +
 616 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
 617 +
 618 +/*-------------------------------------------------------------------------*/
 619 +
 620 +/*
 621 + * Starting DMA using mode 1
 622 + */
 623 +static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req)
 624 +{
 625 +       struct jz4740_udc *dev = ep->dev;
 626 +       uint32_t count = req->req.length;
 627 +       uint32_t physaddr = virt_to_phys((void *)req->req.buf);
 628 +
 629 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 630 +
 631 +       jz_udc_select_ep(ep);
 632 +
 633 +       if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */
 634 +               ep->reg_addr = JZ_REG_UDC_ADDR1;
 635 +
 636 +               dma_cache_wback_inv((unsigned long)req->req.buf, count);
 637 +
 638 +               pio_irq_enable(ep);
 639 +
 640 +               usb_writeb(dev, JZ_REG_UDC_INCSRH,
 641 +                          USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
 642 +
 643 +               usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr);
 644 +               usb_writel(dev, JZ_REG_UDC_COUNT1, count);
 645 +               usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 |
 646 +                          USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
 647 +       }
 648 +       else { /* Bulk-OUT transfer using DMA channel 2 */
 649 +               ep->reg_addr = JZ_REG_UDC_ADDR2;
 650 +
 651 +               dma_cache_wback_inv((unsigned long)req->req.buf, count);
 652 +
 653 +               pio_irq_enable(ep);
 654 +
 655 +               usb_setb(dev, JZ_REG_UDC_OUTCSRH,
 656 +                        USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
 657 +
 658 +               usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr);
 659 +               usb_writel(dev, JZ_REG_UDC_COUNT2, count);
 660 +               usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 |
 661 +                          USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
 662 +       }
 663 +}
 664 +
 665 +/*-------------------------------------------------------------------------*/
 666 +
 667 +/** Write request to FIFO (max write == maxp size)
 668 + *  Return:  0 = still running, 1 = completed, negative = errno
 669 + *  NOTE: INDEX register must be set for EP
 670 + */
 671 +static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
 672 +{
 673 +       struct jz4740_udc *dev = ep->dev;
 674 +       uint32_t max, csr;
 675 +       uint32_t physaddr = virt_to_phys((void *)req->req.buf);
 676 +
 677 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 678 +       max = le16_to_cpu(ep->desc->wMaxPacketSize);
 679 +
 680 +       if (use_dma) {
 681 +               uint32_t dma_count;
 682 +
 683 +               /* DMA interrupt generated due to the last packet loaded into the FIFO */
 684 +
 685 +               dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
 686 +               req->req.actual += dma_count;
 687 +
 688 +               if (dma_count % max) {
 689 +                       /* If the last packet is less than MAXP, set INPKTRDY manually */
 690 +                       usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
 691 +               }
 692 +
 693 +               done(ep, req, 0);
 694 +               if (list_empty(&ep->queue)) {
 695 +                       pio_irq_disable(ep);
 696 +                       return 1;
 697 +               }
 698 +               else {
 699 +                       /* advance the request queue */
 700 +                       req = list_entry(ep->queue.next, struct jz4740_request, queue);
 701 +                       kick_dma(ep, req);
 702 +                       return 0;
 703 +               }
 704 +       }
 705 +
 706 +       /*
 707 +        * PIO mode handling starts here ...
 708 +        */
 709 +
 710 +       csr = usb_readb(dev, ep->csr);
 711 +
 712 +       if (!(csr & USB_INCSR_FFNOTEMPT)) {
 713 +               unsigned count;
 714 +               int is_last, is_short;
 715 +
 716 +               count = write_packet(ep, req, max);
 717 +               usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
 718 +
 719 +               /* last packet is usually short (or a zlp) */
 720 +               if (unlikely(count != max))
 721 +                       is_last = is_short = 1;
 722 +               else {
 723 +                       if (likely(req->req.length != req->req.actual)
 724 +                           || req->req.zero)
 725 +                               is_last = 0;
 726 +                       else
 727 +                               is_last = 1;
 728 +                       /* interrupt/iso maxpacket may not fill the fifo */
 729 +                       is_short = unlikely(max < ep_maxpacket(ep));
 730 +               }
 731 +
 732 +               DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
 733 +                     ep->ep.name, count,
 734 +                     is_last ? "/L" : "", is_short ? "/S" : "",
 735 +                     req->req.length - req->req.actual, req);
 736 +
 737 +               /* requests complete when all IN data is in the FIFO */
 738 +               if (is_last) {
 739 +                       done(ep, req, 0);
 740 +                       if (list_empty(&ep->queue)) {
 741 +                               pio_irq_disable(ep);
 742 +                       }
 743 +                       return 1;
 744 +               }
 745 +       } else {
 746 +               DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
 747 +       }
 748 +
 749 +       return 0;
 750 +}
 751 +
 752 +/** Read to request from FIFO (max read == bytes in fifo)
 753 + *  Return:  0 = still running, 1 = completed, negative = errno
 754 + *  NOTE: INDEX register must be set for EP
 755 + */
 756 +static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
 757 +{
 758 +       struct jz4740_udc *dev = ep->dev;
 759 +       uint32_t csr;
 760 +       unsigned count, is_short;
 761 +
 762 +#if 0
 763 +       uint32_t physaddr = virt_to_phys((void *)req->req.buf);
 764 +
 765 +       if (use_dma) {
 766 +               uint32_t dma_count;
 767 +
 768 +               /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */
 769 +
 770 +               dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
 771 +               req->req.actual += dma_count;
 772 +
 773 +               /* Disable interrupt and DMA */
 774 +               pio_irq_disable(ep);
 775 +               usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
 776 +
 777 +               /* Read all bytes from this packet */
 778 +               count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
 779 +               count = read_packet(ep, req, count);
 780 +
 781 +               if (count) {
 782 +                       /* If the last packet is greater than zero, clear OUTPKTRDY manually */
 783 +                       usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
 784 +               }
 785 +               done(ep, req, 0);
 786 +
 787 +               if (!list_empty(&ep->queue)) {
 788 +                       /* advance the request queue */
 789 +                       req = list_entry(ep->queue.next, struct jz4740_request, queue);
 790 +                       kick_dma(ep, req);
 791 +               }
 792 +
 793 +               return 1;
 794 +       }
 795 +#endif
 796 +       /*
 797 +        * PIO mode handling starts here ...
 798 +        */
 799 +
 800 +       /* make sure there's a packet in the FIFO. */
 801 +       csr = usb_readb(dev, ep->csr);
 802 +       if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
 803 +               DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
 804 +               return -EINVAL;
 805 +       }
 806 +
 807 +       /* read all bytes from this packet */
 808 +       count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
 809 +
 810 +       is_short = (count < ep->ep.maxpacket);
 811 +
 812 +       count = read_packet(ep, req, count);
 813 +
 814 +       DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
 815 +             ep->ep.name, csr, count,
 816 +             is_short ? "/S" : "", req, req->req.actual, req->req.length);
 817 +
 818 +       /* Clear OutPktRdy */
 819 +       usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
 820 +
 821 +       /* completion */
 822 +       if (is_short || req->req.actual == req->req.length) {
 823 +               done(ep, req, 0);
 824 +
 825 +               if (list_empty(&ep->queue))
 826 +                       pio_irq_disable(ep);
 827 +               return 1;
 828 +       }
 829 +
 830 +       /* finished that packet.  the next one may be waiting... */
 831 +       return 0;
 832 +}
 833 +
 834 +/*
 835 + *     done - retire a request; caller blocked irqs
 836 + *  INDEX register is preserved to keep same
 837 + */
 838 +static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
 839 +{
 840 +       unsigned int stopped = ep->stopped;
 841 +       uint32_t index;
 842 +
 843 +       DEBUG("%s, %p\n", __FUNCTION__, ep);
 844 +       list_del_init(&req->queue);
 845 +
 846 +       if (likely(req->req.status == -EINPROGRESS))
 847 +               req->req.status = status;
 848 +       else
 849 +               status = req->req.status;
 850 +
 851 +       if (status && status != -ESHUTDOWN)
 852 +               DEBUG("complete %s req %p stat %d len %u/%u\n",
 853 +                     ep->ep.name, &req->req, status,
 854 +                     req->req.actual, req->req.length);
 855 +
 856 +       /* don't modify queue heads during completion callback */
 857 +       ep->stopped = 1;
 858 +       /* Read current index (completion may modify it) */
 859 +       index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
 860 +       spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
 861 +
 862 +       req->req.complete(&ep->ep, &req->req);
 863 +
 864 +       spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
 865 +       /* Restore index */
 866 +       jz_udc_set_index(ep->dev, index);
 867 +       ep->stopped = stopped;
 868 +}
 869 +
 870 +/** Enable EP interrupt */
 871 +static void pio_irq_enable(struct jz4740_ep *ep)
 872 +{
 873 +       uint8_t index = ep_index(ep);
 874 +       struct jz4740_udc *dev = ep->dev;
 875 +       DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
 876 +
 877 +       if (ep_is_in(ep)) {
 878 +               switch (index) {
 879 +               case 1:
 880 +               case 2:
 881 +                       usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index));
 882 +                       break;
 883 +               default:
 884 +                       DEBUG("Unknown endpoint: %d\n", index);
 885 +                       break;
 886 +               }
 887 +       }
 888 +       else {
 889 +               switch (index) {
 890 +               case 1:
 891 +                       usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index));
 892 +                       break;
 893 +               default:
 894 +                       DEBUG("Unknown endpoint: %d\n", index);
 895 +                       break;
 896 +               }
 897 +       }
 898 +}
 899 +
 900 +/** Disable EP interrupt */
 901 +static void pio_irq_disable(struct jz4740_ep *ep)
 902 +{
 903 +       uint8_t index = ep_index(ep);
 904 +
 905 +       DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
 906 +
 907 +       if (ep_is_in(ep)) {
 908 +               switch (ep_index(ep)) {
 909 +               case 1:
 910 +               case 2:
 911 +                       usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index));
 912 +                       break;
 913 +               default:
 914 +                       DEBUG("Unknown endpoint: %d\n", index);
 915 +                       break;
 916 +               }
 917 +       }
 918 +       else {
 919 +               switch (ep_index(ep)) {
 920 +               case 1:
 921 +                       usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index));
 922 +                       break;
 923 +               default:
 924 +                       DEBUG("Unknown endpoint: %d\n", index);
 925 +                       break;
 926 +           }
 927 +       }
 928 +}
 929 +
 930 +/*
 931 + *     nuke - dequeue ALL requests
 932 + */
 933 +static void nuke(struct jz4740_ep *ep, int status)
 934 +{
 935 +       struct jz4740_request *req;
 936 +
 937 +       DEBUG("%s, %p\n", __FUNCTION__, ep);
 938 +
 939 +       /* Flush FIFO */
 940 +       flush(ep);
 941 +
 942 +       /* called with irqs blocked */
 943 +       while (!list_empty(&ep->queue)) {
 944 +               req = list_entry(ep->queue.next, struct jz4740_request, queue);
 945 +               done(ep, req, status);
 946 +       }
 947 +
 948 +       /* Disable IRQ if EP is enabled (has descriptor) */
 949 +       if (ep->desc)
 950 +               pio_irq_disable(ep);
 951 +}
 952 +
 953 +/** Flush EP FIFO
 954 + * NOTE: INDEX register must be set before this call
 955 + */
 956 +static void flush(struct jz4740_ep *ep)
 957 +{
 958 +       DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
 959 +
 960 +       switch (ep->type) {
 961 +       case ep_bulk_in:
 962 +       case ep_interrupt:
 963 +               usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
 964 +               break;
 965 +       case ep_bulk_out:
 966 +               usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
 967 +               break;
 968 +       case ep_control:
 969 +               break;
 970 +       }
 971 +}
 972 +
 973 +/**
 974 + * jz4740_in_epn - handle IN interrupt
 975 + */
 976 +static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
 977 +{
 978 +       uint32_t csr;
 979 +       struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
 980 +       struct jz4740_request *req;
 981 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 982 +
 983 +       jz_udc_set_index(dev, ep_index(ep));
 984 +
 985 +       csr = usb_readb(dev, ep->csr);
 986 +       DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
 987 +
 988 +       if (csr & USB_INCSR_SENTSTALL) {
 989 +               DEBUG("USB_INCSR_SENTSTALL\n");
 990 +               usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
 991 +               return;
 992 +       }
 993 +
 994 +       if (!ep->desc) {
 995 +               DEBUG("%s: NO EP DESC\n", __FUNCTION__);
 996 +               return;
 997 +       }
 998 +
 999 +       if (!list_empty(&ep->queue)) {
1000 +               req = list_first_entry(&ep->queue, struct jz4740_request, queue);
1001 +               write_fifo(ep, req);
1002 +       }
1003 +}
1004 +
1005 +/*
1006 + * Bulk OUT (recv)
1007 + */
1008 +static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
1009 +{
1010 +       struct jz4740_ep *ep = &dev->ep[ep_idx];
1011 +       struct jz4740_request *req;
1012 +
1013 +       DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
1014 +
1015 +       jz_udc_select_ep(ep);
1016 +       if (ep->desc) {
1017 +               uint32_t csr;
1018 +
1019 +               if (use_dma) {
1020 +                       /* DMA starts here ... */
1021 +                       if (!list_empty(&ep->queue)) {
1022 +                               req = list_first_entry(&ep->queue, struct jz4740_request, queue);
1023 +                               read_fifo(ep, req);
1024 +                       }
1025 +                       return;
1026 +               }
1027 +
1028 +               /*
1029 +                * PIO mode starts here ...
1030 +                */
1031 +
1032 +               while ((csr = usb_readb(dev, ep->csr)) &
1033 +                      (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
1034 +                       DEBUG("%s: %x\n", __FUNCTION__, csr);
1035 +
1036 +                       if (csr & USB_OUTCSR_SENTSTALL) {
1037 +                               DEBUG("%s: stall sent, flush fifo\n",
1038 +                                     __FUNCTION__);
1039 +                               /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
1040 +                               flush(ep);
1041 +                       } else if (csr & USB_OUTCSR_OUTPKTRDY) {
1042 +                               if (list_empty(&ep->queue))
1043 +                                       req = 0;
1044 +                               else
1045 +                                       req =
1046 +                                               list_entry(ep->queue.next,
1047 +                                                          struct jz4740_request,
1048 +                                                          queue);
1049 +
1050 +                               if (!req) {
1051 +                                       DEBUG("%s: NULL REQ %d\n",
1052 +                                             __FUNCTION__, ep_idx);
1053 +                                       break;
1054 +                               } else {
1055 +                                       read_fifo(ep, req);
1056 +                               }
1057 +                       }
1058 +               }
1059 +       } else {
1060 +               /* Throw packet away.. */
1061 +               DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
1062 +               flush(ep);
1063 +       }
1064 +}
1065 +
1066 +/** Halt specific EP
1067 + *  Return 0 if success
1068 + *  NOTE: Sets INDEX register to EP !
1069 + */
1070 +static int jz4740_set_halt(struct usb_ep *_ep, int value)
1071 +{
1072 +       struct jz4740_udc *dev;
1073 +       struct jz4740_ep *ep;
1074 +       unsigned long flags;
1075 +
1076 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1077 +
1078 +       ep = container_of(_ep, struct jz4740_ep, ep);
1079 +       if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1080 +               DEBUG("%s, bad ep\n", __FUNCTION__);
1081 +               return -EINVAL;
1082 +       }
1083 +
1084 +       dev = ep->dev;
1085 +
1086 +       spin_lock_irqsave(&dev->lock, flags);
1087 +
1088 +       jz_udc_select_ep(ep);
1089 +
1090 +       DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
1091 +
1092 +       if (ep_index(ep) == 0) {
1093 +               /* EP0 */
1094 +               usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
1095 +       } else if (ep_is_in(ep)) {
1096 +               uint32_t csr = usb_readb(dev, ep->csr);
1097 +               if (value && ((csr & USB_INCSR_FFNOTEMPT)
1098 +                             || !list_empty(&ep->queue))) {
1099 +                       /*
1100 +                        * Attempts to halt IN endpoints will fail (returning -EAGAIN)
1101 +                        * if any transfer requests are still queued, or if the controller
1102 +                        * FIFO still holds bytes that the host hasn\92t collected.
1103 +                        */
1104 +                       spin_unlock_irqrestore(&dev->lock, flags);
1105 +                       DEBUG
1106 +                           ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
1107 +                            (csr & USB_INCSR_FFNOTEMPT),
1108 +                            !list_empty(&ep->queue));
1109 +                       return -EAGAIN;
1110 +               }
1111 +               flush(ep);
1112 +               if (value) {
1113 +                       usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
1114 +               } else {
1115 +                       usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
1116 +                       usb_setb(dev, ep->csr, USB_INCSR_CDT);
1117 +               }
1118 +       } else {
1119 +
1120 +               flush(ep);
1121 +               if (value) {
1122 +                       usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1123 +               } else {
1124 +                       usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1125 +                       usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
1126 +               }
1127 +       }
1128 +
1129 +       ep->stopped = value;
1130 +
1131 +       spin_unlock_irqrestore(&dev->lock, flags);
1132 +
1133 +       DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
1134 +
1135 +       return 0;
1136 +}
1137 +
1138 +
1139 +static int jz4740_ep_enable(struct usb_ep *_ep,
1140 +                           const struct usb_endpoint_descriptor *desc)
1141 +{
1142 +       struct jz4740_ep *ep;
1143 +       struct jz4740_udc *dev;
1144 +       unsigned long flags;
1145 +       uint32_t max, csrh = 0;
1146 +
1147 +       DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
1148 +
1149 +       if (!_ep || !desc)
1150 +               return -EINVAL;
1151 +
1152 +       ep = container_of(_ep, struct jz4740_ep, ep);
1153 +       if (ep->desc || ep->type == ep_control
1154 +           || desc->bDescriptorType != USB_DT_ENDPOINT
1155 +           || ep->bEndpointAddress != desc->bEndpointAddress) {
1156 +               DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
1157 +               return -EINVAL;
1158 +       }
1159 +
1160 +       /* xfer types must match, except that interrupt ~= bulk */
1161 +       if (ep->bmAttributes != desc->bmAttributes
1162 +           && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
1163 +           && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
1164 +               DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
1165 +               return -EINVAL;
1166 +       }
1167 +
1168 +       dev = ep->dev;
1169 +       if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
1170 +               DEBUG("%s, bogus device state\n", __FUNCTION__);
1171 +               return -ESHUTDOWN;
1172 +       }
1173 +
1174 +       max = le16_to_cpu(desc->wMaxPacketSize);
1175 +
1176 +       spin_lock_irqsave(&ep->dev->lock, flags);
1177 +
1178 +       /* Configure the endpoint */
1179 +       jz_udc_select_ep(ep);
1180 +       if (ep_is_in(ep)) {
1181 +               usb_writew(dev, JZ_REG_UDC_INMAXP, max);
1182 +               switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1183 +               case USB_ENDPOINT_XFER_BULK:
1184 +               case USB_ENDPOINT_XFER_INT:
1185 +                       csrh &= ~USB_INCSRH_ISO;
1186 +                       break;
1187 +               case USB_ENDPOINT_XFER_ISOC:
1188 +                       csrh |= USB_INCSRH_ISO;
1189 +                       break;
1190 +               }
1191 +               usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1192 +       }
1193 +       else {
1194 +               usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1195 +               switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1196 +               case USB_ENDPOINT_XFER_BULK:
1197 +                        csrh &= ~USB_OUTCSRH_ISO;
1198 +                       break;
1199 +               case USB_ENDPOINT_XFER_INT:
1200 +                       csrh &= ~USB_OUTCSRH_ISO;
1201 +                       csrh |= USB_OUTCSRH_DNYT;
1202 +                       break;
1203 +               case USB_ENDPOINT_XFER_ISOC:
1204 +                       csrh |= USB_OUTCSRH_ISO;
1205 +                       break;
1206 +               }
1207 +               usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1208 +       }
1209 +
1210 +
1211 +       ep->stopped = 0;
1212 +       ep->desc = desc;
1213 +       ep->ep.maxpacket = max;
1214 +
1215 +       spin_unlock_irqrestore(&ep->dev->lock, flags);
1216 +
1217 +       /* Reset halt state (does flush) */
1218 +       jz4740_set_halt(_ep, 0);
1219 +
1220 +       DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1221 +
1222 +       return 0;
1223 +}
1224 +
1225 +/** Disable EP
1226 + *  NOTE: Sets INDEX register
1227 + */
1228 +static int jz4740_ep_disable(struct usb_ep *_ep)
1229 +{
1230 +       struct jz4740_ep *ep;
1231 +       unsigned long flags;
1232 +
1233 +       DEBUG("%s, %p\n", __FUNCTION__, _ep);
1234 +
1235 +       ep = container_of(_ep, struct jz4740_ep, ep);
1236 +       if (!_ep || !ep->desc) {
1237 +               DEBUG("%s, %s not enabled\n", __FUNCTION__,
1238 +                     _ep ? ep->ep.name : NULL);
1239 +               return -EINVAL;
1240 +       }
1241 +
1242 +       spin_lock_irqsave(&ep->dev->lock, flags);
1243 +
1244 +       jz_udc_select_ep(ep);
1245 +
1246 +       /* Nuke all pending requests (does flush) */
1247 +       nuke(ep, -ESHUTDOWN);
1248 +
1249 +       /* Disable ep IRQ */
1250 +       pio_irq_disable(ep);
1251 +
1252 +       ep->desc = 0;
1253 +       ep->stopped = 1;
1254 +
1255 +       spin_unlock_irqrestore(&ep->dev->lock, flags);
1256 +
1257 +       DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1258 +       return 0;
1259 +}
1260 +
1261 +static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1262 +{
1263 +       struct jz4740_request *req;
1264 +
1265 +       req = kzalloc(sizeof(*req), gfp_flags);
1266 +       if (!req)
1267 +               return NULL;
1268 +
1269 +       INIT_LIST_HEAD(&req->queue);
1270 +
1271 +       return &req->req;
1272 +}
1273 +
1274 +static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1275 +{
1276 +       struct jz4740_request *req;
1277 +
1278 +       DEBUG("%s, %p\n", __FUNCTION__, ep);
1279 +
1280 +       req = container_of(_req, struct jz4740_request, req);
1281 +       WARN_ON(!list_empty(&req->queue));
1282 +       kfree(req);
1283 +}
1284 +
1285 +/*--------------------------------------------------------------------*/
1286 +
1287 +/** Queue one request
1288 + *  Kickstart transfer if needed
1289 + *  NOTE: Sets INDEX register
1290 + */
1291 +static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1292 +                       gfp_t gfp_flags)
1293 +{
1294 +       struct jz4740_request *req;
1295 +       struct jz4740_ep *ep;
1296 +       struct jz4740_udc *dev;
1297 +
1298 +       DEBUG("%s, %p\n", __FUNCTION__, _ep);
1299 +
1300 +       req = container_of(_req, struct jz4740_request, req);
1301 +       if (unlikely
1302 +           (!_req || !_req->complete || !_req->buf
1303 +            || !list_empty(&req->queue))) {
1304 +               DEBUG("%s, bad params\n", __FUNCTION__);
1305 +               return -EINVAL;
1306 +       }
1307 +
1308 +       ep = container_of(_ep, struct jz4740_ep, ep);
1309 +       if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1310 +               DEBUG("%s, bad ep\n", __FUNCTION__);
1311 +               return -EINVAL;
1312 +       }
1313 +
1314 +       dev = ep->dev;
1315 +       if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1316 +               DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1317 +               return -ESHUTDOWN;
1318 +       }
1319 +
1320 +       DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1321 +             _req->buf);
1322 +
1323 +       spin_lock_irqsave(&dev->lock, dev->lock_flags);
1324 +
1325 +       _req->status = -EINPROGRESS;
1326 +       _req->actual = 0;
1327 +
1328 +       /* kickstart this i/o queue? */
1329 +       DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1330 +             ep->stopped);
1331 +       if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1332 +               uint32_t csr;
1333 +
1334 +               if (unlikely(ep_index(ep) == 0)) {
1335 +                       /* EP0 */
1336 +                       list_add_tail(&req->queue, &ep->queue);
1337 +                       jz4740_ep0_kick(dev, ep);
1338 +                       req = 0;
1339 +               } else if (use_dma) {
1340 +                       /* DMA */
1341 +                       kick_dma(ep, req);
1342 +               }
1343 +               /* PIO */
1344 +               else if (ep_is_in(ep)) {
1345 +                       /* EP1 & EP2 */
1346 +                       jz_udc_select_ep(ep);
1347 +                       csr = usb_readb(dev, ep->csr);
1348 +                       pio_irq_enable(ep);
1349 +                       if (!(csr & USB_INCSR_FFNOTEMPT)) {
1350 +                               if (write_fifo(ep, req) == 1)
1351 +                                       req = 0;
1352 +                       }
1353 +               } else {
1354 +                       /* EP1 */
1355 +                       jz_udc_select_ep(ep);
1356 +                       csr = usb_readb(dev, ep->csr);
1357 +                       pio_irq_enable(ep);
1358 +                       if (csr & USB_OUTCSR_OUTPKTRDY) {
1359 +                               if (read_fifo(ep, req) == 1)
1360 +                                       req = 0;
1361 +                       }
1362 +               }
1363 +       }
1364 +
1365 +       /* pio or dma irq handler advances the queue. */
1366 +       if (likely(req != 0))
1367 +               list_add_tail(&req->queue, &ep->queue);
1368 +
1369 +       spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1370 +
1371 +       return 0;
1372 +}
1373 +
1374 +/* dequeue JUST ONE request */
1375 +static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1376 +{
1377 +       struct jz4740_ep *ep;
1378 +       struct jz4740_request *req;
1379 +       unsigned long flags;
1380 +
1381 +       DEBUG("%s, %p\n", __FUNCTION__, _ep);
1382 +
1383 +       ep = container_of(_ep, struct jz4740_ep, ep);
1384 +       if (!_ep || ep->type == ep_control)
1385 +               return -EINVAL;
1386 +
1387 +       spin_lock_irqsave(&ep->dev->lock, flags);
1388 +
1389 +       /* make sure it's actually queued on this endpoint */
1390 +       list_for_each_entry(req, &ep->queue, queue) {
1391 +               if (&req->req == _req)
1392 +                       break;
1393 +       }
1394 +       if (&req->req != _req) {
1395 +               spin_unlock_irqrestore(&ep->dev->lock, flags);
1396 +               return -EINVAL;
1397 +       }
1398 +       done(ep, req, -ECONNRESET);
1399 +
1400 +       spin_unlock_irqrestore(&ep->dev->lock, flags);
1401 +       return 0;
1402 +}
1403 +
1404 +/** Return bytes in EP FIFO
1405 + *  NOTE: Sets INDEX register to EP
1406 + */
1407 +static int jz4740_fifo_status(struct usb_ep *_ep)
1408 +{
1409 +       uint32_t csr;
1410 +       int count = 0;
1411 +       struct jz4740_ep *ep;
1412 +       unsigned long flags;
1413 +
1414 +       ep = container_of(_ep, struct jz4740_ep, ep);
1415 +       if (!_ep) {
1416 +               DEBUG("%s, bad ep\n", __FUNCTION__);
1417 +               return -ENODEV;
1418 +       }
1419 +
1420 +       DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1421 +
1422 +       /* LPD can't report unclaimed bytes from IN fifos */
1423 +       if (ep_is_in(ep))
1424 +               return -EOPNOTSUPP;
1425 +
1426 +       spin_lock_irqsave(&ep->dev->lock, flags);
1427 +       jz_udc_select_ep(ep);
1428 +
1429 +       csr = usb_readb(ep->dev, ep->csr);
1430 +       if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1431 +           csr & 0x1) {
1432 +               count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1433 +       }
1434 +
1435 +       spin_unlock_irqrestore(&ep->dev->lock, flags);
1436 +
1437 +       return count;
1438 +}
1439 +
1440 +/** Flush EP FIFO
1441 + *  NOTE: Sets INDEX register to EP
1442 + */
1443 +static void jz4740_fifo_flush(struct usb_ep *_ep)
1444 +{
1445 +       struct jz4740_ep *ep;
1446 +       unsigned long flags;
1447 +
1448 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1449 +
1450 +       ep = container_of(_ep, struct jz4740_ep, ep);
1451 +       if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1452 +               DEBUG("%s, bad ep\n", __FUNCTION__);
1453 +               return;
1454 +       }
1455 +
1456 +       spin_lock_irqsave(&ep->dev->lock, flags);
1457 +
1458 +       jz_udc_select_ep(ep);
1459 +       flush(ep);
1460 +
1461 +       spin_unlock_irqrestore(&ep->dev->lock, flags);
1462 +}
1463 +
1464 +/****************************************************************/
1465 +/* End Point 0 related functions                                */
1466 +/****************************************************************/
1467 +
1468 +/* return:  0 = still running, 1 = completed, negative = errno */
1469 +static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1470 +{
1471 +       uint32_t max;
1472 +       unsigned count;
1473 +       int is_last;
1474 +
1475 +    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1476 +       max = ep_maxpacket(ep);
1477 +
1478 +       count = write_packet(ep, req, max);
1479 +
1480 +       /* last packet is usually short (or a zlp) */
1481 +       if (unlikely(count != max))
1482 +               is_last = 1;
1483 +       else {
1484 +               if (likely(req->req.length != req->req.actual) || req->req.zero)
1485 +                       is_last = 0;
1486 +               else
1487 +                       is_last = 1;
1488 +       }
1489 +
1490 +       DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1491 +                 ep->ep.name, count,
1492 +                 is_last ? "/L" : "", req->req.length - req->req.actual, req);
1493 +
1494 +       /* requests complete when all IN data is in the FIFO */
1495 +       if (is_last) {
1496 +               done(ep, req, 0);
1497 +               return 1;
1498 +       }
1499 +
1500 +       return 0;
1501 +}
1502 +
1503 +static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1504 +                                      unsigned char *cp, int max)
1505 +{
1506 +       int bytes;
1507 +       int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1508 +
1509 +       if (count > max)
1510 +               count = max;
1511 +       bytes = count;
1512 +       while (count--)
1513 +               *cp++ = usb_readb(ep->dev, ep->fifo);
1514 +
1515 +       return bytes;
1516 +}
1517 +
1518 +static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1519 +                                        unsigned char *cp, int count)
1520 +{
1521 +       DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1522 +       while (count--)
1523 +               usb_writeb(ep->dev, ep->fifo, *cp++);
1524 +}
1525 +
1526 +static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1527 +{
1528 +       struct jz4740_udc *dev = ep->dev;
1529 +       uint32_t csr;
1530 +       uint8_t *buf;
1531 +       unsigned bufferspace, count, is_short;
1532 +
1533 +       DEBUG_EP0("%s\n", __FUNCTION__);
1534 +
1535 +       csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1536 +       if (!(csr & USB_CSR0_OUTPKTRDY))
1537 +               return 0;
1538 +
1539 +       buf = req->req.buf + req->req.actual;
1540 +       prefetchw(buf);
1541 +       bufferspace = req->req.length - req->req.actual;
1542 +
1543 +       /* read all bytes from this packet */
1544 +       if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1545 +               count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1546 +               req->req.actual += min(count, bufferspace);
1547 +       } else                  /* zlp */
1548 +               count = 0;
1549 +
1550 +       is_short = (count < ep->ep.maxpacket);
1551 +       DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1552 +                 ep->ep.name, csr, count,
1553 +                 is_short ? "/S" : "", req, req->req.actual, req->req.length);
1554 +
1555 +       while (likely(count-- != 0)) {
1556 +               uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1557 +
1558 +               if (unlikely(bufferspace == 0)) {
1559 +                       /* this happens when the driver's buffer
1560 +                        * is smaller than what the host sent.
1561 +                        * discard the extra data.
1562 +                        */
1563 +                       if (req->req.status != -EOVERFLOW)
1564 +                               DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1565 +                                         count);
1566 +                       req->req.status = -EOVERFLOW;
1567 +               } else {
1568 +                       *buf++ = byte;
1569 +                       bufferspace--;
1570 +               }
1571 +       }
1572 +
1573 +       /* completion */
1574 +       if (is_short || req->req.actual == req->req.length) {
1575 +               done(ep, req, 0);
1576 +               return 1;
1577 +       }
1578 +
1579 +       /* finished that packet.  the next one may be waiting... */
1580 +       return 0;
1581 +}
1582 +
1583 +/**
1584 + * udc_set_address - set the USB address for this device
1585 + * @address:
1586 + *
1587 + * Called from control endpoint function after it decodes a set address setup packet.
1588 + */
1589 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1590 +{
1591 +       DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1592 +
1593 +       usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1594 +}
1595 +
1596 +/*
1597 + * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1598 + *      - if error
1599 + *              set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1600 + *      - else
1601 + *              set USB_CSR0_SVDOUTPKTRDY bit
1602 +                               if last set USB_CSR0_DATAEND bit
1603 + */
1604 +static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1605 +{
1606 +       struct jz4740_request *req;
1607 +       struct jz4740_ep *ep = &dev->ep[0];
1608 +       int ret;
1609 +
1610 +       DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1611 +
1612 +       if (list_empty(&ep->queue))
1613 +               req = 0;
1614 +       else
1615 +               req = list_entry(ep->queue.next, struct jz4740_request, queue);
1616 +
1617 +       if (req) {
1618 +               if (req->req.length == 0) {
1619 +                       DEBUG_EP0("ZERO LENGTH OUT!\n");
1620 +                       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1621 +                       dev->ep0state = WAIT_FOR_SETUP;
1622 +                       return;
1623 +               } else if (kickstart) {
1624 +                       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1625 +                       return;
1626 +               }
1627 +               ret = read_fifo_ep0(ep, req);
1628 +               if (ret) {
1629 +                       /* Done! */
1630 +                       DEBUG_EP0("%s: finished, waiting for status\n",
1631 +                                 __FUNCTION__);
1632 +                       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1633 +                       dev->ep0state = WAIT_FOR_SETUP;
1634 +               } else {
1635 +                       /* Not done yet.. */
1636 +                       DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1637 +                       usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1638 +               }
1639 +       } else {
1640 +               DEBUG_EP0("NO REQ??!\n");
1641 +       }
1642 +}
1643 +
1644 +/*
1645 + * DATA_STATE_XMIT
1646 + */
1647 +static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1648 +{
1649 +       struct jz4740_request *req;
1650 +       struct jz4740_ep *ep = &dev->ep[0];
1651 +       int ret, need_zlp = 0;
1652 +
1653 +       DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1654 +
1655 +       if (list_empty(&ep->queue))
1656 +               req = 0;
1657 +       else
1658 +               req = list_entry(ep->queue.next, struct jz4740_request, queue);
1659 +
1660 +       if (!req) {
1661 +               DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1662 +               return 0;
1663 +       }
1664 +
1665 +       if (req->req.length == 0) {
1666 +               usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1667 +               dev->ep0state = WAIT_FOR_SETUP;
1668 +               return 1;
1669 +       }
1670 +
1671 +       if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1672 +               /* Next write will end with the packet size, */
1673 +               /* so we need zero-length-packet */
1674 +               need_zlp = 1;
1675 +       }
1676 +
1677 +       ret = write_fifo_ep0(ep, req);
1678 +
1679 +       if (ret == 1 && !need_zlp) {
1680 +               /* Last packet */
1681 +               DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1682 +
1683 +               usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1684 +               dev->ep0state = WAIT_FOR_SETUP;
1685 +       } else {
1686 +               DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1687 +               usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1688 +       }
1689 +
1690 +       if (need_zlp) {
1691 +               DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1692 +               usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1693 +               dev->ep0state = DATA_STATE_NEED_ZLP;
1694 +       }
1695 +
1696 +       return 1;
1697 +}
1698 +
1699 +static int jz4740_handle_get_status(struct jz4740_udc *dev,
1700 +                                   struct usb_ctrlrequest *ctrl)
1701 +{
1702 +       struct jz4740_ep *ep0 = &dev->ep[0];
1703 +       struct jz4740_ep *qep;
1704 +       int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1705 +       uint16_t val = 0;
1706 +
1707 +    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1708 +
1709 +       if (reqtype == USB_RECIP_INTERFACE) {
1710 +               /* This is not supported.
1711 +                * And according to the USB spec, this one does nothing..
1712 +                * Just return 0
1713 +                */
1714 +               DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1715 +       } else if (reqtype == USB_RECIP_DEVICE) {
1716 +               DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1717 +               val |= (1 << 0);        /* Self powered */
1718 +               /*val |= (1<<1); *//* Remote wakeup */
1719 +       } else if (reqtype == USB_RECIP_ENDPOINT) {
1720 +               int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1721 +
1722 +               DEBUG_SETUP
1723 +                       ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1724 +                        ep_num, ctrl->wLength);
1725 +
1726 +               if (ctrl->wLength > 2 || ep_num > 3)
1727 +                       return -EOPNOTSUPP;
1728 +
1729 +               qep = &dev->ep[ep_num];
1730 +               if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1731 +                   && ep_index(qep) != 0) {
1732 +                       return -EOPNOTSUPP;
1733 +               }
1734 +
1735 +               jz_udc_set_index(dev, ep_index(qep));
1736 +
1737 +               /* Return status on next IN token */
1738 +               switch (qep->type) {
1739 +               case ep_control:
1740 +                       val =
1741 +                           (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1742 +                           USB_CSR0_SENDSTALL;
1743 +                       break;
1744 +               case ep_bulk_in:
1745 +               case ep_interrupt:
1746 +                       val =
1747 +                           (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1748 +                           USB_INCSR_SENDSTALL;
1749 +                       break;
1750 +               case ep_bulk_out:
1751 +                       val =
1752 +                           (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1753 +                           USB_OUTCSR_SENDSTALL;
1754 +                       break;
1755 +               }
1756 +
1757 +               /* Back to EP0 index */
1758 +               jz_udc_set_index(dev, 0);
1759 +
1760 +               DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1761 +                           ctrl->wIndex, val);
1762 +       } else {
1763 +               DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1764 +               return -EOPNOTSUPP;
1765 +       }
1766 +
1767 +       /* Clear "out packet ready" */
1768 +       usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1769 +       /* Put status to FIFO */
1770 +       jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1771 +       /* Issue "In packet ready" */
1772 +       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1773 +
1774 +       return 0;
1775 +}
1776 +
1777 +/*
1778 + * WAIT_FOR_SETUP (OUTPKTRDY)
1779 + *      - read data packet from EP0 FIFO
1780 + *      - decode command
1781 + *      - if error
1782 + *              set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1783 + *      - else
1784 + *              set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1785 + */
1786 +static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1787 +{
1788 +       struct jz4740_ep *ep = &dev->ep[0];
1789 +       struct usb_ctrlrequest ctrl;
1790 +       int i;
1791 +
1792 +       DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1793 +
1794 +       /* Nuke all previous transfers */
1795 +       nuke(ep, -EPROTO);
1796 +
1797 +       /* read control req from fifo (8 bytes) */
1798 +       jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1799 +
1800 +       DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1801 +                   ctrl.bRequestType, ctrl.bRequest,
1802 +                   ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1803 +
1804 +       /* Set direction of EP0 */
1805 +       if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1806 +               ep->bEndpointAddress |= USB_DIR_IN;
1807 +       } else {
1808 +               ep->bEndpointAddress &= ~USB_DIR_IN;
1809 +       }
1810 +
1811 +       /* Handle some SETUP packets ourselves */
1812 +       switch (ctrl.bRequest) {
1813 +       case USB_REQ_SET_ADDRESS:
1814 +               if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1815 +                       break;
1816 +
1817 +               DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1818 +               udc_set_address(dev, ctrl.wValue);
1819 +               usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1820 +               return;
1821 +
1822 +       case USB_REQ_SET_CONFIGURATION:
1823 +               if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1824 +                       break;
1825 +
1826 +               DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1827 +/*             usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1828 +
1829 +               /* Enable RESUME and SUSPEND interrupts */
1830 +               usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1831 +               break;
1832 +
1833 +       case USB_REQ_SET_INTERFACE:
1834 +               if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1835 +                       break;
1836 +
1837 +               DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1838 +/*             usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1839 +               break;
1840 +
1841 +       case USB_REQ_GET_STATUS:
1842 +               if (jz4740_handle_get_status(dev, &ctrl) == 0)
1843 +                       return;
1844 +
1845 +       case USB_REQ_CLEAR_FEATURE:
1846 +       case USB_REQ_SET_FEATURE:
1847 +               if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1848 +                       struct jz4740_ep *qep;
1849 +                       int ep_num = (ctrl.wIndex & 0x0f);
1850 +
1851 +                       /* Support only HALT feature */
1852 +                       if (ctrl.wValue != 0 || ctrl.wLength != 0
1853 +                           || ep_num > 3 || ep_num < 1)
1854 +                               break;
1855 +
1856 +                       qep = &dev->ep[ep_num];
1857 +                       spin_unlock(&dev->lock);
1858 +                       if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1859 +                               DEBUG_SETUP("SET_FEATURE (%d)\n",
1860 +                                           ep_num);
1861 +                               jz4740_set_halt(&qep->ep, 1);
1862 +                       } else {
1863 +                               DEBUG_SETUP("CLR_FEATURE (%d)\n",
1864 +                                           ep_num);
1865 +                               jz4740_set_halt(&qep->ep, 0);
1866 +                       }
1867 +                       spin_lock(&dev->lock);
1868 +
1869 +                       jz_udc_set_index(dev, 0);
1870 +
1871 +                       /* Reply with a ZLP on next IN token */
1872 +                       usb_setb(dev, JZ_REG_UDC_CSR0,
1873 +                                (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1874 +                       return;
1875 +               }
1876 +               break;
1877 +
1878 +       default:
1879 +               break;
1880 +       }
1881 +
1882 +       /* gadget drivers see class/vendor specific requests,
1883 +        * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1884 +        * and more.
1885 +        */
1886 +       if (dev->driver) {
1887 +               /* device-2-host (IN) or no data setup command, process immediately */
1888 +               spin_unlock(&dev->lock);
1889 +
1890 +               i = dev->driver->setup(&dev->gadget, &ctrl);
1891 +               spin_lock(&dev->lock);
1892 +
1893 +               if (unlikely(i < 0)) {
1894 +                       /* setup processing failed, force stall */
1895 +                       DEBUG_SETUP
1896 +                           ("  --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1897 +                            i);
1898 +                       jz_udc_set_index(dev, 0);
1899 +                       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1900 +
1901 +                       /* ep->stopped = 1; */
1902 +                       dev->ep0state = WAIT_FOR_SETUP;
1903 +               }
1904 +               else {
1905 +                       DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1906 +/*                     if (!ctrl.wLength) {
1907 +                               usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1908 +                       }*/
1909 +               }
1910 +       }
1911 +}
1912 +
1913 +/*
1914 + * DATA_STATE_NEED_ZLP
1915 + */
1916 +static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1917 +{
1918 +       DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1919 +
1920 +       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1921 +       dev->ep0state = WAIT_FOR_SETUP;
1922 +}
1923 +
1924 +/*
1925 + * handle ep0 interrupt
1926 + */
1927 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1928 +{
1929 +       struct jz4740_ep *ep = &dev->ep[0];
1930 +       uint32_t csr;
1931 +
1932 +    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1933 +       /* Set index 0 */
1934 +       jz_udc_set_index(dev, 0);
1935 +       csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1936 +
1937 +       DEBUG_EP0("%s: csr = %x  state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1938 +
1939 +       /*
1940 +        * if SENT_STALL is set
1941 +        *      - clear the SENT_STALL bit
1942 +        */
1943 +       if (csr & USB_CSR0_SENTSTALL) {
1944 +               DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1945 +               usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1946 +               nuke(ep, -ECONNABORTED);
1947 +               dev->ep0state = WAIT_FOR_SETUP;
1948 +               return;
1949 +       }
1950 +
1951 +       /*
1952 +        * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1953 +        *      - fill EP0 FIFO
1954 +        *      - if last packet
1955 +        *      -       set IN_PKT_RDY | DATA_END
1956 +        *      - else
1957 +        *              set IN_PKT_RDY
1958 +        */
1959 +       if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1960 +               DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1961 +                         __FUNCTION__);
1962 +
1963 +               switch (dev->ep0state) {
1964 +               case DATA_STATE_XMIT:
1965 +                       DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1966 +                       jz4740_ep0_in(dev, csr);
1967 +                       return;
1968 +               case DATA_STATE_NEED_ZLP:
1969 +                       DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1970 +                       jz4740_ep0_in_zlp(dev, csr);
1971 +                       return;
1972 +               default:
1973 +                       /* Stall? */
1974 +//                     DEBUG_EP0("Odd state!! state = %s\n",
1975 +//                               state_names[dev->ep0state]);
1976 +                       dev->ep0state = WAIT_FOR_SETUP;
1977 +                       /* nuke(ep, 0); */
1978 +                       /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1979 +//                     break;
1980 +                       return;
1981 +               }
1982 +       }
1983 +
1984 +       /*
1985 +        * if SETUPEND is set
1986 +        *      - abort the last transfer
1987 +        *      - set SERVICED_SETUP_END_BIT
1988 +        */
1989 +       if (csr & USB_CSR0_SETUPEND) {
1990 +               DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1991 +
1992 +               usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1993 +               nuke(ep, 0);
1994 +               dev->ep0state = WAIT_FOR_SETUP;
1995 +       }
1996 +
1997 +       /*
1998 +        * if USB_CSR0_OUTPKTRDY is set
1999 +        *      - read data packet from EP0 FIFO
2000 +        *      - decode command
2001 +        *      - if error
2002 +        *              set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
2003 +        *      - else
2004 +        *              set SVDOUTPKTRDY | DATAEND bits
2005 +        */
2006 +       if (csr & USB_CSR0_OUTPKTRDY) {
2007 +
2008 +               DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
2009 +                         csr);
2010 +
2011 +               switch (dev->ep0state) {
2012 +               case WAIT_FOR_SETUP:
2013 +                       DEBUG_EP0("WAIT_FOR_SETUP\n");
2014 +                       jz4740_ep0_setup(dev, csr);
2015 +                       break;
2016 +
2017 +               case DATA_STATE_RECV:
2018 +                       DEBUG_EP0("DATA_STATE_RECV\n");
2019 +                       jz4740_ep0_out(dev, csr, 0);
2020 +                       break;
2021 +
2022 +               default:
2023 +                       /* send stall? */
2024 +                       DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
2025 +                                 dev->ep0state);
2026 +                       break;
2027 +               }
2028 +       }
2029 +}
2030 +
2031 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
2032 +{
2033 +       uint32_t csr;
2034 +
2035 +       jz_udc_set_index(dev, 0);
2036 +
2037 +       DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
2038 +
2039 +       /* Clear "out packet ready" */
2040 +
2041 +       if (ep_is_in(ep)) {
2042 +               usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
2043 +               csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2044 +               dev->ep0state = DATA_STATE_XMIT;
2045 +               jz4740_ep0_in(dev, csr);
2046 +       } else {
2047 +               csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2048 +               dev->ep0state = DATA_STATE_RECV;
2049 +               jz4740_ep0_out(dev, csr, 1);
2050 +       }
2051 +}
2052 +
2053 +/** Handle USB RESET interrupt
2054 + */
2055 +static void jz4740_reset_irq(struct jz4740_udc *dev)
2056 +{
2057 +       dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
2058 +               USB_SPEED_HIGH : USB_SPEED_FULL;
2059 +
2060 +       DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0,
2061 +                   (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
2062 +}
2063 +
2064 +/*
2065 + *     jz4740 usb device interrupt handler.
2066 + */
2067 +static irqreturn_t jz4740_udc_irq(int irq, void *devid)
2068 +{
2069 +       struct jz4740_udc *jz4740_udc = devid;
2070 +       uint8_t index;
2071 +
2072 +       uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
2073 +       uint32_t intr_in  = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN);
2074 +       uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT);
2075 +       uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR);
2076 +
2077 +       if (!intr_usb && !intr_in && !intr_out && !intr_dma)
2078 +               return IRQ_HANDLED;
2079 +
2080 +
2081 +       DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
2082 +             intr_out, intr_in, intr_usb);
2083 +
2084 +       spin_lock(&jz4740_udc->lock);
2085 +       index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX);
2086 +
2087 +       /* Check for resume from suspend mode */
2088 +       if ((intr_usb & USB_INTR_RESUME) &&
2089 +           (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
2090 +               DEBUG("USB resume\n");
2091 +               jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */
2092 +       }
2093 +
2094 +       /* Check for system interrupts */
2095 +       if (intr_usb & USB_INTR_RESET) {
2096 +               DEBUG("USB reset\n");
2097 +               jz4740_reset_irq(jz4740_udc);
2098 +       }
2099 +
2100 +       /* Check for endpoint 0 interrupt */
2101 +       if (intr_in & USB_INTR_EP0) {
2102 +               DEBUG("USB_INTR_EP0 (control)\n");
2103 +               jz4740_handle_ep0(jz4740_udc, intr_in);
2104 +       }
2105 +
2106 +       /* Check for Bulk-IN DMA interrupt */
2107 +       if (intr_dma & 0x1) {
2108 +               int ep_num;
2109 +               struct jz4740_ep *ep;
2110 +               ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
2111 +               ep = &jz4740_udc->ep[ep_num + 1];
2112 +               jz_udc_set_index(jz4740_udc, ep_num);
2113 +               usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY);
2114 +/*             jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/
2115 +       }
2116 +
2117 +       /* Check for Bulk-OUT DMA interrupt */
2118 +       if (intr_dma & 0x2) {
2119 +               int ep_num;
2120 +               ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
2121 +               jz4740_out_epn(jz4740_udc, ep_num, intr_out);
2122 +       }
2123 +
2124 +       /* Check for each configured endpoint interrupt */
2125 +       if (intr_in & USB_INTR_INEP1) {
2126 +               DEBUG("USB_INTR_INEP1\n");
2127 +               jz4740_in_epn(jz4740_udc, 1, intr_in);
2128 +       }
2129 +
2130 +       if (intr_in & USB_INTR_INEP2) {
2131 +               DEBUG("USB_INTR_INEP2\n");
2132 +               jz4740_in_epn(jz4740_udc, 2, intr_in);
2133 +       }
2134 +
2135 +       if (intr_out & USB_INTR_OUTEP1) {
2136 +               DEBUG("USB_INTR_OUTEP1\n");
2137 +               jz4740_out_epn(jz4740_udc, 1, intr_out);
2138 +       }
2139 +
2140 +       /* Check for suspend mode */
2141 +       if ((intr_usb & USB_INTR_SUSPEND) &&
2142 +           (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
2143 +               DEBUG("USB suspend\n");
2144 +               jz4740_udc->driver->suspend(&jz4740_udc->gadget);
2145 +               /* Host unloaded from us, can do something, such as flushing
2146 +                the NAND block cache etc. */
2147 +       }
2148 +
2149 +    jz_udc_set_index(jz4740_udc, index);
2150 +
2151 +       spin_unlock(&jz4740_udc->lock);
2152 +
2153 +       return IRQ_HANDLED;
2154 +}
2155 +
2156 +
2157 +
2158 +/*-------------------------------------------------------------------------*/
2159 +
2160 +
2161 +static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
2162 +{
2163 +       return container_of(gadget, struct jz4740_udc, gadget);
2164 +}
2165 +
2166 +static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
2167 +{
2168 +       DEBUG("%s, %p\n", __FUNCTION__, _gadget);
2169 +       return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
2170 +}
2171 +
2172 +static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
2173 +{
2174 +       /* host may not have enabled remote wakeup */
2175 +       /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
2176 +          return -EHOSTUNREACH;
2177 +          udc_set_mask_UDCCR(UDCCR_RSM); */
2178 +       return -ENOTSUPP;
2179 +}
2180 +
2181 +static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
2182 +{
2183 +       struct jz4740_udc *udc = gadget_to_udc(_gadget);
2184 +       unsigned long flags;
2185 +
2186 +       local_irq_save(flags);
2187 +
2188 +       if (on) {
2189 +               udc->state = UDC_STATE_ENABLE;
2190 +               udc_enable(udc);
2191 +       } else {
2192 +               udc->state = UDC_STATE_DISABLE;
2193 +               udc_disable(udc);
2194 +       }
2195 +
2196 +       local_irq_restore(flags);
2197 +
2198 +       return 0;
2199 +}
2200 +
2201 +
2202 +static const struct usb_gadget_ops jz4740_udc_ops = {
2203 +       .get_frame = jz4740_udc_get_frame,
2204 +       .wakeup = jz4740_udc_wakeup,
2205 +       .pullup = jz4740_udc_pullup,
2206 +};
2207 +
2208 +static struct usb_ep_ops jz4740_ep_ops = {
2209 +       .enable         = jz4740_ep_enable,
2210 +       .disable        = jz4740_ep_disable,
2211 +
2212 +       .alloc_request  = jz4740_alloc_request,
2213 +       .free_request   = jz4740_free_request,
2214 +
2215 +       .queue          = jz4740_queue,
2216 +       .dequeue        = jz4740_dequeue,
2217 +
2218 +       .set_halt       = jz4740_set_halt,
2219 +       .fifo_status    = jz4740_fifo_status,
2220 +       .fifo_flush     = jz4740_fifo_flush,
2221 +};
2222 +
2223 +
2224 +/*-------------------------------------------------------------------------*/
2225 +
2226 +static struct jz4740_udc jz4740_udc_controller = {
2227 +       .gadget = {
2228 +               .ops = &jz4740_udc_ops,
2229 +               .ep0 = &jz4740_udc_controller.ep[0].ep,
2230 +               .name = "jz4740-udc",
2231 +               .dev = {
2232 +                       .init_name = "gadget",
2233 +               },
2234 +       },
2235 +
2236 +       /* control endpoint */
2237 +       .ep[0] = {
2238 +               .ep = {
2239 +                       .name = "ep0",
2240 +                       .ops = &jz4740_ep_ops,
2241 +                       .maxpacket = EP0_MAXPACKETSIZE,
2242 +               },
2243 +               .dev = &jz4740_udc_controller,
2244 +
2245 +               .bEndpointAddress = 0,
2246 +               .bmAttributes = 0,
2247 +
2248 +               .type = ep_control,
2249 +               .fifo = JZ_REG_UDC_EP_FIFO(0),
2250 +               .csr = JZ_REG_UDC_CSR0,
2251 +       },
2252 +
2253 +       /* bulk out endpoint */
2254 +       .ep[1] = {
2255 +               .ep = {
2256 +                       .name = "ep1out-bulk",
2257 +                       .ops = &jz4740_ep_ops,
2258 +                       .maxpacket = EPBULK_MAXPACKETSIZE,
2259 +               },
2260 +               .dev = &jz4740_udc_controller,
2261 +
2262 +               .bEndpointAddress = 1,
2263 +               .bmAttributes = USB_ENDPOINT_XFER_BULK,
2264 +
2265 +               .type = ep_bulk_out,
2266 +               .fifo = JZ_REG_UDC_EP_FIFO(1),
2267 +               .csr = JZ_REG_UDC_OUTCSR,
2268 +       },
2269 +
2270 +       /* bulk in endpoint */
2271 +       .ep[2] = {
2272 +               .ep = {
2273 +                       .name = "ep1in-bulk",
2274 +                       .ops = &jz4740_ep_ops,
2275 +                       .maxpacket = EPBULK_MAXPACKETSIZE,
2276 +               },
2277 +               .dev = &jz4740_udc_controller,
2278 +
2279 +               .bEndpointAddress = 1 | USB_DIR_IN,
2280 +               .bmAttributes = USB_ENDPOINT_XFER_BULK,
2281 +
2282 +               .type = ep_bulk_in,
2283 +               .fifo = JZ_REG_UDC_EP_FIFO(1),
2284 +               .csr = JZ_REG_UDC_INCSR,
2285 +       },
2286 +
2287 +       /* interrupt in endpoint */
2288 +       .ep[3] = {
2289 +               .ep = {
2290 +                       .name = "ep2in-int",
2291 +                       .ops = &jz4740_ep_ops,
2292 +                       .maxpacket = EPINTR_MAXPACKETSIZE,
2293 +               },
2294 +               .dev = &jz4740_udc_controller,
2295 +
2296 +               .bEndpointAddress = 2 | USB_DIR_IN,
2297 +               .bmAttributes = USB_ENDPOINT_XFER_INT,
2298 +
2299 +               .type = ep_interrupt,
2300 +               .fifo = JZ_REG_UDC_EP_FIFO(2),
2301 +               .csr = JZ_REG_UDC_INCSR,
2302 +       },
2303 +};
2304 +
2305 +static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2306 +{
2307 +       struct jz4740_udc *jz4740_udc = &jz4740_udc_controller;
2308 +       int ret;
2309 +
2310 +       spin_lock_init(&jz4740_udc->lock);
2311 +
2312 +       jz4740_udc->dev = &pdev->dev;
2313 +       jz4740_udc->gadget.dev.parent = &pdev->dev;
2314 +       jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
2315 +
2316 +       ret = device_register(&jz4740_udc->gadget.dev);
2317 +       if (ret)
2318 +               return ret;
2319 +
2320 +       jz4740_udc->clk = clk_get(&pdev->dev, "udc");
2321 +       if (IS_ERR(jz4740_udc->clk)) {
2322 +               ret = PTR_ERR(jz4740_udc->clk);
2323 +               dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2324 +               goto err_device_unregister;
2325 +       }
2326 +
2327 +       platform_set_drvdata(pdev, jz4740_udc);
2328 +
2329 +       jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2330 +
2331 +       if (!jz4740_udc->mem) {
2332 +               ret = -ENOENT;
2333 +               dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2334 +               goto err_clk_put;
2335 +       }
2336 +
2337 +       jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start,
2338 +       resource_size(jz4740_udc->mem), pdev->name);
2339 +
2340 +       if (!jz4740_udc->mem) {
2341 +               ret = -EBUSY;
2342 +               dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2343 +               goto err_device_unregister;
2344 +       }
2345 +
2346 +       jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2347 +
2348 +       if (!jz4740_udc->base) {
2349 +               ret = -EBUSY;
2350 +               dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2351 +               goto err_release_mem_region;
2352 +       }
2353 +
2354 +       jz4740_udc->irq = platform_get_irq(pdev, 0);
2355 +       ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name,
2356 +       jz4740_udc);
2357 +        if (ret) {
2358 +                dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2359 +                goto err_iounmap;
2360 +       }
2361 +
2362 +       udc_disable(jz4740_udc);
2363 +       udc_reinit(jz4740_udc);
2364 +
2365 +       return 0;
2366 +
2367 +err_iounmap:
2368 +       iounmap(jz4740_udc->base);
2369 +err_release_mem_region:
2370 +       release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2371 +err_clk_put:
2372 +       clk_put(jz4740_udc->clk);
2373 +err_device_unregister:
2374 +       device_unregister(&jz4740_udc->gadget.dev);
2375 +       platform_set_drvdata(pdev, NULL);
2376 +
2377 +       return ret;
2378 +}
2379 +
2380 +static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2381 +{
2382 +       struct jz4740_udc *dev = platform_get_drvdata(pdev);
2383 +
2384 +       if (dev->driver)
2385 +               return -EBUSY;
2386 +
2387 +       udc_disable(dev);
2388 +
2389 +       free_irq(dev->irq, dev);
2390 +       iounmap(dev->base);
2391 +       release_mem_region(dev->mem->start, resource_size(dev->mem));
2392 +       clk_put(dev->clk);
2393 +
2394 +       platform_set_drvdata(pdev, NULL);
2395 +       device_unregister(&dev->gadget.dev);
2396 +
2397 +       return 0;
2398 +}
2399 +
2400 +#ifdef CONFIG_PM
2401 +
2402 +static int jz4740_udc_suspend(struct device *dev)
2403 +{
2404 +       struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2405 +
2406 +       if (jz4740_udc->state == UDC_STATE_ENABLE)
2407 +               udc_disable(jz4740_udc);
2408 +
2409 +       return 0;
2410 +}
2411 +
2412 +static int jz4740_udc_resume(struct device *dev)
2413 +{
2414 +       struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2415 +
2416 +       if (jz4740_udc->state == UDC_STATE_ENABLE)
2417 +               udc_enable(jz4740_udc);
2418 +
2419 +       return 0;
2420 +}
2421 +
2422 +static const struct dev_pm_ops jz4740_udc_pm_ops = {
2423 +       .suspend = jz4740_udc_suspend,
2424 +       .resume = jz4740_udc_resume,
2425 +};
2426 +
2427 +#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2428 +
2429 +#else
2430 +#define JZ4740_UDC_PM_OPS NULL
2431 +#endif
2432 +
2433 +static struct platform_driver udc_driver = {
2434 +       .probe          = jz4740_udc_probe,
2435 +       .remove         = __devexit_p(jz4740_udc_remove),
2436 +       .driver         = {
2437 +               .name   = "jz-udc",
2438 +               .owner  = THIS_MODULE,
2439 +               .pm             = JZ4740_UDC_PM_OPS,
2440 +       },
2441 +};
2442 +
2443 +/*-------------------------------------------------------------------------*/
2444 +
2445 +static int __init udc_init (void)
2446 +{
2447 +       return platform_driver_register(&udc_driver);
2448 +}
2449 +module_init(udc_init);
2450 +
2451 +static void __exit udc_exit (void)
2452 +{
2453 +       platform_driver_unregister(&udc_driver);
2454 +}
2455 +module_exit(udc_exit);
2456 +
2457 +MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2458 +MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2459 +MODULE_LICENSE("GPL");
2460 --- /dev/null
2461 +++ b/drivers/usb/gadget/jz4740_udc.h
2462 @@ -0,0 +1,101 @@
2463 +/*
2464 + * linux/drivers/usb/gadget/jz4740_udc.h
2465 + *
2466 + * Ingenic JZ4740 on-chip high speed USB device controller
2467 + *
2468 + * Copyright (C) 2006 Ingenic Semiconductor Inc.
2469 + * Author: <jlwei@ingenic.cn>
2470 + *
2471 + * This program is free software; you can redistribute it and/or modify
2472 + * it under the terms of the GNU General Public License as published by
2473 + * the Free Software Foundation; either version 2 of the License, or
2474 + * (at your option) any later version.
2475 + */
2476 +
2477 +#ifndef __USB_GADGET_JZ4740_H__
2478 +#define __USB_GADGET_JZ4740_H__
2479 +
2480 +/*-------------------------------------------------------------------------*/
2481 +
2482 +// Max packet size
2483 +#define EP0_MAXPACKETSIZE      64
2484 +#define EPBULK_MAXPACKETSIZE   512
2485 +#define EPINTR_MAXPACKETSIZE   64
2486 +
2487 +#define UDC_MAX_ENDPOINTS       4
2488 +
2489 +/*-------------------------------------------------------------------------*/
2490 +
2491 +enum ep_type {
2492 +       ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2493 +};
2494 +
2495 +struct jz4740_ep {
2496 +       struct usb_ep ep;
2497 +       struct jz4740_udc *dev;
2498 +
2499 +       const struct usb_endpoint_descriptor *desc;
2500 +
2501 +       uint8_t stopped;
2502 +       uint8_t bEndpointAddress;
2503 +       uint8_t bmAttributes;
2504 +
2505 +       enum ep_type type;
2506 +       size_t fifo;
2507 +       uint32_t csr;
2508 +
2509 +       uint32_t reg_addr;
2510 +       struct list_head queue;
2511 +};
2512 +
2513 +struct jz4740_request {
2514 +       struct usb_request req;
2515 +       struct list_head queue;
2516 +};
2517 +
2518 +enum ep0state {
2519 +       WAIT_FOR_SETUP,         /* between STATUS ack and SETUP report */
2520 +       DATA_STATE_XMIT,        /* data tx stage */
2521 +       DATA_STATE_NEED_ZLP,    /* data tx zlp stage */
2522 +       WAIT_FOR_OUT_STATUS,    /* status stages */
2523 +       DATA_STATE_RECV,        /* data rx stage */
2524 +};
2525 +
2526 +/* For function binding with UDC Disable - Added by River */
2527 +typedef enum {
2528 +       UDC_STATE_ENABLE = 0,
2529 +       UDC_STATE_DISABLE,
2530 +}udc_state_t;
2531 +
2532 +struct jz4740_udc {
2533 +       struct usb_gadget gadget;
2534 +       struct usb_gadget_driver *driver;
2535 +       struct device *dev;
2536 +       spinlock_t lock;
2537 +       unsigned long lock_flags;
2538 +
2539 +       enum ep0state ep0state;
2540 +       struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2541 +
2542 +       udc_state_t state;
2543 +
2544 +       struct resource *mem;
2545 +       void __iomem *base;
2546 +       int irq;
2547 +
2548 +       struct clk *clk;
2549 +};
2550 +
2551 +#define ep_maxpacket(EP)       ((EP)->ep.maxpacket)
2552 +
2553 +static inline bool ep_is_in(const struct jz4740_ep *ep)
2554 +{
2555 +       return (ep->bEndpointAddress & USB_DIR_IN) == USB_DIR_IN;
2556 +}
2557 +
2558 +static inline uint8_t ep_index(const struct jz4740_ep *ep)
2559 +{
2560 +       return ep->bEndpointAddress & 0xf;
2561 +}
2562 +
2563 +#endif /* __USB_GADGET_JZ4740_H__ */