target/linux/xburst/patches-2.6.34/054-mmc.patch

   1 From 63f8a44fa0a452e0f93ca9b88ccdc5ade02f80f3 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 24 Apr 2010 12:48:14 +0200
   4 Subject: [PATCH] Add jz4740 mmc driver
   5
   6 ---
   7  drivers/mmc/host/Kconfig       |   15 +
   8  drivers/mmc/host/Makefile      |    1 +
   9  drivers/mmc/host/jz_mmc.c      | 1005 ++++++++++++++++++++++++++++++++++++++++
  10  include/linux/mmc/jz4740_mmc.h |   15 +
  11  4 files changed, 1036 insertions(+), 0 deletions(-)
  12  create mode 100644 drivers/mmc/host/jz_mmc.c
  13  create mode 100644 include/linux/mmc/jz4740_mmc.h
  14
  15 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
  16 index 2e13b94..94e9240 100644
  17 --- a/drivers/mmc/host/Kconfig
  18 +++ b/drivers/mmc/host/Kconfig
  19 @@ -81,6 +81,21 @@ config MMC_RICOH_MMC
  20
  21           If unsure, say Y.
  22
  23 +config MMC_JZ
  24 +       tristate "JZ SD/Multimedia Card Interface support"
  25 +       depends on SOC_JZ4720 || SOC_JZ4740
  26 +       help
  27 +         This selects the Ingenic JZ4720/JZ4740 SD/Multimedia card Interface.
  28 +         If you have abIngenic platform with a Multimedia Card slot,
  29 +         say Y or M here.
  30 +
  31 +         If unsure, say N.
  32 +
  33 +         To compile this driver as a module, choose M here:
  34 +         the module will be called ricoh_mmc.
  35 +
  36 +         If unsure, say Y.
  37 +
  38  config MMC_SDHCI_OF
  39         tristate "SDHCI support on OpenFirmware platforms"
  40         depends on MMC_SDHCI && PPC_OF
  41 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
  42 index f480397..7e83c54 100644
  43 --- a/drivers/mmc/host/Makefile
  44 +++ b/drivers/mmc/host/Makefile
  45 @@ -6,6 +6,7 @@ ifeq ($(CONFIG_MMC_DEBUG),y)
  46         EXTRA_CFLAGS            += -DDEBUG
  47  endif
  48
  49 +obj-$(CONFIG_MMC_JZ)           += jz_mmc.o
  50  obj-$(CONFIG_MMC_ARMMMCI)      += mmci.o
  51  obj-$(CONFIG_MMC_PXA)          += pxamci.o
  52  obj-$(CONFIG_MMC_IMX)          += imxmmc.o
  53 diff --git a/drivers/mmc/host/jz_mmc.c b/drivers/mmc/host/jz_mmc.c
  54 new file mode 100644
  55 index 0000000..ac7668a
  56 --- /dev/null
  57 +++ b/drivers/mmc/host/jz_mmc.c
  58 @@ -0,0 +1,1005 @@
  59 +/*
  60 + *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
  61 + *      JZ7420/JZ4740 GPIO SD/MMC controller driver
  62 + *
  63 + *  This program is free software; you can redistribute         it and/or modify it
  64 + *  under  the terms of         the GNU General  Public License as published by the
  65 + *  Free Software Foundation;  either version 2 of the License, or (at your
  66 + *  option) any later version.
  67 + *
  68 + *  You should have received a copy of the  GNU General Public License along
  69 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  70 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  71 + *
  72 + */
  73 +
  74 +#include <linux/mmc/host.h>
  75 +#include <linux/io.h>
  76 +#include <linux/irq.h>
  77 +#include <linux/interrupt.h>
  78 +#include <linux/module.h>
  79 +#include <linux/platform_device.h>
  80 +#include <linux/delay.h>
  81 +#include <linux/scatterlist.h>
  82 +#include <linux/clk.h>
  83 +#include <linux/mmc/jz4740_mmc.h>
  84 +
  85 +#include <linux/gpio.h>
  86 +#include <asm/mach-jz4740/gpio.h>
  87 +#include <asm/cacheflush.h>
  88 +#include <linux/dma-mapping.h>
  89 +
  90 +#define JZ_REG_MMC_STRPCL      0x00
  91 +#define JZ_REG_MMC_STATUS      0x04
  92 +#define JZ_REG_MMC_CLKRT       0x08
  93 +#define JZ_REG_MMC_CMDAT       0x0C
  94 +#define JZ_REG_MMC_RESTO       0x10
  95 +#define JZ_REG_MMC_RDTO                0x14
  96 +#define JZ_REG_MMC_BLKLEN      0x18
  97 +#define JZ_REG_MMC_NOB         0x1C
  98 +#define JZ_REG_MMC_SNOB                0x20
  99 +#define JZ_REG_MMC_IMASK       0x24
 100 +#define JZ_REG_MMC_IREG                0x28
 101 +#define JZ_REG_MMC_CMD         0x2C
 102 +#define JZ_REG_MMC_ARG         0x30
 103 +#define JZ_REG_MMC_RESP_FIFO   0x34
 104 +#define JZ_REG_MMC_RXFIFO      0x38
 105 +#define JZ_REG_MMC_TXFIFO      0x3C
 106 +
 107 +#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
 108 +#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
 109 +#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
 110 +#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
 111 +#define JZ_MMC_STRPCL_RESET BIT(3)
 112 +#define JZ_MMC_STRPCL_START_OP BIT(2)
 113 +#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
 114 +#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
 115 +#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
 116 +
 117 +
 118 +#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
 119 +#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
 120 +#define JZ_MMC_STATUS_PRG_DONE BIT(13)
 121 +#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
 122 +#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
 123 +#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
 124 +#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
 125 +#define JZ_MMC_STATUS_CLK_EN BIT(8)
 126 +#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
 127 +#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
 128 +#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
 129 +#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
 130 +#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
 131 +#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
 132 +#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
 133 +#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
 134 +
 135 +#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
 136 +#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
 137 +
 138 +
 139 +#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
 140 +#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
 141 +#define JZ_MMC_CMDAT_DMA_EN BIT(8)
 142 +#define JZ_MMC_CMDAT_INIT BIT(7)
 143 +#define JZ_MMC_CMDAT_BUSY BIT(6)
 144 +#define JZ_MMC_CMDAT_STREAM BIT(5)
 145 +#define JZ_MMC_CMDAT_WRITE BIT(4)
 146 +#define JZ_MMC_CMDAT_DATA_EN BIT(3)
 147 +#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
 148 +#define JZ_MMC_CMDAT_RSP_R1 1
 149 +#define JZ_MMC_CMDAT_RSP_R2 2
 150 +#define JZ_MMC_CMDAT_RSP_R3 3
 151 +
 152 +#define JZ_MMC_IRQ_SDIO BIT(7)
 153 +#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
 154 +#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
 155 +#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
 156 +#define JZ_MMC_IRQ_PRG_DONE BIT(1)
 157 +#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
 158 +
 159 +
 160 +#define JZ_MMC_CLK_RATE 24000000
 161 +
 162 +#define JZ4740_MMC_MAX_TIMEOUT 10000000
 163 +
 164 +struct jz4740_mmc_host {
 165 +       struct mmc_host *mmc;
 166 +       struct platform_device *pdev;
 167 +       struct jz4740_mmc_platform_data *pdata;
 168 +       struct clk *clk;
 169 +
 170 +       int irq;
 171 +       int card_detect_irq;
 172 +
 173 +       struct resource *mem;
 174 +       void __iomem *base;
 175 +       struct mmc_request *req;
 176 +       struct mmc_command *cmd;
 177 +
 178 +       int max_clock;
 179 +       uint32_t cmdat;
 180 +
 181 +       uint16_t irq_mask;
 182 +
 183 +       spinlock_t lock;
 184 +       struct timer_list clock_timer;
 185 +       struct timer_list timeout_timer;
 186 +       unsigned waiting:1;
 187 +};
 188 +
 189 +static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host);
 190 +
 191 +static void jz4740_mmc_enable_irq(struct jz4740_mmc_host *host, unsigned int irq)
 192 +{
 193 +       unsigned long flags;
 194 +       spin_lock_irqsave(&host->lock, flags);
 195 +
 196 +       host->irq_mask &= ~irq;
 197 +       writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
 198 +
 199 +       spin_unlock_irqrestore(&host->lock, flags);
 200 +}
 201 +
 202 +static void jz4740_mmc_disable_irq(struct jz4740_mmc_host *host, unsigned int irq)
 203 +{
 204 +       unsigned long flags;
 205 +       spin_lock_irqsave(&host->lock, flags);
 206 +
 207 +       host->irq_mask |= irq;
 208 +       writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
 209 +
 210 +       spin_unlock_irqrestore(&host->lock, flags);
 211 +}
 212 +
 213 +static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, bool start_transfer)
 214 +{
 215 +       uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
 216 +
 217 +       if (start_transfer)
 218 +               val |= JZ_MMC_STRPCL_START_OP;
 219 +
 220 +       writew(val, host->base + JZ_REG_MMC_STRPCL);
 221 +}
 222 +
 223 +static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
 224 +{
 225 +       uint32_t status;
 226 +
 227 +       writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
 228 +       do {
 229 +               status = readl(host->base + JZ_REG_MMC_STATUS);
 230 +       } while (status & JZ_MMC_STATUS_CLK_EN);
 231 +
 232 +}
 233 +
 234 +static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
 235 +{
 236 +       uint32_t status;
 237 +
 238 +       writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
 239 +       udelay(10);
 240 +       do {
 241 +               status = readl(host->base + JZ_REG_MMC_STATUS);
 242 +       } while (status & JZ_MMC_STATUS_IS_RESETTING);
 243 +}
 244 +
 245 +static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
 246 +{
 247 +       struct mmc_request *req;
 248 +       unsigned long flags;
 249 +
 250 +       spin_lock_irqsave(&host->lock, flags);
 251 +       req = host->req;
 252 +       host->req = NULL;
 253 +       host->waiting = 0;
 254 +       spin_unlock_irqrestore(&host->lock, flags);
 255 +
 256 +       if (!unlikely(req))
 257 +               return;
 258 +
 259 +       mmc_request_done(host->mmc, req);
 260 +}
 261 +
 262 +static inline unsigned int jz4740_mmc_wait_irq(struct jz4740_mmc_host *host,
 263 +       unsigned int irq)
 264 +{
 265 +       unsigned int timeout = JZ4740_MMC_MAX_TIMEOUT;
 266 +       uint16_t status;
 267 +
 268 +       do {
 269 +               status = readw(host->base + JZ_REG_MMC_IREG);
 270 +       } while (!(status & irq) && --timeout);
 271 +
 272 +       return timeout;
 273 +}
 274 +
 275 +static void jz4740_mmc_write_data(struct jz4740_mmc_host *host, struct mmc_data *data)
 276 +{
 277 +       struct scatterlist *sg;
 278 +       uint32_t *sg_pointer;
 279 +       int status;
 280 +       unsigned int timeout;
 281 +       size_t i, j;
 282 +
 283 +       for (sg = data->sg; sg; sg = sg_next(sg)) {
 284 +               sg_pointer = sg_virt(sg);
 285 +               i = sg->length / 4;
 286 +               j = i >> 3;
 287 +               i = i & 0x7;
 288 +               while (j) {
 289 +                       timeout = jz4740_mmc_wait_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
 290 +                       if (unlikely(timeout == 0))
 291 +                               goto err_timeout;
 292 +
 293 +                       writel(sg_pointer[0], host->base + JZ_REG_MMC_TXFIFO);
 294 +                       writel(sg_pointer[1], host->base + JZ_REG_MMC_TXFIFO);
 295 +                       writel(sg_pointer[2], host->base + JZ_REG_MMC_TXFIFO);
 296 +                       writel(sg_pointer[3], host->base + JZ_REG_MMC_TXFIFO);
 297 +                       writel(sg_pointer[4], host->base + JZ_REG_MMC_TXFIFO);
 298 +                       writel(sg_pointer[5], host->base + JZ_REG_MMC_TXFIFO);
 299 +                       writel(sg_pointer[6], host->base + JZ_REG_MMC_TXFIFO);
 300 +                       writel(sg_pointer[7], host->base + JZ_REG_MMC_TXFIFO);
 301 +                       sg_pointer += 8;
 302 +                       --j;
 303 +               }
 304 +               if (i) {
 305 +                       timeout = jz4740_mmc_wait_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
 306 +                       if (unlikely(timeout == 0))
 307 +                               goto err_timeout;
 308 +
 309 +                       while (i) {
 310 +                               writel(*sg_pointer, host->base + JZ_REG_MMC_TXFIFO);
 311 +                               ++sg_pointer;
 312 +                               --i;
 313 +                       }
 314 +               }
 315 +               data->bytes_xfered += sg->length;
 316 +       }
 317 +
 318 +       status = readl(host->base + JZ_REG_MMC_STATUS);
 319 +       if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK)
 320 +               goto err;
 321 +
 322 +       timeout = JZ4740_MMC_MAX_TIMEOUT;
 323 +       do {
 324 +               status = readl(host->base + JZ_REG_MMC_STATUS);
 325 +       } while ((status & JZ_MMC_STATUS_DATA_TRAN_DONE) == 0 && --timeout);
 326 +
 327 +       if (unlikely(timeout == 0))
 328 +               goto err_timeout;
 329 +       writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
 330 +
 331 +       return;
 332 +err_timeout:
 333 +       host->req->cmd->error = -ETIMEDOUT;
 334 +       data->error = -ETIMEDOUT;
 335 +       return;
 336 +err:
 337 +       if(status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
 338 +               host->req->cmd->error = -ETIMEDOUT;
 339 +               data->error = -ETIMEDOUT;
 340 +       } else {
 341 +               host->req->cmd->error = -EILSEQ;
 342 +               data->error = -EILSEQ;
 343 +       }
 344 +}
 345 +
 346 +static void jz4740_mmc_timeout(unsigned long data)
 347 +{
 348 +       struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)data;
 349 +       unsigned long flags;
 350 +
 351 +       spin_lock_irqsave(&host->lock, flags);
 352 +       if (!host->waiting) {
 353 +               spin_unlock_irqrestore(&host->lock, flags);
 354 +               return;
 355 +       }
 356 +
 357 +       host->waiting = 0;
 358 +
 359 +       spin_unlock_irqrestore(&host->lock, flags);
 360 +
 361 +       host->req->cmd->error = -ETIMEDOUT;
 362 +       jz4740_mmc_request_done(host);
 363 +}
 364 +
 365 +static void jz4740_mmc_read_data(struct jz4740_mmc_host *host,
 366 +                               struct mmc_data *data)
 367 +{
 368 +       struct scatterlist *sg;
 369 +       uint32_t *sg_pointer;
 370 +       uint32_t d;
 371 +       uint16_t status = 0;
 372 +       size_t i, j;
 373 +       unsigned int timeout;
 374 +
 375 +       for (sg = data->sg; sg; sg = sg_next(sg)) {
 376 +               sg_pointer = sg_virt(sg);
 377 +               i = sg->length;
 378 +               j = i >> 5;
 379 +               i = i & 0x1f;
 380 +               while (j) {
 381 +                       timeout = jz4740_mmc_wait_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
 382 +                       if (unlikely(timeout == 0))
 383 +                               goto err_timeout;
 384 +
 385 +                       sg_pointer[0] = readl(host->base + JZ_REG_MMC_RXFIFO);
 386 +                       sg_pointer[1] = readl(host->base + JZ_REG_MMC_RXFIFO);
 387 +                       sg_pointer[2] = readl(host->base + JZ_REG_MMC_RXFIFO);
 388 +                       sg_pointer[3] = readl(host->base + JZ_REG_MMC_RXFIFO);
 389 +                       sg_pointer[4] = readl(host->base + JZ_REG_MMC_RXFIFO);
 390 +                       sg_pointer[5] = readl(host->base + JZ_REG_MMC_RXFIFO);
 391 +                       sg_pointer[6] = readl(host->base + JZ_REG_MMC_RXFIFO);
 392 +                       sg_pointer[7] = readl(host->base + JZ_REG_MMC_RXFIFO);
 393 +
 394 +                       sg_pointer += 8;
 395 +                       --j;
 396 +               }
 397 +
 398 +               while (i >= 4) {
 399 +                       timeout = jz4740_mmc_wait_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
 400 +                       if (unlikely(timeout == 0))
 401 +                               goto err_timeout;
 402 +
 403 +                       *sg_pointer = readl(host->base + JZ_REG_MMC_RXFIFO);
 404 +                       ++sg_pointer;
 405 +                       i -= 4;
 406 +               }
 407 +               if (i > 0) {
 408 +                       d = readl(host->base + JZ_REG_MMC_RXFIFO);
 409 +                       memcpy(sg_pointer, &d, i);
 410 +               }
 411 +               data->bytes_xfered += sg->length;
 412 +
 413 +               flush_dcache_page(sg_page(sg));
 414 +       }
 415 +
 416 +       status = readl(host->base + JZ_REG_MMC_STATUS);
 417 +       if (status & JZ_MMC_STATUS_READ_ERROR_MASK)
 418 +               goto err;
 419 +
 420 +       /* For whatever reason there is sometime one word more in the fifo then
 421 +        * requested */
 422 +       while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) == 0 && --timeout) {
 423 +               d = readl(host->base + JZ_REG_MMC_RXFIFO);
 424 +               status = readl(host->base + JZ_REG_MMC_STATUS);
 425 +       }
 426 +       return;
 427 +err_timeout:
 428 +       host->req->cmd->error = -ETIMEDOUT;
 429 +       data->error = -ETIMEDOUT;
 430 +       return;
 431 +err:
 432 +       if (status & JZ_MMC_STATUS_TIMEOUT_READ) {
 433 +               host->req->cmd->error = -ETIMEDOUT;
 434 +               data->error = -ETIMEDOUT;
 435 +       } else {
 436 +               host->req->cmd->error = -EILSEQ;
 437 +               data->error = -EILSEQ;
 438 +       }
 439 +}
 440 +
 441 +static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
 442 +{
 443 +       struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
 444 +
 445 +       if (host->cmd->error)
 446 +               jz4740_mmc_request_done(host);
 447 +       else
 448 +               jz4740_mmc_cmd_done(host);
 449 +
 450 +       return IRQ_HANDLED;
 451 +}
 452 +
 453 +static irqreturn_t jz_mmc_irq(int irq, void *devid)
 454 +{
 455 +       struct jz4740_mmc_host *host = devid;
 456 +       uint16_t irq_reg, status, tmp;
 457 +       unsigned long flags;
 458 +       irqreturn_t ret = IRQ_HANDLED;
 459 +
 460 +       irq_reg = readw(host->base + JZ_REG_MMC_IREG);
 461 +
 462 +       tmp = irq_reg;
 463 +       spin_lock_irqsave(&host->lock, flags);
 464 +       irq_reg &= ~host->irq_mask;
 465 +       spin_unlock_irqrestore(&host->lock, flags);
 466 +
 467 +       tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
 468 +                       JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
 469 +
 470 +       if (tmp != irq_reg) {
 471 +               dev_warn(&host->pdev->dev, "Sparse irq: %x\n", tmp & ~irq_reg);
 472 +               writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
 473 +       }
 474 +
 475 +
 476 +       if (irq_reg & JZ_MMC_IRQ_SDIO) {
 477 +               writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
 478 +               mmc_signal_sdio_irq(host->mmc);
 479 +       }
 480 +
 481 +       if (!host->req || !host->cmd) {
 482 +               goto handled;
 483 +       }
 484 +
 485 +
 486 +       spin_lock_irqsave(&host->lock, flags);
 487 +       if (!host->waiting) {
 488 +               spin_unlock_irqrestore(&host->lock, flags);
 489 +               goto handled;
 490 +       }
 491 +
 492 +       host->waiting = 0;
 493 +       spin_unlock_irqrestore(&host->lock, flags);
 494 +
 495 +       del_timer(&host->timeout_timer);
 496 +
 497 +       status = readl(host->base + JZ_REG_MMC_STATUS);
 498 +
 499 +       if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
 500 +               host->cmd->error = -ETIMEDOUT;
 501 +       } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
 502 +               host->cmd->error = -EIO;
 503 +       } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
 504 +                                               JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
 505 +               host->cmd->data->error = -EIO;
 506 +       } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
 507 +                                               JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
 508 +               host->cmd->data->error = -EIO;
 509 +       }
 510 +
 511 +       if (irq_reg & JZ_MMC_IRQ_END_CMD_RES) {
 512 +               jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
 513 +               writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
 514 +               ret = IRQ_WAKE_THREAD;
 515 +       }
 516 +
 517 +       return ret;
 518 +handled:
 519 +
 520 +       writew(0xff, host->base + JZ_REG_MMC_IREG);
 521 +       return IRQ_HANDLED;
 522 +}
 523 +
 524 +static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) {
 525 +       int div = 0;
 526 +       int real_rate;
 527 +
 528 +       jz4740_mmc_clock_disable(host);
 529 +       clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
 530 +
 531 +       real_rate = clk_get_rate(host->clk);
 532 +
 533 +       while (real_rate > rate && div < 7) {
 534 +               ++div;
 535 +               real_rate >>= 1;
 536 +       }
 537 +
 538 +       writew(div, host->base + JZ_REG_MMC_CLKRT);
 539 +       return real_rate;
 540 +}
 541 +
 542 +
 543 +static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, struct mmc_command *cmd)
 544 +{
 545 +       int i;
 546 +       uint16_t tmp;
 547 +       if (cmd->flags & MMC_RSP_136) {
 548 +               tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
 549 +               for (i = 0; i < 4; ++i) {
 550 +                       cmd->resp[i] = tmp << 24;
 551 +                       cmd->resp[i] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
 552 +                       tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
 553 +                       cmd->resp[i] |= tmp >> 8;
 554 +               }
 555 +       } else {
 556 +               cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24;
 557 +               cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
 558 +               cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff;
 559 +       }
 560 +}
 561 +
 562 +static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, struct mmc_command *cmd)
 563 +{
 564 +       uint32_t cmdat = host->cmdat;
 565 +
 566 +       host->cmdat &= ~JZ_MMC_CMDAT_INIT;
 567 +       jz4740_mmc_clock_disable(host);
 568 +
 569 +       host->cmd = cmd;
 570 +
 571 +       if (cmd->flags & MMC_RSP_BUSY)
 572 +               cmdat |= JZ_MMC_CMDAT_BUSY;
 573 +
 574 +       switch (mmc_resp_type(cmd)) {
 575 +       case MMC_RSP_R1B:
 576 +       case MMC_RSP_R1:
 577 +               cmdat |= JZ_MMC_CMDAT_RSP_R1;
 578 +               break;
 579 +       case MMC_RSP_R2:
 580 +               cmdat |= JZ_MMC_CMDAT_RSP_R2;
 581 +               break;
 582 +       case MMC_RSP_R3:
 583 +               cmdat |= JZ_MMC_CMDAT_RSP_R3;
 584 +               break;
 585 +       default:
 586 +               break;
 587 +       }
 588 +
 589 +       if (cmd->data) {
 590 +               cmdat |= JZ_MMC_CMDAT_DATA_EN;
 591 +               if (cmd->data->flags & MMC_DATA_WRITE)
 592 +                       cmdat |= JZ_MMC_CMDAT_WRITE;
 593 +               if (cmd->data->flags & MMC_DATA_STREAM)
 594 +                       cmdat |= JZ_MMC_CMDAT_STREAM;
 595 +
 596 +               writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
 597 +               writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
 598 +       }
 599 +
 600 +       writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
 601 +       writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
 602 +       writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
 603 +
 604 +       host->waiting = 1;
 605 +       jz4740_mmc_clock_enable(host, 1);
 606 +       mod_timer(&host->timeout_timer, jiffies + 5*HZ);
 607 +}
 608 +
 609 +static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host)
 610 +{
 611 +       uint32_t status;
 612 +       struct mmc_command *cmd = host->req->cmd;
 613 +       struct mmc_request *req = host->req;
 614 +       unsigned int timeout = JZ4740_MMC_MAX_TIMEOUT;
 615 +
 616 +       if (cmd->flags & MMC_RSP_PRESENT)
 617 +               jz4740_mmc_read_response(host, cmd);
 618 +
 619 +       if (cmd->data) {
 620 +               if (cmd->data->flags & MMC_DATA_READ)
 621 +                       jz4740_mmc_read_data(host, cmd->data);
 622 +               else
 623 +                       jz4740_mmc_write_data(host, cmd->data);
 624 +       }
 625 +
 626 +       if (req->stop) {
 627 +               jz4740_mmc_send_command(host, req->stop);
 628 +               do {
 629 +                       status = readw(host->base + JZ_REG_MMC_IREG);
 630 +               } while ((status & JZ_MMC_IRQ_PRG_DONE) == 0 && --timeout);
 631 +               writew(JZ_MMC_IRQ_PRG_DONE, host->base + JZ_REG_MMC_IREG);
 632 +       }
 633 +
 634 +       if (unlikely(timeout == 0))
 635 +               req->stop->error = -ETIMEDOUT;
 636 +
 637 +       jz4740_mmc_request_done(host);
 638 +}
 639 +
 640 +static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 641 +{
 642 +       struct jz4740_mmc_host *host = mmc_priv(mmc);
 643 +
 644 +       host->req = req;
 645 +
 646 +       writew(0xffff, host->base + JZ_REG_MMC_IREG);
 647 +
 648 +       writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
 649 +       jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
 650 +       jz4740_mmc_send_command(host, req->cmd);
 651 +}
 652 +
 653 +
 654 +static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 655 +{
 656 +       struct jz4740_mmc_host *host = mmc_priv(mmc);
 657 +       if (ios->clock)
 658 +               jz4740_mmc_set_clock_rate(host, ios->clock);
 659 +
 660 +       switch (ios->power_mode) {
 661 +       case MMC_POWER_UP:
 662 +               jz4740_mmc_reset(host);
 663 +               if (gpio_is_valid(host->pdata->gpio_power))
 664 +                       gpio_set_value(host->pdata->gpio_power,
 665 +                                       !host->pdata->power_active_low);
 666 +               host->cmdat |= JZ_MMC_CMDAT_INIT;
 667 +               clk_enable(host->clk);
 668 +               break;
 669 +       case MMC_POWER_ON:
 670 +               break;
 671 +       default:
 672 +               if (gpio_is_valid(host->pdata->gpio_power))
 673 +                       gpio_set_value(host->pdata->gpio_power,
 674 +                                       host->pdata->power_active_low);
 675 +               clk_disable(host->clk);
 676 +               break;
 677 +       }
 678 +
 679 +       switch (ios->bus_width) {
 680 +       case MMC_BUS_WIDTH_1:
 681 +               host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
 682 +               break;
 683 +       case MMC_BUS_WIDTH_4:
 684 +               host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
 685 +               break;
 686 +       default:
 687 +               dev_err(&host->pdev->dev, "Invalid bus width: %d\n", ios->bus_width);
 688 +       }
 689 +}
 690 +
 691 +static int jz4740_mmc_get_ro(struct mmc_host *mmc)
 692 +{
 693 +       struct jz4740_mmc_host *host = mmc_priv(mmc);
 694 +       if (!gpio_is_valid(host->pdata->gpio_read_only))
 695 +               return -ENOSYS;
 696 +
 697 +       return gpio_get_value(host->pdata->gpio_read_only) ^
 698 +               host->pdata->read_only_active_low;
 699 +}
 700 +
 701 +static int jz4740_mmc_get_cd(struct mmc_host *mmc)
 702 +{
 703 +       struct jz4740_mmc_host *host = mmc_priv(mmc);
 704 +       if (!gpio_is_valid(host->pdata->gpio_card_detect))
 705 +               return -ENOSYS;
 706 +
 707 +       return gpio_get_value(host->pdata->gpio_card_detect) ^
 708 +                       host->pdata->card_detect_active_low;
 709 +}
 710 +
 711 +static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
 712 +{
 713 +       struct jz4740_mmc_host *host = devid;
 714 +
 715 +       mmc_detect_change(host->mmc, HZ / 3);
 716 +
 717 +       return IRQ_HANDLED;
 718 +}
 719 +
 720 +static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 721 +{
 722 +       struct jz4740_mmc_host *host = mmc_priv(mmc);
 723 +       if (enable)
 724 +               jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_SDIO);
 725 +       else
 726 +               jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_SDIO);
 727 +}
 728 +
 729 +static const struct mmc_host_ops jz4740_mmc_ops = {
 730 +       .request        = jz4740_mmc_request,
 731 +       .set_ios        = jz4740_mmc_set_ios,
 732 +       .get_ro         = jz4740_mmc_get_ro,
 733 +       .get_cd         = jz4740_mmc_get_cd,
 734 +       .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
 735 +};
 736 +
 737 +static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
 738 +       JZ_GPIO_BULK_PIN(MSC_CMD),
 739 +       JZ_GPIO_BULK_PIN(MSC_CLK),
 740 +       JZ_GPIO_BULK_PIN(MSC_DATA0),
 741 +       JZ_GPIO_BULK_PIN(MSC_DATA1),
 742 +       JZ_GPIO_BULK_PIN(MSC_DATA2),
 743 +       JZ_GPIO_BULK_PIN(MSC_DATA3),
 744 +};
 745 +
 746 +static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
 747 +{
 748 +       int ret;
 749 +       struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
 750 +
 751 +       if (!pdata)
 752 +               return 0;
 753 +
 754 +       if (gpio_is_valid(pdata->gpio_card_detect)) {
 755 +               ret = gpio_request(pdata->gpio_card_detect, "MMC detect change");
 756 +               if (ret) {
 757 +                       dev_err(&pdev->dev, "Failed to request detect change gpio\n");
 758 +                       goto err;
 759 +               }
 760 +               gpio_direction_input(pdata->gpio_card_detect);
 761 +       }
 762 +
 763 +       if (gpio_is_valid(pdata->gpio_read_only)) {
 764 +               ret = gpio_request(pdata->gpio_read_only, "MMC read only");
 765 +               if (ret) {
 766 +                       dev_err(&pdev->dev, "Failed to request read only gpio: %d\n", ret);
 767 +                       goto err_free_gpio_card_detect;
 768 +               }
 769 +               gpio_direction_input(pdata->gpio_read_only);
 770 +       }
 771 +
 772 +       if (gpio_is_valid(pdata->gpio_power)) {
 773 +               ret = gpio_request(pdata->gpio_power, "MMC power");
 774 +               if (ret) {
 775 +                       dev_err(&pdev->dev, "Failed to request power gpio: %d\n", ret);
 776 +                       goto err_free_gpio_read_only;
 777 +               }
 778 +               gpio_direction_output(pdata->gpio_power, pdata->power_active_low);
 779 +       }
 780 +
 781 +       return 0;
 782 +
 783 +err_free_gpio_read_only:
 784 +       if (gpio_is_valid(pdata->gpio_read_only))
 785 +               gpio_free(pdata->gpio_read_only);
 786 +err_free_gpio_card_detect:
 787 +       if (gpio_is_valid(pdata->gpio_card_detect))
 788 +               gpio_free(pdata->gpio_card_detect);
 789 +err:
 790 +       return ret;
 791 +}
 792 +
 793 +static void jz4740_mmc_free_gpios(struct platform_device *pdev)
 794 +{
 795 +       struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
 796 +
 797 +       if (!pdata)
 798 +               return;
 799 +
 800 +       if (gpio_is_valid(pdata->gpio_power))
 801 +               gpio_free(pdata->gpio_power);
 802 +       if (gpio_is_valid(pdata->gpio_read_only))
 803 +               gpio_free(pdata->gpio_read_only);
 804 +       if (gpio_is_valid(pdata->gpio_card_detect))
 805 +               gpio_free(pdata->gpio_card_detect);
 806 +}
 807 +
 808 +static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
 809 +{
 810 +       int ret;
 811 +       struct mmc_host *mmc;
 812 +       struct jz4740_mmc_host *host;
 813 +       struct jz4740_mmc_platform_data *pdata;
 814 +
 815 +       pdata = pdev->dev.platform_data;
 816 +
 817 +       mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
 818 +
 819 +       if (!mmc) {
 820 +               dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
 821 +               return -ENOMEM;
 822 +       }
 823 +
 824 +       host = mmc_priv(mmc);
 825 +
 826 +       host->irq = platform_get_irq(pdev, 0);
 827 +
 828 +       if (host->irq < 0) {
 829 +               ret = host->irq;
 830 +               dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
 831 +               goto err_free_host;
 832 +       }
 833 +
 834 +       host->clk = clk_get(&pdev->dev, "mmc");
 835 +       if (!host->clk) {
 836 +               ret = -ENOENT;
 837 +               dev_err(&pdev->dev, "Failed to get mmc clock\n");
 838 +               goto err_free_host;
 839 +       }
 840 +
 841 +       host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 842 +
 843 +       if (!host->mem) {
 844 +               ret = -ENOENT;
 845 +               dev_err(&pdev->dev, "Failed to get base platform memory\n");
 846 +               goto err_clk_put;
 847 +       }
 848 +
 849 +       host->mem = request_mem_region(host->mem->start, resource_size(host->mem),
 850 +                                       pdev->name);
 851 +
 852 +       if (!host->mem) {
 853 +               ret = -EBUSY;
 854 +               dev_err(&pdev->dev, "Failed to request base memory region\n");
 855 +               goto err_clk_put;
 856 +       }
 857 +
 858 +       host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
 859 +
 860 +       if (!host->base) {
 861 +               ret = -EBUSY;
 862 +               dev_err(&pdev->dev, "Failed to ioremap base memory\n");
 863 +               goto err_release_mem_region;
 864 +       }
 865 +
 866 +       if (pdata && pdata->data_1bit)
 867 +               ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 868 +       else
 869 +               ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 870 +
 871 +       if (ret) {
 872 +               dev_err(&pdev->dev, "Failed to request function pins: %d\n", ret);
 873 +               goto err_iounmap;
 874 +       }
 875 +
 876 +       ret = jz4740_mmc_request_gpios(pdev);
 877 +       if (ret)
 878 +               goto err_gpio_bulk_free;
 879 +
 880 +       mmc->ops = &jz4740_mmc_ops;
 881 +       mmc->f_min = JZ_MMC_CLK_RATE / 128;
 882 +       mmc->f_max = JZ_MMC_CLK_RATE;
 883 +       mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 884 +       mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
 885 +       mmc->caps |= MMC_CAP_SDIO_IRQ;
 886 +       mmc->max_seg_size = 4096;
 887 +       mmc->max_phys_segs = 128;
 888 +
 889 +       mmc->max_blk_size = (1 << 10) - 1;
 890 +       mmc->max_blk_count = (1 << 15) - 1;
 891 +       mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 892 +
 893 +       host->mmc = mmc;
 894 +       host->pdev = pdev;
 895 +       host->pdata = pdata;
 896 +       host->max_clock = JZ_MMC_CLK_RATE;
 897 +       spin_lock_init(&host->lock);
 898 +       host->irq_mask = 0xffff;
 899 +
 900 +       host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
 901 +
 902 +       if (host->card_detect_irq < 0) {
 903 +               dev_warn(&pdev->dev, "Failed to get irq for card detect gpio\n");
 904 +       } else {
 905 +               ret = request_irq(host->card_detect_irq,
 906 +                       jz4740_mmc_card_detect_irq,
 907 +                       IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
 908 +                       "MMC card detect", host);
 909 +
 910 +               if (ret) {
 911 +                       dev_err(&pdev->dev, "Failed to request card detect irq");
 912 +                       goto err_free_gpios;
 913 +               }
 914 +       }
 915 +
 916 +       ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker,
 917 +               IRQF_DISABLED, dev_name(&pdev->dev), host);
 918 +       if (ret) {
 919 +               dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
 920 +               goto err_free_card_detect_irq;
 921 +       }
 922 +
 923 +       jz4740_mmc_reset(host);
 924 +       jz4740_mmc_clock_disable(host);
 925 +       setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
 926 +                       (unsigned long)host);
 927 +
 928 +       platform_set_drvdata(pdev, host);
 929 +       ret = mmc_add_host(mmc);
 930 +
 931 +       if (ret) {
 932 +               dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
 933 +               goto err_free_irq;
 934 +       }
 935 +       dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
 936 +
 937 +       return 0;
 938 +
 939 +err_free_irq:
 940 +       free_irq(host->irq, host);
 941 +err_free_card_detect_irq:
 942 +       if (host->card_detect_irq >= 0)
 943 +               free_irq(host->card_detect_irq, host);
 944 +err_free_gpios:
 945 +       jz4740_mmc_free_gpios(pdev);
 946 +err_gpio_bulk_free:
 947 +       if (pdata && pdata->data_1bit)
 948 +               jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 949 +       else
 950 +               jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 951 +err_iounmap:
 952 +       iounmap(host->base);
 953 +err_release_mem_region:
 954 +       release_mem_region(host->mem->start, resource_size(host->mem));
 955 +err_clk_put:
 956 +       clk_put(host->clk);
 957 +err_free_host:
 958 +       platform_set_drvdata(pdev, NULL);
 959 +       mmc_free_host(mmc);
 960 +
 961 +       return ret;
 962 +}
 963 +
 964 +static int __devexit jz4740_mmc_remove(struct platform_device *pdev)
 965 +{
 966 +       struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
 967 +       struct jz4740_mmc_platform_data *pdata = host->pdata;
 968 +
 969 +       del_timer_sync(&host->timeout_timer);
 970 +       jz4740_mmc_disable_irq(host, 0xff);
 971 +       jz4740_mmc_reset(host);
 972 +
 973 +       mmc_remove_host(host->mmc);
 974 +
 975 +       free_irq(host->irq, host);
 976 +       if (host->card_detect_irq >= 0)
 977 +               free_irq(host->card_detect_irq, host);
 978 +
 979 +       jz4740_mmc_free_gpios(pdev);
 980 +       if (pdata && pdata->data_1bit)
 981 +               jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 982 +       else
 983 +               jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 984 +
 985 +       iounmap(host->base);
 986 +       release_mem_region(host->mem->start, resource_size(host->mem));
 987 +
 988 +       clk_put(host->clk);
 989 +
 990 +       platform_set_drvdata(pdev, NULL);
 991 +       mmc_free_host(host->mmc);
 992 +
 993 +       return 0;
 994 +}
 995 +
 996 +#ifdef CONFIG_PM
 997 +static int jz4740_mmc_suspend(struct device *dev)
 998 +{
 999 +       struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1000 +       struct jz4740_mmc_platform_data *pdata = host->pdata;
1001 +
1002 +       mmc_suspend_host(host->mmc, PMSG_SUSPEND);
1003 +
1004 +       if (pdata && pdata->data_1bit)
1005 +               jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
1006 +       else
1007 +               jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
1008 +
1009 +       return 0;
1010 +}
1011 +
1012 +static int jz4740_mmc_resume(struct device *dev)
1013 +{
1014 +       struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1015 +       struct jz4740_mmc_platform_data *pdata = host->pdata;
1016 +
1017 +       if (pdata && pdata->data_1bit)
1018 +               jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
1019 +       else
1020 +               jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
1021 +
1022 +       mmc_resume_host(host->mmc);
1023 +
1024 +       return 0;
1025 +}
1026 +
1027 +const struct dev_pm_ops jz4740_mmc_pm_ops = {
1028 +       .suspend        = jz4740_mmc_suspend,
1029 +       .resume         = jz4740_mmc_resume,
1030 +       .poweroff       = jz4740_mmc_suspend,
1031 +       .restore        = jz4740_mmc_resume,
1032 +};
1033 +
1034 +#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
1035 +#else
1036 +#define JZ4740_MMC_PM_OPS NULL
1037 +#endif
1038 +
1039 +static struct platform_driver jz4740_mmc_driver = {
1040 +       .probe = jz4740_mmc_probe,
1041 +       .remove = __devexit_p(jz4740_mmc_remove),
1042 +       .driver = {
1043 +               .name = "jz4740-mmc",
1044 +               .owner = THIS_MODULE,
1045 +               .pm = JZ4740_MMC_PM_OPS,
1046 +       },
1047 +};
1048 +
1049 +static int __init jz4740_mmc_init(void)
1050 +{
1051 +       return platform_driver_register(&jz4740_mmc_driver);
1052 +}
1053 +module_init(jz4740_mmc_init);
1054 +
1055 +static void __exit jz4740_mmc_exit(void)
1056 +{
1057 +       platform_driver_unregister(&jz4740_mmc_driver);
1058 +}
1059 +module_exit(jz4740_mmc_exit);
1060 +
1061 +MODULE_DESCRIPTION("JZ4720/JZ4740 SD/MMC controller driver");
1062 +MODULE_LICENSE("GPL");
1063 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1064 diff --git a/include/linux/mmc/jz4740_mmc.h b/include/linux/mmc/jz4740_mmc.h
1065 new file mode 100644
1066 index 0000000..8543f43
1067 --- /dev/null
1068 +++ b/include/linux/mmc/jz4740_mmc.h
1069 @@ -0,0 +1,15 @@
1070 +#ifndef __LINUX_MMC_JZ4740_MMC
1071 +#define __LINUX_MMC_JZ4740_MMC
1072 +
1073 +struct jz4740_mmc_platform_data {
1074 +       int gpio_power;
1075 +       int gpio_card_detect;
1076 +       int gpio_read_only;
1077 +       unsigned card_detect_active_low:1;
1078 +       unsigned read_only_active_low:1;
1079 +       unsigned power_active_low:1;
1080 +
1081 +       unsigned data_1bit:1;
1082 +};
1083 +
1084 +#endif
1085 --
1086 1.5.6.5
1087