target/linux/xburst/files-2.6.32/drivers/usb/gadget/jz4740_udc.c

   1 /*
   2  * linux/drivers/usb/gadget/jz4740_udc.c
   3  *
   4  * Ingenic JZ4740 on-chip high speed USB device controller
   5  *
   6  * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
   7  * Author: <jlwei@ingenic.cn>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 /*
  16  * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
  17  *
  18  *  - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
  19  *  - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/delay.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/errno.h>
  29 #include <linux/init.h>
  30 #include <linux/list.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/proc_fs.h>
  33 #include <linux/usb.h>
  34 #include <linux/usb/gadget.h>
  35
  36 #include <asm/byteorder.h>
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/system.h>
  40 #include <asm/mach-jz4740/jz4740.h>
  41 #include <asm/mach-jz4740/clock.h>
  42
  43 #include "jz4740_udc.h"
  44
  45 #define JZ_REG_UDC_FADDR        0x00 /* Function Address 8-bit */
  46 #define JZ_REG_UDC_POWER        0x01 /* Power Managemetn 8-bit */
  47 #define JZ_REG_UDC_INTRIN       0x02 /* Interrupt IN 16-bit */
  48 #define JZ_REG_UDC_INTROUT      0x04 /* Interrupt OUT 16-bit */
  49 #define JZ_REG_UDC_INTRINE      0x06 /* Intr IN enable 16-bit */
  50 #define JZ_REG_UDC_INTROUTE     0x08 /* Intr OUT enable 16-bit */
  51 #define JZ_REG_UDC_INTRUSB      0x0a /* Interrupt USB 8-bit */
  52         #define JZ_REG_UDC_INTRUSBE     0x0b /* Interrupt USB Enable 8-bit */
  53 #define JZ_REG_UDC_FRAME        0x0c /* Frame number 16-bit */
  54 #define JZ_REG_UDC_INDEX        0x0e /* Index register 8-bit */
  55 #define JZ_REG_UDC_TESTMODE     0x0f /* USB test mode 8-bit */
  56
  57 #define JZ_REG_UDC_CSR0         0x12 /* EP0 CSR 8-bit */
  58 #define JZ_REG_UDC_INMAXP       0x10 /* EP1-2 IN Max Pkt Size 16-bit */
  59 #define JZ_REG_UDC_INCSR        0x12 /* EP1-2 IN CSR LSB 8/16bit */
  60 #define JZ_REG_UDC_INCSRH       0x13 /* EP1-2 IN CSR MSB 8-bit */
  61 #define JZ_REG_UDC_OUTMAXP      0x14 /* EP1 OUT Max Pkt Size 16-bit */
  62 #define JZ_REG_UDC_OUTCSR       0x16 /* EP1 OUT CSR LSB 8/16bit */
  63 #define JZ_REG_UDC_OUTCSRH      0x17 /* EP1 OUT CSR MSB 8-bit */
  64 #define JZ_REG_UDC_OUTCOUNT     0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
  65
  66 #define JZ_REG_UDC_EP_FIFO(x)   (4 * (x) + 0x20)
  67
  68 #define JZ_REG_UDC_EPINFO       0x78 /* Endpoint information */
  69 #define JZ_REG_UDC_RAMINFO      0x79 /* RAM information */
  70
  71 #define JZ_REG_UDC_INTR         0x200 /* DMA pending interrupts */
  72 #define JZ_REG_UDC_CNTL1        0x204 /* DMA channel 1 control */
  73 #define JZ_REG_UDC_ADDR1        0x208 /* DMA channel 1 AHB memory addr */
  74 #define JZ_REG_UDC_COUNT1       0x20c /* DMA channel 1 byte count */
  75 #define JZ_REG_UDC_CNTL2        0x214 /* DMA channel 2 control */
  76 #define JZ_REG_UDC_ADDR2        0x218 /* DMA channel 2 AHB memory addr */
  77 #define JZ_REG_UDC_COUNT2       0x21c /* DMA channel 2 byte count */
  78
  79 /* Power register bit masks */
  80 #define USB_POWER_SUSPENDM      0x01
  81 #define USB_POWER_RESUME        0x04
  82 #define USB_POWER_HSMODE        0x10
  83 #define USB_POWER_HSENAB        0x20
  84 #define USB_POWER_SOFTCONN      0x40
  85
  86 /* Interrupt register bit masks */
  87 #define USB_INTR_SUSPEND        0x01
  88 #define USB_INTR_RESUME         0x02
  89 #define USB_INTR_RESET          0x04
  90
  91 #define USB_INTR_EP0            0x0001
  92 #define USB_INTR_INEP1          0x0002
  93 #define USB_INTR_INEP2          0x0004
  94 #define USB_INTR_OUTEP1         0x0002
  95
  96 /* CSR0 bit masks */
  97 #define USB_CSR0_OUTPKTRDY      0x01
  98 #define USB_CSR0_INPKTRDY       0x02
  99 #define USB_CSR0_SENTSTALL      0x04
 100 #define USB_CSR0_DATAEND        0x08
 101 #define USB_CSR0_SETUPEND       0x10
 102 #define USB_CSR0_SENDSTALL      0x20
 103 #define USB_CSR0_SVDOUTPKTRDY   0x40
 104 #define USB_CSR0_SVDSETUPEND    0x80
 105
 106 /* Endpoint CSR register bits */
 107 #define USB_INCSRH_AUTOSET      0x80
 108 #define USB_INCSRH_ISO          0x40
 109 #define USB_INCSRH_MODE         0x20
 110 #define USB_INCSRH_DMAREQENAB   0x10
 111 #define USB_INCSRH_DMAREQMODE   0x04
 112 #define USB_INCSR_CDT           0x40
 113 #define USB_INCSR_SENTSTALL     0x20
 114 #define USB_INCSR_SENDSTALL     0x10
 115 #define USB_INCSR_FF            0x08
 116 #define USB_INCSR_UNDERRUN      0x04
 117 #define USB_INCSR_FFNOTEMPT     0x02
 118 #define USB_INCSR_INPKTRDY      0x01
 119 #define USB_OUTCSRH_AUTOCLR     0x80
 120 #define USB_OUTCSRH_ISO         0x40
 121 #define USB_OUTCSRH_DMAREQENAB  0x20
 122 #define USB_OUTCSRH_DNYT        0x10
 123 #define USB_OUTCSRH_DMAREQMODE  0x08
 124 #define USB_OUTCSR_CDT          0x80
 125 #define USB_OUTCSR_SENTSTALL    0x40
 126 #define USB_OUTCSR_SENDSTALL    0x20
 127 #define USB_OUTCSR_FF           0x10
 128 #define USB_OUTCSR_DATAERR      0x08
 129 #define USB_OUTCSR_OVERRUN      0x04
 130 #define USB_OUTCSR_FFFULL       0x02
 131 #define USB_OUTCSR_OUTPKTRDY    0x01
 132
 133 /* Testmode register bits */
 134 #define USB_TEST_SE0NAK         0x01
 135 #define USB_TEST_J              0x02
 136 #define USB_TEST_K              0x04
 137 #define USB_TEST_PACKET         0x08
 138
 139 /* DMA control bits */
 140 #define USB_CNTL_ENA            0x01
 141 #define USB_CNTL_DIR_IN         0x02
 142 #define USB_CNTL_MODE_1         0x04
 143 #define USB_CNTL_INTR_EN        0x08
 144 #define USB_CNTL_EP(n)          ((n) << 4)
 145 #define USB_CNTL_BURST_0        (0 << 9)
 146 #define USB_CNTL_BURST_4        (1 << 9)
 147 #define USB_CNTL_BURST_8        (2 << 9)
 148 #define USB_CNTL_BURST_16       (3 << 9)
 149
 150
 151 #ifndef DEBUG
 152 # define DEBUG(fmt,args...) do {} while(0)
 153 #endif
 154 #ifndef DEBUG_EP0
 155 # define NO_STATES
 156 # define DEBUG_EP0(fmt,args...) do {} while(0)
 157 #endif
 158 #ifndef DEBUG_SETUP
 159 # define DEBUG_SETUP(fmt,args...) do {} while(0)
 160 #endif
 161
 162 static unsigned int udc_debug = 0; /* 0: normal mode, 1: test udc cable type mode */
 163
 164 module_param(udc_debug, int, 0);
 165 MODULE_PARM_DESC(udc_debug, "test udc cable or power type");
 166
 167 static unsigned int use_dma = 0;   /* 1: use DMA, 0: use PIO */
 168
 169 module_param(use_dma, int, 0);
 170 MODULE_PARM_DESC(use_dma, "DMA mode enable flag");
 171
 172 struct jz4740_udc *the_controller;
 173
 174 /*
 175  * Local declarations.
 176  */
 177 static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
 178 static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
 179
 180 static void done(struct jz4740_ep *ep, struct jz4740_request *req,
 181                  int status);
 182 static void pio_irq_enable(struct jz4740_ep *ep);
 183 static void pio_irq_disable(struct jz4740_ep *ep);
 184 static void stop_activity(struct jz4740_udc *dev,
 185                           struct usb_gadget_driver *driver);
 186 static void nuke(struct jz4740_ep *ep, int status);
 187 static void flush(struct jz4740_ep *ep);
 188 static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
 189
 190 /*-------------------------------------------------------------------------*/
 191
 192 /* inline functions of register read/write/set/clear  */
 193
 194 static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
 195 {
 196         return readb(udc->base + reg);
 197 }
 198
 199 static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
 200 {
 201         return readw(udc->base + reg);
 202 }
 203
 204 static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
 205 {
 206         return readl(udc->base + reg);
 207 }
 208
 209 static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
 210 {
 211         writeb(val, udc->base + reg);
 212 }
 213
 214 static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
 215 {
 216         writew(val, udc->base + reg);
 217 }
 218
 219 static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
 220 {
 221         writel(val, udc->base + reg);
 222 }
 223
 224 static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
 225 {
 226         usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
 227 }
 228
 229 static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask)
 230 {
 231         usb_writew(udc, reg, usb_readw(udc, reg) | mask);
 232 }
 233
 234 static inline void usb_setl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
 235 {
 236         usb_writel(udc, reg, usb_readl(udc, reg) | mask);
 237 }
 238
 239 static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
 240 {
 241         usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
 242 }
 243
 244 static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
 245 {
 246         usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
 247 }
 248
 249 static inline void usb_clearl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
 250 {
 251         usb_writel(udc, reg, usb_readl(udc, reg) & ~mask);
 252 }
 253
 254 /*-------------------------------------------------------------------------*/
 255
 256 static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
 257 {
 258         usb_writeb(udc, JZ_REG_UDC_INDEX, index);
 259 }
 260
 261 static inline void jz_udc_select_ep(struct jz4740_ep *ep)
 262 {
 263         jz_udc_set_index(ep->dev, ep_index(ep));
 264 }
 265
 266 static inline int write_packet(struct jz4740_ep *ep,
 267                                    struct jz4740_request *req, int max)
 268 {
 269         uint8_t *buf;
 270         int length, nlong, nbyte;
 271         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 272
 273         buf = req->req.buf + req->req.actual;
 274         prefetch(buf);
 275
 276         length = req->req.length - req->req.actual;
 277         length = min(length, max);
 278         req->req.actual += length;
 279
 280         DEBUG("Write %d (max %d), fifo %x\n", length, max, ep->fifo);
 281
 282         nlong = length >> 2;
 283         nbyte = length & 0x3;
 284         while (nlong--) {
 285                 usb_writel(ep->dev, ep->fifo, *((uint32_t *)buf));
 286                 buf += 4;
 287         }
 288         while (nbyte--) {
 289                 usb_writeb(ep->dev, ep->fifo, *buf++);
 290         }
 291
 292         return length;
 293 }
 294
 295 static inline int read_packet(struct jz4740_ep *ep,
 296                                   struct jz4740_request *req, int count)
 297 {
 298         uint8_t *buf;
 299         int length, nlong, nbyte;
 300         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 301
 302         buf = req->req.buf + req->req.actual;
 303         prefetchw(buf);
 304
 305         length = req->req.length - req->req.actual;
 306         length = min(length, count);
 307         req->req.actual += length;
 308
 309         DEBUG("Read %d, fifo %x\n", length, ep->fifo);
 310
 311         nlong = length >> 2;
 312         nbyte = length & 0x3;
 313         while (nlong--) {
 314                 *((uint32_t *)buf) = usb_readl(ep->dev, ep->fifo);
 315                 buf += 4;
 316         }
 317         while (nbyte--) {
 318                 *buf++ = usb_readb(ep->dev, ep->fifo);
 319         }
 320
 321         return length;
 322 }
 323
 324 /*-------------------------------------------------------------------------*/
 325
 326 /*
 327  *      udc_disable - disable USB device controller
 328  */
 329 static void udc_disable(struct jz4740_udc *dev)
 330 {
 331         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 332
 333         udc_set_address(dev, 0);
 334
 335         /* Disable interrupts */
 336         usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
 337         usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
 338         usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
 339
 340         /* Disable DMA */
 341         usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
 342         usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
 343
 344         /* Disconnect from usb */
 345         usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
 346
 347         /* Disable the USB PHY */
 348 #ifdef CONFIG_SOC_JZ4740
 349         REG_CPM_SCR &= ~CPM_SCR_USBPHY_ENABLE;
 350 #elif defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D)
 351         REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE;
 352 #endif
 353
 354         dev->ep0state = WAIT_FOR_SETUP;
 355         dev->gadget.speed = USB_SPEED_UNKNOWN;
 356
 357         return;
 358 }
 359
 360 /*
 361  *      udc_reinit - initialize software state
 362  */
 363 static void udc_reinit(struct jz4740_udc *dev)
 364 {
 365         int i;
 366         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 367
 368         /* device/ep0 records init */
 369         INIT_LIST_HEAD(&dev->gadget.ep_list);
 370         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
 371         dev->ep0state = WAIT_FOR_SETUP;
 372
 373         for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
 374                 struct jz4740_ep *ep = &dev->ep[i];
 375
 376                 if (i != 0)
 377                         list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
 378
 379                 INIT_LIST_HEAD(&ep->queue);
 380                 ep->desc = 0;
 381                 ep->stopped = 0;
 382                 ep->pio_irqs = 0;
 383         }
 384 }
 385
 386 /* until it's enabled, this UDC should be completely invisible
 387  * to any USB host.
 388  */
 389 static void udc_enable(struct jz4740_udc *dev)
 390 {
 391         int i;
 392         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 393
 394         /* UDC state is incorrect - Added by River */
 395         if (dev->state != UDC_STATE_ENABLE) {
 396                 return;
 397         }
 398
 399         dev->gadget.speed = USB_SPEED_UNKNOWN;
 400
 401         /* Flush FIFO for each */
 402         for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
 403                 struct jz4740_ep *ep = &dev->ep[i];
 404
 405                 jz_udc_set_index(dev, ep_index(ep));
 406                 flush(ep);
 407         }
 408
 409         /* Set this bit to allow the UDC entering low-power mode when
 410          * there are no actions on the USB bus.
 411          * UDC still works during this bit was set.
 412          */
 413         __cpm_stop_udc();
 414
 415         /* Enable the USB PHY */
 416 #ifdef CONFIG_SOC_JZ4740
 417         REG_CPM_SCR |= CPM_SCR_USBPHY_ENABLE;
 418 #elif defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D)
 419         REG_CPM_OPCR |= CPM_OPCR_UDCPHY_ENABLE;
 420 #endif
 421
 422         /* Disable interrupts */
 423 /*      usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
 424         usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
 425         usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
 426
 427         /* Enable interrupts */
 428         usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
 429         usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
 430         /* Don't enable rest of the interrupts */
 431         /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
 432            usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
 433
 434         /* Enable SUSPEND */
 435         /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
 436
 437         /* Enable HS Mode */
 438         usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
 439
 440         /* Let host detect UDC:
 441          * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
 442          * transistor on and pull the USBDP pin HIGH.
 443          */
 444         usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
 445
 446         return;
 447 }
 448
 449 /*-------------------------------------------------------------------------*/
 450
 451 /* keeping it simple:
 452  * - one bus driver, initted first;
 453  * - one function driver, initted second
 454  */
 455
 456 /*
 457  * Register entry point for the peripheral controller driver.
 458  */
 459
 460 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 461 {
 462         struct jz4740_udc *dev = the_controller;
 463         int retval;
 464
 465         if (!driver || !driver->bind) {
 466                 return -EINVAL;
 467         }
 468
 469         if (!dev) {
 470                 return -ENODEV;
 471         }
 472
 473         if (dev->driver) {
 474                 return -EBUSY;
 475         }
 476
 477         /* hook up the driver */
 478         dev->driver = driver;
 479         dev->gadget.dev.driver = &driver->driver;
 480
 481         retval = driver->bind(&dev->gadget);
 482         if (retval) {
 483                 DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
 484                             driver->driver.name, retval);
 485                 dev->driver = 0;
 486                 return retval;
 487         }
 488
 489         /* then enable host detection and ep0; and we're ready
 490          * for set_configuration as well as eventual disconnect.
 491          */
 492         udc_enable(dev);
 493
 494         DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
 495               driver->driver.name);
 496
 497         return 0;
 498 }
 499
 500 EXPORT_SYMBOL(usb_gadget_register_driver);
 501
 502 static void stop_activity(struct jz4740_udc *dev,
 503                           struct usb_gadget_driver *driver)
 504 {
 505         int i;
 506
 507         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 508
 509         /* don't disconnect drivers more than once */
 510         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
 511                 driver = 0;
 512         dev->gadget.speed = USB_SPEED_UNKNOWN;
 513
 514         /* prevent new request submissions, kill any outstanding requests  */
 515         for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
 516                 struct jz4740_ep *ep = &dev->ep[i];
 517
 518                 ep->stopped = 1;
 519
 520                 jz_udc_set_index(dev, ep_index(ep));
 521                 nuke(ep, -ESHUTDOWN);
 522         }
 523
 524         /* report disconnect; the driver is already quiesced */
 525         if (driver) {
 526                 spin_unlock(&dev->lock);
 527                 driver->disconnect(&dev->gadget);
 528                 spin_lock(&dev->lock);
 529         }
 530
 531         /* re-init driver-visible data structures */
 532         udc_reinit(dev);
 533 }
 534
 535
 536 /*
 537  * Unregister entry point for the peripheral controller driver.
 538  */
 539 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
 540 {
 541         struct jz4740_udc *dev = the_controller;
 542         unsigned long flags;
 543         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 544
 545         if (!dev)
 546                 return -ENODEV;
 547         if (!driver || driver != dev->driver)
 548                 return -EINVAL;
 549         if (!driver->unbind)
 550                 return -EBUSY;
 551
 552         spin_lock_irqsave(&dev->lock, flags);
 553         dev->driver = 0;
 554         stop_activity(dev, driver);
 555         spin_unlock_irqrestore(&dev->lock, flags);
 556
 557         driver->unbind(&dev->gadget);
 558
 559         udc_disable(dev);
 560
 561         DEBUG("unregistered driver '%s'\n", driver->driver.name);
 562
 563         return 0;
 564 }
 565
 566 EXPORT_SYMBOL(usb_gadget_unregister_driver);
 567
 568 /*-------------------------------------------------------------------------*/
 569
 570 /*
 571  * Starting DMA using mode 1
 572  */
 573 static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req)
 574 {
 575         struct jz4740_udc *dev = ep->dev;
 576         uint32_t count = req->req.length;
 577         uint32_t physaddr = virt_to_phys((void *)req->req.buf);
 578
 579         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 580
 581         jz_udc_select_ep(ep);
 582
 583         if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */
 584                 ep->reg_addr = JZ_REG_UDC_ADDR1;
 585
 586                 dma_cache_wback_inv((unsigned long)req->req.buf, count);
 587
 588                 pio_irq_enable(ep);
 589
 590                 usb_writeb(dev, JZ_REG_UDC_INCSRH,
 591                            USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
 592
 593                 usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr);
 594                 usb_writel(dev, JZ_REG_UDC_COUNT1, count);
 595                 usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 |
 596                            USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
 597         }
 598         else { /* Bulk-OUT transfer using DMA channel 2 */
 599                 ep->reg_addr = JZ_REG_UDC_ADDR2;
 600
 601                 dma_cache_wback_inv((unsigned long)req->req.buf, count);
 602
 603                 pio_irq_enable(ep);
 604
 605                 usb_setb(dev, JZ_REG_UDC_OUTCSRH,
 606                          USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
 607
 608                 usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr);
 609                 usb_writel(dev, JZ_REG_UDC_COUNT2, count);
 610                 usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 |
 611                            USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
 612         }
 613 }
 614
 615 /*-------------------------------------------------------------------------*/
 616
 617 /** Write request to FIFO (max write == maxp size)
 618  *  Return:  0 = still running, 1 = completed, negative = errno
 619  *  NOTE: INDEX register must be set for EP
 620  */
 621 static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
 622 {
 623         struct jz4740_udc *dev = ep->dev;
 624         uint32_t max, csr;
 625         uint32_t physaddr = virt_to_phys((void *)req->req.buf);
 626
 627         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 628         max = le16_to_cpu(ep->desc->wMaxPacketSize);
 629
 630         if (use_dma) {
 631                 uint32_t dma_count;
 632
 633                 /* DMA interrupt generated due to the last packet loaded into the FIFO */
 634
 635                 dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
 636                 req->req.actual += dma_count;
 637
 638                 if (dma_count % max) {
 639                         /* If the last packet is less than MAXP, set INPKTRDY manually */
 640                         usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
 641                 }
 642
 643                 done(ep, req, 0);
 644                 if (list_empty(&ep->queue)) {
 645                         pio_irq_disable(ep);
 646                         return 1;
 647                 }
 648                 else {
 649                         /* advance the request queue */
 650                         req = list_entry(ep->queue.next, struct jz4740_request, queue);
 651                         kick_dma(ep, req);
 652                         return 0;
 653                 }
 654         }
 655
 656         /*
 657          * PIO mode handling starts here ...
 658          */
 659
 660         csr = usb_readb(dev, ep->csr);
 661
 662         if (!(csr & USB_INCSR_FFNOTEMPT)) {
 663                 unsigned count;
 664                 int is_last, is_short;
 665
 666                 count = write_packet(ep, req, max);
 667                 usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
 668
 669                 /* last packet is usually short (or a zlp) */
 670                 if (unlikely(count != max))
 671                         is_last = is_short = 1;
 672                 else {
 673                         if (likely(req->req.length != req->req.actual)
 674                             || req->req.zero)
 675                                 is_last = 0;
 676                         else
 677                                 is_last = 1;
 678                         /* interrupt/iso maxpacket may not fill the fifo */
 679                         is_short = unlikely(max < ep_maxpacket(ep));
 680                 }
 681
 682                 DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
 683                       ep->ep.name, count,
 684                       is_last ? "/L" : "", is_short ? "/S" : "",
 685                       req->req.length - req->req.actual, req);
 686
 687                 /* requests complete when all IN data is in the FIFO */
 688                 if (is_last) {
 689                         done(ep, req, 0);
 690                         if (list_empty(&ep->queue)) {
 691                                 pio_irq_disable(ep);
 692                         }
 693                         return 1;
 694                 }
 695         } else {
 696                 DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
 697         }
 698
 699         return 0;
 700 }
 701
 702 /** Read to request from FIFO (max read == bytes in fifo)
 703  *  Return:  0 = still running, 1 = completed, negative = errno
 704  *  NOTE: INDEX register must be set for EP
 705  */
 706 static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
 707 {
 708         struct jz4740_udc *dev = ep->dev;
 709         uint32_t csr;
 710         unsigned count, is_short;
 711         uint32_t physaddr = virt_to_phys((void *)req->req.buf);
 712
 713         if (use_dma) {
 714                 uint32_t dma_count;
 715
 716                 /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */
 717
 718                 dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
 719                 req->req.actual += dma_count;
 720
 721                 /* Disable interrupt and DMA */
 722                 pio_irq_disable(ep);
 723                 usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
 724
 725                 /* Read all bytes from this packet */
 726                 count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
 727                 count = read_packet(ep, req, count);
 728
 729                 if (count) {
 730                         /* If the last packet is greater than zero, clear OUTPKTRDY manually */
 731                         usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
 732                 }
 733                 done(ep, req, 0);
 734
 735                 if (!list_empty(&ep->queue)) {
 736                         /* advance the request queue */
 737                         req = list_entry(ep->queue.next, struct jz4740_request, queue);
 738                         kick_dma(ep, req);
 739                 }
 740
 741                 return 1;
 742         }
 743
 744         /*
 745          * PIO mode handling starts here ...
 746          */
 747
 748         /* make sure there's a packet in the FIFO. */
 749         csr = usb_readb(dev, ep->csr);
 750         if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
 751                 DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
 752                 return -EINVAL;
 753         }
 754
 755         /* read all bytes from this packet */
 756         count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
 757
 758         is_short = (count < ep->ep.maxpacket);
 759
 760         count = read_packet(ep, req, count);
 761
 762         DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
 763               ep->ep.name, csr, count,
 764               is_short ? "/S" : "", req, req->req.actual, req->req.length);
 765
 766         /* Clear OutPktRdy */
 767         usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
 768
 769         /* completion */
 770         if (is_short || req->req.actual == req->req.length) {
 771                 done(ep, req, 0);
 772
 773                 if (list_empty(&ep->queue))
 774                         pio_irq_disable(ep);
 775                 return 1;
 776         }
 777
 778         /* finished that packet.  the next one may be waiting... */
 779         return 0;
 780 }
 781
 782 /*
 783  *      done - retire a request; caller blocked irqs
 784  *  INDEX register is preserved to keep same
 785  */
 786 static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
 787 {
 788         unsigned int stopped = ep->stopped;
 789         unsigned long flags;
 790         uint32_t index;
 791
 792         DEBUG("%s, %p\n", __FUNCTION__, ep);
 793         list_del_init(&req->queue);
 794
 795         if (likely(req->req.status == -EINPROGRESS))
 796                 req->req.status = status;
 797         else
 798                 status = req->req.status;
 799
 800         if (status && status != -ESHUTDOWN)
 801                 DEBUG("complete %s req %p stat %d len %u/%u\n",
 802                       ep->ep.name, &req->req, status,
 803                       req->req.actual, req->req.length);
 804
 805         /* don't modify queue heads during completion callback */
 806         ep->stopped = 1;
 807         /* Read current index (completion may modify it) */
 808         spin_lock_irqsave(&ep->dev->lock, flags);
 809         index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
 810
 811         req->req.complete(&ep->ep, &req->req);
 812
 813         /* Restore index */
 814         jz_udc_set_index(ep->dev, index);
 815         spin_unlock_irqrestore(&ep->dev->lock, flags);
 816         ep->stopped = stopped;
 817 }
 818
 819 /** Enable EP interrupt */
 820 static void pio_irq_enable(struct jz4740_ep *ep)
 821 {
 822         uint8_t index = ep_index(ep);
 823         struct jz4740_udc *dev = ep->dev;
 824         DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
 825
 826         if (ep_is_in(ep)) {
 827                 switch (index) {
 828                 case 1:
 829                 case 2:
 830                         usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index));
 831                         dev->in_mask |= BIT(index);
 832                         break;
 833                 default:
 834                         DEBUG("Unknown endpoint: %d\n", index);
 835                         break;
 836                 }
 837         }
 838         else {
 839                 switch (index) {
 840                 case 1:
 841                         usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index));
 842                         dev->out_mask |= BIT(index);
 843                         break;
 844                 default:
 845                         DEBUG("Unknown endpoint: %d\n", index);
 846                         break;
 847                 }
 848         }
 849 }
 850
 851 /** Disable EP interrupt */
 852 static void pio_irq_disable(struct jz4740_ep *ep)
 853 {
 854         uint8_t index = ep_index(ep);
 855         struct jz4740_udc *dev = ep->dev;
 856
 857         DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
 858
 859         if (ep_is_in(ep)) {
 860                 switch (ep_index(ep)) {
 861                 case 1:
 862                 case 2:
 863                         usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index));
 864                         dev->in_mask &= ~BIT(index);
 865                         break;
 866                 default:
 867                         DEBUG("Unknown endpoint: %d\n", index);
 868                         break;
 869                 }
 870         }
 871         else {
 872                 switch (ep_index(ep)) {
 873                 case 1:
 874                         usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index));
 875                         dev->out_mask &= ~BIT(index);
 876                         break;
 877                 default:
 878                         DEBUG("Unknown endpoint: %d\n", index);
 879                         break;
 880             }
 881         }
 882 }
 883
 884 /*
 885  *      nuke - dequeue ALL requests
 886  */
 887 static void nuke(struct jz4740_ep *ep, int status)
 888 {
 889         struct jz4740_request *req;
 890
 891         DEBUG("%s, %p\n", __FUNCTION__, ep);
 892
 893         /* Flush FIFO */
 894         flush(ep);
 895
 896         /* called with irqs blocked */
 897         while (!list_empty(&ep->queue)) {
 898                 req = list_entry(ep->queue.next, struct jz4740_request, queue);
 899                 done(ep, req, status);
 900         }
 901
 902         /* Disable IRQ if EP is enabled (has descriptor) */
 903         if (ep->desc)
 904                 pio_irq_disable(ep);
 905 }
 906
 907 /** Flush EP FIFO
 908  * NOTE: INDEX register must be set before this call
 909  */
 910 static void flush(struct jz4740_ep *ep)
 911 {
 912         DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
 913
 914         switch (ep->type) {
 915         case ep_bulk_in:
 916         case ep_interrupt:
 917                 usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
 918                 break;
 919         case ep_bulk_out:
 920                 usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
 921                 break;
 922         case ep_control:
 923                 break;
 924         }
 925 }
 926
 927 /**
 928  * jz4740_in_epn - handle IN interrupt
 929  */
 930 static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
 931 {
 932         uint32_t csr;
 933         struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
 934         struct jz4740_request *req;
 935         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 936
 937         jz_udc_set_index(dev, ep_index(ep));
 938
 939         csr = usb_readb(dev, ep->csr);
 940         DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
 941
 942         if (csr & USB_INCSR_SENTSTALL) {
 943                 DEBUG("USB_INCSR_SENTSTALL\n");
 944                 usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
 945                 return;
 946         }
 947
 948         if (!ep->desc) {
 949                 DEBUG("%s: NO EP DESC\n", __FUNCTION__);
 950                 return;
 951         }
 952
 953         if (list_empty(&ep->queue))
 954                 req = 0;
 955         else
 956                 req = list_entry(ep->queue.next, struct jz4740_request, queue);
 957
 958         DEBUG("req: %p\n", req);
 959
 960         if (!req)
 961                 return;
 962
 963         write_fifo(ep, req);
 964 }
 965
 966 /*
 967  * Bulk OUT (recv)
 968  */
 969 static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
 970 {
 971         struct jz4740_ep *ep = &dev->ep[ep_idx];
 972         struct jz4740_request *req;
 973
 974         DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
 975
 976         jz_udc_set_index(dev, ep_index(ep));
 977         if (ep->desc) {
 978                 uint32_t csr;
 979
 980                 if (use_dma) {
 981                         /* DMA starts here ... */
 982                         if (list_empty(&ep->queue))
 983                                 req = 0;
 984                         else
 985                                 req = list_entry(ep->queue.next, struct jz4740_request, queue);
 986
 987                         if (req)
 988                                 read_fifo(ep, req);
 989                         return;
 990                 }
 991
 992                 /*
 993                  * PIO mode starts here ...
 994                  */
 995
 996                 while ((csr = usb_readb(dev, ep->csr)) &
 997                        (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
 998                         DEBUG("%s: %x\n", __FUNCTION__, csr);
 999
1000                         if (csr & USB_OUTCSR_SENTSTALL) {
1001                                 DEBUG("%s: stall sent, flush fifo\n",
1002                                       __FUNCTION__);
1003                                 /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
1004                                 flush(ep);
1005                         } else if (csr & USB_OUTCSR_OUTPKTRDY) {
1006                                 if (list_empty(&ep->queue))
1007                                         req = 0;
1008                                 else
1009                                         req =
1010                                                 list_entry(ep->queue.next,
1011                                                            struct jz4740_request,
1012                                                            queue);
1013
1014                                 if (!req) {
1015                                         DEBUG("%s: NULL REQ %d\n",
1016                                               __FUNCTION__, ep_idx);
1017                                         break;
1018                                 } else {
1019                                         read_fifo(ep, req);
1020                                 }
1021                         }
1022                 }
1023         } else {
1024                 /* Throw packet away.. */
1025                 DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
1026                 flush(ep);
1027         }
1028 }
1029
1030 /** Halt specific EP
1031  *  Return 0 if success
1032  *  NOTE: Sets INDEX register to EP !
1033  */
1034 static int jz4740_set_halt(struct usb_ep *_ep, int value)
1035 {
1036         struct jz4740_udc *dev;
1037         struct jz4740_ep *ep;
1038         unsigned long flags;
1039
1040         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1041
1042         ep = container_of(_ep, struct jz4740_ep, ep);
1043         if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1044                 DEBUG("%s, bad ep\n", __FUNCTION__);
1045                 return -EINVAL;
1046         }
1047
1048         dev = ep->dev;
1049
1050         spin_lock_irqsave(&dev->lock, flags);
1051
1052         jz_udc_select_ep(ep);
1053
1054         DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
1055
1056         if (ep_index(ep) == 0) {
1057                 /* EP0 */
1058                 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
1059         } else if (ep_is_in(ep)) {
1060                 uint32_t csr = usb_readb(dev, ep->csr);
1061                 if (value && ((csr & USB_INCSR_FFNOTEMPT)
1062                               || !list_empty(&ep->queue))) {
1063                         /*
1064                          * Attempts to halt IN endpoints will fail (returning -EAGAIN)
1065                          * if any transfer requests are still queued, or if the controller
1066                          * FIFO still holds bytes that the host hasn\92t collected.
1067                          */
1068                         spin_unlock_irqrestore(&dev->lock, flags);
1069                         DEBUG
1070                             ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
1071                              (csr & USB_INCSR_FFNOTEMPT),
1072                              !list_empty(&ep->queue));
1073                         return -EAGAIN;
1074                 }
1075                 flush(ep);
1076                 if (value) {
1077                         usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
1078                 }
1079                 else {
1080                         usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
1081                         usb_setb(dev, ep->csr, USB_INCSR_CDT);
1082                 }
1083         } else {
1084
1085                 flush(ep);
1086                 if (value) {
1087                         usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1088                 }
1089                 else {
1090                         usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1091                         usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
1092                 }
1093         }
1094
1095         if (value) {
1096                 ep->stopped = 1;
1097         } else {
1098                 ep->stopped = 0;
1099         }
1100
1101         spin_unlock_irqrestore(&dev->lock, flags);
1102
1103         DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
1104
1105         return 0;
1106 }
1107
1108
1109 static int jz4740_ep_enable(struct usb_ep *_ep,
1110                             const struct usb_endpoint_descriptor *desc)
1111 {
1112         struct jz4740_ep *ep;
1113         struct jz4740_udc *dev;
1114         unsigned long flags;
1115         uint32_t max, csrh = 0;
1116
1117         DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
1118
1119         if (!_ep || !desc)
1120                 return -EINVAL;
1121
1122         ep = container_of(_ep, struct jz4740_ep, ep);
1123         if (ep->desc || ep->type == ep_control
1124             || desc->bDescriptorType != USB_DT_ENDPOINT
1125             || ep->bEndpointAddress != desc->bEndpointAddress) {
1126                 DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
1127                 return -EINVAL;
1128         }
1129
1130         /* xfer types must match, except that interrupt ~= bulk */
1131         if (ep->bmAttributes != desc->bmAttributes
1132             && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
1133             && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
1134                 DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
1135                 return -EINVAL;
1136         }
1137
1138         dev = ep->dev;
1139         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
1140                 DEBUG("%s, bogus device state\n", __FUNCTION__);
1141                 return -ESHUTDOWN;
1142         }
1143
1144         max = le16_to_cpu(desc->wMaxPacketSize);
1145
1146         spin_lock_irqsave(&ep->dev->lock, flags);
1147
1148         /* Configure the endpoint */
1149         jz_udc_set_index(dev, desc->bEndpointAddress & 0x0F);
1150         if (ep_is_in(ep)) {
1151                 usb_writew(dev, JZ_REG_UDC_INMAXP, max);
1152                 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1153                 case USB_ENDPOINT_XFER_BULK:
1154                 case USB_ENDPOINT_XFER_INT:
1155                         csrh &= ~USB_INCSRH_ISO;
1156                         break;
1157                 case USB_ENDPOINT_XFER_ISOC:
1158                         csrh |= USB_INCSRH_ISO;
1159                         break;
1160                 }
1161                 usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1162         }
1163         else {
1164                 usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1165                 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1166                 case USB_ENDPOINT_XFER_BULK:
1167                          csrh &= ~USB_OUTCSRH_ISO;
1168                         break;
1169                 case USB_ENDPOINT_XFER_INT:
1170                         csrh &= ~USB_OUTCSRH_ISO;
1171                         csrh |= USB_OUTCSRH_DNYT;
1172                         break;
1173                 case USB_ENDPOINT_XFER_ISOC:
1174                         csrh |= USB_OUTCSRH_ISO;
1175                         break;
1176                 }
1177                 usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1178         }
1179
1180
1181         ep->stopped = 0;
1182         ep->desc = desc;
1183         ep->pio_irqs = 0;
1184         ep->ep.maxpacket = max;
1185
1186         spin_unlock_irqrestore(&ep->dev->lock, flags);
1187
1188         /* Reset halt state (does flush) */
1189         jz4740_set_halt(_ep, 0);
1190
1191         DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1192
1193         return 0;
1194 }
1195
1196 /** Disable EP
1197  *  NOTE: Sets INDEX register
1198  */
1199 static int jz4740_ep_disable(struct usb_ep *_ep)
1200 {
1201         struct jz4740_ep *ep;
1202         unsigned long flags;
1203
1204         DEBUG("%s, %p\n", __FUNCTION__, _ep);
1205
1206         ep = container_of(_ep, struct jz4740_ep, ep);
1207         if (!_ep || !ep->desc) {
1208                 DEBUG("%s, %s not enabled\n", __FUNCTION__,
1209                       _ep ? ep->ep.name : NULL);
1210                 return -EINVAL;
1211         }
1212
1213         spin_lock_irqsave(&ep->dev->lock, flags);
1214
1215         jz_udc_select_ep(ep);
1216
1217         /* Nuke all pending requests (does flush) */
1218         nuke(ep, -ESHUTDOWN);
1219
1220         /* Disable ep IRQ */
1221         pio_irq_disable(ep);
1222
1223         ep->desc = 0;
1224         ep->stopped = 1;
1225
1226         spin_unlock_irqrestore(&ep->dev->lock, flags);
1227
1228         DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1229         return 0;
1230 }
1231
1232 static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1233 {
1234         struct jz4740_request *req;
1235
1236         DEBUG("%s, %p\n", __FUNCTION__, ep);
1237
1238         req = kzalloc(sizeof(*req), gfp_flags);
1239         if (!req)
1240                 return 0;
1241
1242         INIT_LIST_HEAD(&req->queue);
1243
1244         return &req->req;
1245 }
1246
1247 static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1248 {
1249         struct jz4740_request *req;
1250
1251         DEBUG("%s, %p\n", __FUNCTION__, ep);
1252
1253         req = container_of(_req, struct jz4740_request, req);
1254         WARN_ON(!list_empty(&req->queue));
1255         kfree(req);
1256 }
1257
1258 /*--------------------------------------------------------------------*/
1259
1260 /** Queue one request
1261  *  Kickstart transfer if needed
1262  *  NOTE: Sets INDEX register
1263  */
1264 static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1265                         gfp_t gfp_flags)
1266 {
1267         struct jz4740_request *req;
1268         struct jz4740_ep *ep;
1269         struct jz4740_udc *dev;
1270         unsigned long flags;
1271
1272         DEBUG("%s, %p\n", __FUNCTION__, _ep);
1273
1274         req = container_of(_req, struct jz4740_request, req);
1275         if (unlikely
1276             (!_req || !_req->complete || !_req->buf
1277              || !list_empty(&req->queue))) {
1278                 DEBUG("%s, bad params\n", __FUNCTION__);
1279                 return -EINVAL;
1280         }
1281
1282         ep = container_of(_ep, struct jz4740_ep, ep);
1283         if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1284                 DEBUG("%s, bad ep\n", __FUNCTION__);
1285                 return -EINVAL;
1286         }
1287
1288         dev = ep->dev;
1289         if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1290                 DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1291                 return -ESHUTDOWN;
1292         }
1293
1294         DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1295               _req->buf);
1296
1297         spin_lock_irqsave(&dev->lock, flags);
1298
1299         _req->status = -EINPROGRESS;
1300         _req->actual = 0;
1301
1302         /* kickstart this i/o queue? */
1303         DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1304               ep->stopped);
1305         if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1306                 uint32_t csr;
1307
1308                 if (unlikely(ep_index(ep) == 0)) {
1309                         /* EP0 */
1310                         list_add_tail(&req->queue, &ep->queue);
1311                         jz4740_ep0_kick(dev, ep);
1312                         req = 0;
1313                 } else if (use_dma) {
1314                         /* DMA */
1315                         kick_dma(ep, req);
1316                 }
1317                 /* PIO */
1318                 else if (ep_is_in(ep)) {
1319                         /* EP1 & EP2 */
1320                         jz_udc_set_index(dev, ep_index(ep));
1321                         csr = usb_readb(dev, ep->csr);
1322                         pio_irq_enable(ep);
1323                         if (!(csr & USB_INCSR_FFNOTEMPT)) {
1324                                 if (write_fifo(ep, req) == 1)
1325                                         req = 0;
1326                         }
1327                 } else {
1328                         /* EP1 */
1329                         jz_udc_set_index(dev, ep_index(ep));
1330                         csr = usb_readb(dev, ep->csr);
1331                         pio_irq_enable(ep);
1332                         if (csr & USB_OUTCSR_OUTPKTRDY) {
1333                                 if (read_fifo(ep, req) == 1)
1334                                         req = 0;
1335                         }
1336                 }
1337         }
1338
1339         /* pio or dma irq handler advances the queue. */
1340         if (likely(req != 0))
1341                 list_add_tail(&req->queue, &ep->queue);
1342
1343         spin_unlock_irqrestore(&dev->lock, flags);
1344
1345         return 0;
1346 }
1347
1348 /* dequeue JUST ONE request */
1349 static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1350 {
1351         struct jz4740_ep *ep;
1352         struct jz4740_request *req;
1353         unsigned long flags;
1354
1355         DEBUG("%s, %p\n", __FUNCTION__, _ep);
1356
1357         ep = container_of(_ep, struct jz4740_ep, ep);
1358         if (!_ep || ep->type == ep_control)
1359                 return -EINVAL;
1360
1361         spin_lock_irqsave(&ep->dev->lock, flags);
1362
1363         /* make sure it's actually queued on this endpoint */
1364         list_for_each_entry(req, &ep->queue, queue) {
1365                 if (&req->req == _req)
1366                         break;
1367         }
1368         if (&req->req != _req) {
1369                 spin_unlock_irqrestore(&ep->dev->lock, flags);
1370                 return -EINVAL;
1371         }
1372         done(ep, req, -ECONNRESET);
1373
1374         spin_unlock_irqrestore(&ep->dev->lock, flags);
1375         return 0;
1376 }
1377
1378 /** Return bytes in EP FIFO
1379  *  NOTE: Sets INDEX register to EP
1380  */
1381 static int jz4740_fifo_status(struct usb_ep *_ep)
1382 {
1383         uint32_t csr;
1384         int count = 0;
1385         struct jz4740_ep *ep;
1386         unsigned long flags;
1387
1388         ep = container_of(_ep, struct jz4740_ep, ep);
1389         if (!_ep) {
1390                 DEBUG("%s, bad ep\n", __FUNCTION__);
1391                 return -ENODEV;
1392         }
1393
1394         DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1395
1396         /* LPD can't report unclaimed bytes from IN fifos */
1397         if (ep_is_in(ep))
1398                 return -EOPNOTSUPP;
1399
1400         spin_lock_irqsave(&ep->dev->lock, flags);
1401         jz_udc_set_index(ep->dev, ep_index(ep));
1402
1403         csr = usb_readb(ep->dev, ep->csr);
1404         if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1405             csr & 0x1) {
1406                 count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1407         }
1408
1409         spin_unlock_irqrestore(&ep->dev->lock, flags);
1410
1411         return count;
1412 }
1413
1414 /** Flush EP FIFO
1415  *  NOTE: Sets INDEX register to EP
1416  */
1417 static void jz4740_fifo_flush(struct usb_ep *_ep)
1418 {
1419         struct jz4740_ep *ep;
1420         unsigned long flags;
1421
1422         DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1423
1424         ep = container_of(_ep, struct jz4740_ep, ep);
1425         if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1426                 DEBUG("%s, bad ep\n", __FUNCTION__);
1427                 return;
1428         }
1429
1430         spin_lock_irqsave(&ep->dev->lock, flags);
1431
1432         jz_udc_set_index(ep->dev, ep_index(ep));
1433         flush(ep);
1434
1435         spin_unlock_irqrestore(&ep->dev->lock, flags);
1436 }
1437
1438 /****************************************************************/
1439 /* End Point 0 related functions                                */
1440 /****************************************************************/
1441
1442 /* return:  0 = still running, 1 = completed, negative = errno */
1443 static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1444 {
1445         uint32_t max;
1446         unsigned count;
1447         int is_last;
1448
1449     DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1450         max = ep_maxpacket(ep);
1451
1452         count = write_packet(ep, req, max);
1453
1454         /* last packet is usually short (or a zlp) */
1455         if (unlikely(count != max))
1456                 is_last = 1;
1457         else {
1458                 if (likely(req->req.length != req->req.actual) || req->req.zero)
1459                         is_last = 0;
1460                 else
1461                         is_last = 1;
1462         }
1463
1464         DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1465                   ep->ep.name, count,
1466                   is_last ? "/L" : "", req->req.length - req->req.actual, req);
1467
1468         /* requests complete when all IN data is in the FIFO */
1469         if (is_last) {
1470                 done(ep, req, 0);
1471                 return 1;
1472         }
1473
1474         return 0;
1475 }
1476
1477 static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1478                                        unsigned char *cp, int max)
1479 {
1480         int bytes;
1481         int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1482
1483         if (count > max)
1484                 count = max;
1485         bytes = count;
1486         while (count--)
1487                 *cp++ = usb_readb(ep->dev, ep->fifo);
1488
1489         return bytes;
1490 }
1491
1492 static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1493                                          unsigned char *cp, int count)
1494 {
1495         DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1496         while (count--)
1497                 usb_writeb(ep->dev, ep->fifo, *cp++);
1498 }
1499
1500 static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1501 {
1502         struct jz4740_udc *dev = ep->dev;
1503         uint32_t csr;
1504         uint8_t *buf;
1505         unsigned bufferspace, count, is_short;
1506
1507         DEBUG_EP0("%s\n", __FUNCTION__);
1508
1509         csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1510         if (!(csr & USB_CSR0_OUTPKTRDY))
1511                 return 0;
1512
1513         buf = req->req.buf + req->req.actual;
1514         prefetchw(buf);
1515         bufferspace = req->req.length - req->req.actual;
1516
1517         /* read all bytes from this packet */
1518         if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1519                 count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1520                 req->req.actual += min(count, bufferspace);
1521         } else                  /* zlp */
1522                 count = 0;
1523
1524         is_short = (count < ep->ep.maxpacket);
1525         DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1526                   ep->ep.name, csr, count,
1527                   is_short ? "/S" : "", req, req->req.actual, req->req.length);
1528
1529         while (likely(count-- != 0)) {
1530                 uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1531
1532                 if (unlikely(bufferspace == 0)) {
1533                         /* this happens when the driver's buffer
1534                          * is smaller than what the host sent.
1535                          * discard the extra data.
1536                          */
1537                         if (req->req.status != -EOVERFLOW)
1538                                 DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1539                                           count);
1540                         req->req.status = -EOVERFLOW;
1541                 } else {
1542                         *buf++ = byte;
1543                         bufferspace--;
1544                 }
1545         }
1546
1547         /* completion */
1548         if (is_short || req->req.actual == req->req.length) {
1549                 done(ep, req, 0);
1550                 return 1;
1551         }
1552
1553         /* finished that packet.  the next one may be waiting... */
1554         return 0;
1555 }
1556
1557 /**
1558  * udc_set_address - set the USB address for this device
1559  * @address:
1560  *
1561  * Called from control endpoint function after it decodes a set address setup packet.
1562  */
1563 static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1564 {
1565         DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1566
1567         dev->usb_address = address;
1568         usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1569 }
1570
1571 /*
1572  * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1573  *      - if error
1574  *              set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1575  *      - else
1576  *              set USB_CSR0_SVDOUTPKTRDY bit
1577                                 if last set USB_CSR0_DATAEND bit
1578  */
1579 static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1580 {
1581         struct jz4740_request *req;
1582         struct jz4740_ep *ep = &dev->ep[0];
1583         int ret;
1584
1585         DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1586
1587         if (list_empty(&ep->queue))
1588                 req = 0;
1589         else
1590                 req = list_entry(ep->queue.next, struct jz4740_request, queue);
1591
1592         if (req) {
1593                 if (req->req.length == 0) {
1594                         DEBUG_EP0("ZERO LENGTH OUT!\n");
1595                         usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1596                         dev->ep0state = WAIT_FOR_SETUP;
1597                         return;
1598                 } else if (kickstart) {
1599                         usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1600                         return;
1601                 }
1602                 ret = read_fifo_ep0(ep, req);
1603                 if (ret) {
1604                         /* Done! */
1605                         DEBUG_EP0("%s: finished, waiting for status\n",
1606                                   __FUNCTION__);
1607                         usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1608                         dev->ep0state = WAIT_FOR_SETUP;
1609                 } else {
1610                         /* Not done yet.. */
1611                         DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1612                         usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1613                 }
1614         } else {
1615                 DEBUG_EP0("NO REQ??!\n");
1616         }
1617 }
1618
1619 /*
1620  * DATA_STATE_XMIT
1621  */
1622 static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1623 {
1624         struct jz4740_request *req;
1625         struct jz4740_ep *ep = &dev->ep[0];
1626         int ret, need_zlp = 0;
1627
1628         DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1629
1630         if (list_empty(&ep->queue))
1631                 req = 0;
1632         else
1633                 req = list_entry(ep->queue.next, struct jz4740_request, queue);
1634
1635         if (!req) {
1636                 DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1637                 return 0;
1638         }
1639
1640         if (req->req.length == 0) {
1641                 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1642                 dev->ep0state = WAIT_FOR_SETUP;
1643                 return 1;
1644         }
1645
1646         if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1647                 /* Next write will end with the packet size, */
1648                 /* so we need zero-length-packet */
1649                 need_zlp = 1;
1650         }
1651
1652         ret = write_fifo_ep0(ep, req);
1653
1654         if (ret == 1 && !need_zlp) {
1655                 /* Last packet */
1656                 DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1657
1658                 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1659                 dev->ep0state = WAIT_FOR_SETUP;
1660         } else {
1661                 DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1662                 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1663         }
1664
1665         if (need_zlp) {
1666                 DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1667                 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1668                 dev->ep0state = DATA_STATE_NEED_ZLP;
1669         }
1670
1671         return 1;
1672 }
1673
1674 static int jz4740_handle_get_status(struct jz4740_udc *dev,
1675                                     struct usb_ctrlrequest *ctrl)
1676 {
1677         struct jz4740_ep *ep0 = &dev->ep[0];
1678         struct jz4740_ep *qep;
1679         int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1680         uint16_t val = 0;
1681
1682     DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1683
1684         if (reqtype == USB_RECIP_INTERFACE) {
1685                 /* This is not supported.
1686                  * And according to the USB spec, this one does nothing..
1687                  * Just return 0
1688                  */
1689                 DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1690         } else if (reqtype == USB_RECIP_DEVICE) {
1691                 DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1692                 val |= (1 << 0);        /* Self powered */
1693                 /*val |= (1<<1); *//* Remote wakeup */
1694         } else if (reqtype == USB_RECIP_ENDPOINT) {
1695                 int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1696
1697                 DEBUG_SETUP
1698                         ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1699                          ep_num, ctrl->wLength);
1700
1701                 if (ctrl->wLength > 2 || ep_num > 3)
1702                         return -EOPNOTSUPP;
1703
1704                 qep = &dev->ep[ep_num];
1705                 if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1706                     && ep_index(qep) != 0) {
1707                         return -EOPNOTSUPP;
1708                 }
1709
1710                 jz_udc_set_index(dev, ep_index(qep));
1711
1712                 /* Return status on next IN token */
1713                 switch (qep->type) {
1714                 case ep_control:
1715                         val =
1716                             (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1717                             USB_CSR0_SENDSTALL;
1718                         break;
1719                 case ep_bulk_in:
1720                 case ep_interrupt:
1721                         val =
1722                             (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1723                             USB_INCSR_SENDSTALL;
1724                         break;
1725                 case ep_bulk_out:
1726                         val =
1727                             (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1728                             USB_OUTCSR_SENDSTALL;
1729                         break;
1730                 }
1731
1732                 /* Back to EP0 index */
1733                 jz_udc_set_index(dev, 0);
1734
1735                 DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1736                             ctrl->wIndex, val);
1737         } else {
1738                 DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1739                 return -EOPNOTSUPP;
1740         }
1741
1742         /* Clear "out packet ready" */
1743         usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1744         /* Put status to FIFO */
1745         jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1746         /* Issue "In packet ready" */
1747         usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1748
1749         return 0;
1750 }
1751
1752 /*
1753  * WAIT_FOR_SETUP (OUTPKTRDY)
1754  *      - read data packet from EP0 FIFO
1755  *      - decode command
1756  *      - if error
1757  *              set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1758  *      - else
1759  *              set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1760  */
1761 static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1762 {
1763         struct jz4740_ep *ep = &dev->ep[0];
1764         struct usb_ctrlrequest ctrl;
1765         int i;
1766
1767         DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1768
1769         /* Nuke all previous transfers */
1770         nuke(ep, -EPROTO);
1771
1772         /* read control req from fifo (8 bytes) */
1773         jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1774
1775         DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1776                     ctrl.bRequestType, ctrl.bRequest,
1777                     ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1778
1779         /* Set direction of EP0 */
1780         if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1781                 ep->bEndpointAddress |= USB_DIR_IN;
1782         } else {
1783                 ep->bEndpointAddress &= ~USB_DIR_IN;
1784         }
1785
1786         /* Handle some SETUP packets ourselves */
1787         switch (ctrl.bRequest) {
1788         case USB_REQ_SET_ADDRESS:
1789                 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1790                         break;
1791
1792                 DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1793                 udc_set_address(dev, ctrl.wValue);
1794                 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1795                 return;
1796
1797         case USB_REQ_SET_CONFIGURATION:
1798                 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1799                         break;
1800
1801                 DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1802 /*              usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1803
1804                 /* Enable RESUME and SUSPEND interrupts */
1805                 usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1806                 break;
1807
1808         case USB_REQ_SET_INTERFACE:
1809                 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1810                         break;
1811
1812                 DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1813 /*              usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1814                 break;
1815
1816         case USB_REQ_GET_STATUS:
1817                 if (jz4740_handle_get_status(dev, &ctrl) == 0)
1818                         return;
1819
1820         case USB_REQ_CLEAR_FEATURE:
1821         case USB_REQ_SET_FEATURE:
1822                 if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1823                         struct jz4740_ep *qep;
1824                         int ep_num = (ctrl.wIndex & 0x0f);
1825
1826                         /* Support only HALT feature */
1827                         if (ctrl.wValue != 0 || ctrl.wLength != 0
1828                             || ep_num > 3 || ep_num < 1)
1829                                 break;
1830
1831                         qep = &dev->ep[ep_num];
1832                         spin_unlock(&dev->lock);
1833                         if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1834                                 DEBUG_SETUP("SET_FEATURE (%d)\n",
1835                                             ep_num);
1836                                 jz4740_set_halt(&qep->ep, 1);
1837                         } else {
1838                                 DEBUG_SETUP("CLR_FEATURE (%d)\n",
1839                                             ep_num);
1840                                 jz4740_set_halt(&qep->ep, 0);
1841                         }
1842                         spin_lock(&dev->lock);
1843
1844                         jz_udc_set_index(dev, 0);
1845
1846                         /* Reply with a ZLP on next IN token */
1847                         usb_setb(dev, JZ_REG_UDC_CSR0,
1848                                  (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1849                         return;
1850                 }
1851                 break;
1852
1853         default:
1854                 break;
1855         }
1856
1857         /* gadget drivers see class/vendor specific requests,
1858          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1859          * and more.
1860          */
1861         if (dev->driver) {
1862                 /* device-2-host (IN) or no data setup command, process immediately */
1863                 spin_unlock(&dev->lock);
1864
1865                 i = dev->driver->setup(&dev->gadget, &ctrl);
1866                 spin_lock(&dev->lock);
1867
1868                 if (unlikely(i < 0)) {
1869                         /* setup processing failed, force stall */
1870                         DEBUG_SETUP
1871                             ("  --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1872                              i);
1873                         jz_udc_set_index(dev, 0);
1874                         usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1875
1876                         /* ep->stopped = 1; */
1877                         dev->ep0state = WAIT_FOR_SETUP;
1878                 }
1879                 else {
1880                         DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1881 /*                      if (!ctrl.wLength) {
1882                                 usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1883                         }*/
1884                 }
1885         }
1886 }
1887
1888 /*
1889  * DATA_STATE_NEED_ZLP
1890  */
1891 static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1892 {
1893         DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1894
1895         usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1896         dev->ep0state = WAIT_FOR_SETUP;
1897 }
1898
1899 /*
1900  * handle ep0 interrupt
1901  */
1902 static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1903 {
1904         struct jz4740_ep *ep = &dev->ep[0];
1905         uint32_t csr;
1906
1907     DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1908         /* Set index 0 */
1909         jz_udc_set_index(dev, 0);
1910         csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1911
1912         DEBUG_EP0("%s: csr = %x  state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1913
1914         /*
1915          * if SENT_STALL is set
1916          *      - clear the SENT_STALL bit
1917          */
1918         if (csr & USB_CSR0_SENTSTALL) {
1919                 DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1920                 usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1921                 nuke(ep, -ECONNABORTED);
1922                 dev->ep0state = WAIT_FOR_SETUP;
1923                 return;
1924         }
1925
1926         /*
1927          * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1928          *      - fill EP0 FIFO
1929          *      - if last packet
1930          *      -       set IN_PKT_RDY | DATA_END
1931          *      - else
1932          *              set IN_PKT_RDY
1933          */
1934         if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1935                 DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1936                           __FUNCTION__);
1937
1938                 switch (dev->ep0state) {
1939                 case DATA_STATE_XMIT:
1940                         DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1941                         jz4740_ep0_in(dev, csr);
1942                         return;
1943                 case DATA_STATE_NEED_ZLP:
1944                         DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1945                         jz4740_ep0_in_zlp(dev, csr);
1946                         return;
1947                 default:
1948                         /* Stall? */
1949 //                      DEBUG_EP0("Odd state!! state = %s\n",
1950 //                                state_names[dev->ep0state]);
1951                         dev->ep0state = WAIT_FOR_SETUP;
1952                         /* nuke(ep, 0); */
1953                         /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1954 //                      break;
1955                         return;
1956                 }
1957         }
1958
1959         /*
1960          * if SETUPEND is set
1961          *      - abort the last transfer
1962          *      - set SERVICED_SETUP_END_BIT
1963          */
1964         if (csr & USB_CSR0_SETUPEND) {
1965                 DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1966
1967                 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1968                 nuke(ep, 0);
1969                 dev->ep0state = WAIT_FOR_SETUP;
1970         }
1971
1972         /*
1973          * if USB_CSR0_OUTPKTRDY is set
1974          *      - read data packet from EP0 FIFO
1975          *      - decode command
1976          *      - if error
1977          *              set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1978          *      - else
1979          *              set SVDOUTPKTRDY | DATAEND bits
1980          */
1981         if (csr & USB_CSR0_OUTPKTRDY) {
1982
1983                 DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1984                           csr);
1985
1986                 switch (dev->ep0state) {
1987                 case WAIT_FOR_SETUP:
1988                         DEBUG_EP0("WAIT_FOR_SETUP\n");
1989                         jz4740_ep0_setup(dev, csr);
1990                         break;
1991
1992                 case DATA_STATE_RECV:
1993                         DEBUG_EP0("DATA_STATE_RECV\n");
1994                         jz4740_ep0_out(dev, csr, 0);
1995                         break;
1996
1997                 default:
1998                         /* send stall? */
1999                         DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
2000                                   dev->ep0state);
2001                         break;
2002                 }
2003         }
2004 }
2005
2006 static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
2007 {
2008         uint32_t csr;
2009
2010         jz_udc_set_index(dev, 0);
2011
2012         DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
2013
2014         /* Clear "out packet ready" */
2015
2016         if (ep_is_in(ep)) {
2017                 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
2018                 csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2019                 dev->ep0state = DATA_STATE_XMIT;
2020                 jz4740_ep0_in(dev, csr);
2021         } else {
2022                 csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2023                 dev->ep0state = DATA_STATE_RECV;
2024                 jz4740_ep0_out(dev, csr, 1);
2025         }
2026 }
2027
2028 /** Handle USB RESET interrupt
2029  */
2030 static void jz4740_reset_irq(struct jz4740_udc *dev)
2031 {
2032         dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
2033                 USB_SPEED_HIGH : USB_SPEED_FULL;
2034
2035         DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, dev->usb_address,
2036                     (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
2037 }
2038
2039 /*
2040  *      jz4740 usb device interrupt handler.
2041  */
2042 static irqreturn_t jz4740_udc_irq(int irq, void *_dev)
2043 {
2044         struct jz4740_udc *dev = _dev;
2045         uint8_t index;
2046
2047         uint32_t intr_usb = usb_readb(dev, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
2048         uint32_t intr_in  = usb_readw(dev, JZ_REG_UDC_INTRIN);
2049         uint32_t intr_out = usb_readw(dev, JZ_REG_UDC_INTROUT);
2050         uint32_t intr_dma = usb_readb(dev, JZ_REG_UDC_INTR);
2051
2052         if (!intr_usb && !intr_in && !intr_out && !intr_dma)
2053                 return IRQ_HANDLED;
2054
2055
2056         DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
2057               intr_out, intr_in, intr_usb);
2058
2059         spin_lock(&dev->lock);
2060         index = usb_readb(dev, JZ_REG_UDC_INDEX);
2061
2062         /* Check for resume from suspend mode */
2063         if ((intr_usb & USB_INTR_RESUME) &&
2064             (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
2065                 DEBUG("USB resume\n");
2066                 dev->driver->resume(&dev->gadget); /* We have suspend(), so we must have resume() too. */
2067         }
2068
2069         /* Check for system interrupts */
2070         if (intr_usb & USB_INTR_RESET) {
2071                 DEBUG("USB reset\n");
2072                 jz4740_reset_irq(dev);
2073         }
2074
2075         /* Check for endpoint 0 interrupt */
2076         if (intr_in & USB_INTR_EP0) {
2077                 DEBUG("USB_INTR_EP0 (control)\n");
2078                 jz4740_handle_ep0(dev, intr_in);
2079         }
2080
2081         /* Check for Bulk-IN DMA interrupt */
2082         if (intr_dma & 0x1) {
2083                 int ep_num;
2084                 struct jz4740_ep *ep;
2085                 ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
2086                 ep = &dev->ep[ep_num + 1];
2087                 jz_udc_set_index(dev, ep_num);
2088                 usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
2089 /*              jz4740_in_epn(dev, ep_num, intr_in);*/
2090         }
2091
2092         /* Check for Bulk-OUT DMA interrupt */
2093         if (intr_dma & 0x2) {
2094                 int ep_num;
2095                 ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
2096                 jz4740_out_epn(dev, ep_num, intr_out);
2097         }
2098
2099         /* Check for each configured endpoint interrupt */
2100         if (intr_in & USB_INTR_INEP1) {
2101                 DEBUG("USB_INTR_INEP1\n");
2102                 jz4740_in_epn(dev, 1, intr_in);
2103         }
2104
2105         if (intr_in & USB_INTR_INEP2) {
2106                 DEBUG("USB_INTR_INEP2\n");
2107                 jz4740_in_epn(dev, 2, intr_in);
2108         }
2109
2110         if (intr_out & USB_INTR_OUTEP1) {
2111                 DEBUG("USB_INTR_OUTEP1\n");
2112                 jz4740_out_epn(dev, 1, intr_out);
2113         }
2114
2115         /* Check for suspend mode */
2116         if ((intr_usb & USB_INTR_SUSPEND) &&
2117             (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
2118                 DEBUG("USB suspend\n");
2119                 dev->driver->suspend(&dev->gadget);
2120                 /* Host unloaded from us, can do something, such as flushing
2121                  the NAND block cache etc. */
2122         }
2123
2124     jz_udc_set_index(dev, index);
2125
2126         spin_unlock(&dev->lock);
2127
2128         return IRQ_HANDLED;
2129 }
2130
2131
2132
2133 /*-------------------------------------------------------------------------*/
2134
2135 /* Common functions - Added by River */
2136 static struct jz4740_udc udc_dev;
2137
2138 static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
2139 {
2140         return container_of(gadget, struct jz4740_udc, gadget);
2141 }
2142 /* End added */
2143
2144 static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
2145 {
2146         DEBUG("%s, %p\n", __FUNCTION__, _gadget);
2147         return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
2148 }
2149
2150 static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
2151 {
2152         /* host may not have enabled remote wakeup */
2153         /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
2154            return -EHOSTUNREACH;
2155            udc_set_mask_UDCCR(UDCCR_RSM); */
2156         return -ENOTSUPP;
2157 }
2158
2159 static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
2160 {
2161         struct jz4740_udc *udc = gadget_to_udc(_gadget);
2162
2163         unsigned long flags;
2164
2165         local_irq_save(flags);
2166
2167         if (on) {
2168                 udc->state = UDC_STATE_ENABLE;
2169                 udc_enable(udc);
2170         } else {
2171                 udc->state = UDC_STATE_DISABLE;
2172                 udc_disable(udc);
2173         }
2174
2175         local_irq_restore(flags);
2176
2177         return 0;
2178 }
2179
2180 static const struct usb_gadget_ops jz4740_udc_ops = {
2181         .get_frame = jz4740_udc_get_frame,
2182         .wakeup = jz4740_udc_wakeup,
2183         .pullup = jz4740_udc_pullup,
2184         /* current versions must always be self-powered */
2185 };
2186
2187 static struct usb_ep_ops jz4740_ep_ops = {
2188         .enable         = jz4740_ep_enable,
2189         .disable        = jz4740_ep_disable,
2190
2191         .alloc_request  = jz4740_alloc_request,
2192         .free_request   = jz4740_free_request,
2193
2194         .queue          = jz4740_queue,
2195         .dequeue        = jz4740_dequeue,
2196
2197         .set_halt       = jz4740_set_halt,
2198         .fifo_status    = jz4740_fifo_status,
2199         .fifo_flush     = jz4740_fifo_flush,
2200 };
2201
2202
2203 /*-------------------------------------------------------------------------*/
2204
2205 static struct jz4740_udc udc_dev = {
2206         .usb_address = 0,
2207         .gadget = {
2208                 .ops = &jz4740_udc_ops,
2209                 .ep0 = &udc_dev.ep[0].ep,
2210                 .name = "jz-udc",
2211                 .dev = {
2212                         .init_name = "gadget",
2213                 },
2214         },
2215
2216         /* control endpoint */
2217         .ep[0] = {
2218                 .ep = {
2219                         .name = "ep0",
2220                         .ops = &jz4740_ep_ops,
2221                         .maxpacket = EP0_MAXPACKETSIZE,
2222                 },
2223                 .dev = &udc_dev,
2224
2225                 .bEndpointAddress = 0,
2226                 .bmAttributes = 0,
2227
2228                 .type = ep_control,
2229                 .fifo = JZ_REG_UDC_EP_FIFO(0),
2230                 .csr = JZ_REG_UDC_CSR0,
2231         },
2232
2233         /* bulk out endpoint */
2234         .ep[1] = {
2235                 .ep = {
2236                         .name = "ep1out-bulk",
2237                         .ops = &jz4740_ep_ops,
2238                         .maxpacket = EPBULK_MAXPACKETSIZE,
2239                 },
2240                 .dev = &udc_dev,
2241
2242                 .bEndpointAddress = 1,
2243                 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2244
2245                 .type = ep_bulk_out,
2246                 .fifo = JZ_REG_UDC_EP_FIFO(1),
2247                 .csr = JZ_REG_UDC_OUTCSR,
2248         },
2249
2250         /* bulk in endpoint */
2251         .ep[2] = {
2252                 .ep = {
2253                         .name = "ep1in-bulk",
2254                         .ops = &jz4740_ep_ops,
2255                         .maxpacket = EPBULK_MAXPACKETSIZE,
2256                 },
2257                 .dev = &udc_dev,
2258
2259                 .bEndpointAddress = 1 | USB_DIR_IN,
2260                 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2261
2262                 .type = ep_bulk_in,
2263                 .fifo = JZ_REG_UDC_EP_FIFO(1),
2264                 .csr = JZ_REG_UDC_INCSR,
2265         },
2266
2267         /* interrupt in endpoint */
2268         .ep[3] = {
2269                 .ep = {
2270                         .name = "ep2in-int",
2271                         .ops = &jz4740_ep_ops,
2272                         .maxpacket = EPINTR_MAXPACKETSIZE,
2273                 },
2274                 .dev = &udc_dev,
2275
2276                 .bEndpointAddress = 2 | USB_DIR_IN,
2277                 .bmAttributes = USB_ENDPOINT_XFER_INT,
2278
2279                 .type = ep_interrupt,
2280                 .fifo = JZ_REG_UDC_EP_FIFO(2),
2281                 .csr = JZ_REG_UDC_INCSR,
2282         },
2283 };
2284
2285 static void gadget_release(struct device *_dev)
2286 {
2287 }
2288
2289
2290 static int jz4740_udc_probe(struct platform_device *pdev)
2291 {
2292         struct jz4740_udc *dev = &udc_dev;
2293         int ret;
2294
2295         spin_lock_init(&dev->lock);
2296         the_controller = dev;
2297
2298         dev->dev = &pdev->dev;
2299         dev_set_name(&dev->gadget.dev, "gadget");
2300         dev->gadget.dev.parent = &pdev->dev;
2301         dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2302         dev->gadget.dev.release = gadget_release;
2303
2304         ret = device_register(&dev->gadget.dev);
2305         if (ret)
2306                 return ret;
2307
2308         platform_set_drvdata(pdev, dev);
2309
2310         dev->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2311
2312         if (!dev->mem) {
2313                 ret = -ENOENT;
2314                 dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2315                 goto err_device_unregister;
2316         }
2317
2318         dev->mem = request_mem_region(dev->mem->start, resource_size(dev->mem), pdev->name);
2319
2320         if (!dev->mem) {
2321                 ret = -EBUSY;
2322                 dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2323                 goto err_device_unregister;
2324         }
2325
2326         dev->base = ioremap(dev->mem->start, resource_size(dev->mem));
2327
2328         if (!dev->base) {
2329                 ret = -EBUSY;
2330                 dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2331                 goto err_release_mem_region;
2332         }
2333
2334         dev->irq = platform_get_irq(pdev, 0);
2335
2336         ret = request_irq(dev->irq, jz4740_udc_irq, IRQF_DISABLED,
2337                             pdev->name, dev);
2338         if (ret) {
2339                 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2340                 goto err_iounmap;
2341         }
2342
2343         udc_disable(dev);
2344         udc_reinit(dev);
2345
2346         return 0;
2347
2348 err_iounmap:
2349         iounmap(dev->base);
2350 err_release_mem_region:
2351         release_mem_region(dev->mem->start, resource_size(dev->mem));
2352 err_device_unregister:
2353         device_unregister(&dev->gadget.dev);
2354         platform_set_drvdata(pdev, NULL);
2355
2356         the_controller = 0;
2357
2358         return ret;
2359 }
2360
2361 static int jz4740_udc_remove(struct platform_device *pdev)
2362 {
2363         struct jz4740_udc *dev = platform_get_drvdata(pdev);
2364
2365         if (dev->driver)
2366                 return -EBUSY;
2367
2368         udc_disable(dev);
2369 #ifdef  UDC_PROC_FILE
2370         remove_proc_entry(proc_node_name, NULL);
2371 #endif
2372
2373         free_irq(dev->irq, dev);
2374         iounmap(dev->base);
2375         release_mem_region(dev->mem->start, resource_size(dev->mem));
2376
2377         platform_set_drvdata(pdev, NULL);
2378         device_unregister(&dev->gadget.dev);
2379         the_controller = NULL;
2380
2381         return 0;
2382 }
2383
2384 static struct platform_driver udc_driver = {
2385         .probe          = jz4740_udc_probe,
2386         .remove         = jz4740_udc_remove,
2387         .driver         = {
2388                 .name   = "jz-udc",
2389                 .owner  = THIS_MODULE,
2390         },
2391 };
2392
2393 /*-------------------------------------------------------------------------*/
2394
2395 static int __init udc_init (void)
2396 {
2397         return platform_driver_register(&udc_driver);
2398 }
2399
2400 static void __exit udc_exit (void)
2401 {
2402         platform_driver_unregister(&udc_driver);
2403 }
2404
2405 module_init(udc_init);
2406 module_exit(udc_exit);
2407
2408 MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2409 MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2410 MODULE_LICENSE("GPL");