target/linux/sunxi/patches-3.12/143-add-dtsi-for-reset.patch

   1 From 2a906d06b21968803ce504348864908ad1ed66ac Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Tue, 24 Sep 2013 11:10:41 +0300
   4 Subject: [PATCH] ARM: sun6i: Add the reset controller to the DTSI
   5
   6 The A31 has a reset controller IP that maintains a few other IPs in
   7 reset, among which we can find the UARTs, high speed timers or the I2C.
   8 Now that we have support for them, add the reset controllers to the DTSI.
   9
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
  13  1 file changed, 24 insertions(+)
  14
  15 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
  16 index c1751a6..c7e0658 100644
  17 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
  18 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
  19 @@ -209,6 +209,24 @@
  20                         };
  21                 };
  22
  23 +               ahb1_rst: reset@01c202c0 {
  24 +                       #reset-cells = <1>;
  25 +                       compatible = "allwinner,sun6i-a31-ahb1-reset";
  26 +                       reg = <0x01c202c0 0xc>;
  27 +               };
  28 +
  29 +               apb1_rst: reset@01c202d0 {
  30 +                       #reset-cells = <1>;
  31 +                       compatible = "allwinner,sun4i-clock-reset";
  32 +                       reg = <0x01c202d0 0x4>;
  33 +               };
  34 +
  35 +               apb2_rst: reset@01c202d8 {
  36 +                       #reset-cells = <1>;
  37 +                       compatible = "allwinner,sun4i-clock-reset";
  38 +                       reg = <0x01c202d8 0x4>;
  39 +               };
  40 +
  41                 timer@01c20c00 {
  42                         compatible = "allwinner,sun4i-timer";
  43                         reg = <0x01c20c00 0xa0>;
  44 @@ -232,6 +250,7 @@
  45                         reg-shift = <2>;
  46                         reg-io-width = <4>;
  47                         clocks = <&apb2_gates 16>;
  48 +                       resets = <&apb2_rst 16>;
  49                         status = "disabled";
  50                 };
  51
  52 @@ -242,6 +261,7 @@
  53                         reg-shift = <2>;
  54                         reg-io-width = <4>;
  55                         clocks = <&apb2_gates 17>;
  56 +                       resets = <&apb2_rst 17>;
  57                         status = "disabled";
  58                 };
  59
  60 @@ -252,6 +272,7 @@
  61                         reg-shift = <2>;
  62                         reg-io-width = <4>;
  63                         clocks = <&apb2_gates 18>;
  64 +                       resets = <&apb2_rst 18>;
  65                         status = "disabled";
  66                 };
  67
  68 @@ -262,6 +283,7 @@
  69                         reg-shift = <2>;
  70                         reg-io-width = <4>;
  71                         clocks = <&apb2_gates 19>;
  72 +                       resets = <&apb2_rst 19>;
  73                         status = "disabled";
  74                 };
  75
  76 @@ -272,6 +294,7 @@
  77                         reg-shift = <2>;
  78                         reg-io-width = <4>;
  79                         clocks = <&apb2_gates 20>;
  80 +                       resets = <&apb2_rst 20>;
  81                         status = "disabled";
  82                 };
  83
  84 @@ -282,6 +305,7 @@
  85                         reg-shift = <2>;
  86                         reg-io-width = <4>;
  87                         clocks = <&apb2_gates 21>;
  88 +                       resets = <&apb2_rst 21>;
  89                         status = "disabled";
  90                 };
  91
  92 --
  93 1.8.4
  94