target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-mci.c

   1 /*
   2  *  linux/drivers/mmc/host/glamo-mmc.c - Glamo MMC driver
   3  *
   4  *  Copyright (C) 2007 Openmoko, Inc,  Andy Green <andy@openmoko.com>
   5  *  Based on S3C MMC driver that was:
   6  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/mmc/mmc.h>
  15 #include <linux/mmc/sd.h>
  16 #include <linux/mmc/host.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/irq.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/crc7.h>
  24 #include <linux/scatterlist.h>
  25 #include <linux/io.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/mfd/glamo.h>
  28
  29 #include "glamo-core.h"
  30 #include "glamo-regs.h"
  31
  32 #define DRIVER_NAME "glamo-mci"
  33
  34 struct glamo_mci_host {
  35         struct platform_device *pdev;
  36         struct glamo_mmc_platform_data *pdata;
  37         struct mmc_host        *mmc;
  38         struct resource        *mmio_mem;
  39         struct resource        *data_mem;
  40         void __iomem           *mmio_base;
  41         u16 __iomem            *data_base;
  42
  43         struct regulator *regulator;
  44         struct mmc_request *mrq;
  45
  46         unsigned int clk_rate;
  47
  48         unsigned short vdd;
  49         char           power_mode;
  50
  51         unsigned char request_counter;
  52
  53         struct timer_list disable_timer;
  54
  55         struct work_struct irq_work;
  56
  57         unsigned clk_enabled : 1;
  58 };
  59
  60 static void glamo_mci_send_request(struct mmc_host *mmc, struct mmc_request* mrq);
  61 static void glamo_mci_send_command(struct glamo_mci_host *host,
  62                                   struct mmc_command *cmd);
  63
  64 /*
  65  * Max SD clock rate
  66  *
  67  * held at /(3 + 1) due to concerns of 100R recommended series resistor
  68  * allows 16MHz @ 4-bit --> 8MBytes/sec raw
  69  *
  70  * you can override this on kernel commandline using
  71  *
  72  *   glamo_mci.sd_max_clk=10000000
  73  *
  74  * for example
  75  */
  76
  77 static int sd_max_clk = 50000000;
  78 module_param(sd_max_clk, int, 0644);
  79
  80 /*
  81  * Slow SD clock rate
  82  *
  83  * you can override this on kernel commandline using
  84  *
  85  *   glamo_mci.sd_slow_ratio=8
  86  *
  87  * for example
  88  *
  89  * platform callback is used to decide effective clock rate, if not
  90  * defined then max is used, if defined and returns nonzero, rate is
  91  * divided by this factor
  92  */
  93
  94 static int sd_slow_ratio = 8;
  95 module_param(sd_slow_ratio, int, 0644);
  96
  97 /*
  98  * Post-power SD clock rate
  99  *
 100  * you can override this on kernel commandline using
 101  *
 102  *   glamo_mci.sd_post_power_clock=1000000
 103  *
 104  * for example
 105  *
 106  * After changing power to card, clock is held at this rate until first bulk
 107  * transfer completes
 108  */
 109
 110 static int sd_post_power_clock = 1000000;
 111 module_param(sd_post_power_clock, int, 0644);
 112
 113
 114 static inline void glamo_reg_write(struct glamo_mci_host *glamo,
 115                                 u_int16_t reg, u_int16_t val)
 116 {
 117         writew(val, glamo->mmio_base + reg);
 118 }
 119
 120 static inline u_int16_t glamo_reg_read(struct glamo_mci_host *glamo,
 121                                    u_int16_t reg)
 122 {
 123         return readw(glamo->mmio_base + reg);
 124 }
 125
 126 static void glamo_reg_set_bit_mask(struct glamo_mci_host *glamo,
 127                                 u_int16_t reg, u_int16_t mask,
 128                                 u_int16_t val)
 129 {
 130         u_int16_t tmp;
 131
 132         val &= mask;
 133
 134         tmp = glamo_reg_read(glamo, reg);
 135         tmp &= ~mask;
 136         tmp |= val;
 137         glamo_reg_write(glamo, reg, tmp);
 138 }
 139
 140 static void glamo_mci_clock_disable(struct glamo_mci_host *host) {
 141         if (host->clk_enabled) {
 142                 glamo_engine_div_disable(host->pdata->core, GLAMO_ENGINE_MMC);
 143                 host->clk_enabled = 0;
 144         }
 145 }
 146
 147 static void glamo_mci_clock_enable(struct glamo_mci_host *host) {
 148         del_timer_sync(&host->disable_timer);
 149
 150         if (!host->clk_enabled) {
 151                 glamo_engine_div_enable(host->pdata->core, GLAMO_ENGINE_MMC);
 152                 host->clk_enabled = 1;
 153         }
 154 }
 155
 156 static void glamo_mci_disable_timer(unsigned long data) {
 157         struct glamo_mci_host *host = (struct glamo_mci_host *)data;
 158         glamo_mci_clock_disable(host);
 159 }
 160
 161
 162 static void do_pio_read(struct glamo_mci_host *host, struct mmc_data *data)
 163 {
 164         struct scatterlist *sg;
 165         u16 __iomem *from_ptr = host->data_base;
 166         void *sg_pointer;
 167
 168         dev_dbg(&host->pdev->dev, "pio_read():\n");
 169         for (sg = data->sg; sg; sg = sg_next(sg)) {
 170                 sg_pointer = page_address(sg_page(sg)) + sg->offset;
 171
 172
 173                 memcpy(sg_pointer, from_ptr, sg->length);
 174                 from_ptr += sg->length >> 1;
 175
 176                 data->bytes_xfered += sg->length;
 177         }
 178
 179         dev_dbg(&host->pdev->dev, "pio_read(): "
 180                         "complete (no more data).\n");
 181 }
 182
 183 static void do_pio_write(struct glamo_mci_host *host, struct mmc_data *data)
 184 {
 185         struct scatterlist *sg;
 186         u16 __iomem *to_ptr = host->data_base;
 187         void *sg_pointer;
 188
 189         dev_dbg(&host->pdev->dev, "pio_write():\n");
 190         for (sg = data->sg; sg; sg = sg_next(sg)) {
 191                 sg_pointer = page_address(sg_page(sg)) + sg->offset;
 192
 193                 data->bytes_xfered += sg->length;
 194
 195                 memcpy(to_ptr, sg_pointer, sg->length);
 196                 to_ptr += sg->length >> 1;
 197         }
 198
 199         dev_dbg(&host->pdev->dev, "pio_write(): complete\n");
 200 }
 201
 202 static int glamo_mci_set_card_clock(struct glamo_mci_host *host, int freq)
 203 {
 204         int real_rate = 0;
 205
 206         if (freq) {
 207                 glamo_mci_clock_enable(host);
 208                 real_rate = glamo_engine_reclock(host->pdata->core, GLAMO_ENGINE_MMC, freq);
 209         } else {
 210                 glamo_mci_clock_disable(host);
 211         }
 212
 213         return real_rate;
 214 }
 215
 216 static void glamo_mci_request_done(struct glamo_mci_host *host, struct
 217 mmc_request *mrq) {
 218         mod_timer(&host->disable_timer, jiffies + HZ / 16);
 219
 220         mmc_request_done(host->mmc, mrq);
 221 }
 222
 223
 224 static void glamo_mci_irq_worker(struct work_struct *work)
 225 {
 226         struct glamo_mci_host *host = container_of(work, struct glamo_mci_host,
 227                                                                                                 irq_work);
 228         struct mmc_command *cmd;
 229         uint16_t status;
 230
 231         if (!host->mrq || !host->mrq->cmd)
 232                 return;
 233
 234         cmd = host->mrq->cmd;
 235
 236         status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 237         dev_dbg(&host->pdev->dev, "status = 0x%04x\n", status);
 238
 239         /* we ignore a data timeout report if we are also told the data came */
 240         if (status & GLAMO_STAT1_MMC_RB_DRDY)
 241                 status &= ~GLAMO_STAT1_MMC_DTOUT;
 242
 243         if (status & (GLAMO_STAT1_MMC_RTOUT |
 244                           GLAMO_STAT1_MMC_DTOUT))
 245                 cmd->error = -ETIMEDOUT;
 246         if (status & (GLAMO_STAT1_MMC_BWERR |
 247                           GLAMO_STAT1_MMC_BRERR))
 248                 cmd->error = -EILSEQ;
 249         if (cmd->error) {
 250                 dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
 251                 goto done;
 252         }
 253
 254         /* issue STOP if we have been given one to use */
 255         if (host->mrq->stop)
 256                 glamo_mci_send_command(host, host->mrq->stop);
 257
 258         if (cmd->data->flags & MMC_DATA_READ)
 259                 do_pio_read(host, cmd->data);
 260
 261 done:
 262         host->mrq = NULL;
 263         glamo_mci_request_done(host, cmd->mrq);
 264 }
 265
 266 static irqreturn_t glamo_mci_irq(int irq, void *devid)
 267 {
 268         struct glamo_mci_host *host = (struct glamo_mci_host*)devid;
 269
 270         schedule_work(&host->irq_work);
 271
 272         return IRQ_HANDLED;
 273 }
 274
 275 static void glamo_mci_send_command(struct glamo_mci_host *host,
 276                                   struct mmc_command *cmd)
 277 {
 278         u8 u8a[6];
 279         u16 fire = 0;
 280         unsigned int timeout = 1000000;
 281         u16 * reg_resp = (u16 *)(host->mmio_base + GLAMO_REG_MMC_CMD_RSP1);
 282         u16 status;
 283         int triggers_int = 1;
 284
 285         /* if we can't do it, reject as busy */
 286         if (!glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1) &
 287                  GLAMO_STAT1_MMC_IDLE) {
 288                 cmd->error = -EBUSY;
 289                 return;
 290         }
 291
 292         /* create an array in wire order for CRC computation */
 293         u8a[0] = 0x40 | (cmd->opcode & 0x3f);
 294         u8a[1] = (u8)(cmd->arg >> 24);
 295         u8a[2] = (u8)(cmd->arg >> 16);
 296         u8a[3] = (u8)(cmd->arg >> 8);
 297         u8a[4] = (u8)cmd->arg;
 298         u8a[5] = (crc7(0, u8a, 5) << 1) | 0x01; /* crc7 on first 5 bytes of packet */
 299
 300         /* issue the wire-order array including CRC in register order */
 301         glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG1, ((u8a[4] << 8) | u8a[5]));
 302         glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG2, ((u8a[2] << 8) | u8a[3]));
 303         glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG3, ((u8a[0] << 8) | u8a[1]));
 304
 305         /* command index toggle */
 306         fire |= (host->request_counter & 1) << 12;
 307
 308         /* set type of command */
 309         switch (mmc_cmd_type(cmd)) {
 310         case MMC_CMD_BC:
 311                 fire |= GLAMO_FIRE_MMC_CMDT_BNR;
 312                 break;
 313         case MMC_CMD_BCR:
 314                 fire |= GLAMO_FIRE_MMC_CMDT_BR;
 315                 break;
 316         case MMC_CMD_AC:
 317                 fire |= GLAMO_FIRE_MMC_CMDT_AND;
 318                 break;
 319         case MMC_CMD_ADTC:
 320                 fire |= GLAMO_FIRE_MMC_CMDT_AD;
 321                 break;
 322         }
 323         /*
 324          * if it expects a response, set the type expected
 325          *
 326          * R1, Length  : 48bit, Normal response
 327          * R1b, Length : 48bit, same R1, but added card busy status
 328          * R2, Length  : 136bit (really 128 bits with CRC snipped)
 329          * R3, Length  : 48bit (OCR register value)
 330          * R4, Length  : 48bit, SDIO_OP_CONDITION, Reverse SDIO Card
 331          * R5, Length  : 48bit, IO_RW_DIRECTION, Reverse SDIO Card
 332          * R6, Length  : 48bit (RCA register)
 333          * R7, Length  : 48bit (interface condition, VHS(voltage supplied),
 334          *                     check pattern, CRC7)
 335          */
 336         switch (mmc_resp_type(cmd)) {
 337         case MMC_RSP_R1: /* same index as R6 and R7 */
 338                 fire |= GLAMO_FIRE_MMC_RSPT_R1;
 339                 break;
 340         case MMC_RSP_R1B:
 341                 fire |= GLAMO_FIRE_MMC_RSPT_R1b;
 342                 break;
 343         case MMC_RSP_R2:
 344                 fire |= GLAMO_FIRE_MMC_RSPT_R2;
 345                 break;
 346         case MMC_RSP_R3:
 347                 fire |= GLAMO_FIRE_MMC_RSPT_R3;
 348                 break;
 349         /* R4 and R5 supported by chip not defined in linux/mmc/core.h (sdio) */
 350         }
 351         /*
 352          * From the command index, set up the command class in the host ctrllr
 353          *
 354          * missing guys present on chip but couldn't figure out how to use yet:
 355          *     0x0 "stream read"
 356          *     0x9 "cancel running command"
 357          */
 358         switch (cmd->opcode) {
 359         case MMC_READ_SINGLE_BLOCK:
 360                 fire |= GLAMO_FIRE_MMC_CC_SBR; /* single block read */
 361                 break;
 362         case MMC_SWITCH: /* 64 byte payload */
 363         case SD_APP_SEND_SCR:
 364         case MMC_READ_MULTIPLE_BLOCK:
 365                 /* we will get an interrupt off this */
 366                 if (!cmd->mrq->stop)
 367                         /* multiblock no stop */
 368                         fire |= GLAMO_FIRE_MMC_CC_MBRNS;
 369                 else
 370                          /* multiblock with stop */
 371                         fire |= GLAMO_FIRE_MMC_CC_MBRS;
 372                 break;
 373         case MMC_WRITE_BLOCK:
 374                 fire |= GLAMO_FIRE_MMC_CC_SBW; /* single block write */
 375                 break;
 376         case MMC_WRITE_MULTIPLE_BLOCK:
 377                 if (cmd->mrq->stop)
 378                          /* multiblock with stop */
 379                         fire |= GLAMO_FIRE_MMC_CC_MBWS;
 380                 else
 381                          /* multiblock NO stop-- 'RESERVED'? */
 382                         fire |= GLAMO_FIRE_MMC_CC_MBWNS;
 383                 break;
 384         case MMC_STOP_TRANSMISSION:
 385                 fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */
 386                 triggers_int = 0;
 387                 break;
 388         default:
 389                 fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */
 390                 triggers_int = 0;
 391                 break;
 392         }
 393
 394         if (triggers_int)
 395                 host->mrq = cmd->mrq;
 396
 397         /* always largest timeout */
 398         glamo_reg_write(host, GLAMO_REG_MMC_TIMEOUT, 0xfff);
 399
 400         /* Generate interrupt on txfer */
 401         glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC, 0xff36,
 402                         0x0800 |
 403                         GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
 404                         GLAMO_BASIC_MMC_EN_COMPL_INT |
 405                         GLAMO_BASIC_MMC_EN_DATA_PUPS |
 406                         GLAMO_BASIC_MMC_EN_CMD_PUP);
 407
 408         /* send the command out on the wire */
 409         /* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
 410         glamo_reg_write(host, GLAMO_REG_MMC_CMD_FIRE, fire);
 411
 412         /* we are deselecting card?  because it isn't going to ack then... */
 413         if ((cmd->opcode == 7) && (cmd->arg == 0))
 414                 return;
 415
 416         /*
 417          * we must spin until response is ready or timed out
 418          * -- we don't get interrupts unless there is a bulk rx
 419          */
 420         do
 421                 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 422         while (((((status >> 15) & 1) != (host->request_counter & 1)) ||
 423                 (!(status & (GLAMO_STAT1_MMC_RB_RRDY |
 424                                  GLAMO_STAT1_MMC_RTOUT |
 425                                  GLAMO_STAT1_MMC_DTOUT |
 426                                  GLAMO_STAT1_MMC_BWERR |
 427                                  GLAMO_STAT1_MMC_BRERR)))) && (timeout--));
 428
 429         if ((status & (GLAMO_STAT1_MMC_RTOUT |
 430                                    GLAMO_STAT1_MMC_DTOUT)) ||
 431                 (timeout == 0)) {
 432                 cmd->error = -ETIMEDOUT;
 433         } else if (status & (GLAMO_STAT1_MMC_BWERR |
 434                           GLAMO_STAT1_MMC_BRERR)) {
 435                 cmd->error = -EILSEQ;
 436         }
 437
 438         if (cmd->flags & MMC_RSP_PRESENT) {
 439                 if (cmd->flags & MMC_RSP_136) {
 440                         cmd->resp[3] = readw(&reg_resp[0]) |
 441                                                    (readw(&reg_resp[1]) << 16);
 442                         cmd->resp[2] = readw(&reg_resp[2]) |
 443                                                    (readw(&reg_resp[3]) << 16);
 444                         cmd->resp[1] = readw(&reg_resp[4]) |
 445                                                    (readw(&reg_resp[5]) << 16);
 446                         cmd->resp[0] = readw(&reg_resp[6]) |
 447                                                    (readw(&reg_resp[7]) << 16);
 448                 } else {
 449                         cmd->resp[0] = (readw(&reg_resp[0]) >> 8) |
 450                                                    (readw(&reg_resp[1]) << 8) |
 451                                                    ((readw(&reg_resp[2])) << 24);
 452                 }
 453         }
 454 }
 455
 456 static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
 457                                  struct mmc_data *data)
 458 {
 459         /* set up the block info */
 460         glamo_reg_write(host, GLAMO_REG_MMC_DATBLKLEN, data->blksz);
 461         glamo_reg_write(host, GLAMO_REG_MMC_DATBLKCNT, data->blocks);
 462
 463         data->bytes_xfered = 0;
 464
 465         /* if write, prep the write into the shared RAM before the command */
 466         if (data->flags & MMC_DATA_WRITE) {
 467                 do_pio_write(host, data);
 468         }
 469
 470         dev_dbg(&host->pdev->dev, "(blksz=%d, count=%d)\n",
 471                                    data->blksz, data->blocks);
 472         return 0;
 473 }
 474
 475 static int glamo_mci_irq_poll(struct glamo_mci_host *host,
 476                                 struct mmc_command *cmd)
 477 {
 478         int timeout = 1000000;
 479         /*
 480          * if the glamo INT# line isn't wired (*cough* it can happen)
 481          * I'm afraid we have to spin on the IRQ status bit and "be
 482          * our own INT# line"
 483          */
 484         /*
 485          * we have faith we will get an "interrupt"...
 486          * but something insane like suspend problems can mean
 487          * we spin here forever, so we timeout after a LONG time
 488          */
 489         while ((!(readw(host->pdata->core->base +
 490                  GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) &&
 491                    (timeout--));
 492
 493         if (timeout < 0) {
 494                 if (cmd->data->error)
 495                         cmd->data->error = -ETIMEDOUT;
 496                 dev_err(&host->pdev->dev, "Payload timeout\n");
 497                 return -ETIMEDOUT;
 498         }
 499         /* ack this interrupt source */
 500         writew(GLAMO_IRQ_MMC, host->pdata->core->base +
 501                    GLAMO_REG_IRQ_CLEAR);
 502
 503         /* yay we are an interrupt controller! -- call the ISR
 504          * it will stop clock to card
 505          */
 506         glamo_mci_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
 507
 508         return 0;
 509 }
 510
 511 static void glamo_mci_send_request(struct mmc_host *mmc, struct mmc_request *mrq)
 512 {
 513         struct glamo_mci_host *host = mmc_priv(mmc);
 514         struct mmc_command *cmd = mrq->cmd;
 515
 516         host->request_counter++;
 517         if (cmd->data) {
 518                 if(glamo_mci_prepare_pio(host, cmd->data)) {
 519                         cmd->data->error = -EIO;
 520                         goto done;
 521                 }
 522         }
 523
 524         dev_dbg(&host->pdev->dev,"cmd 0x%x, "
 525                  "arg 0x%x data=%p mrq->stop=%p flags 0x%x\n",
 526                  cmd->opcode, cmd->arg, cmd->data, cmd->mrq->stop,
 527                  cmd->flags);
 528
 529         glamo_mci_clock_enable(host);
 530         glamo_mci_send_command(host, cmd);
 531
 532         /*
 533          * if we don't have bulk data to take care of, we're done
 534          */
 535         if (!cmd->data || cmd->error)
 536                 goto done;
 537
 538
 539         if (!host->pdata->core->irq_works) {
 540                 if (glamo_mci_irq_poll(host, mrq->cmd))
 541                         goto done;
 542         }
 543
 544         /*
 545          * Otherwise can can use the interrupt as async completion --
 546          * if there is read data coming, or we wait for write data to complete,
 547          * exit without mmc_request_done() as the payload interrupt
 548          * will service it
 549          */
 550         dev_dbg(&host->pdev->dev, "Waiting for payload data\n");
 551         return;
 552 done:
 553         glamo_mci_request_done(host, mrq);
 554 }
 555
 556 static void glamo_mci_set_power_mode(struct glamo_mci_host *host,
 557                                 unsigned char power_mode) {
 558         int ret;
 559
 560         if (power_mode == host->power_mode)
 561                 return;
 562
 563         switch(power_mode) {
 564         case MMC_POWER_UP:
 565                 if (host->power_mode == MMC_POWER_OFF) {
 566                         ret = regulator_enable(host->regulator);
 567                         if (ret)
 568                                 dev_err(&host->pdev->dev, "Failed to enable regulator: %d\n", ret);
 569                 }
 570                 break;
 571         case MMC_POWER_ON:
 572                 break;
 573         case MMC_POWER_OFF:
 574         default:
 575                 glamo_engine_disable(host->pdata->core,
 576                                      GLAMO_ENGINE_MMC);
 577
 578                 ret = regulator_disable(host->regulator);
 579                 if (ret)
 580                         dev_warn(&host->pdev->dev, "Failed to disable regulator: %d\n", ret);
 581                 break;
 582         }
 583         host->power_mode = power_mode;
 584 }
 585
 586 static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 587 {
 588         struct glamo_mci_host *host = mmc_priv(mmc);
 589         int bus_width = 0;
 590         int rate;
 591         int sd_drive;
 592         int ret;
 593
 594         /* Set power */
 595         glamo_mci_set_power_mode(host, ios->power_mode);
 596
 597         if (host->vdd != ios->vdd) {
 598                 ret = mmc_regulator_set_ocr(host->regulator, ios->vdd);
 599                 if (ret)
 600                         dev_err(&host->pdev->dev, "Failed to set regulator voltage: %d\n", ret);
 601                 else
 602                         host->vdd = ios->vdd;
 603         }
 604         rate = glamo_mci_set_card_clock(host, ios->clock);
 605
 606         if ((ios->power_mode == MMC_POWER_ON) ||
 607             (ios->power_mode == MMC_POWER_UP)) {
 608                 dev_info(&host->pdev->dev,
 609                         "powered (vdd = %hu) clk: %dkHz div=%hu (req: %ukHz). "
 610                         "Bus width=%d\n", ios->vdd,
 611                         rate / 1000, 0,
 612                         ios->clock / 1000, (int)ios->bus_width);
 613         } else {
 614                 dev_info(&host->pdev->dev, "glamo_mci_set_ios: power down.\n");
 615         }
 616
 617         /* set bus width */
 618         if (ios->bus_width == MMC_BUS_WIDTH_4)
 619                 bus_width = GLAMO_BASIC_MMC_EN_4BIT_DATA;
 620
 621         sd_drive = (rate * 4) / host->clk_rate;
 622         if (sd_drive > 3)
 623                 sd_drive = 3;
 624
 625         glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC,
 626                                                GLAMO_BASIC_MMC_EN_4BIT_DATA | 0xb0,
 627                                                    bus_width | sd_drive << 6);
 628 }
 629
 630
 631 /*
 632  * no physical write protect supported by us
 633  */
 634 static int glamo_mci_get_ro(struct mmc_host *mmc)
 635 {
 636         return 0;
 637 }
 638
 639 static struct mmc_host_ops glamo_mci_ops = {
 640         .request        = glamo_mci_send_request,
 641         .set_ios        = glamo_mci_set_ios,
 642         .get_ro         = glamo_mci_get_ro,
 643 };
 644
 645 static int glamo_mci_probe(struct platform_device *pdev)
 646 {
 647         struct mmc_host         *mmc;
 648         struct glamo_mci_host   *host;
 649         int ret;
 650
 651         dev_info(&pdev->dev, "glamo_mci driver (C)2007 Openmoko, Inc\n");
 652
 653         mmc = mmc_alloc_host(sizeof(struct glamo_mci_host), &pdev->dev);
 654         if (!mmc) {
 655                 ret = -ENOMEM;
 656                 goto probe_out;
 657         }
 658
 659         host = mmc_priv(mmc);
 660         host->mmc = mmc;
 661         host->pdev = pdev;
 662         host->pdata = pdev->dev.platform_data;
 663         host->power_mode = MMC_POWER_OFF;
 664         host->clk_enabled = 0;
 665
 666         INIT_WORK(&host->irq_work, glamo_mci_irq_worker);
 667
 668         host->regulator = regulator_get(pdev->dev.parent, "SD_3V3");
 669         if (!host->regulator) {
 670                 dev_err(&pdev->dev, "Cannot proceed without regulator.\n");
 671                 ret = -ENODEV;
 672                 goto probe_free_host;
 673         }
 674
 675         host->mmio_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 676         if (!host->mmio_mem) {
 677                 dev_err(&pdev->dev,
 678                         "failed to get io memory region resouce.\n");
 679                 ret = -ENOENT;
 680                 goto probe_regulator_put;
 681         }
 682
 683         host->mmio_mem = request_mem_region(host->mmio_mem->start,
 684                                             resource_size(host->mmio_mem),
 685                                             pdev->name);
 686
 687         if (!host->mmio_mem) {
 688                 dev_err(&pdev->dev, "failed to request io memory region.\n");
 689                 ret = -ENOENT;
 690                 goto probe_regulator_put;
 691         }
 692
 693         host->mmio_base = ioremap(host->mmio_mem->start,
 694                                   resource_size(host->mmio_mem));
 695         if (!host->mmio_base) {
 696                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
 697                 ret = -EINVAL;
 698                 goto probe_free_mem_region_mmio;
 699         }
 700
 701
 702         /* Get ahold of our data buffer we use for data in and out on MMC */
 703         host->data_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 704         if (!host->data_mem) {
 705                 dev_err(&pdev->dev,
 706                         "failed to get io memory region resource.\n");
 707                 ret = -ENOENT;
 708                 goto probe_iounmap_mmio;
 709         }
 710
 711         host->data_mem = request_mem_region(host->data_mem->start,
 712                                             resource_size(host->data_mem),
 713                                                                                 pdev->name);
 714
 715         if (!host->data_mem) {
 716                 dev_err(&pdev->dev, "failed to request io memory region.\n");
 717                 ret = -ENOENT;
 718                 goto probe_iounmap_mmio;
 719         }
 720         host->data_base = ioremap(host->data_mem->start,
 721                                   resource_size(host->data_mem));
 722
 723         if (host->data_base == 0) {
 724                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
 725                 ret = -EINVAL;
 726                 goto probe_free_mem_region_data;
 727         }
 728
 729         ret = request_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), glamo_mci_irq, IRQF_SHARED,
 730                        pdev->name, host);
 731         if (ret) {
 732                 dev_err(&pdev->dev, "failed to register irq.\n");
 733                 goto probe_iounmap_data;
 734         }
 735
 736
 737         host->vdd = 0;
 738         host->clk_rate = glamo_pll_rate(host->pdata->core, GLAMO_PLL1);
 739
 740         /* explain our host controller capabilities */
 741         mmc->ops       = &glamo_mci_ops;
 742         mmc->ocr_avail = mmc_regulator_get_ocrmask(host->regulator);
 743         mmc->caps      = MMC_CAP_4_BIT_DATA |
 744                          MMC_CAP_MMC_HIGHSPEED |
 745                          MMC_CAP_SD_HIGHSPEED;
 746         mmc->f_min     = host->clk_rate / 256;
 747         mmc->f_max     = host->clk_rate;
 748
 749         mmc->max_blk_count = (1 << 16) - 1; /* GLAMO_REG_MMC_RB_BLKCNT */
 750         mmc->max_blk_size  = (1 << 12) - 1; /* GLAMO_REG_MMC_RB_BLKLEN */
 751         mmc->max_req_size  = resource_size(host->data_mem);
 752         mmc->max_seg_size  = mmc->max_req_size;
 753         mmc->max_phys_segs = 128;
 754         mmc->max_hw_segs   = 128;
 755
 756         if (mmc->ocr_avail < 0) {
 757                 dev_warn(&pdev->dev, "Failed to get ocr list for regulator: %d.\n",
 758                                 mmc->ocr_avail);
 759                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 760         }
 761
 762         platform_set_drvdata(pdev, mmc);
 763
 764         glamo_engine_enable(host->pdata->core, GLAMO_ENGINE_MMC);
 765         glamo_engine_reset(host->pdata->core, GLAMO_ENGINE_MMC);
 766
 767         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
 768                         (u16)(host->data_mem->start));
 769         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
 770                         (u16)(host->data_mem->start >> 16));
 771
 772         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
 773                         (u16)(host->data_mem->start));
 774         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
 775                         (u16)(host->data_mem->start >> 16));
 776
 777         setup_timer(&host->disable_timer, glamo_mci_disable_timer,
 778                                 (unsigned long)host);
 779
 780         if ((ret = mmc_add_host(mmc))) {
 781                 dev_err(&pdev->dev, "failed to add mmc host.\n");
 782                 goto probe_freeirq;
 783         }
 784
 785         dev_info(&pdev->dev,"initialisation done.\n");
 786         return 0;
 787
 788 probe_freeirq:
 789         free_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
 790 probe_iounmap_data:
 791         iounmap(host->data_base);
 792 probe_free_mem_region_data:
 793         release_mem_region(host->data_mem->start, resource_size(host->data_mem));
 794 probe_iounmap_mmio:
 795         iounmap(host->mmio_base);
 796 probe_free_mem_region_mmio:
 797         release_mem_region(host->mmio_mem->start, resource_size(host->mmio_mem));
 798 probe_regulator_put:
 799         regulator_put(host->regulator);
 800 probe_free_host:
 801         mmc_free_host(mmc);
 802 probe_out:
 803         return ret;
 804 }
 805
 806 static int glamo_mci_remove(struct platform_device *pdev)
 807 {
 808         struct mmc_host *mmc = platform_get_drvdata(pdev);
 809         struct glamo_mci_host *host = mmc_priv(mmc);
 810
 811         free_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
 812
 813         mmc_remove_host(mmc);
 814         iounmap(host->mmio_base);
 815         iounmap(host->data_base);
 816         release_mem_region(host->mmio_mem->start, resource_size(host->mmio_mem));
 817         release_mem_region(host->data_mem->start, resource_size(host->data_mem));
 818
 819         regulator_put(host->regulator);
 820
 821         mmc_free_host(mmc);
 822
 823         glamo_engine_disable(host->pdata->core, GLAMO_ENGINE_MMC);
 824         return 0;
 825 }
 826
 827
 828 #ifdef CONFIG_PM
 829
 830 static int glamo_mci_suspend(struct device *dev)
 831 {
 832         struct mmc_host *mmc = dev_get_drvdata(dev);
 833         struct glamo_mci_host *host = mmc_priv(mmc);
 834         int ret;
 835
 836         cancel_work_sync(&host->irq_work);
 837
 838         ret = mmc_suspend_host(mmc, PMSG_SUSPEND);
 839         glamo_mci_clock_enable(host);
 840
 841         return ret;
 842 }
 843
 844 static int glamo_mci_resume(struct device *dev)
 845 {
 846         struct mmc_host *mmc = dev_get_drvdata(dev);
 847         struct glamo_mci_host *host = mmc_priv(mmc);
 848         int ret;
 849
 850         glamo_engine_enable(host->pdata->core, GLAMO_ENGINE_MMC);
 851         glamo_engine_reset(host->pdata->core, GLAMO_ENGINE_MMC);
 852
 853         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
 854                         (u16)(host->data_mem->start));
 855         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
 856                         (u16)(host->data_mem->start >> 16));
 857
 858         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
 859                         (u16)(host->data_mem->start));
 860         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
 861                         (u16)(host->data_mem->start >> 16));
 862         mdelay(5);
 863
 864         ret = mmc_resume_host(host->mmc);
 865 /*      glamo_mci_clock_disable(host);*/
 866
 867         return 0;
 868 }
 869
 870 static struct dev_pm_ops glamo_mci_pm_ops = {
 871         .suspend = glamo_mci_suspend,
 872         .resume  = glamo_mci_resume,
 873 };
 874 #define GLAMO_MCI_PM_OPS (&glamo_mci_pm_ops)
 875
 876 #else /* CONFIG_PM */
 877 #define GLAMO_MCI_PM_OPS NULL
 878 #endif /* CONFIG_PM */
 879
 880
 881 static struct platform_driver glamo_mci_driver =
 882 {
 883         .probe  = glamo_mci_probe,
 884         .remove = glamo_mci_remove,
 885         .driver = {
 886                 .name  = "glamo-mci",
 887                 .owner = THIS_MODULE,
 888                 .pm    = GLAMO_MCI_PM_OPS,
 889         },
 890 };
 891
 892 static int __init glamo_mci_init(void)
 893 {
 894         platform_driver_register(&glamo_mci_driver);
 895         return 0;
 896 }
 897
 898 static void __exit glamo_mci_exit(void)
 899 {
 900         platform_driver_unregister(&glamo_mci_driver);
 901 }
 902
 903 module_init(glamo_mci_init);
 904 module_exit(glamo_mci_exit);
 905
 906 MODULE_DESCRIPTION("Glamo MMC/SD Card Interface driver");
 907 MODULE_LICENSE("GPL");
 908 MODULE_AUTHOR("Andy Green <andy@openmoko.com>");