target/linux/rb532-2.6/patches/100-rb5xx_support.patch

   1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
   2 --- linux.old/arch/mips/Kconfig 2006-11-29 22:57:37.000000000 +0100
   3 +++ linux.dev/arch/mips/Kconfig 2006-12-14 04:09:50.000000000 +0100
   4 @@ -728,6 +728,19 @@
   5         select SYS_SUPPORTS_BIG_ENDIAN
   6         select TOSHIBA_BOARDS
   7
   8 +config MIKROTIK_RB500
   9 +       bool "Support for RB5xx boards"
  10 +       select HW_HAS_PCI
  11 +       select IRQ_CPU
  12 +       select SYS_HAS_CPU_MIPS32_R1
  13 +       select SYS_SUPPORTS_LITTLE_ENDIAN
  14 +       select SYS_SUPPORTS_32BIT_KERNEL
  15 +       select SWAP_IO_SPACE
  16 +       select DMA_NONCOHERENT
  17 +       help
  18 +         Support the Mikrotik(tm) Routerboard 500 series,
  19 +         such as the RB532.
  20 +
  21  config TOSHIBA_RBTX4927
  22         bool "Toshiba TBTX49[23]7 board"
  23         select DMA_NONCOHERENT
  24 @@ -1015,7 +1028,7 @@
  25
  26  config MIPS_L1_CACHE_SHIFT
  27         int
  28 -       default "4" if MACH_DECSTATION
  29 +       default "4" if MACH_DECSTATION || MIKROTIK_RB500
  30         default "7" if SGI_IP27
  31         default "5"
  32
  33 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
  34 --- linux.old/arch/mips/Makefile        2006-12-14 03:13:55.000000000 +0100
  35 +++ linux.dev/arch/mips/Makefile        2006-12-14 04:09:50.000000000 +0100
  36 @@ -586,6 +586,13 @@
  37  load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
  38
  39  #
  40 +# Routerboard 532 board
  41 +#
  42 +core-$(CONFIG_MIKROTIK_RB500)  += arch/mips/rb500/
  43 +cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
  44 +load-$(CONFIG_MIKROTIK_RB500)  += 0xffffffff80101000
  45 +
  46 +#
  47  # Toshiba RBTX4927 board or
  48  # Toshiba RBTX4937 board
  49  #
  50 diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
  51 --- linux.old/arch/mips/pci/fixup-rb500.c       1970-01-01 01:00:00.000000000 +0100
  52 +++ linux.dev/arch/mips/pci/fixup-rb500.c       2006-12-14 04:09:50.000000000 +0100
  53 @@ -0,0 +1,49 @@
  54 +/*
  55 + * Copyright 2001 MontaVista Software Inc.
  56 + * Author: MontaVista Software, Inc.
  57 + *             stevel@mvista.com or source@mvista.com
  58 + *
  59 + *  This program is free software; you can redistribute  it and/or modify it
  60 + *  under  the terms of  the GNU General  Public License as published by the
  61 + *  Free Software Foundation;  either version 2 of the  License, or (at your
  62 + *  option) any later version.
  63 + *
  64 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  65 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  66 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  67 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  68 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  69 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  70 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  71 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  72 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  73 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  74 + *
  75 + *  You should have received a copy of the  GNU General Public License along
  76 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  77 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  78 + */
  79 +
  80 +#include <linux/autoconf.h>
  81 +#include <linux/types.h>
  82 +#include <linux/pci.h>
  83 +#include <linux/kernel.h>
  84 +#include <linux/init.h>
  85 +
  86 +#include <asm/rc32434/rc32434.h>
  87 +
  88 +static int __devinitdata irq_map[2][12] = {
  89 +       { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
  90 +       { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
  91 +};
  92 +
  93 +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  94 +{
  95 +       int irq = 0;
  96 +
  97 +       if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
  98 +               irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
  99 +       }
 100 +       return irq + GROUP4_IRQ_BASE + 4;
 101 +}
 102 +
 103 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
 104 --- linux.old/arch/mips/pci/Makefile    2006-11-29 22:57:37.000000000 +0100
 105 +++ linux.dev/arch/mips/pci/Makefile    2006-12-14 04:09:50.000000000 +0100
 106 @@ -53,3 +53,4 @@
 107  obj-$(CONFIG_VICTOR_MPC30X)    += fixup-mpc30x.o
 108  obj-$(CONFIG_ZAO_CAPCELLA)     += fixup-capcella.o
 109  obj-$(CONFIG_WR_PPMC)          += fixup-wrppmc.o
 110 +obj-$(CONFIG_MIKROTIK_RB500)   += pci-rc32434.o ops-rc32434.o fixup-rb500.o
 111 diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
 112 --- linux.old/arch/mips/pci/ops-rc32434.c       1970-01-01 01:00:00.000000000 +0100
 113 +++ linux.dev/arch/mips/pci/ops-rc32434.c       2006-12-14 04:09:50.000000000 +0100
 114 @@ -0,0 +1,218 @@
 115 +/**************************************************************************
 116 + *
 117 + *  BRIEF MODULE DESCRIPTION
 118 + *     pci_ops for IDT EB434 board
 119 + *
 120 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 121 + *  Copyright 2006 Felix Fietkau <nbd@openwrt.org>
 122 + *
 123 + *  This program is free software; you can redistribute  it and/or modify it
 124 + *  under  the terms of  the GNU General  Public License as published by the
 125 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 126 + *  option) any later version.
 127 + *
 128 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 129 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 130 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 131 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 132 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 133 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 134 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 135 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 136 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 137 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 138 + *
 139 + *  You should have received a copy of the  GNU General Public License along
 140 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 141 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 142 + *
 143 + *
 144 + **************************************************************************
 145 + * May 2004 rkt, neb
 146 + *
 147 + * Initial Release
 148 + *
 149 + *
 150 + *
 151 + **************************************************************************
 152 + */
 153 +
 154 +#include <linux/autoconf.h>
 155 +#include <linux/init.h>
 156 +#include <linux/pci.h>
 157 +#include <linux/types.h>
 158 +#include <linux/delay.h>
 159 +
 160 +#include <asm/cpu.h>
 161 +#include <asm/io.h>
 162 +
 163 +#include <asm/rc32434/rc32434.h>
 164 +#include <asm/rc32434/pci.h>
 165 +
 166 +#define PCI_ACCESS_READ  0
 167 +#define PCI_ACCESS_WRITE 1
 168 +
 169 +
 170 +#define PCI_CFG_SET(bus,slot,func,off) \
 171 +       (rc32434_pci->pcicfga = (0x80000000 | \
 172 +                               ((bus) << 16) | ((slot)<<11) | \
 173 +                               ((func)<<8) | (off)))
 174 +
 175 +static inline int config_access(unsigned char access_type, struct pci_bus *bus,
 176 +                         unsigned int devfn, unsigned char where,
 177 +                         u32 * data)
 178 +{
 179 +       unsigned int slot = PCI_SLOT(devfn);
 180 +       u8 func = PCI_FUNC(devfn);
 181 +
 182 +       /* Setup address */
 183 +       PCI_CFG_SET(bus->number, slot, func, where);
 184 +       rc32434_sync();
 185 +
 186 +       if (access_type == PCI_ACCESS_WRITE)
 187 +               rc32434_pci->pcicfgd = *data;
 188 +       else
 189 +               *data = rc32434_pci->pcicfgd;
 190 +
 191 +       rc32434_sync();
 192 +
 193 +       return 0;
 194 +}
 195 +
 196 +
 197 +/*
 198 + * We can't address 8 and 16 bit words directly.  Instead we have to
 199 + * read/write a 32bit word and mask/modify the data we actually want.
 200 + */
 201 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
 202 +                            int where, u8 * val)
 203 +{
 204 +       u32 data;
 205 +       int ret;
 206 +
 207 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 208 +       *val = (data >> ((where & 3) << 3)) & 0xff;
 209 +       return ret;
 210 +}
 211 +
 212 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
 213 +                            int where, u16 * val)
 214 +{
 215 +       u32 data;
 216 +       int ret;
 217 +
 218 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 219 +       *val = (data >> ((where & 3) << 3)) & 0xffff;
 220 +       return ret;
 221 +}
 222 +
 223 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
 224 +                             int where, u32 * val)
 225 +{
 226 +       int ret;
 227 +       int delay = 1;
 228 +
 229 +       if (bus->number == 0 && PCI_SLOT(devfn) > 21)
 230 +               return 0;
 231 +
 232 +retry:
 233 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
 234 +
 235 +       /* PCI scan: check for invalid values, device may not have
 236 +        * finished initializing */
 237 +
 238 +       if (where == PCI_VENDOR_ID) {
 239 +               if (ret == 0xffffffff || ret == 0x00000000 ||
 240 +                       ret == 0x0000ffff || ret == 0xffff0000) {
 241 +
 242 +                       if (delay > 4)
 243 +                               return 0;
 244 +
 245 +                       delay *= 2;
 246 +                       msleep(delay);
 247 +                       goto retry;
 248 +               }
 249 +       }
 250 +
 251 +       return ret;
 252 +}
 253 +
 254 +static int
 255 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
 256 +                  u8 val)
 257 +{
 258 +       u32 data = 0;
 259 +
 260 +       if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 261 +               return -1;
 262 +
 263 +       data = (data & ~(0xff << ((where & 3) << 3))) |
 264 +               (val << ((where & 3) << 3));
 265 +
 266 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 267 +               return -1;
 268 +
 269 +       return PCIBIOS_SUCCESSFUL;
 270 +}
 271 +
 272 +
 273 +static int
 274 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
 275 +                  u16 val)
 276 +{
 277 +       u32 data = 0;
 278 +
 279 +       if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 280 +               return -1;
 281 +
 282 +       data = (data & ~(0xffff << ((where & 3) << 3))) |
 283 +               (val << ((where & 3) << 3));
 284 +
 285 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 286 +               return -1;
 287 +
 288 +
 289 +       return PCIBIOS_SUCCESSFUL;
 290 +}
 291 +
 292 +
 293 +static int
 294 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
 295 +                   u32 val)
 296 +{
 297 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
 298 +               return -1;
 299 +
 300 +       return PCIBIOS_SUCCESSFUL;
 301 +}
 302 +
 303 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
 304 +                          int where, int size, u32 * val)
 305 +{
 306 +       switch (size) {
 307 +       case 1:
 308 +               return read_config_byte(bus, devfn, where, (u8 *) val);
 309 +       case 2:
 310 +               return read_config_word(bus, devfn, where, (u16 *) val);
 311 +       default:
 312 +               return read_config_dword(bus, devfn, where, val);
 313 +       }
 314 +}
 315 +
 316 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
 317 +                           int where, int size, u32 val)
 318 +{
 319 +       switch (size) {
 320 +       case 1:
 321 +               return write_config_byte(bus, devfn, where, (u8) val);
 322 +       case 2:
 323 +               return write_config_word(bus, devfn, where, (u16) val);
 324 +       default:
 325 +               return write_config_dword(bus, devfn, where, val);
 326 +       }
 327 +}
 328 +
 329 +struct pci_ops rc32434_pci_ops = {
 330 +       .read =  pci_config_read,
 331 +       .write = pci_config_write,
 332 +};
 333 diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
 334 --- linux.old/arch/mips/pci/pci-rc32434.c       1970-01-01 01:00:00.000000000 +0100
 335 +++ linux.dev/arch/mips/pci/pci-rc32434.c       2006-12-14 04:09:50.000000000 +0100
 336 @@ -0,0 +1,234 @@
 337 +/**************************************************************************
 338 + *
 339 + *  BRIEF MODULE DESCRIPTION
 340 + *     PCI initialization for IDT EB434 board
 341 + *
 342 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 343 + *
 344 + *  This program is free software; you can redistribute  it and/or modify it
 345 + *  under  the terms of  the GNU General  Public License as published by the
 346 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 347 + *  option) any later version.
 348 + *
 349 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 350 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 351 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 352 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 353 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 354 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 355 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 356 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 357 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 358 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 359 + *
 360 + *  You should have received a copy of the  GNU General Public License along
 361 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 362 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 363 + *
 364 + *
 365 + **************************************************************************
 366 + * May 2004 rkt, neb
 367 + *
 368 + * Initial Release
 369 + *
 370 + *
 371 + *
 372 + **************************************************************************
 373 + */
 374 +
 375 +#include <linux/autoconf.h>
 376 +#include <linux/types.h>
 377 +#include <linux/pci.h>
 378 +#include <linux/kernel.h>
 379 +#include <linux/init.h>
 380 +
 381 +#include <asm/rc32434/rc32434.h>
 382 +#include <asm/rc32434/pci.h>
 383 +
 384 +#define PCI_ACCESS_READ  0
 385 +#define PCI_ACCESS_WRITE 1
 386 +
 387 +/* define an unsigned array for the PCI registers */
 388 +unsigned int korinaCnfgRegs[25] = {
 389 +       KORINA_CNFG1,    KORINA_CNFG2,  KORINA_CNFG3,  KORINA_CNFG4,
 390 +       KORINA_CNFG5,    KORINA_CNFG6,  KORINA_CNFG7,  KORINA_CNFG8,
 391 +       KORINA_CNFG9,    KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
 392 +       KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
 393 +       KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
 394 +       KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
 395 +};
 396 +static struct resource rc32434_res_pci_mem1;
 397 +static struct resource rc32434_res_pci_mem2;
 398 +
 399 +static struct resource rc32434_res_pci_mem1 = {
 400 +       .name = "PCI MEM1",
 401 +       .start = 0x50000000,
 402 +       .end = 0x5FFFFFFF,
 403 +       .flags = IORESOURCE_MEM,
 404 +       .parent = &rc32434_res_pci_mem1,
 405 +       .sibling = NULL,
 406 +       .child = &rc32434_res_pci_mem2
 407 +};
 408 +
 409 +static struct resource rc32434_res_pci_mem2 = {
 410 +       .name = "PCI Mem2",
 411 +       .start = 0x60000000,
 412 +       .end = 0x6FFFFFFF,
 413 +       .flags = IORESOURCE_MEM,
 414 +       .parent = &rc32434_res_pci_mem1,
 415 +       .sibling = NULL,
 416 +       .child = NULL
 417 +};
 418 +
 419 +static struct resource rc32434_res_pci_io1 = {
 420 +       .name = "PCI I/O1",
 421 +       .start = 0x18800000,
 422 +       .end = 0x188FFFFF,
 423 +       .flags = IORESOURCE_IO,
 424 +};
 425 +
 426 +extern struct pci_ops rc32434_pci_ops;
 427 +
 428 +#define PCI_MEM1_START PCI_ADDR_START
 429 +#define PCI_MEM1_END   PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
 430 +#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
 431 +#define PCI_MEM2_END   PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN)  - 1
 432 +#define PCI_IO1_START  PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
 433 +#define PCI_IO1_END    PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
 434 +#define PCI_IO2_START  PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
 435 +#define PCI_IO2_END    PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
 436 +
 437 +
 438 +struct pci_controller rc32434_controller2;
 439 +
 440 +struct pci_controller rc32434_controller = {
 441 +       .pci_ops        = &rc32434_pci_ops,
 442 +       .mem_resource   = &rc32434_res_pci_mem1,
 443 +       .io_resource    = &rc32434_res_pci_io1,
 444 +       .mem_offset     = 0,
 445 +       .io_offset      = 0,
 446 +
 447 +};
 448 +
 449 +#ifdef __MIPSEB__
 450 +#define PCI_ENDIAN_FLAG PCILBAC_sb_m
 451 +#else
 452 +#define PCI_ENDIAN_FLAG 0
 453 +#endif
 454 +
 455 +static int __init rc32434_pcibridge_init(void)
 456 +{
 457 +       unsigned int pcicValue, pcicData = 0;
 458 +       unsigned int dummyRead, pciCntlVal;
 459 +       int loopCount;
 460 +       unsigned int pciConfigAddr;
 461 +
 462 +       pcicValue = rc32434_pci->pcic;
 463 +       pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
 464 +       if (!((pcicValue == PCIM_H_EA) ||
 465 +                (pcicValue == PCIM_H_IA_FIX) ||
 466 +               (pcicValue == PCIM_H_IA_RR))) {
 467 +               printk("PCI init error!!!\n");
 468 +               /* Not in Host Mode, return ERROR */
 469 +               return -1;
 470 +       }
 471 +       /* Enables the Idle Grant mode, Arbiter Parking */
 472 +       pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
 473 +       rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
 474 +       /* Zero out the PCI status & PCI Status Mask */
 475 +       for(;;)
 476 +       {
 477 +          pcicData = rc32434_pci->pcis;
 478 +          if (!(pcicData & PCIS_rip_m))
 479 +                   break;
 480 +       }
 481 +
 482 +       rc32434_pci->pcis = 0;
 483 +       rc32434_pci->pcism = 0xFFFFFFFF;
 484 +       /* Zero out the PCI decoupled registers */
 485 +       rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
 486 +       rc32434_pci->pcidas=0; /* clear the status */
 487 +       rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
 488 +       /* Mask PCI Messaging Interrupts */
 489 +       rc32434_pci_msg->pciiic = 0;
 490 +       rc32434_pci_msg->pciiim = 0xFFFFFFFF;
 491 +       rc32434_pci_msg->pciioic = 0;
 492 +       rc32434_pci_msg->pciioim = 0;
 493 +
 494 +
 495 +       /* Setup PCILB0 as Memory Window */
 496 +       rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
 497 +
 498 +       /* setup the PCI map address as same as the local address */
 499 +
 500 +       rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
 501 +
 502 +
 503 +       /* Setup PCILBA1 as MEM */
 504 +       rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
 505 +       dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
 506 +       rc32434_pci->pcilba[1].a = 0x60000000;
 507 +       rc32434_pci->pcilba[1].m = 0x60000000;
 508 +
 509 +       /* setup PCILBA2 as IO Window*/
 510 +       rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
 511 +       dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
 512 +       rc32434_pci->pcilba[2].a = 0x18C00000;
 513 +       rc32434_pci->pcilba[2].m = 0x18FFFFFF;
 514 +
 515 +       /* setup PCILBA2 as IO Window*/
 516 +       rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
 517 +       dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
 518 +
 519 +       /* Setup PCILBA3 as IO Window */
 520 +       rc32434_pci->pcilba[3].a = 0x18800000;
 521 +       rc32434_pci->pcilba[3].m = 0x18800000;
 522 +       rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
 523 +       dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
 524 +
 525 +       pciConfigAddr=(unsigned int)(0x80000004);
 526 +       for(loopCount=0;loopCount<24;loopCount++){
 527 +               rc32434_pci->pcicfga=pciConfigAddr;
 528 +               dummyRead=rc32434_pci->pcicfga;
 529 +               rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
 530 +               dummyRead=rc32434_pci->pcicfgd;
 531 +               pciConfigAddr += 4;
 532 +       }
 533 +       rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
 534 +               | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
 535 +
 536 +       pciCntlVal=rc32434_pci->pcic;
 537 +       pciCntlVal &=~(PCIC_tnr_m);
 538 +       rc32434_pci->pcic = pciCntlVal;
 539 +       pciCntlVal=rc32434_pci->pcic;
 540 +       return 0;
 541 +}
 542 +
 543 +/* Do platform specific device initialization at pci_enable_device() time */
 544 +int pcibios_plat_dev_init(struct pci_dev *dev)
 545 +{
 546 +       if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
 547 +               /* disable prefetched memory range */
 548 +               pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
 549 +               pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
 550 +
 551 +               pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
 552 +       }
 553 +       return 0;
 554 +}
 555 +
 556 +static int __init rc32434_pci_init(void)
 557 +{
 558 +       printk("PCI: Initializing PCI\n");
 559 +
 560 +       ioport_resource.start = rc32434_res_pci_io1.start;
 561 +       ioport_resource.end = rc32434_res_pci_io1.end;
 562 +
 563 +       rc32434_pcibridge_init();
 564 +
 565 +       register_pci_controller(&rc32434_controller);
 566 +       rc32434_sync();
 567 +}
 568 +
 569 +arch_initcall(rc32434_pci_init);
 570 +
 571 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
 572 --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
 573 +++ linux.dev/arch/mips/rb500/devices.c 2006-12-14 04:09:50.000000000 +0100
 574 @@ -0,0 +1,210 @@
 575 +/*
 576 + *  RouterBoard 500 Platform devices
 577 + *
 578 + *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
 579 + *
 580 + *  This program is free software; you can redistribute it and/or modify
 581 + *  it under the terms of the GNU General Public License as published by
 582 + *  the Free Software Foundation; either version 2 of the License, or
 583 + *  (at your option) any later version.
 584 + *
 585 + *  This program is distributed in the hope that it will be useful,
 586 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 587 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 588 + *  GNU General Public License for more details.
 589 + *
 590 + *  $Id$
 591 + */
 592 +#include <linux/kernel.h>
 593 +#include <linux/init.h>
 594 +#include <linux/module.h>
 595 +#include <linux/ctype.h>
 596 +#include <linux/string.h>
 597 +#include <linux/platform_device.h>
 598 +#include <asm/unaligned.h>
 599 +#include <asm/io.h>
 600 +
 601 +#include <asm/rc32434/rc32434.h>
 602 +#include <asm/rc32434/dma.h>
 603 +#include <asm/rc32434/dma_v.h>
 604 +#include <asm/rc32434/eth.h>
 605 +#include <asm/rc32434/rb.h>
 606 +
 607 +#define ETH0_DMA_RX_IRQ        GROUP1_IRQ_BASE + 0
 608 +#define ETH0_DMA_TX_IRQ        GROUP1_IRQ_BASE + 1
 609 +#define ETH0_RX_OVR_IRQ        GROUP3_IRQ_BASE + 9
 610 +#define ETH0_TX_UND_IRQ        GROUP3_IRQ_BASE + 10
 611 +
 612 +#define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
 613 +#define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
 614 +
 615 +static struct resource korina_dev0_res[] = {
 616 +       {
 617 +               .name  = "korina_regs",
 618 +               .start = ETH0_PhysicalAddress,
 619 +               .end   = ETH0_PhysicalAddress + sizeof(ETH_t),
 620 +               .flags = IORESOURCE_MEM,
 621 +       },
 622 +       {
 623 +               .name  = "korina_rx",
 624 +               .start = ETH0_DMA_RX_IRQ,
 625 +               .end   = ETH0_DMA_RX_IRQ,
 626 +               .flags = IORESOURCE_IRQ
 627 +       },
 628 +       {
 629 +               .name  = "korina_tx",
 630 +               .start = ETH0_DMA_TX_IRQ,
 631 +               .end   = ETH0_DMA_TX_IRQ,
 632 +               .flags = IORESOURCE_IRQ
 633 +       },
 634 +       {
 635 +               .name  = "korina_ovr",
 636 +               .start = ETH0_RX_OVR_IRQ,
 637 +               .end   = ETH0_RX_OVR_IRQ,
 638 +               .flags = IORESOURCE_IRQ
 639 +       },
 640 +       {
 641 +               .name  = "korina_und",
 642 +               .start = ETH0_TX_UND_IRQ,
 643 +               .end   = ETH0_TX_UND_IRQ,
 644 +               .flags = IORESOURCE_IRQ
 645 +       },
 646 +       {
 647 +               .name  = "korina_dma_rx",
 648 +               .start = ETH0_RX_DMA_ADDR,
 649 +               .end   = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
 650 +               .flags = IORESOURCE_MEM,
 651 +       },
 652 +       {
 653 +               .name  = "korina_dma_tx",
 654 +               .start = ETH0_TX_DMA_ADDR,
 655 +               .end   = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
 656 +               .flags = IORESOURCE_MEM,
 657 +       }
 658 +};
 659 +
 660 +static struct korina_device korina_dev0_data = {
 661 +       .name = "korina0",
 662 +       .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee }
 663 +};
 664 +
 665 +static struct platform_device korina_dev0 = {
 666 +       .id = 0,
 667 +       .name = "korina",
 668 +       .dev.platform_data = &korina_dev0_data,
 669 +       .resource = korina_dev0_res,
 670 +       .num_resources = ARRAY_SIZE(korina_dev0_res),
 671 +};
 672 +
 673 +
 674 +#define CF_GPIO_NUM 13
 675 +
 676 +static struct resource cf_slot0_res[] = {
 677 +       {
 678 +               .name  = "cf_membase",
 679 +               .flags = IORESOURCE_MEM
 680 +       },
 681 +       {
 682 +               .name  = "cf_irq",
 683 +               .start = (8 + 4 * 32 + CF_GPIO_NUM),  /* 149 */
 684 +               .end   = (8 + 4 * 32 + CF_GPIO_NUM),
 685 +               .flags = IORESOURCE_IRQ
 686 +       }
 687 +};
 688 +
 689 +static struct cf_device cf_slot0_data = {
 690 +       .gpio_pin = 13
 691 +};
 692 +
 693 +static struct platform_device cf_slot0 = {
 694 +       .id = 0,
 695 +       .name = "rb500-cf",
 696 +       .dev.platform_data = &cf_slot0_data,
 697 +       .resource = cf_slot0_res,
 698 +       .num_resources = ARRAY_SIZE(cf_slot0_res),
 699 +};
 700 +
 701 +/* Resources and device for NAND.  There is no data needed and no irqs, so just define the memory used. */
 702 +static struct resource nand_slot0_res[] = {
 703 +       {
 704 +               .name = "nand_membase",
 705 +               .flags = IORESOURCE_MEM
 706 +       }
 707 +};
 708 +
 709 +static struct platform_device nand_slot0 = {
 710 +       .id = 0,
 711 +       .name = "rb500-nand",
 712 +       .resource = nand_slot0_res,
 713 +       .num_resources = ARRAY_SIZE(nand_slot0_res),
 714 +};
 715 +
 716 +
 717 +static struct platform_device *rb500_devs[] = {
 718 +       &korina_dev0,
 719 +       &nand_slot0,
 720 +       &cf_slot0
 721 +};
 722 +
 723 +static void __init parse_mac_addr(char* macstr)
 724 +{
 725 +       int i, j;
 726 +       unsigned char result, value;
 727 +
 728 +       for (i=0; i<6; i++) {
 729 +               result = 0;
 730 +               if (i != 5 && *(macstr+2) != ':') {
 731 +                       return;
 732 +               }
 733 +               for (j=0; j<2; j++) {
 734 +                       if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
 735 +                                                 toupper(*macstr)-'A'+10) < 16) {
 736 +                               result = result*16 + value;
 737 +                               macstr++;
 738 +                       }
 739 +                       else return;
 740 +               }
 741 +
 742 +               macstr++;
 743 +               korina_dev0_data.mac[i] = result;
 744 +       }
 745 +}
 746 +
 747 +
 748 +/* DEVICE CONTROLLER 1 */
 749 +#define CFG_DC_DEV1 (void*)0xb8010010
 750 +#define CFG_DC_DEV2 (void*)0xb8010020
 751 +#define CFG_DC_DEVBASE    0x0
 752 +#define CFG_DC_DEVMASK    0x4
 753 +#define CFG_DC_DEVC       0x8
 754 +#define CFG_DC_DEVTC      0xC
 755 +
 756 +
 757 +static int __init plat_setup_devices(void)
 758 +{
 759 +       /* Look for the CF card reader */
 760 +       if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
 761 +               rb500_devs[1] = NULL;
 762 +       else {
 763 +               cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
 764 +               cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
 765 +       }
 766 +
 767 +       /* There is always a NAND device */
 768 +       nand_slot0_res[0].start = readl( CFG_DC_DEV2 + CFG_DC_DEVBASE);
 769 +       nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
 770 +
 771 +       return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
 772 +}
 773 +
 774 +static int __init setup_kmac(char *s)
 775 +{
 776 +    printk("korina mac = %s\n",s);
 777 +       parse_mac_addr(s);
 778 +    return 0;
 779 +}
 780 +
 781 +__setup("kmac=", setup_kmac);
 782 +arch_initcall(plat_setup_devices);
 783 +
 784 +
 785 diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
 786 --- linux.old/arch/mips/rb500/irq.c     1970-01-01 01:00:00.000000000 +0100
 787 +++ linux.dev/arch/mips/rb500/irq.c     2006-12-14 04:14:16.000000000 +0100
 788 @@ -0,0 +1,264 @@
 789 +/*
 790 + * BRIEF MODULE DESCRIPTION
 791 + *     RC32434 interrupt routines.
 792 + *
 793 + * Copyright 2002 MontaVista Software Inc.
 794 + * Author: MontaVista Software, Inc.
 795 + *             stevel@mvista.com or source@mvista.com
 796 + *
 797 + *  This program is free software; you can redistribute         it and/or modify it
 798 + *  under  the terms of         the GNU General  Public License as published by the
 799 + *  Free Software Foundation;  either version 2 of the License, or (at your
 800 + *  option) any later version.
 801 + *
 802 + *  THIS  SOFTWARE  IS PROVIDED          ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 803 + *  WARRANTIES,          INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 804 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 805 + *  NO EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 806 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 807 + *  NOT LIMITED          TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 808 + *  USE, DATA, OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 809 + *  ANY THEORY OF LIABILITY, WHETHER IN         CONTRACT, STRICT LIABILITY, OR TORT
 810 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 811 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 812 + *
 813 + *  You should have received a copy of the  GNU General Public License along
 814 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 815 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 816 + */
 817 +
 818 +#include <linux/errno.h>
 819 +#include <linux/init.h>
 820 +#include <linux/kernel_stat.h>
 821 +#include <linux/module.h>
 822 +#include <linux/signal.h>
 823 +#include <linux/sched.h>
 824 +#include <linux/types.h>
 825 +#include <linux/interrupt.h>
 826 +#include <linux/ioport.h>
 827 +#include <linux/timex.h>
 828 +#include <linux/slab.h>
 829 +#include <linux/random.h>
 830 +#include <linux/delay.h>
 831 +
 832 +#include <asm/bitops.h>
 833 +#include <asm/bootinfo.h>
 834 +#include <asm/io.h>
 835 +#include <asm/irq.h>
 836 +#include <asm/time.h>
 837 +#include <asm/mipsregs.h>
 838 +#include <asm/system.h>
 839 +#include <asm/rc32434/rc32434.h>
 840 +#include <asm/rc32434/gpio.h>
 841 +
 842 +extern void set_debug_traps(void);
 843 +extern irq_cpustat_t irq_stat [NR_CPUS];
 844 +unsigned int local_bh_count[NR_CPUS];
 845 +unsigned int local_irq_count[NR_CPUS];
 846 +
 847 +static unsigned int startup_irq(unsigned int irq);
 848 +static void rb500_end_irq(unsigned int irq_nr);
 849 +static void mask_and_ack_irq(unsigned int irq_nr);
 850 +static void rb500_enable_irq(unsigned int irq_nr);
 851 +static void rb500_disable_irq(unsigned int irq_nr);
 852 +
 853 +extern void __init init_generic_irq(void);
 854 +
 855 +typedef struct {
 856 +  u32 mask;       /* mask of valid bits in pending/mask registers */
 857 +  volatile u32 *base_addr;
 858 +} intr_group_t;
 859 +
 860 +#define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
 861 +
 862 +#if (NR_IRQS < RC32434_NR_IRQS)
 863 +#error Too little irqs defined. Did you override <asm/irq.h> ?
 864 +#endif
 865 +
 866 +static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
 867 +  { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
 868 +  { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
 869 +  { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
 870 +  { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
 871 +  { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
 872 +};
 873 +
 874 +#define READ_PEND(base) (*(base))
 875 +#define READ_MASK(base) (*(base + 2))
 876 +#define WRITE_MASK(base, val) (*(base + 2) = (val))
 877 +
 878 +static inline int irq_to_group(unsigned int irq_nr)
 879 +{
 880 +  return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
 881 +}
 882 +
 883 +static inline int group_to_ip(unsigned int group)
 884 +{
 885 +  return group + 2;
 886 +}
 887 +
 888 +static inline void enable_local_irq(unsigned int ip)
 889 +{
 890 +  int ipnum = 0x100 << ip;
 891 +  clear_c0_cause(ipnum);
 892 +  set_c0_status(ipnum);
 893 +}
 894 +
 895 +static inline void disable_local_irq(unsigned int ip)
 896 +{
 897 +  int ipnum = 0x100 << ip;
 898 +  clear_c0_status(ipnum);
 899 +}
 900 +
 901 +static inline void ack_local_irq(unsigned int ip)
 902 +{
 903 +  int ipnum = 0x100 << ip;
 904 +  clear_c0_cause(ipnum);
 905 +}
 906 +
 907 +static void rb500_enable_irq(unsigned int irq_nr)
 908 +{
 909 +  int           ip = irq_nr - GROUP0_IRQ_BASE;
 910 +  unsigned int  group, intr_bit;
 911 +  volatile unsigned int  *addr;
 912 +
 913 +
 914 +  if (ip < 0)
 915 +    enable_local_irq(irq_nr);
 916 +  else {
 917 +    group = ip >> 5;
 918 +
 919 +    ip &= (1<<5)-1;
 920 +    intr_bit = 1 << ip;
 921 +
 922 +    enable_local_irq(group_to_ip(group));
 923 +
 924 +    addr = intr_group[group].base_addr;
 925 +    WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
 926 +  }
 927 +}
 928 +
 929 +static void rb500_disable_irq(unsigned int irq_nr)
 930 +{
 931 +  int           ip = irq_nr - GROUP0_IRQ_BASE;
 932 +  unsigned int  group, intr_bit, mask;
 933 +  volatile unsigned int  *addr;
 934 +
 935 +  if (ip < 0) {
 936 +       disable_local_irq(irq_nr);
 937 +    }else{
 938 +    group = ip >> 5;
 939 +
 940 +    ip &= (1<<5) -1;
 941 +    intr_bit = 1 << ip;
 942 +    addr = intr_group[group].base_addr;
 943 +    mask = READ_MASK(addr);
 944 +    mask |= intr_bit;
 945 +    WRITE_MASK(addr,mask);
 946 +
 947 +    /*
 948 +     * if there are no more interrupts enabled in this
 949 +     * group, disable corresponding IP
 950 +     */
 951 +    if (mask == intr_group[group].mask)
 952 +      disable_local_irq(group_to_ip(group));
 953 +  }
 954 +}
 955 +
 956 +static unsigned int startup_irq(unsigned int irq_nr)
 957 +{
 958 +  rb500_enable_irq(irq_nr);
 959 +  return 0;
 960 +}
 961 +
 962 +static void shutdown_irq(unsigned int irq_nr)
 963 +{
 964 +  rb500_disable_irq(irq_nr);
 965 +  return;
 966 +}
 967 +
 968 +static void mask_and_ack_irq(unsigned int irq_nr)
 969 +{
 970 +  rb500_disable_irq(irq_nr);
 971 +  ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
 972 +}
 973 +
 974 +static void rb500_end_irq(unsigned int irq_nr)
 975 +{
 976 +
 977 +  int ip = irq_nr - GROUP0_IRQ_BASE;
 978 +  unsigned int intr_bit, group;
 979 +  volatile unsigned int *addr;
 980 +
 981 +       if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 982 +               printk("warning: end_irq %d did not enable (%x)\n",
 983 +                       irq_nr, irq_desc[irq_nr].status);
 984 +               return;
 985 +       }
 986 +
 987 +       if (ip < 0) {
 988 +               enable_local_irq(irq_nr);
 989 +       } else {
 990 +               group = ip >> 5;
 991 +
 992 +               ip &= (1 << 5) - 1;
 993 +               intr_bit = 1 << ip;
 994 +
 995 +               if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
 996 +                       gpio->gpioistat = gpio->gpioistat & ~intr_bit;
 997 +               }
 998 +
 999 +               enable_local_irq(group_to_ip(group));
1000 +
1001 +               addr = intr_group[group].base_addr;
1002 +               WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1003 +       }
1004 +}
1005 +
1006 +static struct hw_interrupt_type rc32434_irq_type = {
1007 +  .typename = "RB500",
1008 +  .startup = startup_irq,
1009 +  .shutdown = shutdown_irq,
1010 +  .enable = rb500_enable_irq,
1011 +  .disable = rb500_disable_irq,
1012 +  .ack = mask_and_ack_irq,
1013 +  .end = rb500_end_irq,
1014 +};
1015 +
1016 +
1017 +void __init arch_init_irq(void)
1018 +{
1019 +       int i;
1020 +
1021 +       printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
1022 +       memset(irq_desc, 0, sizeof(irq_desc));
1023 +
1024 +       for (i = 0; i < RC32434_NR_IRQS; i++) {
1025 +               irq_desc[i].status = IRQ_DISABLED;
1026 +               irq_desc[i].action = NULL;
1027 +               irq_desc[i].depth = 1;
1028 +               irq_desc[i].chip = &rc32434_irq_type;
1029 +               spin_lock_init(&irq_desc[i].lock);
1030 +       }
1031 +}
1032 +
1033 +/* Main Interrupt dispatcher */
1034 +asmlinkage void plat_irq_dispatch(void)
1035 +{
1036 +       unsigned int ip, pend, group;
1037 +       volatile unsigned int *addr;
1038 +       unsigned int cp0_cause = read_c0_cause() & read_c0_status();
1039 +
1040 +       if (cp0_cause & CAUSEF_IP7) {
1041 +               ll_timer_interrupt(7);
1042 +       } else if ((ip = (cp0_cause & 0x7c00))) {
1043 +               group = 21 - rc32434_clz(ip);
1044 +
1045 +               addr = intr_group[group].base_addr;
1046 +
1047 +               pend = READ_PEND(addr);
1048 +               pend &= ~READ_MASK(addr); // only unmasked interrupts
1049 +               pend = 39 - rc32434_clz(pend);
1050 +               do_IRQ((group << 5) + pend);
1051 +       }
1052 +}
1053 diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
1054 --- linux.old/arch/mips/rb500/Makefile  1970-01-01 01:00:00.000000000 +0100
1055 +++ linux.dev/arch/mips/rb500/Makefile  2006-12-14 04:09:50.000000000 +0100
1056 @@ -0,0 +1,5 @@
1057 +#
1058 +# Makefile for the RB500 board specific parts of the kernel
1059 +#
1060 +
1061 +obj-y   += irq.o time.o setup.o serial.o prom.o misc.o devices.o
1062 diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
1063 --- linux.old/arch/mips/rb500/misc.c    1970-01-01 01:00:00.000000000 +0100
1064 +++ linux.dev/arch/mips/rb500/misc.c    2006-12-14 04:09:50.000000000 +0100
1065 @@ -0,0 +1,56 @@
1066 +#include <linux/module.h>
1067 +#include <linux/kernel.h>   /* printk() */
1068 +#include <linux/types.h>    /* size_t */
1069 +#include <linux/pci.h>
1070 +#include <linux/spinlock.h>
1071 +#include <asm/rc32434/rb.h>
1072 +
1073 +#define GPIO_BADDR  0xb8050000
1074 +
1075 +
1076 +static volatile unsigned char *devCtl3Base = 0;
1077 +static unsigned char latchU5State = 0;
1078 +static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
1079 +
1080 +void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) {
1081 +    unsigned flags, data;
1082 +    unsigned i = 0;
1083 +    spin_lock_irqsave(&clu5Lock, flags);
1084 +    data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
1085 +    for (i = 0; i != len; ++i) {
1086 +       if (val & (1 << i)) data |= (1 << (i + bit));
1087 +       else data &= ~(1 << (i + bit));
1088 +    }
1089 +    *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
1090 +    spin_unlock_irqrestore(&clu5Lock, flags);
1091 +}
1092 +
1093 +void changeLatchU5(unsigned char orMask, unsigned char nandMask) {
1094 +    unsigned flags;
1095 +    spin_lock_irqsave(&clu5Lock, flags);
1096 +    latchU5State = (latchU5State | orMask) & ~nandMask;
1097 +    if( !devCtl3Base) devCtl3Base = (volatile unsigned char *)
1098 +               KSEG1ADDR(*(volatile unsigned *) KSEG1ADDR(0x18010030));
1099 +    *devCtl3Base = latchU5State;
1100 +    spin_unlock_irqrestore(&clu5Lock, flags);
1101 +}
1102 +
1103 +u32 gpio_get(gpio_func func)
1104 +{
1105 +       return readl((void *) GPIO_BADDR + func);
1106 +}
1107 +
1108 +void gpio_set(gpio_func func, u32 mask, u32 value)
1109 +{
1110 +       u32 val = readl((void *) GPIO_BADDR + func);
1111 +
1112 +       val &= ~mask;
1113 +       val |= value & mask;
1114 +
1115 +       writel(val, (void *) GPIO_BADDR + func);
1116 +}
1117 +
1118 +EXPORT_SYMBOL(gpio_set);
1119 +EXPORT_SYMBOL(gpio_get);
1120 +EXPORT_SYMBOL(set434Reg);
1121 +EXPORT_SYMBOL(changeLatchU5);
1122 diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
1123 --- linux.old/arch/mips/rb500/prom.c    1970-01-01 01:00:00.000000000 +0100
1124 +++ linux.dev/arch/mips/rb500/prom.c    2006-12-14 05:15:05.000000000 +0100
1125 @@ -0,0 +1,161 @@
1126 +/*
1127 +* prom.c
1128 +**********************************************************************
1129 +* P . Sadik Oct 10, 2003
1130 +*
1131 +* Started change log
1132 +* idt_cpu_freq is make a kernel configuration parameter
1133 +* idt_cpu_freq is exported so that other modules can use it.
1134 +* Code cleanup
1135 +**********************************************************************
1136 +* P. Sadik Oct 20, 2003
1137 +*
1138 +* Removed NVRAM code from here, since they are already available under
1139 +* nvram directory.
1140 +* Added serial port initialisation.
1141 +**********************************************************************
1142 +**********************************************************************
1143 +* P. Sadik Oct 30, 2003
1144 +*
1145 +* Added reset_cons_port
1146 +**********************************************************************
1147 +
1148 +  P.Christeas, 2005-2006
1149 +  Port to 2.6, add 2.6 cmdline parsing
1150 +
1151 +*/
1152 +
1153 +#include <linux/autoconf.h>
1154 +#include <linux/init.h>
1155 +#include <linux/mm.h>
1156 +#include <linux/module.h>
1157 +#include <linux/string.h>
1158 +#include <linux/console.h>
1159 +#include <asm/bootinfo.h>
1160 +#include <linux/bootmem.h>
1161 +#include <linux/ioport.h>
1162 +#include <linux/blkdev.h>
1163 +#include <asm/rc32434/ddr.h>
1164 +
1165 +#define PROM_ENTRY(x)   (0xbfc00000+((x)*8))
1166 +extern void __init setup_serial_port(void);
1167 +
1168 +unsigned int idt_cpu_freq = 132000000;
1169 +EXPORT_SYMBOL(idt_cpu_freq);
1170 +unsigned int board_type = 500;
1171 +EXPORT_SYMBOL(board_type);
1172 +unsigned int gpio_bootup_state = 0;
1173 +EXPORT_SYMBOL(gpio_bootup_state);
1174 +
1175 +
1176 +char mips_mac_address[18] = "08:00:06:05:40:01";
1177 +EXPORT_SYMBOL(mips_mac_address);
1178 +
1179 +/* what to append to cmdline when button is [not] pressed */
1180 +#define GPIO_INIT_NOBUTTON ""
1181 +#define GPIO_INIT_BUTTON   " 2"
1182 +
1183 +#ifdef CONFIG_MIKROTIK_RB500
1184 +unsigned soft_reboot = 0;
1185 +EXPORT_SYMBOL(soft_reboot);
1186 +#endif
1187 +
1188 +#define SR_NMI                 0x00180000      /* NMI */
1189 +#define SERIAL_SPEED_ENTRY     0x00000001
1190 +
1191 +#ifdef CONFIG_REMOTE_DEBUG
1192 +extern int remote_debug;
1193 +#endif
1194 +
1195 +extern unsigned long mips_machgroup;
1196 +extern unsigned long mips_machtype;
1197 +
1198 +#define FREQ_TAG   "HZ="
1199 +#define GPIO_TAG   "gpio="
1200 +#define KMAC_TAG   "kmac="
1201 +#define MEM_TAG           "mem="
1202 +#define BOARD_TAG  "board="
1203 +#define IGNORE_CMDLINE_MEM 1
1204 +#define DEBUG_DDR
1205 +
1206 +void parse_soft_settings(unsigned *ptr, unsigned size);
1207 +void parse_hard_settings(unsigned *ptr, unsigned size);
1208 +
1209 +void __init prom_setup_cmdline(void);
1210 +
1211 +void __init prom_init(void)
1212 +{
1213 +       DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
1214 +       phys_t memsize = 0-ddr->ddrmask;
1215 +
1216 +       /* this should be the very first message, even before serial is properly initialized */
1217 +       prom_setup_cmdline();
1218 +       setup_serial_port();
1219 +
1220 +       mips_machgroup = MACH_GROUP_MIKROTIK;
1221 +       soft_reboot = read_c0_status() & SR_NMI;
1222 +       pm_power_off = NULL;
1223 +
1224 +       /*
1225 +        * give all RAM to boot allocator,
1226 +        * except for the first 0x400 and the last 0x200 bytes
1227 +        */
1228 +       add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
1229 +}
1230 +
1231 +void prom_free_prom_memory(void)
1232 +{
1233 +       /* FIXME: STUB */
1234 +}
1235 +
1236 +void __init prom_setup_cmdline(void){
1237 +       char cmd_line[CL_SIZE];
1238 +       char *cp;
1239 +       int prom_argc;
1240 +       char **prom_argv, **prom_envp;
1241 +       int i;
1242 +
1243 +       prom_argc = fw_arg0;
1244 +       prom_argv = (char **) fw_arg1;
1245 +       prom_envp = (char **) fw_arg2;
1246 +
1247 +       cp=cmd_line;
1248 +               /* Note: it is common that parameters start at argv[1] and not argv[0],
1249 +               however, our elf loader starts at [0] */
1250 +       for(i=0;i<prom_argc;i++){
1251 +               if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) {
1252 +                       idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10);
1253 +                       continue;
1254 +               }
1255 +#ifdef IGNORE_CMDLINE_MEM
1256 +               /* parses out the "mem=xx" arg */
1257 +               if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) {
1258 +                       continue;
1259 +               }
1260 +#endif
1261 +               if (i>0) *(cp++) = ' ';
1262 +               if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
1263 +                       board_type =  simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10);
1264 +               }
1265 +               if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {
1266 +                       gpio_bootup_state =  simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10);
1267 +               }
1268 +               strcpy(cp,prom_argv[i]);
1269 +               cp+=strlen(prom_argv[i]);
1270 +       }
1271 +
1272 +       i=strlen(arcs_cmdline);
1273 +       if (i>0){
1274 +               *(cp++) = ' ';
1275 +               strcpy(cp,arcs_cmdline);
1276 +               cp+=strlen(arcs_cmdline);
1277 +       }
1278 +       if (gpio_bootup_state&0x02)
1279 +               strcpy(cp,GPIO_INIT_NOBUTTON);
1280 +       else
1281 +               strcpy(cp,GPIO_INIT_BUTTON);
1282 +       cmd_line[CL_SIZE-1] = '\0';
1283 +
1284 +       strcpy(arcs_cmdline,cmd_line);
1285 +}
1286 +
1287 diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
1288 --- linux.old/arch/mips/rb500/serial.c  1970-01-01 01:00:00.000000000 +0100
1289 +++ linux.dev/arch/mips/rb500/serial.c  2006-12-14 04:09:50.000000000 +0100
1290 @@ -0,0 +1,77 @@
1291 +/**************************************************************************
1292 + *
1293 + *  BRIEF MODULE DESCRIPTION
1294 + *     Serial port initialisation.
1295 + *
1296 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
1297 + *
1298 + *  This program is free software; you can redistribute  it and/or modify it
1299 + *  under  the terms of  the GNU General  Public License as published by the
1300 + *  Free Software Foundation;  either version 2 of the  License, or (at your
1301 + *  option) any later version.
1302 + *
1303 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
1304 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
1305 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
1306 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
1307 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1308 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
1309 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1310 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
1311 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1312 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1313 + *
1314 + *  You should have received a copy of the  GNU General Public License along
1315 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
1316 + *  675 Mass Ave, Cambridge, MA 02139, USA.
1317 + *
1318 + *
1319 + **************************************************************************
1320 + * May 2004 rkt, neb
1321 + *
1322 + * Initial Release
1323 + *
1324 + *
1325 + *
1326 + **************************************************************************
1327 + */
1328 +
1329 +
1330 +#include <linux/autoconf.h>
1331 +#include <linux/init.h>
1332 +#include <linux/sched.h>
1333 +#include <linux/pci.h>
1334 +#include <linux/interrupt.h>
1335 +#include <linux/tty.h>
1336 +#include <linux/serial.h>
1337 +#include <linux/serial_core.h>
1338 +
1339 +#include <asm/time.h>
1340 +#include <asm/cpu.h>
1341 +#include <asm/bootinfo.h>
1342 +#include <asm/irq.h>
1343 +#include <asm/serial.h>
1344 +#include <asm/rc32434/rc32434.h>
1345 +
1346 +extern unsigned int idt_cpu_freq;
1347 +
1348 +static struct uart_port serial_req = {
1349 +       .type = PORT_16550A,
1350 +       .line = 0,
1351 +       .irq = RC32434_UART0_IRQ,
1352 +       .flags = STD_COM_FLAGS,
1353 +       .iotype = UPIO_MEM,
1354 +       .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
1355 +//     .fifosize = 14
1356 +       .regshift = 2
1357 +};
1358 +
1359 +int __init setup_serial_port(void)
1360 +{
1361 +       serial_req.uartclk = idt_cpu_freq;
1362 +
1363 +       if (early_serial_setup(&serial_req))
1364 +               return -ENODEV;
1365 +
1366 +       return(0);
1367 +}
1368 diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
1369 --- linux.old/arch/mips/rb500/setup.c   1970-01-01 01:00:00.000000000 +0100
1370 +++ linux.dev/arch/mips/rb500/setup.c   2006-12-14 04:51:12.000000000 +0100
1371 @@ -0,0 +1,81 @@
1372 +/*
1373 + * setup.c - boot time setup code
1374 + */
1375 +
1376 +#include <linux/init.h>
1377 +#include <linux/mm.h>
1378 +#include <linux/sched.h>
1379 +#include <linux/irq.h>
1380 +#include <linux/ioport.h>
1381 +#include <linux/pm.h>
1382 +#include <asm/bootinfo.h>
1383 +#include <asm/mipsregs.h>
1384 +#include <asm/pgtable.h>
1385 +#include <asm/reboot.h>
1386 +#include <asm/addrspace.h>     /* for KSEG1ADDR() */
1387 +#include <asm/time.h>
1388 +#include <asm/io.h>
1389 +#include <asm/rc32434/rc32434.h>
1390 +#include <asm/rc32434/pci.h>
1391 +
1392 +#ifdef CONFIG_PCI
1393 +extern void *rc32434_time_init(void);
1394 +extern int __init rc32434_pcibridge_init(void);
1395 +#endif
1396 +
1397 +#define epldMask ((volatile unsigned char *)0xB900000d)
1398 +
1399 +static void rb_machine_restart(char *command)
1400 +{
1401 +       /* just jump to the reset vector */
1402 +       * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
1403 +       ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
1404 +}
1405 +
1406 +static void rb_machine_halt(void)
1407 +{
1408 +       for(;;) continue;
1409 +}
1410 +
1411 +#ifdef CONFIG_CPU_HAS_WB
1412 +void (*__wbflush) (void);
1413 +
1414 +static void rb_write_buffer_flush(void)
1415 +{
1416 +       __asm__ __volatile__
1417 +           ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
1418 +}
1419 +#endif
1420 +
1421 +void __init plat_mem_setup(void)
1422 +{
1423 +       unsigned int pciCntlVal;
1424 +
1425 +       board_time_init = rc32434_time_init;
1426 +
1427 +#ifdef CONFIG_CPU_HAS_WB
1428 +       __wbflush = rb_write_buffer_flush;
1429 +#endif
1430 +       _machine_restart = rb_machine_restart;
1431 +       _machine_halt = rb_machine_halt;
1432 +       /*_machine_power_off = rb_machine_power_halt;*/
1433 +       pm_power_off = rb_machine_halt;
1434 +
1435 +       set_io_port_base(KSEG1);
1436 +
1437 +       pciCntlVal=rc32434_pci->pcic;
1438 +       pciCntlVal &= 0xFFFFFF7;
1439 +       rc32434_pci->pcic = pciCntlVal;
1440 +
1441 +#ifdef CONFIG_PCI
1442 +       /* Enable PCI interrupts in EPLD Mask register */
1443 +       *epldMask = 0x0;
1444 +       *(epldMask + 1) = 0x0;
1445 +#endif
1446 +       write_c0_wired(0);
1447 +}
1448 +
1449 +const char *get_system_type(void)
1450 +{
1451 +       return "MIPS RB500";
1452 +}
1453 diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
1454 --- linux.old/arch/mips/rb500/time.c    1970-01-01 01:00:00.000000000 +0100
1455 +++ linux.dev/arch/mips/rb500/time.c    2006-12-14 04:48:33.000000000 +0100
1456 @@ -0,0 +1,93 @@
1457 +/*
1458 +****************************************************************************
1459 +* Carsten Langgaard, carstenl@mips.com
1460 +* Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1461 +*
1462 +***************************************************************************
1463 +*
1464 +*  This program is free software; you can distribute it and/or modify it
1465 +*  under the terms of the GNU General Public License (Version 2) as
1466 +*  published by the Free Software Foundation.
1467 +*
1468 +*  This program is distributed in the hope it will be useful, but WITHOUT
1469 +*  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1470 +*  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1471 +*  for more details.
1472 +*
1473 +*  You should have received a copy of the GNU General Public License along
1474 +*  with this program; if not, write to the Free Software Foundation, Inc.,
1475 +*  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1476 +*
1477 +****************************************************************************
1478 +*
1479 +* Setting up the clock on the MIPS boards.
1480 +*
1481 +****************************************************************************
1482 +* P. Sadik Oct 10, 2003
1483 +*
1484 +* Started change log.
1485 +* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
1486 +* Code cleanup
1487 +****************************************************************************
1488 +*/
1489 +
1490 +#include <linux/autoconf.h>
1491 +#include <linux/init.h>
1492 +#include <linux/kernel_stat.h>
1493 +#include <linux/sched.h>
1494 +#include <linux/spinlock.h>
1495 +#include <linux/mc146818rtc.h>
1496 +#include <linux/irq.h>
1497 +#include <linux/timex.h>
1498 +
1499 +#include <asm/mipsregs.h>
1500 +#include <asm/ptrace.h>
1501 +#include <asm/debug.h>
1502 +#include <asm/rc32434/rc32434.h>
1503 +
1504 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1505 +static unsigned long r4k_cur;    /* What counter should be at next timer irq */
1506 +extern unsigned int mips_hpt_frequency;
1507 +extern unsigned int idt_cpu_freq;
1508 +
1509 +/*
1510 + * Figure out the r4k offset, the amount to increment the compare
1511 + * register for each time tick. There is no RTC available.
1512 + *
1513 + * The RC32434 counts at half the CPU *core* speed.
1514 + */
1515 +static unsigned long __init cal_r4koff(void)
1516 +{
1517 +       mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1518 +       return (mips_hpt_frequency / HZ);
1519 +}
1520 +
1521 +
1522 +void __init rc32434_time_init(void)
1523 +{
1524 +       unsigned int est_freq, flags;
1525 +
1526 +       local_irq_save(flags);
1527 +
1528 +       printk("calculating r4koff... ");
1529 +       r4k_offset = cal_r4koff();
1530 +       printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1531 +
1532 +       est_freq = 2*r4k_offset*HZ;
1533 +       est_freq += 5000;       /* round */
1534 +       est_freq -= est_freq%10000;
1535 +       printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1536 +              (est_freq%1000000)*100/1000000);
1537 +       local_irq_restore(flags);
1538 +}
1539 +
1540 +void __init plat_timer_setup(struct irqaction *irq)
1541 +{
1542 +       /* we are using the cpu counter for timer interrupts */
1543 +       setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1544 +
1545 +       /* to generate the first timer interrupt */
1546 +       r4k_cur = (read_c0_count() + r4k_offset);
1547 +       write_c0_compare(r4k_cur);
1548 +}
1549 +
1550 diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
1551 --- linux.old/drivers/pci/Makefile      2006-11-29 22:57:37.000000000 +0100
1552 +++ linux.dev/drivers/pci/Makefile      2006-12-14 04:09:50.000000000 +0100
1553 @@ -16,6 +16,7 @@
1554
1555  # Build the PCI MSI interrupt support
1556  obj-$(CONFIG_PCI_MSI) += msi.o
1557 +obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
1558
1559  # Build the Hypertransport interrupt support
1560  obj-$(CONFIG_HT_IRQ) += htirq.o
1561 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1562 --- linux.old/include/asm-mips/bootinfo.h       2006-11-29 22:57:37.000000000 +0100
1563 +++ linux.dev/include/asm-mips/bootinfo.h       2006-12-14 04:09:50.000000000 +0100
1564 @@ -212,6 +212,8 @@
1565  #define MACH_GROUP_NEC_EMMA2RH 25      /* NEC EMMA2RH (was 23)         */
1566  #define  MACH_NEC_MARKEINS     0       /* NEC EMMA2RH Mark-eins        */
1567
1568 +#define MACH_GROUP_MIKROTIK    24 /* Mikrotik Boards                       */
1569 +
1570  #define CL_SIZE                        COMMAND_LINE_SIZE
1571
1572  const char *get_system_type(void);
1573 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
1574 --- linux.old/include/asm-mips/cpu.h    2006-11-29 22:57:37.000000000 +0100
1575 +++ linux.dev/include/asm-mips/cpu.h    2006-12-14 04:09:50.000000000 +0100
1576 @@ -200,7 +200,8 @@
1577  #define CPU_SB1A               62
1578  #define CPU_74K                        63
1579  #define CPU_R14000             64
1580 -#define CPU_LAST               64
1581 +#define CPU_RC32300            65
1582 +#define CPU_LAST               65
1583
1584  /*
1585   * ISA Level encodings
1586 diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
1587 --- linux.old/include/asm-mips/rc32434/ddr.h    1970-01-01 01:00:00.000000000 +0100
1588 +++ linux.dev/include/asm-mips/rc32434/ddr.h    2006-12-14 04:09:50.000000000 +0100
1589 @@ -0,0 +1,173 @@
1590 +#ifndef __IDT_DDR_H__
1591 +#define __IDT_DDR_H__
1592 +
1593 +/*******************************************************************************
1594 + *
1595 + * Copyright 2002 Integrated Device Technology, Inc.
1596 + *             All rights reserved.
1597 + *
1598 + * DDR register definition.
1599 + *
1600 + * File   : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1601 + *
1602 + * Author : ryan.holmQVist@idt.com
1603 + * Date   : 20011005
1604 + * Update :
1605 + *          $Log: ddr.h,v $
1606 + *          Revision 1.2  2002/06/06 18:34:03  astichte
1607 + *          Added XXX_PhysicalAddress and XXX_VirtualAddress
1608 + *
1609 + *          Revision 1.1  2002/05/29 17:33:21  sysarch
1610 + *          jba File moved from vcode/include/idt/acacia
1611 + *
1612 + *
1613 + ******************************************************************************/
1614 +
1615 +enum
1616 +{
1617 +       DDR0_PhysicalAddress    = 0x18018000,
1618 +       DDR_PhysicalAddress     = DDR0_PhysicalAddress,         // Default
1619 +
1620 +       DDR0_VirtualAddress     = 0xb8018000,
1621 +       DDR_VirtualAddress      = DDR0_VirtualAddress,          // Default
1622 +} ;
1623 +
1624 +typedef struct DDR_s
1625 +{
1626 +       u32     ddrbase ;
1627 +       u32     ddrmask ;
1628 +       u32     res1;
1629 +       u32     res2;
1630 +       u32     ddrc ;
1631 +       u32     ddrabase ;
1632 +       u32     ddramask ;
1633 +       u32     ddramap ;
1634 +       u32     ddrcust;
1635 +       u32     ddrrdc;
1636 +       u32     ddrspare;
1637 +} volatile *DDR_t ;
1638 +
1639 +enum
1640 +{
1641 +       DDR0BASE_baseaddr_b     = 16,
1642 +       DDR0BASE_baseaddr_m     = 0xffff0000,
1643 +
1644 +       DDR0MASK_mask_b         = 16,
1645 +       DDR0MASK_mask_m         = 0xffff0000,
1646 +
1647 +       DDR1BASE_baseaddr_b     = 16,
1648 +       DDR1BASE_baseaddr_m     = 0xffff0000,
1649 +
1650 +       DDR1MASK_mask_b         = 16,
1651 +       DDR1MASK_mask_m         = 0xffff0000,
1652 +
1653 +       DDRC_ata_b              = 5,
1654 +       DDRC_ata_m              = 0x000000E0,
1655 +       DDRC_dbw_b              = 8,
1656 +       DDRC_dbw_m              = 0x00000100,
1657 +       DDRC_wr_b               = 9,
1658 +       DDRC_wr_m               = 0x00000600,
1659 +       DDRC_ps_b               = 11,
1660 +       DDRC_ps_m               = 0x00001800,
1661 +       DDRC_dtype_b            = 13,
1662 +       DDRC_dtype_m            = 0x0000e000,
1663 +       DDRC_rfc_b              = 16,
1664 +       DDRC_rfc_m              = 0x000f0000,
1665 +       DDRC_rp_b               = 20,
1666 +       DDRC_rp_m               = 0x00300000,
1667 +       DDRC_ap_b               = 22,
1668 +       DDRC_ap_m               = 0x00400000,
1669 +       DDRC_rcd_b              = 23,
1670 +       DDRC_rcd_m              = 0x01800000,
1671 +       DDRC_cl_b               = 25,
1672 +       DDRC_cl_m               = 0x06000000,
1673 +       DDRC_dbm_b              = 27,
1674 +       DDRC_dbm_m              = 0x08000000,
1675 +       DDRC_sds_b              = 28,
1676 +       DDRC_sds_m              = 0x10000000,
1677 +       DDRC_atp_b              = 29,
1678 +       DDRC_atp_m              = 0x60000000,
1679 +       DDRC_re_b               = 31,
1680 +       DDRC_re_m               = 0x80000000,
1681 +
1682 +       DDRRDC_ces_b            = 0,
1683 +       DDRRDC_ces_m            = 0x00000001,
1684 +       DDRRDC_ace_b            = 1,
1685 +       DDRRDC_ace_m            = 0x00000002,
1686 +
1687 +       DDRABASE_baseaddr_b     = 16,
1688 +       DDRABASE_baseaddr_m     = 0xffff0000,
1689 +
1690 +       DDRAMASK_mask_b         = 16,
1691 +       DDRAMASK_mask_m         = 0xffff0000,
1692 +
1693 +       DDRAMAP_map_b           = 16,
1694 +       DDRAMAP_map_m           = 0xffff0000,
1695 +
1696 +       DDRCUST_cs_b            = 0,
1697 +       DDRCUST_cs_m            = 0x00000003,
1698 +       DDRCUST_we_b            = 2,
1699 +       DDRCUST_we_m            = 0x00000004,
1700 +       DDRCUST_ras_b           = 3,
1701 +       DDRCUST_ras_m           = 0x00000008,
1702 +       DDRCUST_cas_b           = 4,
1703 +       DDRCUST_cas_m           = 0x00000010,
1704 +       DDRCUST_cke_b           = 5,
1705 +       DDRCUST_cke_m           = 0x00000020,
1706 +       DDRCUST_ba_b            = 6,
1707 +       DDRCUST_ba_m            = 0x000000c0,
1708 +
1709 +       RCOUNT_rcount_b         = 0,
1710 +       RCOUNT_rcount_m         = 0x0000ffff,
1711 +
1712 +       RCOMPARE_rcompare_b     = 0,
1713 +       RCOMPARE_rcompare_m     = 0x0000ffff,
1714 +
1715 +       RTC_ce_b                = 0,
1716 +       RTC_ce_m                = 0x00000001,
1717 +       RTC_to_b                = 1,
1718 +       RTC_to_m                = 0x00000002,
1719 +       RTC_rqe_b               = 2,
1720 +       RTC_rqe_m               = 0x00000004,
1721 +
1722 +       DDRDQSC_dm_b            = 0,
1723 +       DDRDQSC_dm_m            = 0x00000003,
1724 +       DDRDQSC_dqsbs_b         = 2,
1725 +       DDRDQSC_dqsbs_m         = 0x000000fc,
1726 +       DDRDQSC_db_b            = 8,
1727 +       DDRDQSC_db_m            = 0x00000100,
1728 +       DDRDQSC_dbsp_b          = 9,
1729 +       DDRDQSC_dbsp_m          = 0x01fffe00,
1730 +       DDRDQSC_bdp_b           = 25,
1731 +       DDRDQSC_bdp_m           = 0x7e000000,
1732 +
1733 +       DDRDLLC_eao_b           = 0,
1734 +       DDRDLLC_eao_m           = 0x00000001,
1735 +       DDRDLLC_eo_b            = 1,
1736 +       DDRDLLC_eo_m            = 0x0000003e,
1737 +       DDRDLLC_fs_b            = 6,
1738 +       DDRDLLC_fs_m            = 0x000000c0,
1739 +       DDRDLLC_as_b            = 8,
1740 +       DDRDLLC_as_m            = 0x00000700,
1741 +       DDRDLLC_sp_b            = 11,
1742 +       DDRDLLC_sp_m            = 0x001ff800,
1743 +
1744 +       DDRDLLFC_men_b          = 0,
1745 +       DDRDLLFC_men_m          = 0x00000001,
1746 +       DDRDLLFC_aen_b          = 1,
1747 +       DDRDLLFC_aen_m          = 0x00000002,
1748 +       DDRDLLFC_ff_b           = 2,
1749 +       DDRDLLFC_ff_m           = 0x00000004,
1750 +
1751 +       DDRDLLTA_addr_b         = 2,
1752 +       DDRDLLTA_addr_m         = 0xfffffffc,
1753 +
1754 +       DDRDLLED_dbe_b          = 0,
1755 +       DDRDLLED_dbe_m          = 0x00000001,
1756 +       DDRDLLED_dte_b          = 1,
1757 +       DDRDLLED_dte_m          = 0x00000002,
1758 +
1759 +
1760 +} ;
1761 +
1762 +#endif // __IDT_DDR_H__
1763 diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
1764 --- linux.old/include/asm-mips/rc32434/dma.h    1970-01-01 01:00:00.000000000 +0100
1765 +++ linux.dev/include/asm-mips/rc32434/dma.h    2006-12-14 04:09:50.000000000 +0100
1766 @@ -0,0 +1,168 @@
1767 +#ifndef __IDT_DMA_H__
1768 +#define __IDT_DMA_H__
1769 +
1770 +/*******************************************************************************
1771 + *
1772 + * Copyright 2002 Integrated Device Technology, Inc.
1773 + *             All rights reserved.
1774 + *
1775 + * DMA register definition.
1776 + *
1777 + * File   : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
1778 + *
1779 + * Author : ryan.holmQVist@idt.com
1780 + * Date   : 20011005
1781 + * Update :
1782 + *         $Log: dma.h,v $
1783 + *         Revision 1.3  2002/06/06 18:34:03  astichte
1784 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
1785 + *
1786 + *         Revision 1.2  2002/06/05 18:30:46  astichte
1787 + *         Removed IDTField
1788 + *
1789 + *         Revision 1.1  2002/05/29 17:33:21  sysarch
1790 + *         jba File moved from vcode/include/idt/acacia
1791 + *
1792 + *
1793 + ******************************************************************************/
1794 +
1795 +enum
1796 +{
1797 +       DMA0_PhysicalAddress    = 0x18040000,
1798 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
1799 +
1800 +       DMA0_VirtualAddress     = 0xb8040000,
1801 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
1802 +} ;
1803 +
1804 +/*
1805 + * DMA descriptor (in physical memory).
1806 + */
1807 +
1808 +typedef struct DMAD_s
1809 +{
1810 +       u32                     control ;       // Control. use DMAD_*
1811 +       u32                     ca ;            // Current Address.
1812 +       u32                     devcs ;         // Device control and status.
1813 +       u32                     link ;          // Next descriptor in chain.
1814 +} volatile *DMAD_t ;
1815 +
1816 +enum
1817 +{
1818 +       DMAD_size               = sizeof (struct DMAD_s),
1819 +       DMAD_count_b            = 0,            // in DMAD_t -> control
1820 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
1821 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
1822 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
1823 +               DMAD_ds_ethRcv_v        = 0,
1824 +               DMAD_ds_ethXmt_v        = 0,
1825 +               DMAD_ds_memToFifo_v     = 0,
1826 +               DMAD_ds_fifoToMem_v     = 0,
1827 +               DMAD_ds_pciToMem_v      = 0,
1828 +               DMAD_ds_memToPci_v      = 0,
1829 +
1830 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
1831 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
1832 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
1833 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
1834 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
1835 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
1836 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
1837 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
1838 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
1839 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
1840 +       DMAD_cof_b              = 25,           // chain on finished
1841 +       DMAD_cof_m              = 0x02000000,   //
1842 +       DMAD_cod_b              = 26,           // chain on done
1843 +       DMAD_cod_m              = 0x04000000,   //
1844 +       DMAD_iof_b              = 27,           // interrupt on finished
1845 +       DMAD_iof_m              = 0x08000000,   //
1846 +       DMAD_iod_b              = 28,           // interrupt on done
1847 +       DMAD_iod_m              = 0x10000000,   //
1848 +       DMAD_t_b                = 29,           // terminated
1849 +       DMAD_t_m                = 0x20000000,   //
1850 +       DMAD_d_b                = 30,           // done
1851 +       DMAD_d_m                = 0x40000000,   //
1852 +       DMAD_f_b                = 31,           // finished
1853 +       DMAD_f_m                = 0x80000000,   //
1854 +} ;
1855 +
1856 +/*
1857 + * DMA register (within Internal Register Map).
1858 + */
1859 +
1860 +struct DMA_Chan_s
1861 +{
1862 +       u32             dmac ;          // Control.
1863 +       u32             dmas ;          // Status.
1864 +       u32             dmasm ;         // Mask.
1865 +       u32             dmadptr ;       // Descriptor pointer.
1866 +       u32             dmandptr ;      // Next descriptor pointer.
1867 +};
1868 +
1869 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
1870 +
1871 +//DMA_Channels   use DMACH_count instead
1872 +
1873 +enum
1874 +{
1875 +       DMAC_run_b      = 0,            //
1876 +       DMAC_run_m      = 0x00000001,   //
1877 +       DMAC_dm_b       = 1,            // done mask
1878 +       DMAC_dm_m       = 0x00000002,   //
1879 +       DMAC_mode_b     = 2,            //
1880 +       DMAC_mode_m     = 0x0000000c,   //
1881 +               DMAC_mode_auto_v        = 0,
1882 +               DMAC_mode_burst_v       = 1,
1883 +               DMAC_mode_transfer_v    = 2, //usually used
1884 +               DMAC_mode_reserved_v    = 3,
1885 +       DMAC_a_b        = 4,            //
1886 +       DMAC_a_m        = 0x00000010,   //
1887 +
1888 +       DMAS_f_b        = 0,            // finished (sticky)
1889 +       DMAS_f_m        = 0x00000001,   //
1890 +       DMAS_d_b        = 1,            // done (sticky)
1891 +       DMAS_d_m        = 0x00000002,   //
1892 +       DMAS_c_b        = 2,            // chain (sticky)
1893 +       DMAS_c_m        = 0x00000004,   //
1894 +       DMAS_e_b        = 3,            // error (sticky)
1895 +       DMAS_e_m        = 0x00000008,   //
1896 +       DMAS_h_b        = 4,            // halt (sticky)
1897 +       DMAS_h_m        = 0x00000010,   //
1898 +
1899 +       DMASM_f_b       = 0,            // finished (1=mask)
1900 +       DMASM_f_m       = 0x00000001,   //
1901 +       DMASM_d_b       = 1,            // done (1=mask)
1902 +       DMASM_d_m       = 0x00000002,   //
1903 +       DMASM_c_b       = 2,            // chain (1=mask)
1904 +       DMASM_c_m       = 0x00000004,   //
1905 +       DMASM_e_b       = 3,            // error (1=mask)
1906 +       DMASM_e_m       = 0x00000008,   //
1907 +       DMASM_h_b       = 4,            // halt (1=mask)
1908 +       DMASM_h_m       = 0x00000010,   //
1909 +} ;
1910 +
1911 +/*
1912 + * DMA channel definitions
1913 + */
1914 +
1915 +enum
1916 +{
1917 +       DMACH_ethRcv = 0,
1918 +       DMACH_ethXmt = 1,
1919 +       DMACH_memToFifo = 2,
1920 +       DMACH_fifoToMem = 3,
1921 +       DMACH_pciToMem = 4,
1922 +       DMACH_memToPci = 5,
1923 +
1924 +       DMACH_count //must be last
1925 +};
1926 +
1927 +
1928 +typedef struct DMAC_s
1929 +{
1930 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
1931 +} volatile *DMA_t ;
1932 +
1933 +#endif // __IDT_DMA_H__
1934 +
1935 diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
1936 --- linux.old/include/asm-mips/rc32434/dma_v.h  1970-01-01 01:00:00.000000000 +0100
1937 +++ linux.dev/include/asm-mips/rc32434/dma_v.h  2006-12-14 04:09:50.000000000 +0100
1938 @@ -0,0 +1,72 @@
1939 +#ifndef __IDT_DMA_V_H__
1940 +#define __IDT_DMA_V_H__
1941 +
1942 +/*******************************************************************************
1943 + *
1944 + * Copyright 2002 Integrated Device Technology, Inc.
1945 + *             All rights reserved.
1946 + *
1947 + * DMA register definition.
1948 + *
1949 + * File   : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
1950 + *
1951 + * Author : ryan.holmQVist@idt.com
1952 + * Date   : 20011005
1953 + * Update :
1954 + *         $Log: dma.h,v $
1955 + *         Revision 1.3  2002/06/06 18:34:03  astichte
1956 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
1957 + *
1958 + *         Revision 1.2  2002/06/05 18:30:46  astichte
1959 + *         Removed IDTField
1960 + *
1961 + *         Revision 1.1  2002/05/29 17:33:21  sysarch
1962 + *         jba File moved from vcode/include/idt/acacia
1963 + *
1964 + *
1965 + ******************************************************************************/
1966 +#include  <asm/rc32434/dma.h>
1967 +#include  <asm/rc32434/rc32434.h>
1968 +#define DMA_CHAN_OFFSET  0x14
1969 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
1970 +#define DMA_COUNT(count)   \
1971 +  ((count) & DMAD_count_m)
1972 +
1973 +#define DMA_HALT_TIMEOUT 500
1974 +
1975 +
1976 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
1977 +{
1978 +       int timeout=1;
1979 +       if (local_readl(&ch->dmac) & DMAC_run_m) {
1980 +               local_writel(0, &ch->dmac);
1981 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
1982 +                       if (local_readl(&ch->dmas) & DMAS_h_m) {
1983 +                               local_writel(0, &ch->dmas);
1984 +                               break;
1985 +                       }
1986 +               }
1987 +       }
1988 +
1989 +       return timeout ? 0 : 1;
1990 +}
1991 +
1992 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
1993 +{
1994 +       local_writel(0, &ch->dmandptr);
1995 +       local_writel(dma_addr, &ch->dmadptr);
1996 +}
1997 +
1998 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
1999 +{
2000 +       local_writel(dma_addr, &ch->dmandptr);
2001 +}
2002 +
2003 +#endif // __IDT_DMA_V_H__
2004 +
2005 +
2006 +
2007 +
2008 +
2009 +
2010 +
2011 diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
2012 --- linux.old/include/asm-mips/rc32434/eth.h    1970-01-01 01:00:00.000000000 +0100
2013 +++ linux.dev/include/asm-mips/rc32434/eth.h    2006-12-14 04:09:50.000000000 +0100
2014 @@ -0,0 +1,320 @@
2015 +#ifndef        __IDT_ETH_H__
2016 +#define        __IDT_ETH_H__
2017 +
2018 +/*******************************************************************************
2019 + *
2020 + * Copyright 2002 Integrated Device Technology, Inc.
2021 + *             All rights reserved.
2022 + *
2023 + * Ethernet register definition.
2024 + *
2025 + * File   : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2026 + *
2027 + * Author : Allen.Stichter@idt.com
2028 + * Date   : 20020605
2029 + * Update :
2030 + *         $Log: eth.h,v $
2031 + *         Revision 1.3  2002/06/06 18:34:04  astichte
2032 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2033 + *
2034 + *         Revision 1.2  2002/06/05 18:19:46  astichte
2035 + *         Added
2036 + *
2037 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
2038 + *         jba File moved from vcode/include/idt/acacia
2039 + *
2040 + ******************************************************************************/
2041 +
2042 +enum
2043 +{
2044 +       ETH0_PhysicalAddress    = 0x18060000,
2045 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
2046 +
2047 +       ETH0_VirtualAddress     = 0xb8060000,
2048 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
2049 +} ;
2050 +
2051 +typedef struct
2052 +{
2053 +       u32 ethintfc            ;
2054 +       u32 ethfifott           ;
2055 +       u32 etharc              ;
2056 +       u32 ethhash0            ;
2057 +       u32 ethhash1            ;
2058 +       u32 ethu0 [4]           ;       // Reserved.
2059 +       u32 ethpfs              ;
2060 +       u32 ethmcp              ;
2061 +       u32 eth_u1 [10]         ;       // Reserved.
2062 +       u32 ethspare            ;
2063 +       u32 eth_u2 [42]         ;       // Reserved.
2064 +       u32 ethsal0             ;
2065 +       u32 ethsah0             ;
2066 +       u32 ethsal1             ;
2067 +       u32 ethsah1             ;
2068 +       u32 ethsal2             ;
2069 +       u32 ethsah2             ;
2070 +       u32 ethsal3             ;
2071 +       u32 ethsah3             ;
2072 +       u32 ethrbc              ;
2073 +       u32 ethrpc              ;
2074 +       u32 ethrupc             ;
2075 +       u32 ethrfc              ;
2076 +       u32 ethtbc              ;
2077 +       u32 ethgpf              ;
2078 +       u32 eth_u9 [50]         ;       // Reserved.
2079 +       u32 ethmac1             ;
2080 +       u32 ethmac2             ;
2081 +       u32 ethipgt             ;
2082 +       u32 ethipgr             ;
2083 +       u32 ethclrt             ;
2084 +       u32 ethmaxf             ;
2085 +       u32 eth_u10             ;       // Reserved.
2086 +       u32 ethmtest            ;
2087 +       u32 miimcfg             ;
2088 +       u32 miimcmd             ;
2089 +       u32 miimaddr            ;
2090 +       u32 miimwtd             ;
2091 +       u32 miimrdd             ;
2092 +       u32 miimind             ;
2093 +       u32 eth_u11             ;       // Reserved.
2094 +       u32 eth_u12             ;       // Reserved.
2095 +       u32 ethcfsa0            ;
2096 +       u32 ethcfsa1            ;
2097 +       u32 ethcfsa2            ;
2098 +} volatile *ETH_t;
2099 +
2100 +enum
2101 +{
2102 +       ETHINTFC_en_b           = 0,
2103 +       ETHINTFC_en_m           = 0x00000001,
2104 +       ETHINTFC_its_b          = 1,
2105 +       ETHINTFC_its_m          = 0x00000002,
2106 +       ETHINTFC_rip_b          = 2,
2107 +       ETHINTFC_rip_m          = 0x00000004,
2108 +       ETHINTFC_jam_b          = 3,
2109 +       ETHINTFC_jam_m          = 0x00000008,
2110 +       ETHINTFC_ovr_b          = 4,
2111 +       ETHINTFC_ovr_m          = 0x00000010,
2112 +       ETHINTFC_und_b          = 5,
2113 +       ETHINTFC_und_m          = 0x00000020,
2114 +       ETHINTFC_iom_b          = 6,
2115 +       ETHINTFC_iom_m          = 0x000000c0,
2116 +
2117 +       ETHFIFOTT_tth_b         = 0,
2118 +       ETHFIFOTT_tth_m         = 0x0000007f,
2119 +
2120 +       ETHARC_pro_b            = 0,
2121 +       ETHARC_pro_m            = 0x00000001,
2122 +       ETHARC_am_b             = 1,
2123 +       ETHARC_am_m             = 0x00000002,
2124 +       ETHARC_afm_b            = 2,
2125 +       ETHARC_afm_m            = 0x00000004,
2126 +       ETHARC_ab_b             = 3,
2127 +       ETHARC_ab_m             = 0x00000008,
2128 +
2129 +       ETHSAL_byte5_b          = 0,
2130 +       ETHSAL_byte5_m          = 0x000000ff,
2131 +       ETHSAL_byte4_b          = 8,
2132 +       ETHSAL_byte4_m          = 0x0000ff00,
2133 +       ETHSAL_byte3_b          = 16,
2134 +       ETHSAL_byte3_m          = 0x00ff0000,
2135 +       ETHSAL_byte2_b          = 24,
2136 +       ETHSAL_byte2_m          = 0xff000000,
2137 +
2138 +       ETHSAH_byte1_b          = 0,
2139 +       ETHSAH_byte1_m          = 0x000000ff,
2140 +       ETHSAH_byte0_b          = 8,
2141 +       ETHSAH_byte0_m          = 0x0000ff00,
2142 +
2143 +       ETHGPF_ptv_b            = 0,
2144 +       ETHGPF_ptv_m            = 0x0000ffff,
2145 +
2146 +       ETHPFS_pfd_b            = 0,
2147 +       ETHPFS_pfd_m            = 0x00000001,
2148 +
2149 +       ETHCFSA0_cfsa4_b        = 0,
2150 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
2151 +       ETHCFSA0_cfsa5_b        = 8,
2152 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
2153 +
2154 +       ETHCFSA1_cfsa2_b        = 0,
2155 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
2156 +       ETHCFSA1_cfsa3_b        = 8,
2157 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
2158 +
2159 +       ETHCFSA2_cfsa0_b        = 0,
2160 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
2161 +       ETHCFSA2_cfsa1_b        = 8,
2162 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
2163 +
2164 +       ETHMAC1_re_b            = 0,
2165 +       ETHMAC1_re_m            = 0x00000001,
2166 +       ETHMAC1_paf_b           = 1,
2167 +       ETHMAC1_paf_m           = 0x00000002,
2168 +       ETHMAC1_rfc_b           = 2,
2169 +       ETHMAC1_rfc_m           = 0x00000004,
2170 +       ETHMAC1_tfc_b           = 3,
2171 +       ETHMAC1_tfc_m           = 0x00000008,
2172 +       ETHMAC1_lb_b            = 4,
2173 +       ETHMAC1_lb_m            = 0x00000010,
2174 +       ETHMAC1_mr_b            = 31,
2175 +       ETHMAC1_mr_m            = 0x80000000,
2176 +
2177 +       ETHMAC2_fd_b            = 0,
2178 +       ETHMAC2_fd_m            = 0x00000001,
2179 +       ETHMAC2_flc_b           = 1,
2180 +       ETHMAC2_flc_m           = 0x00000002,
2181 +       ETHMAC2_hfe_b           = 2,
2182 +       ETHMAC2_hfe_m           = 0x00000004,
2183 +       ETHMAC2_dc_b            = 3,
2184 +       ETHMAC2_dc_m            = 0x00000008,
2185 +       ETHMAC2_cen_b           = 4,
2186 +       ETHMAC2_cen_m           = 0x00000010,
2187 +       ETHMAC2_pe_b            = 5,
2188 +       ETHMAC2_pe_m            = 0x00000020,
2189 +       ETHMAC2_vpe_b           = 6,
2190 +       ETHMAC2_vpe_m           = 0x00000040,
2191 +       ETHMAC2_ape_b           = 7,
2192 +       ETHMAC2_ape_m           = 0x00000080,
2193 +       ETHMAC2_ppe_b           = 8,
2194 +       ETHMAC2_ppe_m           = 0x00000100,
2195 +       ETHMAC2_lpe_b           = 9,
2196 +       ETHMAC2_lpe_m           = 0x00000200,
2197 +       ETHMAC2_nb_b            = 12,
2198 +       ETHMAC2_nb_m            = 0x00001000,
2199 +       ETHMAC2_bp_b            = 13,
2200 +       ETHMAC2_bp_m            = 0x00002000,
2201 +       ETHMAC2_ed_b            = 14,
2202 +       ETHMAC2_ed_m            = 0x00004000,
2203 +
2204 +       ETHIPGT_ipgt_b          = 0,
2205 +       ETHIPGT_ipgt_m          = 0x0000007f,
2206 +
2207 +       ETHIPGR_ipgr2_b         = 0,
2208 +       ETHIPGR_ipgr2_m         = 0x0000007f,
2209 +       ETHIPGR_ipgr1_b         = 8,
2210 +       ETHIPGR_ipgr1_m         = 0x00007f00,
2211 +
2212 +       ETHCLRT_maxret_b        = 0,
2213 +       ETHCLRT_maxret_m        = 0x0000000f,
2214 +       ETHCLRT_colwin_b        = 8,
2215 +       ETHCLRT_colwin_m        = 0x00003f00,
2216 +
2217 +       ETHMAXF_maxf_b          = 0,
2218 +       ETHMAXF_maxf_m          = 0x0000ffff,
2219 +
2220 +       ETHMTEST_tb_b           = 2,
2221 +       ETHMTEST_tb_m           = 0x00000004,
2222 +
2223 +       ETHMCP_div_b            = 0,
2224 +       ETHMCP_div_m            = 0x000000ff,
2225 +
2226 +       MIIMCFG_rsv_b           = 0,
2227 +       MIIMCFG_rsv_m           = 0x0000000c,
2228 +
2229 +       MIIMCMD_rd_b            = 0,
2230 +       MIIMCMD_rd_m            = 0x00000001,
2231 +       MIIMCMD_scn_b           = 1,
2232 +       MIIMCMD_scn_m           = 0x00000002,
2233 +
2234 +       MIIMADDR_regaddr_b      = 0,
2235 +       MIIMADDR_regaddr_m      = 0x0000001f,
2236 +       MIIMADDR_phyaddr_b      = 8,
2237 +       MIIMADDR_phyaddr_m      = 0x00001f00,
2238 +
2239 +       MIIMWTD_wdata_b         = 0,
2240 +       MIIMWTD_wdata_m         = 0x0000ffff,
2241 +
2242 +       MIIMRDD_rdata_b         = 0,
2243 +       MIIMRDD_rdata_m         = 0x0000ffff,
2244 +
2245 +       MIIMIND_bsy_b           = 0,
2246 +       MIIMIND_bsy_m           = 0x00000001,
2247 +       MIIMIND_scn_b           = 1,
2248 +       MIIMIND_scn_m           = 0x00000002,
2249 +       MIIMIND_nv_b            = 2,
2250 +       MIIMIND_nv_m            = 0x00000004,
2251 +
2252 +} ;
2253 +
2254 +/*
2255 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
2256 + */
2257 +enum
2258 +{
2259 +       ETHRX_fd_b              = 0,
2260 +       ETHRX_fd_m              = 0x00000001,
2261 +       ETHRX_ld_b              = 1,
2262 +       ETHRX_ld_m              = 0x00000002,
2263 +       ETHRX_rok_b             = 2,
2264 +       ETHRX_rok_m             = 0x00000004,
2265 +       ETHRX_fm_b              = 3,
2266 +       ETHRX_fm_m              = 0x00000008,
2267 +       ETHRX_mp_b              = 4,
2268 +       ETHRX_mp_m              = 0x00000010,
2269 +       ETHRX_bp_b              = 5,
2270 +       ETHRX_bp_m              = 0x00000020,
2271 +       ETHRX_vlt_b             = 6,
2272 +       ETHRX_vlt_m             = 0x00000040,
2273 +       ETHRX_cf_b              = 7,
2274 +       ETHRX_cf_m              = 0x00000080,
2275 +       ETHRX_ovr_b             = 8,
2276 +       ETHRX_ovr_m             = 0x00000100,
2277 +       ETHRX_crc_b             = 9,
2278 +       ETHRX_crc_m             = 0x00000200,
2279 +       ETHRX_cv_b              = 10,
2280 +       ETHRX_cv_m              = 0x00000400,
2281 +       ETHRX_db_b              = 11,
2282 +       ETHRX_db_m              = 0x00000800,
2283 +       ETHRX_le_b              = 12,
2284 +       ETHRX_le_m              = 0x00001000,
2285 +       ETHRX_lor_b             = 13,
2286 +       ETHRX_lor_m             = 0x00002000,
2287 +       ETHRX_ces_b             = 14,
2288 +       ETHRX_ces_m             = 0x00004000,
2289 +       ETHRX_length_b          = 16,
2290 +       ETHRX_length_m          = 0xffff0000,
2291 +
2292 +       ETHTX_fd_b              = 0,
2293 +       ETHTX_fd_m              = 0x00000001,
2294 +       ETHTX_ld_b              = 1,
2295 +       ETHTX_ld_m              = 0x00000002,
2296 +       ETHTX_oen_b             = 2,
2297 +       ETHTX_oen_m             = 0x00000004,
2298 +       ETHTX_pen_b             = 3,
2299 +       ETHTX_pen_m             = 0x00000008,
2300 +       ETHTX_cen_b             = 4,
2301 +       ETHTX_cen_m             = 0x00000010,
2302 +       ETHTX_hen_b             = 5,
2303 +       ETHTX_hen_m             = 0x00000020,
2304 +       ETHTX_tok_b             = 6,
2305 +       ETHTX_tok_m             = 0x00000040,
2306 +       ETHTX_mp_b              = 7,
2307 +       ETHTX_mp_m              = 0x00000080,
2308 +       ETHTX_bp_b              = 8,
2309 +       ETHTX_bp_m              = 0x00000100,
2310 +       ETHTX_und_b             = 9,
2311 +       ETHTX_und_m             = 0x00000200,
2312 +       ETHTX_of_b              = 10,
2313 +       ETHTX_of_m              = 0x00000400,
2314 +       ETHTX_ed_b              = 11,
2315 +       ETHTX_ed_m              = 0x00000800,
2316 +       ETHTX_ec_b              = 12,
2317 +       ETHTX_ec_m              = 0x00001000,
2318 +       ETHTX_lc_b              = 13,
2319 +       ETHTX_lc_m              = 0x00002000,
2320 +       ETHTX_td_b              = 14,
2321 +       ETHTX_td_m              = 0x00004000,
2322 +       ETHTX_crc_b             = 15,
2323 +       ETHTX_crc_m             = 0x00008000,
2324 +       ETHTX_le_b              = 16,
2325 +       ETHTX_le_m              = 0x00010000,
2326 +       ETHTX_cc_b              = 17,
2327 +       ETHTX_cc_m              = 0x001E0000,
2328 +} ;
2329 +
2330 +#endif // __IDT_ETH_H__
2331 +
2332 +
2333 +
2334 +
2335 diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
2336 --- linux.old/include/asm-mips/rc32434/eth_v.h  1970-01-01 01:00:00.000000000 +0100
2337 +++ linux.dev/include/asm-mips/rc32434/eth_v.h  2006-12-14 04:09:50.000000000 +0100
2338 @@ -0,0 +1,63 @@
2339 +#ifndef        __IDT_ETH_V_H__
2340 +#define        __IDT_ETH_V_H__
2341 +
2342 +/*******************************************************************************
2343 + *
2344 + * Copyright 2002 Integrated Device Technology, Inc.
2345 + *             All rights reserved.
2346 + *
2347 + * Ethernet register definition.
2348 + *
2349 + * File   : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2350 + *
2351 + * Author : Allen.Stichter@idt.com
2352 + * Date   : 20020605
2353 + * Update :
2354 + *         $Log: eth.h,v $
2355 + *         Revision 1.3  2002/06/06 18:34:04  astichte
2356 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2357 + *
2358 + *         Revision 1.2  2002/06/05 18:19:46  astichte
2359 + *         Added
2360 + *
2361 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
2362 + *         jba File moved from vcode/include/idt/acacia
2363 + *
2364 + ******************************************************************************/
2365 +
2366 +#include  <asm/rc32434/eth.h>
2367 +
2368 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
2369 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
2370 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
2371 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
2372 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
2373 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
2374 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
2375 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
2376 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
2377 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
2378 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
2379 +
2380 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
2381 +
2382 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
2383 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
2384 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
2385 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
2386 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
2387 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
2388 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
2389 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
2390 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
2391 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
2392 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
2393 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
2394 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
2395 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
2396 +#endif // __IDT_ETH_V_H__
2397 +
2398 +
2399 +
2400 +
2401 +
2402 diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
2403 --- linux.old/include/asm-mips/rc32434/gpio.h   1970-01-01 01:00:00.000000000 +0100
2404 +++ linux.dev/include/asm-mips/rc32434/gpio.h   2006-12-14 04:09:50.000000000 +0100
2405 @@ -0,0 +1,181 @@
2406 +#ifndef __IDT_GPIO_H__
2407 +#define __IDT_GPIO_H__
2408 +
2409 +/*******************************************************************************
2410 + *
2411 + * Copyright 2002 Integrated Device Technology, Inc.
2412 + *             All rights reserved.
2413 + *
2414 + * GPIO register definition.
2415 + *
2416 + * File   : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
2417 + *
2418 + * Author : ryan.holmQVist@idt.com
2419 + * Date   : 20011005
2420 + * Update :
2421 + *         $Log: gpio.h,v $
2422 + *         Revision 1.2  2002/06/06 18:34:04  astichte
2423 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2424 + *
2425 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
2426 + *         jba File moved from vcode/include/idt/acacia
2427 + *
2428 + *
2429 + ******************************************************************************/
2430 +
2431 +enum
2432 +{
2433 +       GPIO0_PhysicalAddress   = 0x18050000,
2434 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
2435 +
2436 +       GPIO0_VirtualAddress    = 0xb8050000,
2437 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
2438 +} ;
2439 +
2440 +typedef struct
2441 +{
2442 +       u32   gpiofunc;   /* GPIO Function Register
2443 +                          * gpiofunc[x]==0 bit = gpio
2444 +                          * func[x]==1  bit = altfunc
2445 +                          */
2446 +       u32   gpiocfg;    /* GPIO Configuration Register
2447 +                          * gpiocfg[x]==0 bit = input
2448 +                          * gpiocfg[x]==1 bit = output
2449 +                          */
2450 +       u32   gpiod;      /* GPIO Data Register
2451 +                          * gpiod[x] read/write gpio pinX status
2452 +                          */
2453 +       u32   gpioilevel; /* GPIO Interrupt Status Register
2454 +                          * interrupt level (see gpioistat)
2455 +                          */
2456 +       u32   gpioistat;  /* Gpio Interrupt Status Register
2457 +                          * istat[x] = (gpiod[x] == level[x])
2458 +                          * cleared in ISR (STICKY bits)
2459 +                          */
2460 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
2461 +} volatile * GPIO_t ;
2462 +
2463 +typedef enum
2464 +{
2465 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
2466 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
2467 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
2468 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
2469 +       GPIO_pin0_b             = 0,
2470 +       GPIO_pin0_m             = 0x00000001,
2471 +       GPIO_pin1_b             = 1,
2472 +       GPIO_pin1_m             = 0x00000002,
2473 +       GPIO_pin2_b             = 2,
2474 +       GPIO_pin2_m             = 0x00000004,
2475 +       GPIO_pin3_b             = 3,
2476 +       GPIO_pin3_m             = 0x00000008,
2477 +       GPIO_pin4_b             = 4,
2478 +       GPIO_pin4_m             = 0x00000010,
2479 +       GPIO_pin5_b             = 5,
2480 +       GPIO_pin5_m             = 0x00000020,
2481 +       GPIO_pin6_b             = 6,
2482 +       GPIO_pin6_m             = 0x00000040,
2483 +       GPIO_pin7_b             = 7,
2484 +       GPIO_pin7_m             = 0x00000080,
2485 +       GPIO_pin8_b             = 8,
2486 +       GPIO_pin8_m             = 0x00000100,
2487 +       GPIO_pin9_b             = 9,
2488 +       GPIO_pin9_m             = 0x00000200,
2489 +       GPIO_pin10_b            = 10,
2490 +       GPIO_pin10_m            = 0x00000400,
2491 +       GPIO_pin11_b            = 11,
2492 +       GPIO_pin11_m            = 0x00000800,
2493 +       GPIO_pin12_b            = 12,
2494 +       GPIO_pin12_m            = 0x00001000,
2495 +       GPIO_pin13_b            = 13,
2496 +       GPIO_pin13_m            = 0x00002000,
2497 +       GPIO_pin14_b            = 14,
2498 +       GPIO_pin14_m            = 0x00004000,
2499 +       GPIO_pin15_b            = 15,
2500 +       GPIO_pin15_m            = 0x00008000,
2501 +       GPIO_pin16_b            = 16,
2502 +       GPIO_pin16_m            = 0x00010000,
2503 +       GPIO_pin17_b            = 17,
2504 +       GPIO_pin17_m            = 0x00020000,
2505 +       GPIO_pin18_b            = 18,
2506 +       GPIO_pin18_m            = 0x00040000,
2507 +       GPIO_pin19_b            = 19,
2508 +       GPIO_pin19_m            = 0x00080000,
2509 +       GPIO_pin20_b            = 20,
2510 +       GPIO_pin20_m            = 0x00100000,
2511 +       GPIO_pin21_b            = 21,
2512 +       GPIO_pin21_m            = 0x00200000,
2513 +       GPIO_pin22_b            = 22,
2514 +       GPIO_pin22_m            = 0x00400000,
2515 +       GPIO_pin23_b            = 23,
2516 +       GPIO_pin23_m            = 0x00800000,
2517 +       GPIO_pin24_b            = 24,
2518 +       GPIO_pin24_m            = 0x01000000,
2519 +       GPIO_pin25_b            = 25,
2520 +       GPIO_pin25_m            = 0x02000000,
2521 +       GPIO_pin26_b            = 26,
2522 +       GPIO_pin26_m            = 0x04000000,
2523 +       GPIO_pin27_b            = 27,
2524 +       GPIO_pin27_m            = 0x08000000,
2525 +       GPIO_pin28_b            = 28,
2526 +       GPIO_pin28_m            = 0x10000000,
2527 +       GPIO_pin29_b            = 29,
2528 +       GPIO_pin29_m            = 0x20000000,
2529 +       GPIO_pin30_b            = 30,
2530 +       GPIO_pin30_m            = 0x40000000,
2531 +       GPIO_pin31_b            = 31,
2532 +       GPIO_pin31_m            = 0x80000000,
2533 +
2534 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
2535 +
2536 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
2537 +       GPIO_u0sout_m           = GPIO_pin0_m,
2538 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
2539 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
2540 +       GPIO_u0sinp_m   = GPIO_pin1_m,
2541 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
2542 +       GPIO_u0rtsn_b   = GPIO_pin2_b,                  // UART 0 req. to send.
2543 +       GPIO_u0rtsn_m   = GPIO_pin2_m,
2544 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
2545 +       GPIO_u0ctsn_b   = GPIO_pin3_b,                  // UART 0 clear to send.
2546 +       GPIO_u0ctsn_m   = GPIO_pin3_m,
2547 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
2548 +       GPIO_maddr22_b          = GPIO_pin4_b,  // M&P bus bit 22.
2549 +       GPIO_maddr22_m          = GPIO_pin4_m,
2550 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
2551 +
2552 +       GPIO_maddr23_b          = GPIO_pin5_b,  // M&P bus bit 23.
2553 +       GPIO_maddr23_m          = GPIO_pin5_m,
2554 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
2555 +
2556 +       GPIO_maddr24_b          = GPIO_pin6_b,  // M&P bus bit 24.
2557 +       GPIO_maddr24_m          = GPIO_pin6_m,
2558 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
2559 +
2560 +       GPIO_maddr25_b          = GPIO_pin7_b,  // M&P bus bit 25.
2561 +       GPIO_maddr25_m          = GPIO_pin7_m,
2562 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
2563 +
2564 +       GPIO_cpu_b              = GPIO_pin8_b,  // M&P bus bit 25.
2565 +       GPIO_cpu_m              = GPIO_pin8_m,
2566 +               GPIO_cpu_cfg_v  = GPIO_output_v,
2567 +       GPIO_afspare6_b         = GPIO_pin9_b,  // reserved.
2568 +       GPIO_afspare6_m         = GPIO_pin9_m,
2569 +               GPIO_afspare6_cfg_v     = GPIO_input_v,
2570 +       GPIO_afspare4_b         = GPIO_pin10_b,         // reserved.
2571 +       GPIO_afspare4_m         = GPIO_pin10_m,
2572 +               GPIO_afspare4_cfg_v     = GPIO_input_v,
2573 +       GPIO_afspare3_b         = GPIO_pin11_b,         // reserved.
2574 +       GPIO_afspare3_m         = GPIO_pin11_m,
2575 +               GPIO_afspare3_cfg_v     = GPIO_input_v,
2576 +       GPIO_afspare2_b         = GPIO_pin12_b,         // reserved.
2577 +       GPIO_afspare2_m         = GPIO_pin12_m,
2578 +               GPIO_afspare2_cfg_v     = GPIO_input_v,
2579 +       GPIO_pcimuintn_b        = GPIO_pin13_b,         // PCI messaging int.
2580 +       GPIO_pcimuintn_m        = GPIO_pin13_m,
2581 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
2582 +
2583 +} GPIO_DEFS_t;
2584 +
2585 +#endif // __IDT_GPIO_H__
2586 +
2587 diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
2588 --- linux.old/include/asm-mips/rc32434/irq.h    1970-01-01 01:00:00.000000000 +0100
2589 +++ linux.dev/include/asm-mips/rc32434/irq.h    2006-12-14 04:09:50.000000000 +0100
2590 @@ -0,0 +1,8 @@
2591 +#ifndef __ASM_MACH_MIPS_IRQ_H
2592 +#define __ASM_MACH_MIPS_IRQ_H
2593 +
2594 +#include <linux/autoconf.h>
2595 +
2596 +#define NR_IRQS        256
2597 +
2598 +#endif /* __ASM_MACH_MIPS_IRQ_H */
2599 diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
2600 --- linux.old/include/asm-mips/rc32434/pci.h    1970-01-01 01:00:00.000000000 +0100
2601 +++ linux.dev/include/asm-mips/rc32434/pci.h    2006-12-14 04:09:50.000000000 +0100
2602 @@ -0,0 +1,692 @@
2603 +/**************************************************************************
2604 + *
2605 + *  BRIEF MODULE DESCRIPTION
2606 + *   PCI register definitio
2607 + *
2608 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2609 + *
2610 + *  This program is free software; you can redistribute  it and/or modify it
2611 + *  under  the terms of  the GNU General  Public License as published by the
2612 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2613 + *  option) any later version.
2614 + *
2615 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2616 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2617 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2618 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2619 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2620 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2621 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2622 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2623 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2624 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2625 + *
2626 + *  You should have received a copy of the  GNU General Public License along
2627 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2628 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2629 + *
2630 + *
2631 + **************************************************************************
2632 + * May 2004 rkt, neb.
2633 + *
2634 + * Initial Release
2635 + *
2636 + *
2637 + *
2638 + **************************************************************************
2639 + */
2640 +
2641 +#ifndef __IDT_PCI_H__
2642 +#define __IDT_PCI_H__
2643 +
2644 +enum
2645 +{
2646 +       PCI0_PhysicalAddress    = 0x18080000,
2647 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
2648 +
2649 +       PCI0_VirtualAddress     = 0xB8080000,
2650 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
2651 +} ;
2652 +
2653 +enum
2654 +{
2655 +       PCI_LbaCount    = 4,            // Local base addresses.
2656 +} ;
2657 +
2658 +typedef struct
2659 +{
2660 +       u32     a ;             // Address.
2661 +       u32     c ;             // Control.
2662 +       u32     m ;             // mapping.
2663 +} PCI_Map_s ;
2664 +
2665 +typedef struct
2666 +{
2667 +       u32             pcic ;
2668 +       u32             pcis ;
2669 +       u32             pcism ;
2670 +       u32             pcicfga ;
2671 +       u32             pcicfgd ;
2672 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
2673 +       u32             pcidac ;
2674 +       u32             pcidas ;
2675 +       u32             pcidasm ;
2676 +       u32             pcidad ;
2677 +       u32             pcidma8c ;
2678 +       u32             pcidma9c ;
2679 +       u32             pcitc ;
2680 +} volatile *PCI_t ;
2681 +
2682 +// PCI messaging unit.
2683 +enum
2684 +{
2685 +       PCIM_Count      = 2,
2686 +} ;
2687 +typedef struct
2688 +{
2689 +       u32             pciim [PCIM_Count] ;
2690 +       u32             pciom [PCIM_Count] ;
2691 +       u32             pciid ;
2692 +       u32             pciiic ;
2693 +       u32             pciiim ;
2694 +       u32             pciiod ;
2695 +       u32             pciioic ;
2696 +       u32             pciioim ;
2697 +} volatile *PCIM_t ;
2698 +
2699 +/*******************************************************************************
2700 + *
2701 + * PCI Control Register
2702 + *
2703 + ******************************************************************************/
2704 +enum
2705 +{
2706 +       PCIC_en_b       = 0,
2707 +       PCIC_en_m       = 0x00000001,
2708 +       PCIC_tnr_b      = 1,
2709 +       PCIC_tnr_m      = 0x00000002,
2710 +       PCIC_sce_b      = 2,
2711 +       PCIC_sce_m      = 0x00000004,
2712 +       PCIC_ien_b      = 3,
2713 +       PCIC_ien_m      = 0x00000008,
2714 +       PCIC_aaa_b      = 4,
2715 +       PCIC_aaa_m      = 0x00000010,
2716 +       PCIC_eap_b      = 5,
2717 +       PCIC_eap_m      = 0x00000020,
2718 +       PCIC_pcim_b     = 6,
2719 +       PCIC_pcim_m     = 0x000001c0,
2720 +               PCIC_pcim_disabled_v    = 0,
2721 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
2722 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
2723 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
2724 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
2725 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
2726 +               PCIC_pcim_reserved6_v   = 6,
2727 +               PCIC_pcim_reserved7_v   = 7,
2728 +       PCIC_igm_b      = 9,
2729 +       PCIC_igm_m      = 0x00000200,
2730 +} ;
2731 +
2732 +/*******************************************************************************
2733 + *
2734 + * PCI Status Register
2735 + *
2736 + ******************************************************************************/
2737 +enum {
2738 +       PCIS_eed_b      = 0,
2739 +       PCIS_eed_m      = 0x00000001,
2740 +       PCIS_wr_b       = 1,
2741 +       PCIS_wr_m       = 0x00000002,
2742 +       PCIS_nmi_b      = 2,
2743 +       PCIS_nmi_m      = 0x00000004,
2744 +       PCIS_ii_b       = 3,
2745 +       PCIS_ii_m       = 0x00000008,
2746 +       PCIS_cwe_b      = 4,
2747 +       PCIS_cwe_m      = 0x00000010,
2748 +       PCIS_cre_b      = 5,
2749 +       PCIS_cre_m      = 0x00000020,
2750 +       PCIS_mdpe_b     = 6,
2751 +       PCIS_mdpe_m     = 0x00000040,
2752 +       PCIS_sta_b      = 7,
2753 +       PCIS_sta_m      = 0x00000080,
2754 +       PCIS_rta_b      = 8,
2755 +       PCIS_rta_m      = 0x00000100,
2756 +       PCIS_rma_b      = 9,
2757 +       PCIS_rma_m      = 0x00000200,
2758 +       PCIS_sse_b      = 10,
2759 +       PCIS_sse_m      = 0x00000400,
2760 +       PCIS_ose_b      = 11,
2761 +       PCIS_ose_m      = 0x00000800,
2762 +       PCIS_pe_b       = 12,
2763 +       PCIS_pe_m       = 0x00001000,
2764 +       PCIS_tae_b      = 13,
2765 +       PCIS_tae_m      = 0x00002000,
2766 +       PCIS_rle_b      = 14,
2767 +       PCIS_rle_m      = 0x00004000,
2768 +       PCIS_bme_b      = 15,
2769 +       PCIS_bme_m      = 0x00008000,
2770 +       PCIS_prd_b      = 16,
2771 +       PCIS_prd_m      = 0x00010000,
2772 +       PCIS_rip_b      = 17,
2773 +       PCIS_rip_m      = 0x00020000,
2774 +} ;
2775 +
2776 +/*******************************************************************************
2777 + *
2778 + * PCI Status Mask Register
2779 + *
2780 + ******************************************************************************/
2781 +enum {
2782 +       PCISM_eed_b             = 0,
2783 +       PCISM_eed_m             = 0x00000001,
2784 +       PCISM_wr_b              = 1,
2785 +       PCISM_wr_m              = 0x00000002,
2786 +       PCISM_nmi_b             = 2,
2787 +       PCISM_nmi_m             = 0x00000004,
2788 +       PCISM_ii_b              = 3,
2789 +       PCISM_ii_m              = 0x00000008,
2790 +       PCISM_cwe_b             = 4,
2791 +       PCISM_cwe_m             = 0x00000010,
2792 +       PCISM_cre_b             = 5,
2793 +       PCISM_cre_m             = 0x00000020,
2794 +       PCISM_mdpe_b            = 6,
2795 +       PCISM_mdpe_m            = 0x00000040,
2796 +       PCISM_sta_b             = 7,
2797 +       PCISM_sta_m             = 0x00000080,
2798 +       PCISM_rta_b             = 8,
2799 +       PCISM_rta_m             = 0x00000100,
2800 +       PCISM_rma_b             = 9,
2801 +       PCISM_rma_m             = 0x00000200,
2802 +       PCISM_sse_b             = 10,
2803 +       PCISM_sse_m             = 0x00000400,
2804 +       PCISM_ose_b             = 11,
2805 +       PCISM_ose_m             = 0x00000800,
2806 +       PCISM_pe_b              = 12,
2807 +       PCISM_pe_m              = 0x00001000,
2808 +       PCISM_tae_b             = 13,
2809 +       PCISM_tae_m             = 0x00002000,
2810 +       PCISM_rle_b             = 14,
2811 +       PCISM_rle_m             = 0x00004000,
2812 +       PCISM_bme_b             = 15,
2813 +       PCISM_bme_m             = 0x00008000,
2814 +       PCISM_prd_b             = 16,
2815 +       PCISM_prd_m             = 0x00010000,
2816 +       PCISM_rip_b             = 17,
2817 +       PCISM_rip_m             = 0x00020000,
2818 +} ;
2819 +
2820 +/*******************************************************************************
2821 + *
2822 + * PCI Configuration Address Register
2823 + *
2824 + ******************************************************************************/
2825 +enum {
2826 +       PCICFGA_reg_b           = 2,
2827 +       PCICFGA_reg_m           = 0x000000fc,
2828 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
2829 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
2830 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
2831 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
2832 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
2833 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
2834 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
2835 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
2836 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
2837 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
2838 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
2839 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
2840 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
2841 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
2842 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
2843 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
2844 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
2845 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
2846 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
2847 +       PCICFGA_func_b          = 8,
2848 +       PCICFGA_func_m          = 0x00000700,
2849 +       PCICFGA_dev_b           = 11,
2850 +       PCICFGA_dev_m           = 0x0000f800,
2851 +               PCICFGA_dev_internal_v  = 0,
2852 +       PCICFGA_bus_b           = 16,
2853 +       PCICFGA_bus_m           = 0x00ff0000,
2854 +               PCICFGA_bus_type0_v     = 0,    //local bus
2855 +       PCICFGA_en_b            = 31,           // read only
2856 +       PCICFGA_en_m            = 0x80000000,
2857 +} ;
2858 +
2859 +enum {
2860 +       PCFGID_vendor_b         = 0,
2861 +       PCFGID_vendor_m         = 0x0000ffff,
2862 +               PCFGID_vendor_IDT_v             = 0x111d,
2863 +       PCFGID_device_b         = 16,
2864 +       PCFGID_device_m         = 0xffff0000,
2865 +               PCFGID_device_Korinade_v        = 0x0214,
2866 +
2867 +       PCFG04_command_ioena_b          = 1,
2868 +       PCFG04_command_ioena_m          = 0x00000001,
2869 +       PCFG04_command_memena_b         = 2,
2870 +       PCFG04_command_memena_m         = 0x00000002,
2871 +       PCFG04_command_bmena_b          = 3,
2872 +       PCFG04_command_bmena_m          = 0x00000004,
2873 +       PCFG04_command_mwinv_b          = 5,
2874 +       PCFG04_command_mwinv_m          = 0x00000010,
2875 +       PCFG04_command_parena_b         = 7,
2876 +       PCFG04_command_parena_m         = 0x00000040,
2877 +       PCFG04_command_serrena_b        = 9,
2878 +       PCFG04_command_serrena_m        = 0x00000100,
2879 +       PCFG04_command_fastbbena_b      = 10,
2880 +       PCFG04_command_fastbbena_m      = 0x00000200,
2881 +       PCFG04_status_b                 = 16,
2882 +       PCFG04_status_m                 = 0xffff0000,
2883 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
2884 +       PCFG04_status_66MHz_m           = 0x00200000,
2885 +       PCFG04_status_fbb_b             = 23,
2886 +       PCFG04_status_fbb_m             = 0x00800000,
2887 +       PCFG04_status_mdpe_b            = 24,
2888 +       PCFG04_status_mdpe_m            = 0x01000000,
2889 +       PCFG04_status_dst_b             = 25,
2890 +       PCFG04_status_dst_m             = 0x06000000,
2891 +       PCFG04_status_sta_b             = 27,
2892 +       PCFG04_status_sta_m             = 0x08000000,
2893 +       PCFG04_status_rta_b             = 28,
2894 +       PCFG04_status_rta_m             = 0x10000000,
2895 +       PCFG04_status_rma_b             = 29,
2896 +       PCFG04_status_rma_m             = 0x20000000,
2897 +       PCFG04_status_sse_b             = 30,
2898 +       PCFG04_status_sse_m             = 0x40000000,
2899 +       PCFG04_status_pe_b              = 31,
2900 +       PCFG04_status_pe_m              = 0x40000000,
2901 +
2902 +       PCFG08_revId_b                  = 0,
2903 +       PCFG08_revId_m                  = 0x000000ff,
2904 +       PCFG08_classCode_b              = 0,
2905 +       PCFG08_classCode_m              = 0xffffff00,
2906 +               PCFG08_classCode_bridge_v       = 06,
2907 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
2908 +       PCFG0C_cacheline_b              = 0,
2909 +       PCFG0C_cacheline_m              = 0x000000ff,
2910 +       PCFG0C_masterLatency_b          = 8,
2911 +       PCFG0C_masterLatency_m          = 0x0000ff00,
2912 +       PCFG0C_headerType_b             = 16,
2913 +       PCFG0C_headerType_m             = 0x00ff0000,
2914 +       PCFG0C_bist_b                   = 24,
2915 +       PCFG0C_bist_m                   = 0xff000000,
2916 +
2917 +       PCIPBA_msi_b                    = 0,
2918 +       PCIPBA_msi_m                    = 0x00000001,
2919 +       PCIPBA_p_b                      = 3,
2920 +       PCIPBA_p_m                      = 0x00000004,
2921 +       PCIPBA_baddr_b                  = 8,
2922 +       PCIPBA_baddr_m                  = 0xffffff00,
2923 +
2924 +       PCFGSS_vendorId_b               = 0,
2925 +       PCFGSS_vendorId_m               = 0x0000ffff,
2926 +       PCFGSS_id_b                     = 16,
2927 +       PCFGSS_id_m                     = 0xffff0000,
2928 +
2929 +       PCFG3C_interruptLine_b          = 0,
2930 +       PCFG3C_interruptLine_m          = 0x000000ff,
2931 +       PCFG3C_interruptPin_b           = 8,
2932 +       PCFG3C_interruptPin_m           = 0x0000ff00,
2933 +       PCFG3C_minGrant_b               = 16,
2934 +       PCFG3C_minGrant_m               = 0x00ff0000,
2935 +       PCFG3C_maxLat_b                 = 24,
2936 +       PCFG3C_maxLat_m                 = 0xff000000,
2937 +
2938 +       PCIPBAC_msi_b                   = 0,
2939 +       PCIPBAC_msi_m                   = 0x00000001,
2940 +       PCIPBAC_p_b                     = 1,
2941 +       PCIPBAC_p_m                     = 0x00000002,
2942 +       PCIPBAC_size_b                  = 2,
2943 +       PCIPBAC_size_m                  = 0x0000007c,
2944 +       PCIPBAC_sb_b                    = 7,
2945 +       PCIPBAC_sb_m                    = 0x00000080,
2946 +       PCIPBAC_pp_b                    = 8,
2947 +       PCIPBAC_pp_m                    = 0x00000100,
2948 +       PCIPBAC_mr_b                    = 9,
2949 +       PCIPBAC_mr_m                    = 0x00000600,
2950 +               PCIPBAC_mr_read_v       =0,     //no prefetching
2951 +               PCIPBAC_mr_readLine_v   =1,
2952 +               PCIPBAC_mr_readMult_v   =2,
2953 +       PCIPBAC_mrl_b                   = 11,
2954 +       PCIPBAC_mrl_m                   = 0x00000800,
2955 +       PCIPBAC_mrm_b                   = 12,
2956 +       PCIPBAC_mrm_m                   = 0x00001000,
2957 +       PCIPBAC_trp_b                   = 13,
2958 +       PCIPBAC_trp_m                   = 0x00002000,
2959 +
2960 +       PCFG40_trdyTimeout_b            = 0,
2961 +       PCFG40_trdyTimeout_m            = 0x000000ff,
2962 +       PCFG40_retryLim_b               = 8,
2963 +       PCFG40_retryLim_m               = 0x0000ff00,
2964 +};
2965 +
2966 +/*******************************************************************************
2967 + *
2968 + * PCI Local Base Address [0|1|2|3] Register
2969 + *
2970 + ******************************************************************************/
2971 +enum {
2972 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
2973 +       PCILBA_baddr_m          = 0xffffff00,
2974 +} ;
2975 +/*******************************************************************************
2976 + *
2977 + * PCI Local Base Address Control Register
2978 + *
2979 + ******************************************************************************/
2980 +enum {
2981 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
2982 +       PCILBAC_msi_m           = 0x00000001,
2983 +               PCILBAC_msi_mem_v       = 0,
2984 +               PCILBAC_msi_io_v        = 1,
2985 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
2986 +       PCILBAC_size_m          = 0x0000007c,
2987 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
2988 +       PCILBAC_sb_m            = 0x00000080,
2989 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
2990 +       PCILBAC_rt_m            = 0x00000100,
2991 +               PCILBAC_rt_noprefetch_v = 0, // mem read
2992 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
2993 +} ;
2994 +
2995 +/*******************************************************************************
2996 + *
2997 + * PCI Local Base Address [0|1|2|3] Mapping Register
2998 + *
2999 + ******************************************************************************/
3000 +enum {
3001 +       PCILBAM_maddr_b         = 8,
3002 +       PCILBAM_maddr_m         = 0xffffff00,
3003 +} ;
3004 +
3005 +/*******************************************************************************
3006 + *
3007 + * PCI Decoupled Access Control Register
3008 + *
3009 + ******************************************************************************/
3010 +enum {
3011 +       PCIDAC_den_b            = 0,
3012 +       PCIDAC_den_m            = 0x00000001,
3013 +} ;
3014 +
3015 +/*******************************************************************************
3016 + *
3017 + * PCI Decoupled Access Status Register
3018 + *
3019 + ******************************************************************************/
3020 +enum {
3021 +       PCIDAS_d_b      = 0,
3022 +       PCIDAS_d_m      = 0x00000001,
3023 +       PCIDAS_b_b      = 1,
3024 +       PCIDAS_b_m      = 0x00000002,
3025 +       PCIDAS_e_b      = 2,
3026 +       PCIDAS_e_m      = 0x00000004,
3027 +       PCIDAS_ofe_b    = 3,
3028 +       PCIDAS_ofe_m    = 0x00000008,
3029 +       PCIDAS_off_b    = 4,
3030 +       PCIDAS_off_m    = 0x00000010,
3031 +       PCIDAS_ife_b    = 5,
3032 +       PCIDAS_ife_m    = 0x00000020,
3033 +       PCIDAS_iff_b    = 6,
3034 +       PCIDAS_iff_m    = 0x00000040,
3035 +} ;
3036 +
3037 +/*******************************************************************************
3038 + *
3039 + * PCI DMA Channel 8 Configuration Register
3040 + *
3041 + ******************************************************************************/
3042 +enum
3043 +{
3044 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
3045 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
3046 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
3047 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
3048 +} ;
3049 +
3050 +/*******************************************************************************
3051 + *
3052 + * PCI DMA Channel 9 Configuration Register
3053 + *
3054 + ******************************************************************************/
3055 +enum
3056 +{
3057 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
3058 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
3059 +} ;
3060 +
3061 +/*******************************************************************************
3062 + *
3063 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
3064 + *
3065 + ******************************************************************************/
3066 +enum {
3067 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
3068 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
3069 +               // These are for reads (DMA channel 8)
3070 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
3071 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
3072 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
3073 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
3074 +               // These are for writes (DMA channel 9)
3075 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
3076 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
3077 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
3078 +
3079 +       // Swap byte field applies to both DMA channel 8 and 9
3080 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
3081 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
3082 +} ;
3083 +
3084 +
3085 +/*******************************************************************************
3086 + *
3087 + * PCI Target Control Register
3088 + *
3089 + ******************************************************************************/
3090 +enum
3091 +{
3092 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
3093 +       PCITC_rtimer_m          = 0x000000ff,
3094 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
3095 +       PCITC_dtimer_m          = 0x0000ff00,
3096 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
3097 +       PCITC_rdr_m             = 0x00040000,
3098 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
3099 +       PCITC_ddt_m             = 0x00080000,
3100 +} ;
3101 +/*******************************************************************************
3102 + *
3103 + * PCI messaging unit [applies to both inbound and outbound registers ]
3104 + *
3105 + ******************************************************************************/
3106 +enum
3107 +{
3108 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3109 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
3110 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3111 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
3112 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3113 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
3114 +};
3115 +
3116 +
3117 +
3118 +
3119 +
3120 +
3121 +#define PCI_MSG_VirtualAddress      0xB8088010
3122 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
3123 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
3124 +
3125 +#define PCIM_SHFT              0x6
3126 +#define PCIM_BIT_LEN           0x7
3127 +#define PCIM_H_EA              0x3
3128 +#define PCIM_H_IA_FIX          0x4
3129 +#define PCIM_H_IA_RR           0x5
3130 +
3131 +#define PCI_ADDR_START         0x50000000
3132 +
3133 +#define CPUTOPCI_MEM_WIN       0x02000000
3134 +#define CPUTOPCI_IO_WIN                0x00100000
3135 +#define PCILBA_SIZE_SHFT       2
3136 +#define PCILBA_SIZE_MASK       0x1F
3137 +#define SIZE_256MB             0x1C
3138 +#define SIZE_128MB             0x1B
3139 +#define SIZE_64MB               0x1A
3140 +#define SIZE_32MB              0x19
3141 +#define SIZE_16MB               0x18
3142 +#define SIZE_4MB               0x16
3143 +#define SIZE_2MB               0x15
3144 +#define SIZE_1MB               0x14
3145 +#define KORINA_CONFIG0_ADDR    0x80000000
3146 +#define KORINA_CONFIG1_ADDR    0x80000004
3147 +#define KORINA_CONFIG2_ADDR    0x80000008
3148 +#define KORINA_CONFIG3_ADDR    0x8000000C
3149 +#define KORINA_CONFIG4_ADDR    0x80000010
3150 +#define KORINA_CONFIG5_ADDR    0x80000014
3151 +#define KORINA_CONFIG6_ADDR    0x80000018
3152 +#define KORINA_CONFIG7_ADDR    0x8000001C
3153 +#define KORINA_CONFIG8_ADDR    0x80000020
3154 +#define KORINA_CONFIG9_ADDR    0x80000024
3155 +#define KORINA_CONFIG10_ADDR   0x80000028
3156 +#define KORINA_CONFIG11_ADDR   0x8000002C
3157 +#define KORINA_CONFIG12_ADDR   0x80000030
3158 +#define KORINA_CONFIG13_ADDR   0x80000034
3159 +#define KORINA_CONFIG14_ADDR   0x80000038
3160 +#define KORINA_CONFIG15_ADDR   0x8000003C
3161 +#define KORINA_CONFIG16_ADDR   0x80000040
3162 +#define KORINA_CONFIG17_ADDR   0x80000044
3163 +#define KORINA_CONFIG18_ADDR   0x80000048
3164 +#define KORINA_CONFIG19_ADDR   0x8000004C
3165 +#define KORINA_CONFIG20_ADDR   0x80000050
3166 +#define KORINA_CONFIG21_ADDR   0x80000054
3167 +#define KORINA_CONFIG22_ADDR   0x80000058
3168 +#define KORINA_CONFIG23_ADDR   0x8000005C
3169 +#define KORINA_CONFIG24_ADDR   0x80000060
3170 +#define KORINA_CONFIG25_ADDR   0x80000064
3171 +#define KORINA_CMD             (PCFG04_command_ioena_m | \
3172 +                                PCFG04_command_memena_m | \
3173 +                                PCFG04_command_bmena_m | \
3174 +                                PCFG04_command_mwinv_m | \
3175 +                                PCFG04_command_parena_m | \
3176 +                                PCFG04_command_serrena_m )
3177 +
3178 +#define KORINA_STAT            (PCFG04_status_mdpe_m | \
3179 +                                PCFG04_status_sta_m  | \
3180 +                                PCFG04_status_rta_m  | \
3181 +                                PCFG04_status_rma_m  | \
3182 +                                PCFG04_status_sse_m  | \
3183 +                                PCFG04_status_pe_m)
3184 +
3185 +#define KORINA_CNFG1           ((KORINA_STAT<<16)|KORINA_CMD)
3186 +
3187 +#define KORINA_REVID           0
3188 +#define KORINA_CLASS_CODE      0
3189 +#define KORINA_CNFG2           ((KORINA_CLASS_CODE<<8) | \
3190 +                                 KORINA_REVID)
3191 +
3192 +#define KORINA_CACHE_LINE_SIZE 4
3193 +#define KORINA_MASTER_LAT      0x3c
3194 +#define KORINA_HEADER_TYPE     0
3195 +#define KORINA_BIST            0
3196 +
3197 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
3198 +                     (KORINA_HEADER_TYPE<<16) | \
3199 +                     (KORINA_MASTER_LAT<<8) | \
3200 +                     KORINA_CACHE_LINE_SIZE )
3201 +
3202 +#define KORINA_BAR0    0x00000008 /* 128 MB Memory */
3203 +#define KORINA_BAR1    0x18800001 /* 1 MB IO */
3204 +#define KORINA_BAR2    0x18000001 /* 2 MB IO window for Korina
3205 +                                       internal Registers */
3206 +#define KORINA_BAR3    0x48000008 /* Spare 128 MB Memory */
3207 +
3208 +#define KORINA_CNFG4   KORINA_BAR0
3209 +#define KORINA_CNFG5    KORINA_BAR1
3210 +#define KORINA_CNFG6   KORINA_BAR2
3211 +#define KORINA_CNFG7   KORINA_BAR3
3212 +
3213 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
3214 +#define KORINA_SUBSYSTEM_ID    0x0214
3215 +#define KORINA_CNFG8           0
3216 +#define KORINA_CNFG9           0
3217 +#define KORINA_CNFG10          0
3218 +#define KORINA_CNFG11  ((KORINA_SUBSYS_VENDOR_ID<<16) | \
3219 +                         KORINA_SUBSYSTEM_ID)
3220 +#define KORINA_INT_LINE                1
3221 +#define KORINA_INT_PIN         1
3222 +#define KORINA_MIN_GNT         8
3223 +#define KORINA_MAX_LAT         0x38
3224 +#define KORINA_CNFG12          0
3225 +#define KORINA_CNFG13          0
3226 +#define KORINA_CNFG14          0
3227 +#define KORINA_CNFG15  ((KORINA_MAX_LAT<<24) | \
3228 +                        (KORINA_MIN_GNT<<16) | \
3229 +                        (KORINA_INT_PIN<<8)  | \
3230 +                         KORINA_INT_LINE)
3231 +#define        KORINA_RETRY_LIMIT      0x80
3232 +#define KORINA_TRDY_LIMIT      0x80
3233 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
3234 +                       KORINA_TRDY_LIMIT)
3235 +#define PCI_PBAxC_R            0x0
3236 +#define PCI_PBAxC_RL           0x1
3237 +#define PCI_PBAxC_RM           0x2
3238 +#define SIZE_SHFT              2
3239 +
3240 +#if defined(__MIPSEB__)
3241 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
3242 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
3243 +                         PCIPBAC_pp_m | \
3244 +                         (SIZE_128MB<<SIZE_SHFT) | \
3245 +                          PCIPBAC_p_m)
3246 +#else
3247 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | \
3248 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
3249 +                         PCIPBAC_pp_m | \
3250 +                         (SIZE_128MB<<SIZE_SHFT) | \
3251 +                          PCIPBAC_p_m)
3252 +#endif
3253 +#define KORINA_CNFG17  KORINA_PBA0C
3254 +#define KORINA_PBA0M   0x0
3255 +#define KORINA_CNFG18  KORINA_PBA0M
3256 +
3257 +#if defined(__MIPSEB__)
3258 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
3259 +                         PCIPBAC_msi_m)
3260 +#else
3261 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | \
3262 +                         PCIPBAC_msi_m)
3263 +#endif
3264 +#define KORINA_CNFG19  KORINA_PBA1C
3265 +#define KORINA_PBA1M   0x0
3266 +#define KORINA_CNFG20  KORINA_PBA1M
3267 +
3268 +#if defined(__MIPSEB__)
3269 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
3270 +                         PCIPBAC_msi_m)
3271 +#else
3272 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | \
3273 +                         PCIPBAC_msi_m)
3274 +#endif
3275 +#define KORINA_CNFG21  KORINA_PBA2C
3276 +#define KORINA_PBA2M   0x18000000
3277 +#define KORINA_CNFG22  KORINA_PBA2M
3278 +#define KORINA_PBA3C   0
3279 +#define KORINA_CNFG23  KORINA_PBA3C
3280 +#define KORINA_PBA3M   0
3281 +#define KORINA_CNFG24  KORINA_PBA3M
3282 +
3283 +
3284 +
3285 +#define        PCITC_DTIMER_VAL        8
3286 +#define PCITC_RTIMER_VAL       0x10
3287 +
3288 +
3289 +
3290 +
3291 +#endif // __IDT_PCI_H__
3292 +
3293 +
3294 +
3295 diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
3296 --- linux.old/include/asm-mips/rc32434/rb.h     1970-01-01 01:00:00.000000000 +0100
3297 +++ linux.dev/include/asm-mips/rc32434/rb.h     2006-12-14 04:09:50.000000000 +0100
3298 @@ -0,0 +1,84 @@
3299 +/*
3300 + *  Copyright (C) 2004 IDT Inc.
3301 + *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
3302 + *
3303 + *  This program is free software; you can redistribute it and/or modify
3304 + *  it under the terms of the GNU General Public License as published by
3305 + *  the Free Software Foundation; either version 2 of the License, or
3306 + *  (at your option) any later version.
3307 + *
3308 + *  This program is distributed in the hope that it will be useful,
3309 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
3310 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3311 + *  GNU General Public License for more details.
3312 + *
3313 + */
3314 +#ifndef __MIPS_RB_H__
3315 +#define __MIPS_RB_H__
3316 +#include <linux/genhd.h>
3317 +
3318 +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
3319 +#define DEV0BASE 0x010000
3320 +#define DEV0MASK 0x010004
3321 +#define DEV0C 0x010008
3322 +#define DEV0TC 0x01000C
3323 +#define DEV1BASE 0x010010
3324 +#define DEV1MASK 0x010014
3325 +#define DEV1C 0x010018
3326 +#define DEV1TC 0x01001C
3327 +#define DEV2BASE 0x010020
3328 +#define DEV2MASK 0x010024
3329 +#define DEV2C 0x010028
3330 +#define DEV2TC 0x01002C
3331 +#define DEV3BASE 0x010030
3332 +#define DEV3MASK 0x010034
3333 +#define DEV3C 0x010038
3334 +#define DEV3TC 0x01003C
3335 +#define BTCS 0x010040
3336 +#define BTCOMPARE 0x010044
3337 +#define GPIOFUNC 0x050000
3338 +#define GPIOCFG 0x050004
3339 +#define GPIOD 0x050008
3340 +#define GPIOILEVEL 0x05000C
3341 +#define GPIOISTAT 0x050010
3342 +#define GPIONMIEN 0x050014
3343 +#define IMASK6 0x038038
3344 +
3345 +#define LO_WPX (1 << 0)
3346 +#define LO_ALE (1 << 1)
3347 +#define LO_CLE (1 << 2)
3348 +#define LO_CEX (1 << 3)
3349 +#define LO_FOFF (1 << 5)
3350 +#define LO_SPICS (1 << 6)
3351 +#define LO_ULED (1 << 7)
3352 +
3353 +typedef enum {
3354 +       FUNC = 0x00,
3355 +       CFG = 0x04,
3356 +       DATA = 0x08,
3357 +       ILEVEL = 0x0c,
3358 +       ISTAT = 0x10,
3359 +       NMIEN = 0x14
3360 +} gpio_func;
3361 +
3362 +extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
3363 +extern unsigned get434Reg(unsigned regOffs);
3364 +extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
3365 +extern void gpio_set(gpio_func func, u32 mask, u32 value);
3366 +extern u32 gpio_get(gpio_func func);
3367 +
3368 +#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
3369 +
3370 +struct korina_device {
3371 +       char *name;
3372 +       unsigned char mac[6];
3373 +       struct net_device *dev;
3374 +};
3375 +
3376 +struct cf_device {
3377 +       int gpio_pin;
3378 +       void *dev;
3379 +       struct gendisk *gd;
3380 +};
3381 +
3382 +#endif
3383 diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h
3384 --- linux.old/include/asm-mips/rc32434/rc32434.h        1970-01-01 01:00:00.000000000 +0100
3385 +++ linux.dev/include/asm-mips/rc32434/rc32434.h        2006-12-14 04:09:50.000000000 +0100
3386 @@ -0,0 +1,122 @@
3387 +/*
3388 + ***************************************************************************
3389 + * Definitions for IDT RC323434 CPU.
3390 + *
3391 + ****************************************************************************
3392 + * Kiran Rao
3393 + *
3394 + * Original form
3395 + ****************************************************************************
3396 + * P. Sadik   Oct 08, 2003
3397 + *
3398 + * Started revision history
3399 + * Made IDT_BUS_FREQ a kernel configuration parameter
3400 + ****************************************************************************
3401 + * P. Sadik   Oct 10, 2003
3402 + *
3403 + * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
3404 + * idt_cpu_freq is used everywhere
3405 + ****************************************************************************
3406 + * P. Sadik   Oct 20, 2003
3407 + *
3408 + * Removed RC32434_BASE_BAUD
3409 + ****************************************************************************
3410 +*/
3411 +#ifndef _RC32434_H_
3412 +#define _RC32434_H_
3413 +
3414 +#include <linux/autoconf.h>
3415 +#include <linux/delay.h>
3416 +#include <asm/io.h>
3417 +
3418 +#define RC32434_REG_BASE   0x18000000
3419 +
3420 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
3421 +#define gpio     ((volatile GPIO_t) GPIO0_VirtualAddress)
3422 +
3423 +
3424 +#define IDT_CLOCK_MULT 2
3425 +#define MIPS_CPU_TIMER_IRQ 7
3426 +/* Interrupt Controller */
3427 +#define IC_GROUP0_PEND     (RC32434_REG_BASE + 0x38000)
3428 +#define IC_GROUP0_MASK     (RC32434_REG_BASE + 0x38008)
3429 +#define IC_GROUP_OFFSET    0x0C
3430 +
3431 +#define NUM_INTR_GROUPS    5
3432 +/* 16550 UARTs */
3433 +
3434 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
3435 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
3436 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
3437 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
3438 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
3439 +
3440 +
3441 +#ifdef __MIPSEB__
3442 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
3443 +#else
3444 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
3445 +#endif
3446 +
3447 +#define RC32434_UART0_IRQ  GROUP3_IRQ_BASE + 0
3448 +// #define EB434_UART1_IRQ    GROUP4_IRQ_BASE + 11
3449 +
3450 +#define local_readl(addr) __raw_readl(addr)
3451 +#define local_writel(l,addr) __raw_writel(l,addr)
3452 +
3453 +/* cpu pipeline flush */
3454 +static inline void rc32434_sync(void)
3455 +{
3456 +        __asm__ volatile ("sync");
3457 +}
3458 +
3459 +static inline void rc32434_sync_udelay(int us)
3460 +{
3461 +        __asm__ volatile ("sync");
3462 +        udelay(us);
3463 +}
3464 +
3465 +static inline void rc32434_sync_delay(int ms)
3466 +{
3467 +        __asm__ volatile ("sync");
3468 +        mdelay(ms);
3469 +}
3470 +
3471 +/*
3472 + * C access to CLZ and CLO instructions
3473 + * (count leading zeroes/ones).
3474 + */
3475 +static inline int rc32434_clz(unsigned long val)
3476 +{
3477 +       int ret;
3478 +        __asm__ volatile (
3479 +               ".set\tnoreorder\n\t"
3480 +               ".set\tnoat\n\t"
3481 +               ".set\tmips32\n\t"
3482 +               "clz\t%0,%1\n\t"
3483 +                ".set\tmips0\n\t"
3484 +                ".set\tat\n\t"
3485 +                ".set\treorder"
3486 +                : "=r" (ret)
3487 +               : "r" (val));
3488 +
3489 +       return ret;
3490 +}
3491 +static inline int rc32434_clo(unsigned long val)
3492 +{
3493 +       int ret;
3494 +        __asm__ volatile (
3495 +               ".set\tnoreorder\n\t"
3496 +               ".set\tnoat\n\t"
3497 +               ".set\tmips32\n\t"
3498 +               "clo\t%0,%1\n\t"
3499 +                ".set\tmips0\n\t"
3500 +                ".set\tat\n\t"
3501 +                ".set\treorder"
3502 +                : "=r" (ret)
3503 +               : "r" (val));
3504 +
3505 +       return ret;
3506 +}
3507 +
3508 +#endif /* _RC32434_H_ */
3509