target/linux/ramips/patches-3.10/0215-SPI-ralink-add-mt7621-support.patch

   1 From 1a961f146e65e2716dbe9065baa4c0931fcb6b3e Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 16 Mar 2014 05:34:11 +0000
   4 Subject: [PATCH 215/215] SPI: ralink: add mt7621 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/spi/spi-rt2880.c |  218 +++++++++++++++++++++++++++++++++++++++++++---
   9  1 file changed, 205 insertions(+), 13 deletions(-)
  10
  11 --- a/drivers/spi/spi-rt2880.c
  12 +++ b/drivers/spi/spi-rt2880.c
  13 @@ -21,8 +21,13 @@
  14  #include <linux/io.h>
  15  #include <linux/reset.h>
  16  #include <linux/spi/spi.h>
  17 +#include <linux/of_device.h>
  18  #include <linux/platform_device.h>
  19
  20 +#include <ralink_regs.h>
  21 +
  22 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
  23 +
  24  #define DRIVER_NAME                    "spi-rt2880"
  25  /* only one slave is supported*/
  26  #define RALINK_NUM_CHIPSELECTS         1
  27 @@ -63,6 +68,25 @@
  28  /* SPIFIFOSTAT register bit field */
  29  #define SPIFIFOSTAT_TXFULL             BIT(17)
  30
  31 +#define MT7621_SPI_TRANS       0x00
  32 +#define SPITRANS_BUSY          BIT(16)
  33 +#define MT7621_SPI_OPCODE      0x04
  34 +#define MT7621_SPI_DATA0       0x08
  35 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
  36 +#define SPI_CTL_START          BIT(8)
  37 +#define MT7621_SPI_POLAR       0x38
  38 +#define MT7621_SPI_MASTER      0x28
  39 +#define MT7621_SPI_SPACE       0x3c
  40 +
  41 +struct rt2880_spi;
  42 +
  43 +struct rt2880_spi_ops {
  44 +       void (*init_hw)(struct rt2880_spi *rs);
  45 +       void (*set_cs)(struct rt2880_spi *rs, int enable);
  46 +       int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
  47 +       unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
  48 +};
  49 +
  50  struct rt2880_spi {
  51         struct spi_master       *master;
  52         void __iomem            *base;
  53 @@ -70,6 +94,8 @@ struct rt2880_spi {
  54         unsigned int            speed;
  55         struct clk              *clk;
  56         spinlock_t              lock;
  57 +
  58 +       struct rt2880_spi_ops   *ops;
  59  };
  60
  61  static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
  62 @@ -149,6 +175,17 @@ static int rt2880_spi_baudrate_set(struc
  63         return 0;
  64  }
  65
  66 +static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
  67 +{
  68 +/*     u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
  69 +
  70 +       // set default clock to hclk/5
  71 +       master &= ~(0xfff << 16);
  72 +       master |= 0x3 << 16;
  73 +*/
  74 +       return 0;
  75 +}
  76 +
  77  /*
  78   * called only when no transfer is active on the bus
  79   */
  80 @@ -164,7 +201,7 @@ rt2880_spi_setup_transfer(struct spi_dev
  81
  82         if (rs->speed != speed) {
  83                 dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
  84 -               rc = rt2880_spi_baudrate_set(spi, speed);
  85 +               rc = rs->ops->baudrate_set(spi, speed);
  86                 if (rc)
  87                         return rc;
  88         }
  89 @@ -180,6 +217,17 @@ static void rt2880_spi_set_cs(struct rt2
  90                 rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
  91  }
  92
  93 +static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
  94 +{
  95 +       u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
  96 +
  97 +       if (enable)
  98 +               polar |= 1;
  99 +       else
 100 +               polar &= ~1;
 101 +       rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
 102 +}
 103 +
 104  static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
 105  {
 106         int i;
 107 @@ -198,8 +246,26 @@ static inline int rt2880_spi_wait_till_r
 108         return -ETIMEDOUT;
 109  }
 110
 111 +static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
 112 +{
 113 +       int i;
 114 +
 115 +       for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 116 +               u32 status;
 117 +
 118 +               status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
 119 +               if ((status & SPITRANS_BUSY) == 0) {
 120 +                       return 0;
 121 +               }
 122 +               cpu_relax();
 123 +               udelay(1);
 124 +       }
 125 +
 126 +       return -ETIMEDOUT;
 127 +}
 128 +
 129  static unsigned int
 130 -rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 131 +rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
 132  {
 133         struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 134         unsigned count = 0;
 135 @@ -239,6 +305,100 @@ out:
 136         return count;
 137  }
 138
 139 +static unsigned int
 140 +mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
 141 +{
 142 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 143 +       struct spi_transfer *next = NULL;
 144 +       const u8 *tx = xfer->tx_buf;
 145 +       u8 *rx = NULL;
 146 +       u32 trans;
 147 +       int len = xfer->len;
 148 +
 149 +       if (!tx)
 150 +               return 0;
 151 +
 152 +       if (!list_is_last(&xfer->transfer_list, list)) {
 153 +               next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
 154 +               rx = next->rx_buf;
 155 +       }
 156 +
 157 +       trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
 158 +       trans &= ~SPI_CTL_TX_RX_CNT_MASK;
 159 +
 160 +       if (tx) {
 161 +               u32 data0 = 0, opcode = 0;
 162 +
 163 +               switch (xfer->len) {
 164 +               case 8:
 165 +                       data0 |= tx[7] << 24;
 166 +               case 7:
 167 +                       data0 |= tx[6] << 16;
 168 +               case 6:
 169 +                       data0 |= tx[5] << 8;
 170 +               case 5:
 171 +                       data0 |= tx[4];
 172 +               case 4:
 173 +                       opcode |= tx[3] << 8;
 174 +               case 3:
 175 +                       opcode |= tx[2] << 16;
 176 +               case 2:
 177 +                       opcode |= tx[1] << 24;
 178 +               case 1:
 179 +                       opcode |= tx[0];
 180 +                       break;
 181 +
 182 +               default:
 183 +                       dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
 184 +                       return -EINVAL;
 185 +               }
 186 +
 187 +               rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
 188 +               rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
 189 +               trans |= xfer->len;
 190 +       }
 191 +
 192 +       if (rx)
 193 +               trans |= (next->len << 4);
 194 +       rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
 195 +       trans |= SPI_CTL_START;
 196 +       rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
 197 +
 198 +       mt7621_spi_wait_till_ready(rs);
 199 +
 200 +       if (rx) {
 201 +               u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
 202 +               u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
 203 +
 204 +               switch (next->len) {
 205 +               case 8:
 206 +                       rx[7] = (opcode >> 24) & 0xff;
 207 +               case 7:
 208 +                       rx[6] = (opcode >> 16) & 0xff;
 209 +               case 6:
 210 +                       rx[5] = (opcode >> 8) & 0xff;
 211 +               case 5:
 212 +                       rx[4] = opcode & 0xff;
 213 +               case 4:
 214 +                       rx[3] = (data0 >> 24) & 0xff;
 215 +               case 3:
 216 +                       rx[2] = (data0 >> 16) & 0xff;
 217 +               case 2:
 218 +                       rx[1] = (data0 >> 8) & 0xff;
 219 +               case 1:
 220 +                       rx[0] = data0 & 0xff;
 221 +                       break;
 222 +
 223 +               default:
 224 +                       dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
 225 +                       return -EINVAL;
 226 +               }
 227 +               len += next->len;
 228 +       }
 229 +
 230 +       return len;
 231 +}
 232 +
 233  static int rt2880_spi_transfer_one_message(struct spi_master *master,
 234                                            struct spi_message *m)
 235  {
 236 @@ -280,25 +440,25 @@ static int rt2880_spi_transfer_one_messa
 237                 }
 238
 239                 if (!cs_active) {
 240 -                       rt2880_spi_set_cs(rs, 1);
 241 +                       rs->ops->set_cs(rs, 1);
 242                         cs_active = 1;
 243                 }
 244
 245                 if (t->len)
 246 -                       m->actual_length += rt2880_spi_write_read(spi, t);
 247 +                       m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
 248
 249                 if (t->delay_usecs)
 250                         udelay(t->delay_usecs);
 251
 252                 if (t->cs_change) {
 253 -                       rt2880_spi_set_cs(rs, 0);
 254 +                       rs->ops->set_cs(rs, 0);
 255                         cs_active = 0;
 256                 }
 257         }
 258
 259  msg_done:
 260         if (cs_active)
 261 -               rt2880_spi_set_cs(rs, 0);
 262 +               rs->ops->set_cs(rs, 0);
 263
 264         m->status = status;
 265         spi_finalize_current_message(master);
 266 @@ -334,8 +494,41 @@ static void rt2880_spi_reset(struct rt28
 267         rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 268  }
 269
 270 +static void mt7621_spi_reset(struct rt2880_spi *rs)
 271 +{
 272 +       u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
 273 +
 274 +       master &= ~(0xfff << 16);
 275 +       master |= 3 << 16;
 276 +
 277 +       master |= 7 << 29;
 278 +       rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
 279 +}
 280 +
 281 +static struct rt2880_spi_ops spi_ops[] = {
 282 +       {
 283 +               .init_hw = rt2880_spi_reset,
 284 +               .set_cs = rt2880_spi_set_cs,
 285 +               .baudrate_set = rt2880_spi_baudrate_set,
 286 +               .write_read = rt2880_spi_write_read,
 287 +       }, {
 288 +               .init_hw = mt7621_spi_reset,
 289 +               .set_cs = mt7621_spi_set_cs,
 290 +               .baudrate_set = mt7621_spi_baudrate_set,
 291 +               .write_read = mt7621_spi_write_read,
 292 +       },
 293 +};
 294 +
 295 +static const struct of_device_id rt2880_spi_match[] = {
 296 +       { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
 297 +       { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
 298 +       {},
 299 +};
 300 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 301 +
 302  static int rt2880_spi_probe(struct platform_device *pdev)
 303  {
 304 +        const struct of_device_id *match;
 305         struct spi_master *master;
 306         struct rt2880_spi *rs;
 307         unsigned long flags;
 308 @@ -344,6 +537,10 @@ static int rt2880_spi_probe(struct platf
 309         int status = 0;
 310         struct clk *clk;
 311
 312 +        match = of_match_device(rt2880_spi_match, &pdev->dev);
 313 +       if (!match)
 314 +               return -EINVAL;
 315 +
 316         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 317         base = devm_ioremap_resource(&pdev->dev, r);
 318         if (IS_ERR(base))
 319 @@ -382,12 +579,13 @@ static int rt2880_spi_probe(struct platf
 320         rs->clk = clk;
 321         rs->master = master;
 322         rs->sys_freq = clk_get_rate(rs->clk);
 323 +       rs->ops = (struct rt2880_spi_ops *) match->data;
 324         dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
 325         spin_lock_irqsave(&rs->lock, flags);
 326
 327         device_reset(&pdev->dev);
 328
 329 -       rt2880_spi_reset(rs);
 330 +       rs->ops->init_hw(rs);
 331
 332         return spi_register_master(master);
 333  }
 334 @@ -408,12 +606,6 @@ static int rt2880_spi_remove(struct plat
 335
 336  MODULE_ALIAS("platform:" DRIVER_NAME);
 337
 338 -static const struct of_device_id rt2880_spi_match[] = {
 339 -       { .compatible = "ralink,rt2880-spi" },
 340 -       {},
 341 -};
 342 -MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 343 -
 344  static struct platform_driver rt2880_spi_driver = {
 345         .driver = {
 346                 .name = DRIVER_NAME,