target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_esw.c

   1 #include <linux/ioport.h>
   2 #include <linux/switch.h>
   3
   4 #include <rt305x_regs.h>
   5 #include <rt305x_esw_platform.h>
   6
   7 /*
   8  * HW limitations for this switch:
   9  * - No large frame support (PKT_MAX_LEN at most 1536)
  10  * - Can't have untagged vlan and tagged vlan on one port at the same time,
  11  *   though this might be possible using the undocumented PPE.
  12  */
  13
  14 #define RT305X_ESW_REG_FCT0             0x08
  15 #define RT305X_ESW_REG_PFC1             0x14
  16 #define RT305X_ESW_REG_ATS              0x24
  17 #define RT305X_ESW_REG_ATS0             0x28
  18 #define RT305X_ESW_REG_ATS1             0x2c
  19 #define RT305X_ESW_REG_ATS2             0x30
  20 #define RT305X_ESW_REG_PVIDC(_n)        (0x40 + 4 * (_n))
  21 #define RT305X_ESW_REG_VLANI(_n)        (0x50 + 4 * (_n))
  22 #define RT305X_ESW_REG_VMSC(_n)         (0x70 + 4 * (_n))
  23 #define RT305X_ESW_REG_POA              0x80
  24 #define RT305X_ESW_REG_FPA              0x84
  25 #define RT305X_ESW_REG_SOCPC            0x8c
  26 #define RT305X_ESW_REG_POC0             0x90
  27 #define RT305X_ESW_REG_POC1             0x94
  28 #define RT305X_ESW_REG_POC2             0x98
  29 #define RT305X_ESW_REG_SGC              0x9c
  30 #define RT305X_ESW_REG_STRT             0xa0
  31 #define RT305X_ESW_REG_PCR0             0xc0
  32 #define RT305X_ESW_REG_PCR1             0xc4
  33 #define RT305X_ESW_REG_FPA2             0xc8
  34 #define RT305X_ESW_REG_FCT2             0xcc
  35 #define RT305X_ESW_REG_SGC2             0xe4
  36 #define RT305X_ESW_REG_P0LED            0xa4
  37 #define RT305X_ESW_REG_P1LED            0xa8
  38 #define RT305X_ESW_REG_P2LED            0xac
  39 #define RT305X_ESW_REG_P3LED            0xb0
  40 #define RT305X_ESW_REG_P4LED            0xb4
  41 #define RT305X_ESW_REG_P0PC             0xe8
  42 #define RT305X_ESW_REG_P1PC             0xec
  43 #define RT305X_ESW_REG_P2PC             0xf0
  44 #define RT305X_ESW_REG_P3PC             0xf4
  45 #define RT305X_ESW_REG_P4PC             0xf8
  46 #define RT305X_ESW_REG_P5PC             0xfc
  47
  48 #define RT305X_ESW_LED_LINK             0
  49 #define RT305X_ESW_LED_100M             1
  50 #define RT305X_ESW_LED_DUPLEX           2
  51 #define RT305X_ESW_LED_ACTIVITY         3
  52 #define RT305X_ESW_LED_COLLISION        4
  53 #define RT305X_ESW_LED_LINKACT          5
  54 #define RT305X_ESW_LED_DUPLCOLL         6
  55 #define RT305X_ESW_LED_10MACT           7
  56 #define RT305X_ESW_LED_100MACT          8
  57 /* Additional led states not in datasheet: */
  58 #define RT305X_ESW_LED_BLINK            10
  59 #define RT305X_ESW_LED_ON               12
  60
  61 #define RT305X_ESW_LINK_S               25
  62 #define RT305X_ESW_DUPLEX_S             9
  63 #define RT305X_ESW_SPD_S                0
  64
  65 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S  16
  66 #define RT305X_ESW_PCR0_WT_PHY_CMD      BIT(13)
  67 #define RT305X_ESW_PCR0_CPU_PHY_REG_S   8
  68
  69 #define RT305X_ESW_PCR1_WT_DONE         BIT(0)
  70
  71 #define RT305X_ESW_ATS_TIMEOUT          (5 * HZ)
  72 #define RT305X_ESW_PHY_TIMEOUT          (5 * HZ)
  73
  74 #define RT305X_ESW_PVIDC_PVID_M         0xfff
  75 #define RT305X_ESW_PVIDC_PVID_S         12
  76
  77 #define RT305X_ESW_VLANI_VID_M          0xfff
  78 #define RT305X_ESW_VLANI_VID_S          12
  79
  80 #define RT305X_ESW_VMSC_MSC_M           0xff
  81 #define RT305X_ESW_VMSC_MSC_S           8
  82
  83 #define RT305X_ESW_SOCPC_DISUN2CPU_S    0
  84 #define RT305X_ESW_SOCPC_DISMC2CPU_S    8
  85 #define RT305X_ESW_SOCPC_DISBC2CPU_S    16
  86 #define RT305X_ESW_SOCPC_CRC_PADDING    BIT(25)
  87
  88 #define RT305X_ESW_POC0_EN_BP_S         0
  89 #define RT305X_ESW_POC0_EN_FC_S         8
  90 #define RT305X_ESW_POC0_DIS_RMC2CPU_S   16
  91 #define RT305X_ESW_POC0_DIS_PORT_M      0x7f
  92 #define RT305X_ESW_POC0_DIS_PORT_S      23
  93
  94 #define RT305X_ESW_POC2_UNTAG_EN_M      0xff
  95 #define RT305X_ESW_POC2_UNTAG_EN_S      0
  96 #define RT305X_ESW_POC2_ENAGING_S       8
  97 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S  16
  98
  99 #define RT305X_ESW_SGC2_DOUBLE_TAG_M    0x7f
 100 #define RT305X_ESW_SGC2_DOUBLE_TAG_S    0
 101 #define RT305X_ESW_SGC2_LAN_PMAP_M      0x3f
 102 #define RT305X_ESW_SGC2_LAN_PMAP_S      24
 103
 104 #define RT305X_ESW_PFC1_EN_VLAN_M       0xff
 105 #define RT305X_ESW_PFC1_EN_VLAN_S       16
 106 #define RT305X_ESW_PFC1_EN_TOS_S        24
 107
 108 #define RT305X_ESW_VLAN_NONE            0xfff
 109
 110 #define RT305X_ESW_PORT0                0
 111 #define RT305X_ESW_PORT1                1
 112 #define RT305X_ESW_PORT2                2
 113 #define RT305X_ESW_PORT3                3
 114 #define RT305X_ESW_PORT4                4
 115 #define RT305X_ESW_PORT5                5
 116 #define RT305X_ESW_PORT6                6
 117
 118 #define RT305X_ESW_PORTS_NONE           0
 119
 120 #define RT305X_ESW_PMAP_LLLLLL          0x3f
 121 #define RT305X_ESW_PMAP_LLLLWL          0x2f
 122 #define RT305X_ESW_PMAP_WLLLLL          0x3e
 123
 124 #define RT305X_ESW_PORTS_INTERNAL                                       \
 125                 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
 126                  BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
 127                  BIT(RT305X_ESW_PORT4))
 128
 129 #define RT305X_ESW_PORTS_NOCPU                                          \
 130                 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
 131
 132 #define RT305X_ESW_PORTS_CPU    BIT(RT305X_ESW_PORT6)
 133
 134 #define RT305X_ESW_PORTS_ALL                                            \
 135                 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
 136
 137 #define RT305X_ESW_NUM_VLANS            16
 138 #define RT305X_ESW_NUM_VIDS             4096
 139 #define RT305X_ESW_NUM_PORTS            7
 140 #define RT305X_ESW_NUM_LANWAN           6
 141 #define RT305X_ESW_NUM_LEDS             5
 142
 143 enum {
 144         /* Global attributes. */
 145         RT305X_ESW_ATTR_ENABLE_VLAN,
 146         RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
 147         /* Port attributes. */
 148         RT305X_ESW_ATTR_PORT_DISABLE,
 149         RT305X_ESW_ATTR_PORT_DOUBLETAG,
 150         RT305X_ESW_ATTR_PORT_UNTAG,
 151         RT305X_ESW_ATTR_PORT_LED,
 152         RT305X_ESW_ATTR_PORT_LAN,
 153         RT305X_ESW_ATTR_PORT_RECV_BAD,
 154         RT305X_ESW_ATTR_PORT_RECV_GOOD,
 155 };
 156
 157 struct rt305x_esw_port {
 158         bool    disable;
 159         bool    doubletag;
 160         bool    untag;
 161         u8      led;
 162         u16     pvid;
 163 };
 164
 165 struct rt305x_esw_vlan {
 166         u8      ports;
 167         u16     vid;
 168 };
 169
 170 struct rt305x_esw {
 171         void __iomem            *base;
 172         struct rt305x_esw_platform_data *pdata;
 173         /* Protects against concurrent register rmw operations. */
 174         spinlock_t              reg_rw_lock;
 175
 176         struct switch_dev       swdev;
 177         bool                    global_vlan_enable;
 178         bool                    alt_vlan_disable;
 179         struct rt305x_esw_vlan vlans[RT305X_ESW_NUM_VLANS];
 180         struct rt305x_esw_port ports[RT305X_ESW_NUM_PORTS];
 181
 182 };
 183
 184 static inline void
 185 rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
 186 {
 187         __raw_writel(val, esw->base + reg);
 188 }
 189
 190 static inline u32
 191 rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
 192 {
 193         return __raw_readl(esw->base + reg);
 194 }
 195
 196 static inline void
 197 rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 198                    unsigned long val)
 199 {
 200         unsigned long t;
 201
 202         t = __raw_readl(esw->base + reg) & ~mask;
 203         __raw_writel(t | val, esw->base + reg);
 204 }
 205
 206 static void
 207 rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 208                unsigned long val)
 209 {
 210         unsigned long flags;
 211
 212         spin_lock_irqsave(&esw->reg_rw_lock, flags);
 213         rt305x_esw_rmw_raw(esw, reg, mask, val);
 214         spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
 215 }
 216
 217 static u32
 218 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
 219                  u32 write_data)
 220 {
 221         unsigned long t_start = jiffies;
 222         int ret = 0;
 223
 224         while (1) {
 225                 if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
 226                       RT305X_ESW_PCR1_WT_DONE))
 227                         break;
 228                 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 229                         ret = 1;
 230                         goto out;
 231                 }
 232         }
 233
 234         write_data &= 0xffff;
 235         rt305x_esw_wr(esw,
 236                       (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
 237                       (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
 238                       (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
 239                       RT305X_ESW_REG_PCR0);
 240
 241         t_start = jiffies;
 242         while (1) {
 243                 if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
 244                     RT305X_ESW_PCR1_WT_DONE)
 245                         break;
 246
 247                 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 248                         ret = 1;
 249                         break;
 250                 }
 251         }
 252 out:
 253         if (ret)
 254                 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
 255         return ret;
 256 }
 257
 258 static unsigned
 259 rt305x_esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
 260 {
 261         unsigned s;
 262         unsigned val;
 263
 264         s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 265         val = rt305x_esw_rr(esw, RT305X_ESW_REG_VLANI(vlan / 2));
 266         val = (val >> s) & RT305X_ESW_VLANI_VID_M;
 267
 268         return val;
 269 }
 270
 271 static void
 272 rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
 273 {
 274         unsigned s;
 275
 276         s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 277         rt305x_esw_rmw(esw,
 278                        RT305X_ESW_REG_VLANI(vlan / 2),
 279                        RT305X_ESW_VLANI_VID_M << s,
 280                        (vid & RT305X_ESW_VLANI_VID_M) << s);
 281 }
 282
 283 static unsigned
 284 rt305x_esw_get_pvid(struct rt305x_esw *esw, unsigned port)
 285 {
 286         unsigned s, val;
 287
 288         s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 289         val = rt305x_esw_rr(esw, RT305X_ESW_REG_PVIDC(port / 2));
 290         return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
 291 }
 292
 293 static void
 294 rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
 295 {
 296         unsigned s;
 297
 298         s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 299         rt305x_esw_rmw(esw,
 300                        RT305X_ESW_REG_PVIDC(port / 2),
 301                        RT305X_ESW_PVIDC_PVID_M << s,
 302                        (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
 303 }
 304
 305 static unsigned
 306 rt305x_esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
 307 {
 308         unsigned s, val;
 309
 310         s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 311         val = rt305x_esw_rr(esw, RT305X_ESW_REG_VMSC(vlan / 4));
 312         val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
 313
 314         return val;
 315 }
 316
 317 static void
 318 rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
 319 {
 320         unsigned s;
 321
 322         s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 323         rt305x_esw_rmw(esw,
 324                        RT305X_ESW_REG_VMSC(vlan / 4),
 325                        RT305X_ESW_VMSC_MSC_M << s,
 326                        (msc & RT305X_ESW_VMSC_MSC_M) << s);
 327 }
 328
 329 static int
 330 rt305x_esw_apply_config(struct switch_dev *dev);
 331
 332 static void
 333 rt305x_esw_hw_init(struct rt305x_esw *esw)
 334 {
 335         int i;
 336         u8 port_map = RT305X_ESW_PMAP_LLLLLL;
 337
 338         /* vodoo from original driver */
 339         rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
 340         rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
 341         /* Port priority 1 for all ports, vlan enabled. */
 342         rt305x_esw_wr(esw, 0x00005555 |
 343                       (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
 344                       RT305X_ESW_REG_PFC1);
 345
 346         /* Enable Back Pressure, and Flow Control */
 347         rt305x_esw_wr(esw,
 348                       ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
 349                        (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
 350                       RT305X_ESW_REG_POC0);
 351
 352         /* Enable Aging, and VLAN TAG removal */
 353         rt305x_esw_wr(esw,
 354                       ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
 355                        (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
 356                       RT305X_ESW_REG_POC2);
 357
 358         rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 359
 360         /*
 361          * 300s aging timer, max packet len 1536, broadcast storm prevention
 362          * disabled, disable collision abort, mac xor48 hash, 10 packet back
 363          * pressure jam, GMII disable was_transmit, back pressure disabled,
 364          * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
 365          * ports.
 366          */
 367         rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
 368
 369         /* Setup SoC Port control register */
 370         rt305x_esw_wr(esw,
 371                       (RT305X_ESW_SOCPC_CRC_PADDING |
 372                        (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
 373                        (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
 374                        (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
 375                       RT305X_ESW_REG_SOCPC);
 376
 377         rt305x_esw_wr(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 378         rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
 379
 380         /* Force Link/Activity on ports */
 381         rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED);
 382         rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED);
 383         rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED);
 384         rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED);
 385         rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED);
 386
 387         rt305x_mii_write(esw, 0, 31, 0x8000);
 388         for (i = 0; i < 5; i++) {
 389                 /* TX10 waveform coefficient */
 390                 rt305x_mii_write(esw, i, 0, 0x3100);
 391                 /* TX10 waveform coefficient */
 392                 rt305x_mii_write(esw, i, 26, 0x1601);
 393                 /* TX100/TX10 AD/DA current bias */
 394                 rt305x_mii_write(esw, i, 29, 0x7058);
 395                 /* TX100 slew rate control */
 396                 rt305x_mii_write(esw, i, 30, 0x0018);
 397         }
 398
 399         /* PHY IOT */
 400         /* select global register */
 401         rt305x_mii_write(esw, 0, 31, 0x0);
 402         /* tune TP_IDL tail and head waveform */
 403         rt305x_mii_write(esw, 0, 22, 0x052f);
 404         /* set TX10 signal amplitude threshold to minimum */
 405         rt305x_mii_write(esw, 0, 17, 0x0fe0);
 406         /* set squelch amplitude to higher threshold */
 407         rt305x_mii_write(esw, 0, 18, 0x40ba);
 408         /* longer TP_IDL tail length */
 409         rt305x_mii_write(esw, 0, 14, 0x65);
 410         /* select local register */
 411         rt305x_mii_write(esw, 0, 31, 0x8000);
 412
 413         switch (esw->pdata->vlan_config) {
 414         case RT305X_ESW_VLAN_CONFIG_NONE:
 415                 port_map = RT305X_ESW_PMAP_LLLLLL;
 416                 break;
 417         case RT305X_ESW_VLAN_CONFIG_LLLLW:
 418                 port_map = RT305X_ESW_PMAP_LLLLWL;
 419                 break;
 420         case RT305X_ESW_VLAN_CONFIG_WLLLL:
 421                 port_map = RT305X_ESW_PMAP_WLLLLL;
 422                 break;
 423         default:
 424                 BUG();
 425         }
 426
 427         /*
 428          * Unused HW feature, but still nice to be consistent here...
 429          * This is also exported to userspace ('lan' attribute) so it's
 430          * conveniently usable to decide which ports go into the wan vlan by
 431          * default.
 432          */
 433         rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
 434                        RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
 435                        port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
 436
 437         /* Apply the empty config. */
 438         rt305x_esw_apply_config(&esw->swdev);
 439 }
 440
 441 static int
 442 rt305x_esw_apply_config(struct switch_dev *dev)
 443 {
 444         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 445         int i;
 446         u8 disable = 0;
 447         u8 doubletag = 0;
 448         u8 en_vlan = 0;
 449         u8 untag = 0;
 450
 451         for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 452                 u32 vid, vmsc;
 453                 if (esw->global_vlan_enable) {
 454                         vid = esw->vlans[i].vid;
 455                         vmsc = esw->vlans[i].ports;
 456                 } else {
 457                         vid = RT305X_ESW_VLAN_NONE;
 458                         vmsc = RT305X_ESW_PORTS_NONE;
 459                 }
 460                 rt305x_esw_set_vlan_id(esw, i, vid);
 461                 rt305x_esw_set_vmsc(esw, i, vmsc);
 462         }
 463
 464         for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
 465                 u32 pvid;
 466                 disable |= esw->ports[i].disable << i;
 467                 if (esw->global_vlan_enable) {
 468                         doubletag |= esw->ports[i].doubletag << i;
 469                         en_vlan   |= 1                       << i;
 470                         untag     |= esw->ports[i].untag     << i;
 471                         pvid       = esw->ports[i].pvid;
 472                 } else {
 473                         int x = esw->alt_vlan_disable ? 1 : 0;
 474                         doubletag |= x << i;
 475                         en_vlan   |= x << i;
 476                         untag     |= x << i;
 477                         pvid       = 0;
 478                 }
 479                 rt305x_esw_set_pvid(esw, i, pvid);
 480                 if (i < RT305X_ESW_NUM_LEDS)
 481                         rt305x_esw_wr(esw, esw->ports[i].led,
 482                                       RT305X_ESW_REG_P0LED + 4*i);
 483         }
 484
 485         rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
 486                        RT305X_ESW_POC0_DIS_PORT_M << RT305X_ESW_POC0_DIS_PORT_S,
 487                        disable << RT305X_ESW_POC0_DIS_PORT_S);
 488         rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
 489                        (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
 490                         RT305X_ESW_SGC2_DOUBLE_TAG_S),
 491                        doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
 492         rt305x_esw_rmw(esw, RT305X_ESW_REG_PFC1,
 493                        RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
 494                        en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
 495         rt305x_esw_rmw(esw, RT305X_ESW_REG_POC2,
 496                        RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
 497                        untag << RT305X_ESW_POC2_UNTAG_EN_S);
 498
 499         if (!esw->global_vlan_enable) {
 500                 /*
 501                  * Still need to put all ports into vlan 0 or they'll be
 502                  * isolated.
 503                  * NOTE: vlan 0 is special, no vlan tag is prepended
 504                  */
 505                 rt305x_esw_set_vlan_id(esw, 0, 0);
 506                 rt305x_esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int
 513 rt305x_esw_reset_switch(struct switch_dev *dev)
 514 {
 515         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 516         esw->global_vlan_enable = 0;
 517         memset(esw->ports, 0, sizeof(esw->ports));
 518         memset(esw->vlans, 0, sizeof(esw->vlans));
 519         rt305x_esw_hw_init(esw);
 520
 521         return 0;
 522 }
 523
 524 static int
 525 rt305x_esw_get_vlan_enable(struct switch_dev *dev,
 526                            const struct switch_attr *attr,
 527                            struct switch_val *val)
 528 {
 529         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 530
 531         val->value.i = esw->global_vlan_enable;
 532
 533         return 0;
 534 }
 535
 536 static int
 537 rt305x_esw_set_vlan_enable(struct switch_dev *dev,
 538                            const struct switch_attr *attr,
 539                            struct switch_val *val)
 540 {
 541         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 542
 543         esw->global_vlan_enable = val->value.i != 0;
 544
 545         return 0;
 546 }
 547
 548 static int
 549 rt305x_esw_get_alt_vlan_disable(struct switch_dev *dev,
 550                                 const struct switch_attr *attr,
 551                                 struct switch_val *val)
 552 {
 553         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 554
 555         val->value.i = esw->alt_vlan_disable;
 556
 557         return 0;
 558 }
 559
 560 static int
 561 rt305x_esw_set_alt_vlan_disable(struct switch_dev *dev,
 562                                 const struct switch_attr *attr,
 563                                 struct switch_val *val)
 564 {
 565         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 566
 567         esw->alt_vlan_disable = val->value.i != 0;
 568
 569         return 0;
 570 }
 571
 572 static int
 573 rt305x_esw_get_port_link(struct switch_dev *dev,
 574                          int port,
 575                          struct switch_port_link *link)
 576 {
 577         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 578         u32 speed, poa;
 579
 580         if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
 581                 return -EINVAL;
 582
 583         poa = rt305x_esw_rr(esw, RT305X_ESW_REG_POA) >> port;
 584
 585         link->link = (poa >> RT305X_ESW_LINK_S) & 1;
 586         link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
 587         if (port < RT305X_ESW_NUM_LEDS) {
 588                 speed = (poa >> RT305X_ESW_SPD_S) & 1;
 589         } else {
 590                 if (port == RT305X_ESW_NUM_PORTS - 1)
 591                         poa >>= 1;
 592                 speed = (poa >> RT305X_ESW_SPD_S) & 3;
 593         }
 594         switch (speed) {
 595         case 0:
 596                 link->speed = SWITCH_PORT_SPEED_10;
 597                 break;
 598         case 1:
 599                 link->speed = SWITCH_PORT_SPEED_100;
 600                 break;
 601         case 2:
 602         case 3: /* forced gige speed can be 2 or 3 */
 603                 link->speed = SWITCH_PORT_SPEED_1000;
 604                 break;
 605         default:
 606                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 607                 break;
 608         }
 609
 610         return 0;
 611 }
 612
 613 static int
 614 rt305x_esw_get_port_bool(struct switch_dev *dev,
 615                          const struct switch_attr *attr,
 616                          struct switch_val *val)
 617 {
 618         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 619         int idx = val->port_vlan;
 620         u32 x, reg, shift;
 621
 622         if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
 623                 return -EINVAL;
 624
 625         switch (attr->id) {
 626         case RT305X_ESW_ATTR_PORT_DISABLE:
 627                 reg = RT305X_ESW_REG_POC0;
 628                 shift = RT305X_ESW_POC0_DIS_PORT_S;
 629                 break;
 630         case RT305X_ESW_ATTR_PORT_DOUBLETAG:
 631                 reg = RT305X_ESW_REG_SGC2;
 632                 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
 633                 break;
 634         case RT305X_ESW_ATTR_PORT_UNTAG:
 635                 reg = RT305X_ESW_REG_POC2;
 636                 shift = RT305X_ESW_POC2_UNTAG_EN_S;
 637                 break;
 638         case RT305X_ESW_ATTR_PORT_LAN:
 639                 reg = RT305X_ESW_REG_SGC2;
 640                 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
 641                 if (idx >= RT305X_ESW_NUM_LANWAN)
 642                         return -EINVAL;
 643                 break;
 644         default:
 645                 return -EINVAL;
 646         }
 647
 648         x = rt305x_esw_rr(esw, reg);
 649         val->value.i = (x >> (idx + shift)) & 1;
 650
 651         return 0;
 652 }
 653
 654 static int
 655 rt305x_esw_set_port_bool(struct switch_dev *dev,
 656                          const struct switch_attr *attr,
 657                          struct switch_val *val)
 658 {
 659         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 660         int idx = val->port_vlan;
 661
 662         if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
 663             val->value.i < 0 || val->value.i > 1)
 664                 return -EINVAL;
 665
 666         switch (attr->id) {
 667         case RT305X_ESW_ATTR_PORT_DISABLE:
 668                 esw->ports[idx].disable = val->value.i;
 669                 break;
 670         case RT305X_ESW_ATTR_PORT_DOUBLETAG:
 671                 esw->ports[idx].doubletag = val->value.i;
 672                 break;
 673         case RT305X_ESW_ATTR_PORT_UNTAG:
 674                 esw->ports[idx].untag = val->value.i;
 675                 break;
 676         default:
 677                 return -EINVAL;
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int
 684 rt305x_esw_get_port_recv_badgood(struct switch_dev *dev,
 685                                  const struct switch_attr *attr,
 686                                  struct switch_val *val)
 687 {
 688         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 689         int idx = val->port_vlan;
 690         int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
 691
 692         if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
 693                 return -EINVAL;
 694
 695         val->value.i = rt305x_esw_rr(esw, RT305X_ESW_REG_P0PC + 4*idx) >> shift;
 696
 697         return 0;
 698 }
 699
 700 static int
 701 rt305x_esw_get_port_led(struct switch_dev *dev,
 702                         const struct switch_attr *attr,
 703                         struct switch_val *val)
 704 {
 705         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 706         int idx = val->port_vlan;
 707
 708         if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
 709             idx >= RT305X_ESW_NUM_LEDS)
 710                 return -EINVAL;
 711
 712         val->value.i = rt305x_esw_rr(esw, RT305X_ESW_REG_P0LED + 4*idx);
 713
 714         return 0;
 715 }
 716
 717 static int
 718 rt305x_esw_set_port_led(struct switch_dev *dev,
 719                         const struct switch_attr *attr,
 720                         struct switch_val *val)
 721 {
 722         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 723         int idx = val->port_vlan;
 724
 725         if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
 726                 return -EINVAL;
 727
 728         esw->ports[idx].led = val->value.i;
 729
 730         return 0;
 731 }
 732
 733 static int
 734 rt305x_esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
 735 {
 736         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 737
 738         if (port >= RT305X_ESW_NUM_PORTS)
 739                 return -EINVAL;
 740
 741         *val = rt305x_esw_get_pvid(esw, port);
 742
 743         return 0;
 744 }
 745
 746 static int
 747 rt305x_esw_set_port_pvid(struct switch_dev *dev, int port, int val)
 748 {
 749         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 750
 751         if (port >= RT305X_ESW_NUM_PORTS)
 752                 return -EINVAL;
 753
 754         esw->ports[port].pvid = val;
 755
 756         return 0;
 757 }
 758
 759 static int
 760 rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
 761 {
 762         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 763         u32 vmsc, poc2;
 764         int vlan_idx = -1;
 765         int i;
 766
 767         val->len = 0;
 768
 769         if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
 770                 return -EINVAL;
 771
 772         /* valid vlan? */
 773         for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 774                 if (rt305x_esw_get_vlan_id(esw, i) == val->port_vlan &&
 775                     rt305x_esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
 776                         vlan_idx = i;
 777                         break;
 778                 }
 779         }
 780
 781         if (vlan_idx == -1)
 782                 return -EINVAL;
 783
 784         vmsc = rt305x_esw_get_vmsc(esw, vlan_idx);
 785         poc2 = rt305x_esw_rr(esw, RT305X_ESW_REG_POC2);
 786
 787         for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
 788                 struct switch_port *p;
 789                 int port_mask = 1 << i;
 790
 791                 if (!(vmsc & port_mask))
 792                         continue;
 793
 794                 p = &val->value.ports[val->len++];
 795                 p->id = i;
 796                 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
 797                         p->flags = 0;
 798                 else
 799                         p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
 800         }
 801
 802         return 0;
 803 }
 804
 805 static int
 806 rt305x_esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
 807 {
 808         struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 809         int ports;
 810         int vlan_idx = -1;
 811         int i;
 812
 813         if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
 814             val->len > RT305X_ESW_NUM_PORTS)
 815                 return -EINVAL;
 816
 817         /* one of the already defined vlans? */
 818         for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 819                 if (esw->vlans[i].vid == val->port_vlan &&
 820                     esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
 821                         vlan_idx = i;
 822                         break;
 823                 }
 824         }
 825
 826         /* select a free slot */
 827         for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
 828                 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
 829                         vlan_idx = i;
 830         }
 831
 832         /* bail if all slots are in use */
 833         if (vlan_idx == -1)
 834                 return -EINVAL;
 835
 836         ports = RT305X_ESW_PORTS_NONE;
 837         for (i = 0; i < val->len; i++) {
 838                 struct switch_port *p = &val->value.ports[i];
 839                 int port_mask = 1 << p->id;
 840                 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
 841
 842                 if (p->id >= RT305X_ESW_NUM_PORTS)
 843                         return -EINVAL;
 844
 845                 ports |= port_mask;
 846                 esw->ports[p->id].untag = untagged;
 847         }
 848         esw->vlans[vlan_idx].ports = ports;
 849         if (ports == RT305X_ESW_PORTS_NONE)
 850                 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
 851         else
 852                 esw->vlans[vlan_idx].vid = val->port_vlan;
 853
 854         return 0;
 855 }
 856
 857 static const struct switch_attr rt305x_esw_global[] = {
 858         {
 859                 .type = SWITCH_TYPE_INT,
 860                 .name = "enable_vlan",
 861                 .description = "VLAN mode (1:enabled)",
 862                 .max = 1,
 863                 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
 864                 .get = rt305x_esw_get_vlan_enable,
 865                 .set = rt305x_esw_set_vlan_enable,
 866         },
 867         {
 868                 .type = SWITCH_TYPE_INT,
 869                 .name = "alternate_vlan_disable",
 870                 .description = "Use en_vlan instead of doubletag to disable"
 871                                 " VLAN mode",
 872                 .max = 1,
 873                 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
 874                 .get = rt305x_esw_get_alt_vlan_disable,
 875                 .set = rt305x_esw_set_alt_vlan_disable,
 876         },
 877 };
 878
 879 static const struct switch_attr rt305x_esw_port[] = {
 880         {
 881                 .type = SWITCH_TYPE_INT,
 882                 .name = "disable",
 883                 .description = "Port state (1:disabled)",
 884                 .max = 1,
 885                 .id = RT305X_ESW_ATTR_PORT_DISABLE,
 886                 .get = rt305x_esw_get_port_bool,
 887                 .set = rt305x_esw_set_port_bool,
 888         },
 889         {
 890                 .type = SWITCH_TYPE_INT,
 891                 .name = "doubletag",
 892                 .description = "Double tagging for incoming vlan packets "
 893                                 "(1:enabled)",
 894                 .max = 1,
 895                 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
 896                 .get = rt305x_esw_get_port_bool,
 897                 .set = rt305x_esw_set_port_bool,
 898         },
 899         {
 900                 .type = SWITCH_TYPE_INT,
 901                 .name = "untag",
 902                 .description = "Untag (1:strip outgoing vlan tag)",
 903                 .max = 1,
 904                 .id = RT305X_ESW_ATTR_PORT_UNTAG,
 905                 .get = rt305x_esw_get_port_bool,
 906                 .set = rt305x_esw_set_port_bool,
 907         },
 908         {
 909                 .type = SWITCH_TYPE_INT,
 910                 .name = "led",
 911                 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
 912                                 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
 913                                 " 8:100mact, 10:blink, 12:on)",
 914                 .max = 15,
 915                 .id = RT305X_ESW_ATTR_PORT_LED,
 916                 .get = rt305x_esw_get_port_led,
 917                 .set = rt305x_esw_set_port_led,
 918         },
 919         {
 920                 .type = SWITCH_TYPE_INT,
 921                 .name = "lan",
 922                 .description = "HW port group (0:wan, 1:lan)",
 923                 .max = 1,
 924                 .id = RT305X_ESW_ATTR_PORT_LAN,
 925                 .get = rt305x_esw_get_port_bool,
 926         },
 927         {
 928                 .type = SWITCH_TYPE_INT,
 929                 .name = "recv_bad",
 930                 .description = "Receive bad packet counter",
 931                 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
 932                 .get = rt305x_esw_get_port_recv_badgood,
 933         },
 934         {
 935                 .type = SWITCH_TYPE_INT,
 936                 .name = "recv_good",
 937                 .description = "Receive good packet counter",
 938                 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
 939                 .get = rt305x_esw_get_port_recv_badgood,
 940         },
 941 };
 942
 943 static const struct switch_attr rt305x_esw_vlan[] = {
 944 };
 945
 946 static const struct switch_dev_ops rt305x_esw_ops = {
 947         .attr_global = {
 948                 .attr = rt305x_esw_global,
 949                 .n_attr = ARRAY_SIZE(rt305x_esw_global),
 950         },
 951         .attr_port = {
 952                 .attr = rt305x_esw_port,
 953                 .n_attr = ARRAY_SIZE(rt305x_esw_port),
 954         },
 955         .attr_vlan = {
 956                 .attr = rt305x_esw_vlan,
 957                 .n_attr = ARRAY_SIZE(rt305x_esw_vlan),
 958         },
 959         .get_vlan_ports = rt305x_esw_get_vlan_ports,
 960         .set_vlan_ports = rt305x_esw_set_vlan_ports,
 961         .get_port_pvid = rt305x_esw_get_port_pvid,
 962         .set_port_pvid = rt305x_esw_set_port_pvid,
 963         .get_port_link = rt305x_esw_get_port_link,
 964         .apply_config = rt305x_esw_apply_config,
 965         .reset_switch = rt305x_esw_reset_switch,
 966 };
 967
 968 static int
 969 rt305x_esw_probe(struct platform_device *pdev)
 970 {
 971         struct rt305x_esw_platform_data *pdata;
 972         struct rt305x_esw *esw;
 973         struct switch_dev *swdev;
 974         struct resource *res;
 975         int err;
 976
 977         pdata = pdev->dev.platform_data;
 978         if (!pdata)
 979                 return -EINVAL;
 980
 981         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 982         if (!res) {
 983                 dev_err(&pdev->dev, "no memory resource found\n");
 984                 return -ENOMEM;
 985         }
 986
 987         esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
 988         if (!esw) {
 989                 dev_err(&pdev->dev, "no memory for private data\n");
 990                 return -ENOMEM;
 991         }
 992
 993         esw->base = ioremap(res->start, resource_size(res));
 994         if (!esw->base) {
 995                 dev_err(&pdev->dev, "ioremap failed\n");
 996                 err = -ENOMEM;
 997                 goto free_esw;
 998         }
 999
1000         swdev = &esw->swdev;
1001         swdev->name = "rt305x-esw";
1002         swdev->alias = "rt305x";
1003         swdev->cpu_port = RT305X_ESW_PORT6;
1004         swdev->ports = RT305X_ESW_NUM_PORTS;
1005         swdev->vlans = RT305X_ESW_NUM_VIDS;
1006         swdev->ops = &rt305x_esw_ops;
1007
1008         err = register_switch(swdev, NULL);
1009         if (err < 0) {
1010                 dev_err(&pdev->dev, "register_switch failed\n");
1011                 goto unmap_base;
1012         }
1013
1014         platform_set_drvdata(pdev, esw);
1015
1016         esw->pdata = pdata;
1017         spin_lock_init(&esw->reg_rw_lock);
1018         rt305x_esw_hw_init(esw);
1019
1020         return 0;
1021
1022 unmap_base:
1023         iounmap(esw->base);
1024 free_esw:
1025         kfree(esw);
1026         return err;
1027 }
1028
1029 static int
1030 rt305x_esw_remove(struct platform_device *pdev)
1031 {
1032         struct rt305x_esw *esw;
1033
1034         esw = platform_get_drvdata(pdev);
1035         if (esw) {
1036                 unregister_switch(&esw->swdev);
1037                 platform_set_drvdata(pdev, NULL);
1038                 iounmap(esw->base);
1039                 kfree(esw);
1040         }
1041
1042         return 0;
1043 }
1044
1045 static struct platform_driver rt305x_esw_driver = {
1046         .probe = rt305x_esw_probe,
1047         .remove = rt305x_esw_remove,
1048         .driver = {
1049                 .name = "rt305x-esw",
1050                 .owner = THIS_MODULE,
1051         },
1052 };
1053
1054 static int __init
1055 rt305x_esw_init(void)
1056 {
1057         return platform_driver_register(&rt305x_esw_driver);
1058 }
1059
1060 static void
1061 rt305x_esw_exit(void)
1062 {
1063         platform_driver_unregister(&rt305x_esw_driver);
1064 }