2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
22 #include <asm/mach-ralink/ralink_regs.h>
25 #include "ralink_soc_eth.h"
26 #include "gsw_mt7620a.h"
28 #define MT7620A_CDMA_CSG_CFG 0x400
29 #define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
30 #define MT7620A_DMA_2B_OFFSET BIT(31)
31 #define MT7620A_RESET_FE BIT(21)
32 #define MT7620A_RESET_ESW BIT(23)
33 #define MT7620_L4_VALID BIT(23)
35 #define MT7620_TX_DMA_UDF BIT(15)
36 #define TX_DMA_FP_BMAP ((0xff) << 19)
38 #define SYSC_REG_RESET_CTRL 0x34
40 #define CDMA_ICS_EN BIT(2)
41 #define CDMA_UCS_EN BIT(1)
42 #define CDMA_TCS_EN BIT(0)
44 #define GDMA_ICS_EN BIT(22)
45 #define GDMA_TCS_EN BIT(21)
46 #define GDMA_UCS_EN BIT(20)
48 /* frame engine counters */
49 #define MT7620_REG_MIB_OFFSET 0x1000
50 #define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
51 #define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
52 #define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
54 static const u32 mt7620_reg_table[FE_REG_COUNT] = {
55 [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
56 [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
57 [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
58 [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
59 [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
60 [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
61 [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
62 [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
63 [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
64 [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
65 [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
66 [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
67 [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
70 static void mt7620_fe_reset(void)
72 rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
73 rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
76 static void mt7620_rxcsum_config(bool enable)
79 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
80 GDMA_TCS_EN | GDMA_UCS_EN),
81 MT7620A_GDMA1_FWD_CFG);
83 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
84 GDMA_TCS_EN | GDMA_UCS_EN),
85 MT7620A_GDMA1_FWD_CFG);
88 static void mt7620_txcsum_config(bool enable)
91 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
92 CDMA_UCS_EN | CDMA_TCS_EN),
93 MT7620A_CDMA_CSG_CFG);
95 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
96 CDMA_UCS_EN | CDMA_TCS_EN),
97 MT7620A_CDMA_CSG_CFG);
100 static int mt7620_fwd_config(struct fe_priv *priv)
102 struct net_device *dev = priv_netdev(priv);
104 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
106 mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
107 mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
112 static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
114 priv->tx_dma[idx].txd4 = 0;
117 static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
119 priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
122 static void mt7620_init_data(struct fe_soc_data *data,
123 struct net_device *netdev)
125 struct fe_priv *priv = netdev_priv(netdev);
127 priv->flags = FE_FLAG_PADDING_64B;
128 netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
129 NETIF_F_HW_VLAN_CTAG_TX;
131 if (mt7620_get_eco() >= 5)
132 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
136 static struct fe_soc_data mt7620_data = {
137 .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
138 .init_data = mt7620_init_data,
139 .reset_fe = mt7620_fe_reset,
140 .set_mac = mt7620_set_mac,
141 .fwd_config = mt7620_fwd_config,
142 .tx_dma = mt7620_tx_dma,
143 .rx_dma = mt7620_rx_dma,
144 .switch_init = mt7620_gsw_probe,
145 .switch_config = mt7620_gsw_config,
146 .port_init = mt7620_port_init,
147 .reg_table = mt7620_reg_table,
148 .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
149 .rx_dly_int = RT5350_RX_DLY_INT,
150 .tx_dly_int = RT5350_TX_DLY_INT,
151 .checksum_bit = MT7620_L4_VALID,
152 .tx_udf_bit = MT7620_TX_DMA_UDF,
153 .has_carrier = mt7620a_has_carrier,
154 .mdio_read = mt7620_mdio_read,
155 .mdio_write = mt7620_mdio_write,
156 .mdio_adjust_link = mt7620_mdio_link_adjust,
159 const struct of_device_id of_fe_match[] = {
160 { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
164 MODULE_DEVICE_TABLE(of, of_fe_match);