target/linux/lantiq/patches-3.9/0009-NET-PHY-adds-driver-for-lantiq-PHY11G.patch

   1 From 615cd43fa886a79cf717bba38a3243aeb3b66217 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 29 Jun 2013 19:13:39 +0200
   4 Subject: [PATCH 09/22] NET: PHY: adds driver for lantiq PHY11G
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/net/phy/Kconfig  |    5 ++
   9  drivers/net/phy/Makefile |    1 +
  10  drivers/net/phy/lantiq.c |  220 ++++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 226 insertions(+)
  12  create mode 100644 drivers/net/phy/lantiq.c
  13
  14 --- a/drivers/net/phy/Kconfig
  15 +++ b/drivers/net/phy/Kconfig
  16 @@ -149,6 +149,11 @@ config MICREL_PHY
  17         ---help---
  18           Currently has a driver for the KSZ8041
  19
  20 +config LANTIQ_PHY
  21 +       tristate "Driver for Lantiq PHYs"
  22 +       ---help---
  23 +         Supports the 11G and 22E PHYs.
  24 +
  25  config FIXED_PHY
  26         bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
  27         depends on PHYLIB=y
  28 --- a/drivers/net/phy/Makefile
  29 +++ b/drivers/net/phy/Makefile
  30 @@ -39,6 +39,7 @@ obj-$(CONFIG_NATIONAL_PHY)    += national.o
  31  obj-$(CONFIG_DP83640_PHY)      += dp83640.o
  32  obj-$(CONFIG_STE10XP)          += ste10Xp.o
  33  obj-$(CONFIG_MICREL_PHY)       += micrel.o
  34 +obj-$(CONFIG_LANTIQ_PHY)        += lantiq.o
  35  obj-$(CONFIG_MDIO_OCTEON)      += mdio-octeon.o
  36  obj-$(CONFIG_MICREL_KS8995MA)  += spi_ks8995.o
  37  obj-$(CONFIG_AT803X_PHY)       += at803x.o
  38 --- /dev/null
  39 +++ b/drivers/net/phy/lantiq.c
  40 @@ -0,0 +1,220 @@
  41 +/*
  42 + *   This program is free software; you can redistribute it and/or modify
  43 + *   it under the terms of the GNU General Public License as published by
  44 + *   the Free Software Foundation; either version 2 of the License, or
  45 + *   (at your option) any later version.
  46 + *
  47 + *   This program is distributed in the hope that it will be useful,
  48 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  49 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  50 + *   GNU General Public License for more details.
  51 + *
  52 + *   You should have received a copy of the GNU General Public License
  53 + *   along with this program; if not, write to the Free Software
  54 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  55 + *
  56 + *   Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  57 + */
  58 +
  59 +#include <linux/module.h>
  60 +#include <linux/phy.h>
  61 +
  62 +#define MII_MMDCTRL            0x0d
  63 +#define MII_MMDDATA            0x0e
  64 +
  65 +#define MII_VR9_11G_IMASK      0x19    /* interrupt mask */
  66 +#define MII_VR9_11G_ISTAT      0x1a    /* interrupt status */
  67 +
  68 +#define INT_VR9_11G_WOL                BIT(15) /* Wake-On-LAN */
  69 +#define INT_VR9_11G_ANE                BIT(11) /* Auto-Neg error */
  70 +#define INT_VR9_11G_ANC                BIT(10) /* Auto-Neg complete */
  71 +#define INT_VR9_11G_ADSC       BIT(5)  /* Link auto-downspeed detect */
  72 +#define INT_VR9_11G_DXMC       BIT(2)  /* Duplex mode change */
  73 +#define INT_VR9_11G_LSPC       BIT(1)  /* Link speed change */
  74 +#define INT_VR9_11G_LSTC       BIT(0)  /* Link state change */
  75 +#define INT_VR9_11G_MASK       (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC)
  76 +
  77 +#define ADVERTISED_MPD         BIT(10) /* Multi-port device */
  78 +
  79 +#define MMD_DEVAD              0x1f
  80 +#define MMD_ACTYPE_SHIFT       14
  81 +#define MMD_ACTYPE_ADDRESS     (0 << MMD_ACTYPE_SHIFT)
  82 +#define MMD_ACTYPE_DATA                (1 << MMD_ACTYPE_SHIFT)
  83 +#define MMD_ACTYPE_DATA_PI     (2 << MMD_ACTYPE_SHIFT)
  84 +#define MMD_ACTYPE_DATA_PIWR   (3 << MMD_ACTYPE_SHIFT)
  85 +
  86 +static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev,
  87 +                                               u16 regnum)
  88 +{
  89 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
  90 +       phy_write(phydev, MII_MMDDATA, regnum);
  91 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
  92 +
  93 +       return phy_read(phydev, MII_MMDDATA);
  94 +}
  95 +
  96 +static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev,
  97 +                                               u16 regnum, u16 val)
  98 +{
  99 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
 100 +       phy_write(phydev, MII_MMDDATA, regnum);
 101 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
 102 +       phy_write(phydev, MII_MMDDATA, val);
 103 +
 104 +       return 0;
 105 +}
 106 +
 107 +static int vr9_gphy_config_init(struct phy_device *phydev)
 108 +{
 109 +       int err;
 110 +
 111 +       dev_dbg(&phydev->dev, "%s\n", __func__);
 112 +
 113 +       /* Mask all interrupts */
 114 +       err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
 115 +       if (err)
 116 +               return err;
 117 +
 118 +       /* Clear all pending interrupts */
 119 +       phy_read(phydev, MII_VR9_11G_ISTAT);
 120 +
 121 +       return 0;
 122 +}
 123 +
 124 +static int vr9_gphy_config_aneg(struct phy_device *phydev)
 125 +{
 126 +       int reg, err;
 127 +
 128 +       /* Advertise as multi-port device */
 129 +       reg = phy_read(phydev, MII_CTRL1000);
 130 +       reg |= ADVERTISED_MPD;
 131 +       err = phy_write(phydev, MII_CTRL1000, reg);
 132 +       if (err)
 133 +               return err;
 134 +
 135 +       return genphy_config_aneg(phydev);
 136 +}
 137 +
 138 +static int vr9_gphy_ack_interrupt(struct phy_device *phydev)
 139 +{
 140 +       int reg;
 141 +
 142 +       /*
 143 +        * Possible IRQ numbers:
 144 +        * - IM3_IRL18 for GPHY0
 145 +        * - IM3_IRL17 for GPHY1
 146 +        *
 147 +        * Due to a silicon bug IRQ lines are not really independent from
 148 +        * each other. Sometimes the two lines are driven at the same time
 149 +        * if only one GPHY core raises the interrupt.
 150 +        */
 151 +
 152 +       reg = phy_read(phydev, MII_VR9_11G_ISTAT);
 153 +
 154 +       return (reg < 0) ? reg : 0;
 155 +}
 156 +
 157 +static int vr9_gphy_did_interrupt(struct phy_device *phydev)
 158 +{
 159 +       int reg;
 160 +
 161 +       reg = phy_read(phydev, MII_VR9_11G_ISTAT);
 162 +
 163 +       return reg > 0;
 164 +}
 165 +
 166 +static int vr9_gphy_config_intr(struct phy_device *phydev)
 167 +{
 168 +       int err;
 169 +
 170 +       if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 171 +               err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK);
 172 +       else
 173 +               err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
 174 +
 175 +       return err;
 176 +}
 177 +
 178 +static struct phy_driver lantiq_phy[] = {
 179 +       {
 180 +               .phy_id         = 0xd565a400,
 181 +               .phy_id_mask    = 0xffffffff,
 182 +               .name           = "Lantiq XWAY PEF7071",
 183 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 184 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 185 +               .config_init    = vr9_gphy_config_init,
 186 +               .config_aneg    = vr9_gphy_config_aneg,
 187 +               .read_status    = genphy_read_status,
 188 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 189 +               .did_interrupt  = vr9_gphy_did_interrupt,
 190 +               .config_intr    = vr9_gphy_config_intr,
 191 +               .driver         = { .owner = THIS_MODULE },
 192 +       }, {
 193 +               .phy_id         = 0x030260D0,
 194 +               .phy_id_mask    = 0xfffffff0,
 195 +               .name           = "Lantiq XWAY VR9 GPHY 11G v1.3",
 196 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 197 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 198 +               .config_init    = vr9_gphy_config_init,
 199 +               .config_aneg    = vr9_gphy_config_aneg,
 200 +               .read_status    = genphy_read_status,
 201 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 202 +               .did_interrupt  = vr9_gphy_did_interrupt,
 203 +               .config_intr    = vr9_gphy_config_intr,
 204 +               .driver         = { .owner = THIS_MODULE },
 205 +       }, {
 206 +               .phy_id         = 0xd565a408,
 207 +               .phy_id_mask    = 0xfffffff8,
 208 +               .name           = "Lantiq XWAY VR9 GPHY 11G v1.4",
 209 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 210 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 211 +               .config_init    = vr9_gphy_config_init,
 212 +               .config_aneg    = vr9_gphy_config_aneg,
 213 +               .read_status    = genphy_read_status,
 214 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 215 +               .did_interrupt  = vr9_gphy_did_interrupt,
 216 +               .config_intr    = vr9_gphy_config_intr,
 217 +               .driver         = { .owner = THIS_MODULE },
 218 +       }, {
 219 +               .phy_id         = 0xd565a418,
 220 +               .phy_id_mask    = 0xfffffff8,
 221 +               .name           = "Lantiq XWAY XRX PHY22F v1.4",
 222 +               .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 223 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 224 +               .config_init    = vr9_gphy_config_init,
 225 +               .config_aneg    = vr9_gphy_config_aneg,
 226 +               .read_status    = genphy_read_status,
 227 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 228 +               .did_interrupt  = vr9_gphy_did_interrupt,
 229 +               .config_intr    = vr9_gphy_config_intr,
 230 +               .driver         = { .owner = THIS_MODULE },
 231 +       },
 232 +};
 233 +
 234 +static int __init ltq_phy_init(void)
 235 +{
 236 +       int i;
 237 +
 238 +       for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) {
 239 +               int err = phy_driver_register(&lantiq_phy[i]);
 240 +               if (err)
 241 +                       pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name);
 242 +       }
 243 +
 244 +       return 0;
 245 +}
 246 +
 247 +static void __exit ltq_phy_exit(void)
 248 +{
 249 +       int i;
 250 +
 251 +       for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++)
 252 +               phy_driver_unregister(&lantiq_phy[i]);
 253 +}
 254 +
 255 +module_init(ltq_phy_init);
 256 +module_exit(ltq_phy_exit);
 257 +
 258 +MODULE_DESCRIPTION("Lantiq PHY drivers");
 259 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
 260 +MODULE_LICENSE("GPL");