target/linux/lantiq/patches-3.2/0063-MIPS-lantiq-fixes-ar9-vr9-clock.patch

   1 From 449adc45e29be18da14b23e9ccd97ba5251ffcc9 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 17 Mar 2012 09:58:07 +0100
   4 Subject: [PATCH 63/70] MIPS: lantiq: fixes ar9/vr9 clock
   5
   6 ---
   7  arch/mips/lantiq/clk.h          |    4 +++-
   8  arch/mips/lantiq/xway/clk.c     |   29 ++++++++++++++++++++++++-----
   9  arch/mips/lantiq/xway/sysctrl.c |   13 ++++++++-----
  10  3 files changed, 35 insertions(+), 11 deletions(-)
  11
  12 diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
  13 index b34e675..010dfa7 100644
  14 --- a/arch/mips/lantiq/clk.h
  15 +++ b/arch/mips/lantiq/clk.h
  16 @@ -56,8 +56,10 @@ extern unsigned long ltq_danube_cpu_hz(void);
  17  extern unsigned long ltq_danube_fpi_hz(void);
  18  extern unsigned long ltq_danube_io_region_clock(void);
  19
  20 +extern unsigned long ltq_ar9_cpu_hz(void);
  21 +extern unsigned long ltq_ar9_fpi_hz(void);
  22 +
  23  extern unsigned long ltq_vr9_cpu_hz(void);
  24  extern unsigned long ltq_vr9_fpi_hz(void);
  25 -extern unsigned long ltq_vr9_io_region_clock(void);
  26
  27  #endif
  28 diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
  29 index 3635c9f..2bafc04 100644
  30 --- a/arch/mips/lantiq/xway/clk.c
  31 +++ b/arch/mips/lantiq/xway/clk.c
  32 @@ -217,6 +217,30 @@ unsigned long ltq_danube_cpu_hz(void)
  33         }
  34  }
  35
  36 +unsigned long ltq_ar9_sys_hz(void)
  37 +{
  38 +       if (((ltq_cgu_r32(LTQ_CGU_SYS) >> 3) & 0x3) == 0x2)
  39 +               return CLOCK_393M;
  40 +       return CLOCK_333M;
  41 +}
  42 +
  43 +unsigned long ltq_ar9_fpi_hz(void)
  44 +{
  45 +       unsigned long sys = ltq_ar9_sys_hz();
  46 +
  47 +       if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(0))
  48 +               return sys;
  49 +       return sys >> 1;
  50 +}
  51 +
  52 +unsigned long ltq_ar9_cpu_hz(void)
  53 +{
  54 +       if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(2))
  55 +               return ltq_ar9_fpi_hz();
  56 +       else
  57 +               return ltq_ar9_sys_hz();
  58 +}
  59 +
  60  unsigned long ltq_danube_fpi_hz(void)
  61  {
  62         unsigned long ddr_clock = DDR_HZ;
  63 @@ -299,11 +323,6 @@ unsigned long ltq_vr9_fpi_hz(void)
  64         return clk;
  65  }
  66
  67 -unsigned long ltq_vr9_io_region_clock(void)
  68 -{
  69 -       return ltq_vr9_fpi_hz();
  70 -}
  71 -
  72  unsigned long ltq_vr9_fpi_bus_clock(int fpi)
  73  {
  74         return ltq_vr9_fpi_hz();
  75 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
  76 index 9df048c..6771a7e 100644
  77 --- a/arch/mips/lantiq/xway/sysctrl.c
  78 +++ b/arch/mips/lantiq/xway/sysctrl.c
  79 @@ -237,6 +237,8 @@ void __init ltq_soc_init(void)
  80          clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU);
  81         if (!ltq_is_vr9())
  82                 clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
  83 +       if (!ltq_is_ase())
  84 +               clkdev_add_pci();
  85         if (ltq_is_ase()) {
  86                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
  87                         clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
  88 @@ -246,7 +248,7 @@ void __init ltq_soc_init(void)
  89                 clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
  90         } else if (ltq_is_vr9()) {
  91                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
  92 -                                       ltq_vr9_io_region_clock());
  93 +                       ltq_vr9_fpi_hz());
  94                 clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY);
  95                 clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK);
  96                 clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI);
  97 @@ -259,11 +261,12 @@ void __init ltq_soc_init(void)
  98                         PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
  99                         PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 100                         PMU_PPE_QSB);
 101 +       } else if (ltq_is_ar9()) {
 102 +               clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 103 +                       ltq_ar9_fpi_hz());
 104 +               clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
 105         } else {
 106                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 107 -                                       ltq_danube_io_region_clock());
 108 -               clkdev_add_pci();
 109 -               if (ltq_is_ar9())
 110 -                       clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
 111 +                       ltq_danube_io_region_clock());
 112         }
 113  }
 114 --
 115 1.7.7.1
 116