target/linux/lantiq/patches-3.2/0050-MIPS-adds-ifxhcd.patch

   1 From 09071b501014528984b158bc5408d8a738ef6883 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 11 Mar 2012 15:59:39 +0100
   4 Subject: [PATCH 50/70] MIPS: adds ifxhcd
   5
   6 ---
   7  arch/mips/lantiq/xway/Makefile      |    2 +-
   8  arch/mips/lantiq/xway/dev-ifxhcd.c  |   45 +
   9  arch/mips/lantiq/xway/dev-ifxhcd.h  |   17 +
  10  arch/mips/lantiq/xway/sysctrl.c     |    2 +
  11  drivers/usb/Kconfig                 |    2 +
  12  drivers/usb/Makefile                |    2 +
  13  drivers/usb/ifxhcd/Kconfig          |   58 +
  14  drivers/usb/ifxhcd/Makefile         |   85 +
  15  drivers/usb/ifxhcd/TagHistory       |  171 ++
  16  drivers/usb/ifxhcd/ifxhcd.c         | 2523 +++++++++++++++++++++++
  17  drivers/usb/ifxhcd/ifxhcd.h         |  628 ++++++
  18  drivers/usb/ifxhcd/ifxhcd_es.c      |  549 +++++
  19  drivers/usb/ifxhcd/ifxhcd_intr.c    | 3742 +++++++++++++++++++++++++++++++++++
  20  drivers/usb/ifxhcd/ifxhcd_queue.c   |  418 ++++
  21  drivers/usb/ifxhcd/ifxusb_cif.c     | 1458 ++++++++++++++
  22  drivers/usb/ifxhcd/ifxusb_cif.h     |  665 +++++++
  23  drivers/usb/ifxhcd/ifxusb_cif_d.c   |  458 +++++
  24  drivers/usb/ifxhcd/ifxusb_cif_h.c   |  846 ++++++++
  25  drivers/usb/ifxhcd/ifxusb_ctl.c     | 1385 +++++++++++++
  26  drivers/usb/ifxhcd/ifxusb_driver.c  |  970 +++++++++
  27  drivers/usb/ifxhcd/ifxusb_plat.h    | 1018 ++++++++++
  28  drivers/usb/ifxhcd/ifxusb_regs.h    | 1420 +++++++++++++
  29  drivers/usb/ifxhcd/ifxusb_version.h |    5 +
  30  23 files changed, 16468 insertions(+), 1 deletions(-)
  31  create mode 100644 arch/mips/lantiq/xway/dev-ifxhcd.c
  32  create mode 100644 arch/mips/lantiq/xway/dev-ifxhcd.h
  33  create mode 100644 drivers/usb/ifxhcd/Kconfig
  34  create mode 100644 drivers/usb/ifxhcd/Makefile
  35  create mode 100644 drivers/usb/ifxhcd/TagHistory
  36  create mode 100644 drivers/usb/ifxhcd/ifxhcd.c
  37  create mode 100644 drivers/usb/ifxhcd/ifxhcd.h
  38  create mode 100644 drivers/usb/ifxhcd/ifxhcd_es.c
  39  create mode 100644 drivers/usb/ifxhcd/ifxhcd_intr.c
  40  create mode 100644 drivers/usb/ifxhcd/ifxhcd_queue.c
  41  create mode 100644 drivers/usb/ifxhcd/ifxusb_cif.c
  42  create mode 100644 drivers/usb/ifxhcd/ifxusb_cif.h
  43  create mode 100644 drivers/usb/ifxhcd/ifxusb_cif_d.c
  44  create mode 100644 drivers/usb/ifxhcd/ifxusb_cif_h.c
  45  create mode 100644 drivers/usb/ifxhcd/ifxusb_ctl.c
  46  create mode 100644 drivers/usb/ifxhcd/ifxusb_driver.c
  47  create mode 100644 drivers/usb/ifxhcd/ifxusb_plat.h
  48  create mode 100644 drivers/usb/ifxhcd/ifxusb_regs.h
  49  create mode 100644 drivers/usb/ifxhcd/ifxusb_version.h
  50
  51 --- a/arch/mips/lantiq/xway/Makefile
  52 +++ b/arch/mips/lantiq/xway/Makefile
  53 @@ -1,4 +1,4 @@
  54 -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o
  55 +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o dev-ifxhcd.o
  56
  57  obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
  58  obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
  59 --- /dev/null
  60 +++ b/arch/mips/lantiq/xway/dev-ifxhcd.c
  61 @@ -0,0 +1,45 @@
  62 +/*
  63 + * This program is free software; you can redistribute it and/or modify
  64 + * it under the terms of the GNU General Public License as published by
  65 + * the Free Software Foundation; either version 2 of the License, or
  66 + * (at your option) any later version.
  67 + *
  68 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
  69 + */
  70 +
  71 +#include <linux/init.h>
  72 +#include <linux/module.h>
  73 +#include <linux/types.h>
  74 +#include <linux/string.h>
  75 +#include <linux/mtd/physmap.h>
  76 +#include <linux/kernel.h>
  77 +#include <linux/reboot.h>
  78 +#include <linux/platform_device.h>
  79 +#include <linux/leds.h>
  80 +#include <linux/etherdevice.h>
  81 +#include <linux/reboot.h>
  82 +#include <linux/time.h>
  83 +#include <linux/io.h>
  84 +#include <linux/gpio.h>
  85 +#include <linux/leds.h>
  86 +
  87 +#include <asm/bootinfo.h>
  88 +#include <asm/irq.h>
  89 +
  90 +#include <lantiq_soc.h>
  91 +#include <lantiq_irq.h>
  92 +#include <lantiq_platform.h>
  93 +
  94 +static u64 dmamask = (u32)0x1fffffff;
  95 +
  96 +static struct platform_device platform_dev = {
  97 +       .name = "ifxusb_hcd",
  98 +       .dev.dma_mask = &dmamask,
  99 +};
 100 +
 101 +int __init
 102 +xway_register_hcd(int *pins)
 103 +{
 104 +       platform_dev.dev.platform_data = pins;
 105 +       return platform_device_register(&platform_dev);
 106 +}
 107 --- /dev/null
 108 +++ b/arch/mips/lantiq/xway/dev-ifxhcd.h
 109 @@ -0,0 +1,17 @@
 110 +/*
 111 + * This program is free software; you can redistribute it and/or modify
 112 + * it under the terms of the GNU General Public License as published by
 113 + * the Free Software Foundation; either version 2 of the License, or
 114 + * (at your option) any later version.
 115 + *
 116 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
 117 + */
 118 +
 119 +#ifndef _LTQ_DEV_HCD_H__
 120 +#define _LTQ_DEV_HCD_H__
 121 +
 122 +#include <lantiq_platform.h>
 123 +
 124 +extern void __init xway_register_hcd(int *pin);
 125 +
 126 +#endif
 127 --- a/arch/mips/lantiq/xway/sysctrl.c
 128 +++ b/arch/mips/lantiq/xway/sysctrl.c
 129 @@ -166,6 +166,8 @@ void __init ltq_soc_init(void)
 130                 clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
 131                 clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
 132                 clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
 133 +               clkdev_add_pmu("usb0", NULL, 0, (1<<6) | 1);
 134 +               clkdev_add_pmu("usb1", NULL, 0, (1<<26) | (1<<27));
 135         } else {
 136                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 137                                         ltq_danube_io_region_clock());
 138 --- a/drivers/usb/Kconfig
 139 +++ b/drivers/usb/Kconfig
 140 @@ -183,4 +183,6 @@ source "drivers/usb/gadget/Kconfig"
 141
 142  source "drivers/usb/otg/Kconfig"
 143
 144 +source "drivers/usb/ifxhcd/Kconfig"
 145 +
 146  endif # USB_SUPPORT
 147 --- a/drivers/usb/Makefile
 148 +++ b/drivers/usb/Makefile
 149 @@ -57,3 +57,5 @@ obj-$(CONFIG_USB_OTG_UTILS)   += otg/
 150  obj-$(CONFIG_USB_GADGET)       += gadget/
 151
 152  obj-$(CONFIG_USB_COMMON)       += usb-common.o
 153 +
 154 +obj-$(CONFIG_USB_HOST_IFX)     += ifxhcd/
 155 --- /dev/null
 156 +++ b/drivers/usb/ifxhcd/Kconfig
 157 @@ -0,0 +1,58 @@
 158 +
 159 +config USB_HOST_IFX
 160 +       tristate "Infineon USB Host Controller Driver"
 161 +       depends on USB
 162 +       default n
 163 +       help
 164 +       Infineon USB Host Controller
 165 +
 166 +config USB_HOST_IFX_B
 167 +       bool "USB host mode on core 1 and 2"
 168 +       depends on USB_HOST_IFX
 169 +       help
 170 +       Both cores run as host
 171 +
 172 +#config USB_HOST_IFX_1
 173 +#config USB_HOST_IFX_2
 174 +
 175 +#config IFX_DANUBE
 176 +#config IFX_AMAZON_SE
 177 +config IFX_AR9
 178 +       depends on USB_HOST_IFX
 179 +       bool "AR9"
 180 +
 181 +config IFX_VR9
 182 +       depends on USB_HOST_IFX
 183 +       bool "VR9"
 184 +
 185 +#config USB_HOST_IFX_FORCE_USB11
 186 +#      bool "Forced USB1.1"
 187 +#      depends on USB_HOST_IFX
 188 +#      default n
 189 +#      help
 190 +#      force to be USB 1.1
 191 +
 192 +#config USB_HOST_IFX_WITH_HS_ELECT_TST
 193 +#      bool "With HS_Electrical Test"
 194 +#      depends on USB_HOST_IFX
 195 +#      default n
 196 +#      help
 197 +#      With USBIF HSET routines
 198 +
 199 +#config USB_HOST_IFX_WITH_ISO
 200 +#      bool "With ISO transfer"
 201 +#      depends on USB_HOST_IFX
 202 +#      default n
 203 +#      help
 204 +#      With USBIF ISO transfer
 205 +
 206 +config USB_HOST_IFX_UNALIGNED_ADJ
 207 +       bool "Adjust"
 208 +       depends on USB_HOST_IFX
 209 +       help
 210 +       USB_HOST_IFX_UNALIGNED_ADJ
 211 +
 212 +#config USB_HOST_IFX_UNALIGNED_CHK
 213 +#config USB_HOST_IFX_UNALIGNED_NONE
 214 +
 215 +
 216 --- /dev/null
 217 +++ b/drivers/usb/ifxhcd/Makefile
 218 @@ -0,0 +1,85 @@
 219 +
 220 +#
 221 +# Makefile for USB Core files and filesystem
 222 +#
 223 +       ifxusb_host-objs    := ifxusb_driver.o
 224 +       ifxusb_host-objs    += ifxusb_ctl.o
 225 +       ifxusb_host-objs    += ifxusb_cif.o
 226 +       ifxusb_host-objs    += ifxusb_cif_h.o
 227 +       ifxusb_host-objs    += ifxhcd.o
 228 +       ifxusb_host-objs    += ifxhcd_es.o
 229 +       ifxusb_host-objs    += ifxhcd_intr.o
 230 +       ifxusb_host-objs    += ifxhcd_queue.o
 231 +
 232 +ifeq ($(CONFIG_IFX_TWINPASS),y)
 233 +        EXTRA_CFLAGS        += -D__IS_TWINPASS__
 234 +endif
 235 +ifeq ($(CONFIG_IFX_DANUBE),y)
 236 +        EXTRA_CFLAGS        += -D__IS_DANUBE__
 237 +endif
 238 +ifeq ($(CONFIG_IFX_AMAZON_SE),y)
 239 +        EXTRA_CFLAGS        += -D__IS_AMAZON_SE__
 240 +endif
 241 +ifeq ($(CONFIG_IFX_AR9),y)
 242 +        EXTRA_CFLAGS        += -D__IS_AR9__
 243 +endif
 244 +ifeq ($(CONFIG_IFX_AMAZON_S),y)
 245 +        EXTRA_CFLAGS        += -D__IS_AR9__
 246 +endif
 247 +ifeq ($(CONFIG_IFX_VR9),y)
 248 +        EXTRA_CFLAGS        += -D__IS_VR9__
 249 +endif
 250 +
 251 +ifeq ($(CONFIG_USB_HOST_IFX),y)
 252 +       EXTRA_CFLAGS  += -Dlinux -D__LINUX__
 253 +       EXTRA_CFLAGS  += -D__IS_HOST__
 254 +       EXTRA_CFLAGS  += -D__KERNEL__
 255 +endif
 256 +
 257 +ifeq ($(CONFIG_USB_HOST_IFX),m)
 258 +       EXTRA_CFLAGS  += -Dlinux -D__LINUX__
 259 +       EXTRA_CFLAGS  += -D__IS_HOST__
 260 +       EXTRA_CFLAGS  += -D__KERNEL__
 261 +endif
 262 +
 263 +ifeq ($(CONFIG_USB_DEBUG),y)
 264 +       EXTRA_CFLAGS  += -D__DEBUG__
 265 +       EXTRA_CFLAGS  += -D__ENABLE_DUMP__
 266 +endif
 267 +
 268 +ifeq ($(CONFIG_USB_HOST_IFX_B),y)
 269 +        EXTRA_CFLAGS  += -D__IS_DUAL__
 270 +endif
 271 +ifeq ($(CONFIG_USB_HOST_IFX_1),y)
 272 +        EXTRA_CFLAGS  += -D__IS_FIRST__
 273 +endif
 274 +ifeq ($(CONFIG_USB_HOST_IFX_2),y)
 275 +        EXTRA_CFLAGS  += -D__IS_SECOND__
 276 +endif
 277 +
 278 +ifeq ($(CONFIG_USB_HOST_IFX_FORCE_USB11),y)
 279 +       EXTRA_CFLAGS  += -D__FORCE_USB11__
 280 +endif
 281 +ifeq ($(CONFIG_USB_HOST_IFX_WITH_HS_ELECT_TST),y)
 282 +       EXTRA_CFLAGS  += -D__WITH_HS_ELECT_TST__
 283 +endif
 284 +ifeq ($(CONFIG_USB_HOST_IFX_WITH_ISO),y)
 285 +       EXTRA_CFLAGS  += -D__EN_ISOC__
 286 +endif
 287 +ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_ADJ),y)
 288 +       EXTRA_CFLAGS  += -D__UNALIGNED_BUFFER_ADJ__
 289 +endif
 290 +ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_CHK),y)
 291 +       EXTRA_CFLAGS  += -D__UNALIGNED_BUFFER_CHK__
 292 +endif
 293 +
 294 +#      EXTRA_CFLAGS  += -D__DYN_SOF_INTR__
 295 +       EXTRA_CFLAGS  += -D__UEIP__
 296 +#      EXTRA_CFLAGS  += -D__EN_ISOC__
 297 +#      EXTRA_CFLAGS  += -D__EN_ISOC_SPLIT__
 298 +
 299 +## 20110628 AVM/WK New flag for less SOF IRQs
 300 +       EXTRA_CFLAGS  += -D__USE_TIMER_4_SOF__
 301 +
 302 +obj-$(CONFIG_USB_HOST_IFX)     += ifxusb_host.o
 303 +
 304 --- /dev/null
 305 +++ b/drivers/usb/ifxhcd/TagHistory
 306 @@ -0,0 +1,171 @@
 307 +
 308 +
 309 ++----------------------------------------------------------------------+
 310 +| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.18-r240-non_musb_ar9_vr9-SOF_Timer_Fixed
 311 +| Erzeugt mit SVN-Tagger Version 3.74.
 312 ++----------------------------------------------------------------------+
 313 +FIX - Korrektur bei der SOF-Timer/IRQ Steuerung. (Bug in Tag 5.17)
 314 +FIX - Fehlerbehandlung an mehreren Stellen korrigiert bzw. eingebaut.
 315 +
 316 +
 317 +
 318 ++----------------------------------------------------------------------+
 319 +| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.17-r237-non_musb_ar9_vr9-2_6_32_41_Kompatibel
 320 +| Erzeugt mit SVN-Tagger Version 3.73.
 321 ++----------------------------------------------------------------------+
 322 +FIX - Kompatiblität zum Update auf Kernel 2.6.32-41. Weiterhin für 28er geeignet.
 323 +ENH - Reduktion der Interrruptlast durch Nutzung eines hrtimers anstatt SOF-IRQ.
 324 +
 325 +
 326 +
 327 ++----------------------------------------------------------------------+
 328 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.16-r208-non_musb_ar9_vr9-20110421_Zero_Paket_Optimiert
 329 +| Erzeugt mit SVN-Tagger Version 3.66.
 330 ++----------------------------------------------------------------------+
 331 +
 332 +FIX - VR9 / AR9 - Zero Packet. Optimierung korrigiert.
 333 +
 334 +
 335 +
 336 ++----------------------------------------------------------------------+
 337 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.15-r205-non_musb_ar9_vr9-20110421_Zero_Paket_WA_funktioniert
 338 +| Erzeugt mit SVN-Tagger Version 3.66.
 339 ++----------------------------------------------------------------------+
 340 +
 341 +FIX - VR9 / AR9 - "Zero Packet" funktioniert nun wirklich. Letzter Tag hatte einen Bug.
 342 +
 343 +
 344 +
 345 ++----------------------------------------------------------------------+
 346 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.14-r202-non_musb_ar9_vr9-20110420_Zero_Paket_WA
 347 +| Erzeugt mit SVN-Tagger Version 3.66.
 348 ++----------------------------------------------------------------------+
 349 +
 350 +FIX - VR9 / AR9 - Zero Packet Workaround: ZLP wird nun geschickt wenn URB_ZERO_PACKET aktiv ist.
 351 +                  Wird von LTE Altair Firmware benoetig.
 352 +
 353 +
 354 +
 355 ++----------------------------------------------------------------------+
 356 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.13-r199-non_musb_ar9_vr9-20110310_Init_Fix
 357 +| Erzeugt mit SVN-Tagger Version 3.64.
 358 ++----------------------------------------------------------------------+
 359 +
 360 +FIX - VR9 / AR9 - Timing der Initialisierungsphase angepasst zum Kernel 2.6.28 mit UGW-4.3.1.
 361 +
 362 +
 363 +
 364 ++----------------------------------------------------------------------+
 365 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.12-r184-non_musb_ar9_vr9-20110118_Full_Speed_Fix
 366 +| Erzeugt mit SVN-Tagger Version 3.58.
 367 ++----------------------------------------------------------------------+
 368 +AR9/VR9 (3370,6840,7320):
 369 +Makefile - FIX - (Workaround) Debug Modus hilft gegen Enumerationsfehler bei Full Speed Drucker.
 370 +
 371 +
 372 +
 373 ++----------------------------------------------------------------------+
 374 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.11-r175-non_musb_ar9_vr9-20101220_VR9_2_Ports_DMA_Fix
 375 +| Erzeugt mit SVN-Tagger Version 3.58.
 376 ++----------------------------------------------------------------------+
 377 +
 378 +FIX - VR9 - Workaround DMA Burst Size. Wenn beiden USB Ports benutzt werden, geht der USB Host nicht mehr.
 379 +
 380 +
 381 +
 382 ++----------------------------------------------------------------------+
 383 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.10-r169-non_musb_ar9_vr9-Fix_Spontan_Reboot
 384 +| Erzeugt mit SVN-Tagger Version 3.58.
 385 ++----------------------------------------------------------------------+
 386 +
 387 +FIX - Endlosschleife führte zu einem spontanen Reboot.
 388 +
 389 +
 390 +
 391 ++----------------------------------------------------------------------+
 392 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.9-r166-non_musb_ar9_vr9-20101112_deferred_completion
 393 +| Erzeugt mit SVN-Tagger Version 3.58.
 394 ++----------------------------------------------------------------------+
 395 +
 396 +ENH - Deferred URB Completion Mechanismus eingebaut. Nun ca. 10% schneller bei usb-storage.
 397 +
 398 +FIX - PING Flow Control gefixt.
 399 +FIX - Channel Halt wird nun immer angerufen. (Split Transaction wurde nicht erfolgreich gestoppt).
 400 +FIX - Spinlock Benutzung verbessert. Mehr Stabilitaet.
 401 +
 402 +CHG - Ubersetztungsoption __DEBUG__ ist nun abhaengig von CONFIG_USB_DEBUG
 403 +
 404 +
 405 +
 406 ++----------------------------------------------------------------------+
 407 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.8-r149-non_musb_ar9_vr9-20100827_LTE_Interrupt_EP_Fix
 408 +| Erzeugt mit SVN-Tagger Version 3.57.
 409 ++----------------------------------------------------------------------+
 410 +AR9/VR9 - FIX - Interrupt Packets gingen verloren, wegen falschem Timing beim OddFrame Bit.
 411 +
 412 +
 413 +
 414 ++----------------------------------------------------------------------+
 415 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.7-r142-non_musb_ar9_vr9-20100728_Unaligned_Buf_Fix
 416 +| Erzeugt mit SVN-Tagger Version 3.57.
 417 ++----------------------------------------------------------------------+
 418 +FIX - "Unaligned Data" Flag wieder nach Transfer geloescht.
 419 +
 420 +
 421 +
 422 ++----------------------------------------------------------------------+
 423 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.6-r133-non_musb_ar9_vr9-20100714_Toggle_Datenverlust_Fix
 424 +| Erzeugt mit SVN-Tagger Version 3.57.
 425 ++----------------------------------------------------------------------+
 426 +TL5508 - Einige UMTS Modems funktionierten nicht korrekt an der 7320 (AR9).
 427 +FIX - USB Data Toggle des usbcore benutzen. Datenverlust nach EP-Halt.
 428 +
 429 +
 430 +
 431 ++----------------------------------------------------------------------+
 432 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.5-r130-non_musb_ar9_vr9-20100712_USB_Ports_abschaltbar
 433 +| Erzeugt mit SVN-Tagger Version 3.57.
 434 ++----------------------------------------------------------------------+
 435 +Power - Fix - Beide USB Port abschaltbar bei rmmod.
 436 +rmmod - FIX - URB_Dequeue funktionierte beim Entladen des Treibers nicht (mehrere Ursachen).
 437 +
 438 +
 439 +
 440 ++----------------------------------------------------------------------+
 441 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.4-r126-non_musb_ar9_vr9-20100701_Lost_Interrupt_Workaround
 442 +| Erzeugt mit SVN-Tagger Version 3.57.
 443 ++----------------------------------------------------------------------+
 444 +FIX - Workaround wegen verpasstem Interrupt, bei Full-Speed Interrupt EP.
 445 +
 446 +
 447 ++----------------------------------------------------------------------+
 448 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.3-r123-non_musb_ar9_vr9-20100630_UMTS_Fixes
 449 +| Erzeugt mit SVN-Tagger Version 3.57.
 450 ++----------------------------------------------------------------------+
 451 +FIX - Full-Speed Interrupt Endpoint hinter Hi-Speed Hub funktioniert nun (UMTS Modems)
 452 +FIX - usb_hcd_link_urb_from_ep API von USBCore muss benutzt werden.
 453 +FIX - Interrupt URBs nicht bei NAK completen.
 454 +
 455 +
 456 ++----------------------------------------------------------------------+
 457 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.2-r114-non_musb_ar9_vr9-20100520_StickAndSurf_funktioniert
 458 +| Erzeugt mit SVN-Tagger Version 3.56.
 459 ++----------------------------------------------------------------------+
 460 +- Merge mit neuen LANTIQ Sourcen "3.0alpha B100312"
 461 +- Fix - Spin_lock eingebaut, Stick&Surf funktioniert nun
 462 +
 463 +- DEP - CONFIG_USB_HOST_IFX_WITH_ISO wird nicht unterstuetzt: In der Kernel Config deaktivieren.
 464 +
 465 +
 466 +
 467 ++----------------------------------------------------------------------+
 468 +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.1-r107-non_musb_ar9_vr9-20100505_IFXUSB_Host_mit_Energiemonitor
 469 +| Erzeugt mit SVN-Tagger Version 3.56.
 470 ++----------------------------------------------------------------------+
 471 +USB Host Treiber für AR9 und VR9
 472 +--------------------------------
 473 +FIX - Toggle Error nach STALL - Einfacher Workaround - Nun werden Massenspeicherpartitionen erkannt!
 474 +AVM_POWERMETER - USB Energiemonitor Support.
 475 +
 476 +Bekanntes Problem: Stick and Surf funktioniert nur sporadisch, weil CONTROL_IRQ manchmal ausbleibt.
 477 +
 478 --- /dev/null
 479 +++ b/drivers/usb/ifxhcd/ifxhcd.c
 480 @@ -0,0 +1,2523 @@
 481 +/*****************************************************************************
 482 + **   FILE NAME       : ifxhcd.c
 483 + **   PROJECT         : IFX USB sub-system V3
 484 + **   MODULES         : IFX USB sub-system Host and Device driver
 485 + **   SRC VERSION     : 1.0
 486 + **   DATE            : 1/Jan/2009
 487 + **   AUTHOR          : Chen, Howard
 488 + **   DESCRIPTION     : This file contains the structures, constants, and interfaces for
 489 + **                     the Host Contoller Driver (HCD).
 490 + **
 491 + **                     The Host Controller Driver (HCD) is responsible for translating requests
 492 + **                     from the USB Driver into the appropriate actions on the IFXUSB controller.
 493 + **                     It isolates the USBD from the specifics of the controller by providing an
 494 + **                     API to the USBD.
 495 + *****************************************************************************/
 496 +
 497 +/*!
 498 +  \file ifxhcd.c
 499 +  \ingroup IFXUSB_DRIVER_V3
 500 +  \brief This file contains the implementation of the HCD. In Linux,
 501 +   the HCD implements the hc_driver API.
 502 +*/
 503 +
 504 +#include <linux/version.h>
 505 +#include "ifxusb_version.h"
 506 +
 507 +#include <linux/kernel.h>
 508 +#include <linux/module.h>
 509 +#include <linux/moduleparam.h>
 510 +#include <linux/init.h>
 511 +
 512 +#include <linux/device.h>
 513 +
 514 +#include <linux/errno.h>
 515 +#include <linux/list.h>
 516 +#include <linux/interrupt.h>
 517 +#include <linux/string.h>
 518 +
 519 +#include <linux/dma-mapping.h>
 520 +
 521 +
 522 +#include "ifxusb_plat.h"
 523 +#include "ifxusb_regs.h"
 524 +#include "ifxusb_cif.h"
 525 +#include "ifxhcd.h"
 526 +
 527 +#include <asm/irq.h>
 528 +
 529 +#ifdef CONFIG_AVM_POWERMETER
 530 +#include <linux/avm_power.h>
 531 +#endif /*--- #ifdef CONFIG_AVM_POWERMETER ---*/
 532 +
 533 +#ifdef __DEBUG__
 534 +       static void dump_urb_info(struct urb *_urb, char* _fn_name);
 535 +       static void dump_channel_info(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
 536 +#endif
 537 +
 538 +
 539 +/*!
 540 + \brief Sets the final status of an URB and returns it to the device driver. Any
 541 +  required cleanup of the URB is performed.
 542 + */
 543 +void ifxhcd_complete_urb(ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd,  int _status)
 544 +{
 545 +       struct urb *urb=NULL;
 546 +       unsigned long flags = 0;
 547 +
 548 +       /*== AVM/BC 20101111 Function called with Lock ==*/
 549 +       //SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
 550 +
 551 +       if (!list_empty(&_urbd->urbd_list_entry))
 552 +               list_del_init (&_urbd->urbd_list_entry);
 553 +
 554 +       if(!_urbd->urb)
 555 +       {
 556 +               IFX_ERROR("%s: invalid urb\n",__func__);
 557 +               /*== AVM/BC 20101111 Function called with Lock ==*/
 558 +               //SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
 559 +               return;
 560 +       }
 561 +
 562 +       urb=_urbd->urb;
 563 +
 564 +       #ifdef __DEBUG__
 565 +               if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB))
 566 +               {
 567 +                       IFX_PRINT("%s: _urbd %p, urb %p, device %d, ep %d %s/%s, status=%d\n",
 568 +                                 __func__, _urbd,_urbd->urb, usb_pipedevice(_urbd->urb->pipe),
 569 +                                 usb_pipeendpoint(_urbd->urb->pipe),
 570 +                                 usb_pipein(_urbd->urb->pipe) ? "IN" : "OUT",
 571 +                                 (_urbd->is_in) ? "IN" : "OUT",
 572 +                                  _status);
 573 +                       if (_urbd->epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
 574 +                       {
 575 +                               int i;
 576 +                               for (i = 0; i < _urbd->urb->number_of_packets; i++)
 577 +                                       IFX_PRINT("  ISO Desc %d status: %d\n", i, _urbd->urb->iso_frame_desc[i].status);
 578 +                       }
 579 +               }
 580 +       #endif
 581 +
 582 +       if (!_urbd->epqh)
 583 +               IFX_ERROR("%s: invalid epqd\n",__func__);
 584 +
 585 +       #if   defined(__UNALIGNED_BUFFER_ADJ__)
 586 +               else if(_urbd->is_active)
 587 +               {
 588 +                       if( _urbd->epqh->aligned_checked   &&
 589 +                           _urbd->epqh->using_aligned_buf &&
 590 +                           _urbd->xfer_buff &&
 591 +                           _urbd->is_in )
 592 +                               memcpy(_urbd->xfer_buff,_urbd->epqh->aligned_buf,_urbd->xfer_len);
 593 +                       _urbd->epqh->using_aligned_buf=0;
 594 +                       _urbd->epqh->using_aligned_setup=0;
 595 +                       _urbd->epqh->aligned_checked=0;
 596 +               }
 597 +       #endif
 598 +
 599 +       urb->status = _status;
 600 +       urb->hcpriv=NULL;
 601 +       kfree(_urbd);
 602 +
 603 +       usb_hcd_unlink_urb_from_ep(ifxhcd_to_syshcd(_ifxhcd), urb);
 604 +       SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
 605 +
 606 +//    usb_hcd_giveback_urb(ifxhcd_to_syshcd(_ifxhcd), urb);
 607 +    usb_hcd_giveback_urb(ifxhcd_to_syshcd(_ifxhcd), urb, _status);
 608 +
 609 +    /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/
 610 +       SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
 611 +}
 612 +
 613 +/*== AVM/BC 20101111 URB Complete deferred
 614 + * Must be called with Spinlock
 615 + */
 616 +
 617 +/*!
 618 + \brief Inserts an urbd structur in the completion list. The urbd will be
 619 +  later completed by select_eps_sub
 620 + */
 621 +void defer_ifxhcd_complete_urb(ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd,  int _status)
 622 +{
 623 +
 624 +       _urbd->status = _status;
 625 +
 626 +       //Unlink Urbd from epqh / Insert it into the complete list
 627 +       list_move_tail(&_urbd->urbd_list_entry, &_ifxhcd->urbd_complete_list);
 628 +
 629 +}
 630 +
 631 +/*!
 632 + \brief Processes all the URBs in a single EPQHs. Completes them with
 633 +        status and frees the URBD.
 634 + */
 635 +//static
 636 +void kill_all_urbs_in_epqh(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh, int _status)
 637 +{
 638 +       struct list_head *urbd_item;
 639 +       ifxhcd_urbd_t    *urbd;
 640 +
 641 +       if(!_epqh)
 642 +               return;
 643 +
 644 +       for (urbd_item  =  _epqh->urbd_list.next;
 645 +            urbd_item != &_epqh->urbd_list;
 646 +            urbd_item  =  _epqh->urbd_list.next)
 647 +       {
 648 +               urbd = list_entry(urbd_item, ifxhcd_urbd_t, urbd_list_entry);
 649 +               ifxhcd_complete_urb(_ifxhcd, urbd, _status);
 650 +       }
 651 +}
 652 +
 653 +
 654 +/*!
 655 + \brief Free all EPS in one Processes all the URBs in a single list of EPQHs. Completes them with
 656 +        -ETIMEDOUT and frees the URBD.
 657 + */
 658 +//static
 659 +void epqh_list_free(ifxhcd_hcd_t *_ifxhcd, struct list_head *_epqh_list)
 660 +{
 661 +               struct list_head *item;
 662 +               ifxhcd_epqh_t    *epqh;
 663 +
 664 +               if (!_epqh_list)
 665 +                       return;
 666 +               if (_epqh_list->next == NULL) /* The list hasn't been initialized yet. */
 667 +                       return;
 668 +
 669 +       /* Ensure there are no URBDs or URBs left. */
 670 +       for (item = _epqh_list->next; item != _epqh_list; item = _epqh_list->next)
 671 +       {
 672 +               epqh = list_entry(item, ifxhcd_epqh_t, epqh_list_entry);
 673 +               kill_all_urbs_in_epqh(_ifxhcd, epqh, -ETIMEDOUT);
 674 +               ifxhcd_epqh_free(epqh);
 675 +       }
 676 +}
 677 +
 678 +
 679 +
 680 +//static
 681 +void epqh_list_free_all(ifxhcd_hcd_t *_ifxhcd)
 682 +{
 683 +       unsigned long flags;
 684 +
 685 +       /*== AVM/BC 20101111 - 2.6.28 Needs Spinlock ==*/
 686 +       SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
 687 +
 688 +       epqh_list_free(_ifxhcd, &_ifxhcd->epqh_np_active   );
 689 +       epqh_list_free(_ifxhcd, &_ifxhcd->epqh_np_ready    );
 690 +       epqh_list_free(_ifxhcd, &_ifxhcd->epqh_intr_active );
 691 +       epqh_list_free(_ifxhcd, &_ifxhcd->epqh_intr_ready  );
 692 +       #ifdef __EN_ISOC__
 693 +               epqh_list_free(_ifxhcd, &_ifxhcd->epqh_isoc_active );
 694 +               epqh_list_free(_ifxhcd, &_ifxhcd->epqh_isoc_ready  );
 695 +       #endif
 696 +       epqh_list_free(_ifxhcd, &_ifxhcd->epqh_stdby       );
 697 +
 698 +       SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
 699 +
 700 +}
 701 +
 702 +
 703 +/*!
 704 +   \brief This function is called to handle the disconnection of host port.
 705 + */
 706 +int32_t ifxhcd_disconnect(ifxhcd_hcd_t *_ifxhcd)
 707 +{
 708 +       IFX_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _ifxhcd);
 709 +
 710 +       /* Set status flags for the hub driver. */
 711 +       _ifxhcd->flags.b.port_connect_status_change = 1;
 712 +       _ifxhcd->flags.b.port_connect_status = 0;
 713 +
 714 +       /*
 715 +        * Shutdown any transfers in process by clearing the Tx FIFO Empty
 716 +        * interrupt mask and status bits and disabling subsequent host
 717 +        * channel interrupts.
 718 +        */
 719 +        {
 720 +               gint_data_t intr = { .d32 = 0 };
 721 +               intr.b.nptxfempty = 1;
 722 +               intr.b.ptxfempty  = 1;
 723 +               intr.b.hcintr     = 1;
 724 +               ifxusb_mreg (&_ifxhcd->core_if.core_global_regs->gintmsk, intr.d32, 0);
 725 +               ifxusb_mreg (&_ifxhcd->core_if.core_global_regs->gintsts, intr.d32, 0);
 726 +       }
 727 +
 728 +       /* Respond with an error status to all URBs in the schedule. */
 729 +       epqh_list_free_all(_ifxhcd);
 730 +
 731 +       /* Clean up any host channels that were in use. */
 732 +       {
 733 +               int               num_channels;
 734 +               ifxhcd_hc_t      *channel;
 735 +               ifxusb_hc_regs_t *hc_regs;
 736 +               hcchar_data_t     hcchar;
 737 +               int                   i;
 738 +
 739 +               num_channels = _ifxhcd->core_if.params.host_channels;
 740 +
 741 +               for (i = 0; i < num_channels; i++)
 742 +               {
 743 +                       channel = &_ifxhcd->ifxhc[i];
 744 +                       if (list_empty(&channel->hc_list_entry))
 745 +                       {
 746 +                               hc_regs = _ifxhcd->core_if.hc_regs[i];
 747 +                               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
 748 +                               if (hcchar.b.chen)
 749 +                               {
 750 +                                       /* Halt the channel. */
 751 +                                       hcchar.b.chdis = 1;
 752 +                                       ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
 753 +                               }
 754 +                               list_add_tail(&channel->hc_list_entry, &_ifxhcd->free_hc_list);
 755 +                               ifxhcd_hc_cleanup(&_ifxhcd->core_if, channel);
 756 +                       }
 757 +               }
 758 +       }
 759 +       return 1;
 760 +}
 761 +
 762 +
 763 +/*!
 764 +   \brief Frees secondary storage associated with the ifxhcd_hcd structure contained
 765 +          in the struct usb_hcd field.
 766 + */
 767 +static void ifxhcd_freeextra(struct usb_hcd *_syshcd)
 768 +{
 769 +       ifxhcd_hcd_t    *ifxhcd = syshcd_to_ifxhcd(_syshcd);
 770 +
 771 +       IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD FREE\n");
 772 +
 773 +       /* Free memory for EPQH/URBD lists */
 774 +       epqh_list_free_all(ifxhcd);
 775 +
 776 +       /* Free memory for the host channels. */
 777 +       ifxusb_free_buf(ifxhcd->status_buf);
 778 +       return;
 779 +}
 780 +#ifdef __USE_TIMER_4_SOF__
 781 +static enum hrtimer_restart ifxhcd_timer_func(struct hrtimer *timer) {
 782 +       ifxhcd_hcd_t    *ifxhcd = container_of(timer, ifxhcd_hcd_t, hr_timer);
 783 +
 784 +       ifxhcd_handle_intr(ifxhcd);
 785 +
 786 +    return HRTIMER_NORESTART;
 787 +}
 788 +#endif
 789 +
 790 +/*!
 791 +   \brief Initializes the HCD. This function allocates memory for and initializes the
 792 +  static parts of the usb_hcd and ifxhcd_hcd structures. It also registers the
 793 +  USB bus with the core and calls the hc_driver->start() function. It returns
 794 +  a negative error on failure.
 795 + */
 796 +int ifxhcd_init(ifxhcd_hcd_t *_ifxhcd)
 797 +{
 798 +       int retval = 0;
 799 +       struct usb_hcd *syshcd = NULL;
 800 +
 801 +       IFX_DEBUGPL(DBG_HCD, "IFX USB HCD INIT\n");
 802 +
 803 +       spin_lock_init(&_ifxhcd->lock);
 804 +#ifdef __USE_TIMER_4_SOF__
 805 +       hrtimer_init(&_ifxhcd->hr_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 806 +       _ifxhcd->hr_timer.function = ifxhcd_timer_func;
 807 +#endif
 808 +       _ifxhcd->hc_driver.description      = _ifxhcd->core_if.core_name;
 809 +       _ifxhcd->hc_driver.product_desc     = "IFX USB Controller";
 810 +       //_ifxhcd->hc_driver.hcd_priv_size    = sizeof(ifxhcd_hcd_t);
 811 +       _ifxhcd->hc_driver.hcd_priv_size    = sizeof(unsigned long);
 812 +       _ifxhcd->hc_driver.irq              = ifxhcd_irq;
 813 +       _ifxhcd->hc_driver.flags            = HCD_MEMORY | HCD_USB2;
 814 +       _ifxhcd->hc_driver.start            = ifxhcd_start;
 815 +       _ifxhcd->hc_driver.stop             = ifxhcd_stop;
 816 +       //_ifxhcd->hc_driver.reset          =
 817 +       //_ifxhcd->hc_driver.suspend        =
 818 +       //_ifxhcd->hc_driver.resume         =
 819 +       _ifxhcd->hc_driver.urb_enqueue      = ifxhcd_urb_enqueue;
 820 +       _ifxhcd->hc_driver.urb_dequeue      = ifxhcd_urb_dequeue;
 821 +       _ifxhcd->hc_driver.endpoint_disable = ifxhcd_endpoint_disable;
 822 +       _ifxhcd->hc_driver.get_frame_number = ifxhcd_get_frame_number;
 823 +       _ifxhcd->hc_driver.hub_status_data  = ifxhcd_hub_status_data;
 824 +       _ifxhcd->hc_driver.hub_control      = ifxhcd_hub_control;
 825 +       //_ifxhcd->hc_driver.hub_suspend    =
 826 +       //_ifxhcd->hc_driver.hub_resume     =
 827 +
 828 +       /* Allocate memory for and initialize the base HCD and  */
 829 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
 830 +       syshcd = usb_create_hcd(&_ifxhcd->hc_driver, _ifxhcd->dev, _ifxhcd->core_if.core_name);
 831 +#else
 832 +       syshcd = usb_create_hcd(&_ifxhcd->hc_driver, _ifxhcd->dev, _ifxhcd->dev->bus_id);
 833 +#endif
 834 +
 835 +       if (syshcd == NULL)
 836 +       {
 837 +               retval = -ENOMEM;
 838 +               goto error1;
 839 +       }
 840 +
 841 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
 842 +       syshcd->has_tt = 1;
 843 +#endif
 844 +
 845 +       syshcd->rsrc_start = (unsigned long)_ifxhcd->core_if.core_global_regs;
 846 +       syshcd->regs       = (void *)_ifxhcd->core_if.core_global_regs;
 847 +       syshcd->self.otg_port = 0;
 848 +
 849 +       //*((unsigned long *)(&(syshcd->hcd_priv)))=(unsigned long)_ifxhcd;
 850 +       //*((unsigned long *)(&(syshcd->hcd_priv[0])))=(unsigned long)_ifxhcd;
 851 +       syshcd->hcd_priv[0]=(unsigned long)_ifxhcd;
 852 +       _ifxhcd->syshcd=syshcd;
 853 +
 854 +       INIT_LIST_HEAD(&_ifxhcd->epqh_np_active   );
 855 +       INIT_LIST_HEAD(&_ifxhcd->epqh_np_ready    );
 856 +       INIT_LIST_HEAD(&_ifxhcd->epqh_intr_active );
 857 +       INIT_LIST_HEAD(&_ifxhcd->epqh_intr_ready  );
 858 +       #ifdef __EN_ISOC__
 859 +               INIT_LIST_HEAD(&_ifxhcd->epqh_isoc_active );
 860 +               INIT_LIST_HEAD(&_ifxhcd->epqh_isoc_ready  );
 861 +       #endif
 862 +       INIT_LIST_HEAD(&_ifxhcd->epqh_stdby       );
 863 +       INIT_LIST_HEAD(&_ifxhcd->urbd_complete_list);
 864 +
 865 +       /*
 866 +        * Create a host channel descriptor for each host channel implemented
 867 +        * in the controller. Initialize the channel descriptor array.
 868 +        */
 869 +       INIT_LIST_HEAD(&_ifxhcd->free_hc_list);
 870 +       {
 871 +               int          num_channels = _ifxhcd->core_if.params.host_channels;
 872 +               int i;
 873 +               for (i = 0; i < num_channels; i++)
 874 +               {
 875 +                       _ifxhcd->ifxhc[i].hc_num = i;
 876 +                       IFX_DEBUGPL(DBG_HCDV, "HCD Added channel #%d\n", i);
 877 +               }
 878 +       }
 879 +
 880 +       /* Set device flags indicating whether the HCD supports DMA. */
 881 +       if(_ifxhcd->dev->dma_mask)
 882 +               *(_ifxhcd->dev->dma_mask) = ~0;
 883 +       _ifxhcd->dev->coherent_dma_mask = ~0;
 884 +
 885 +       /*
 886 +        * Finish generic HCD initialization and start the HCD. This function
 887 +        * allocates the DMA buffer pool, registers the USB bus, requests the
 888 +        * IRQ line, and calls ifxusb_hcd_start method.
 889 +        */
 890 +//     retval = usb_add_hcd(syshcd, _ifxhcd->core_if.irq, SA_INTERRUPT|SA_SHIRQ);
 891 +       retval = usb_add_hcd(syshcd, _ifxhcd->core_if.irq, IRQF_DISABLED | IRQF_SHARED );
 892 +       if (retval < 0)
 893 +               goto error2;
 894 +
 895 +       /*
 896 +        * Allocate space for storing data on status transactions. Normally no
 897 +        * data is sent, but this space acts as a bit bucket. This must be
 898 +        * done after usb_add_hcd since that function allocates the DMA buffer
 899 +        * pool.
 900 +        */
 901 +       _ifxhcd->status_buf = ifxusb_alloc_buf(IFXHCD_STATUS_BUF_SIZE, 1);
 902 +
 903 +       if (_ifxhcd->status_buf)
 904 +       {
 905 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
 906 +               IFX_DEBUGPL(DBG_HCD, "IFX USB HCD Initialized, bus=%s, usbbus=%d\n", _ifxhcd->core_if.core_name, syshcd->self.busnum);
 907 +#else
 908 +               IFX_DEBUGPL(DBG_HCD, "IFX USB HCD Initialized, bus=%s, usbbus=%d\n", _ifxhcd->dev->bus_id, syshcd->self.busnum);
 909 +#endif
 910 +               return 0;
 911 +       }
 912 +       IFX_ERROR("%s: status_buf allocation failed\n", __func__);
 913 +
 914 +       /* Error conditions */
 915 +       usb_remove_hcd(syshcd);
 916 +error2:
 917 +       ifxhcd_freeextra(syshcd);
 918 +       usb_put_hcd(syshcd);
 919 +error1:
 920 +       return retval;
 921 +}
 922 +
 923 +/*!
 924 +   \brief Removes the HCD.
 925 +  Frees memory and resources associated with the HCD and deregisters the bus.
 926 + */
 927 +void ifxhcd_remove(ifxhcd_hcd_t *_ifxhcd)
 928 +{
 929 +       struct usb_hcd *syshcd = ifxhcd_to_syshcd(_ifxhcd);
 930 +
 931 +       IFX_DEBUGPL(DBG_HCD, "IFX USB HCD REMOVE\n");
 932 +
 933 +/* == AVM/WK 20100709 - Fix: Order changed, disable IRQs not before remove_hcd == */
 934 +
 935 +       usb_remove_hcd(syshcd);
 936 +
 937 +       /* Turn off all interrupts */
 938 +       ifxusb_wreg (&_ifxhcd->core_if.core_global_regs->gintmsk, 0);
 939 +       ifxusb_mreg (&_ifxhcd->core_if.core_global_regs->gahbcfg, 1, 0);
 940 +
 941 +       ifxhcd_freeextra(syshcd);
 942 +
 943 +       usb_put_hcd(syshcd);
 944 +
 945 +       return;
 946 +}
 947 +
 948 +
 949 +/* =========================================================================
 950 + *  Linux HC Driver Functions
 951 + * ========================================================================= */
 952 +
 953 +/*!
 954 +   \brief Initializes the IFXUSB controller and its root hub and prepares it for host
 955 + mode operation. Activates the root port. Returns 0 on success and a negative
 956 + error code on failure.
 957 + Called by USB stack.
 958 + */
 959 +int ifxhcd_start(struct usb_hcd *_syshcd)
 960 +{
 961 +       ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd);
 962 +       ifxusb_core_if_t *core_if = &ifxhcd->core_if;
 963 +       struct usb_bus *bus;
 964 +
 965 +       IFX_DEBUGPL(DBG_HCD, "IFX USB HCD START\n");
 966 +
 967 +       bus = hcd_to_bus(_syshcd);
 968 +
 969 +       /* Initialize the bus state.  */
 970 +       _syshcd->state = HC_STATE_RUNNING;
 971 +
 972 +       /* Initialize and connect root hub if one is not already attached */
 973 +       if (bus->root_hub)
 974 +       {
 975 +               IFX_DEBUGPL(DBG_HCD, "IFX USB HCD Has Root Hub\n");
 976 +               /* Inform the HUB driver to resume. */
 977 +               usb_hcd_resume_root_hub(_syshcd);
 978 +       }
 979 +
 980 +       ifxhcd->flags.d32 = 0;
 981 +
 982 +       /* Put all channels in the free channel list and clean up channel states.*/
 983 +       {
 984 +               struct list_head        *item;
 985 +               item = ifxhcd->free_hc_list.next;
 986 +               while (item != &ifxhcd->free_hc_list)
 987 +               {
 988 +                       list_del(item);
 989 +                       item = ifxhcd->free_hc_list.next;
 990 +               }
 991 +       }
 992 +       {
 993 +               int num_channels = ifxhcd->core_if.params.host_channels;
 994 +               int i;
 995 +               for (i = 0; i < num_channels; i++)
 996 +               {
 997 +                       ifxhcd_hc_t      *channel;
 998 +                       channel = &ifxhcd->ifxhc[i];
 999 +                       list_add_tail(&channel->hc_list_entry, &ifxhcd->free_hc_list);
1000 +                       ifxhcd_hc_cleanup(&ifxhcd->core_if, channel);
1001 +               }
1002 +       }
1003 +       /* Initialize the USB core for host mode operation. */
1004 +
1005 +       ifxusb_host_enable_interrupts(core_if);
1006 +       ifxusb_enable_global_interrupts(core_if);
1007 +       ifxusb_phy_power_on (core_if);
1008 +
1009 +       ifxusb_vbus_init(core_if);
1010 +
1011 +       /* Turn on the vbus power. */
1012 +       {
1013 +               hprt0_data_t hprt0;
1014 +               hprt0.d32 = ifxusb_read_hprt0(core_if);
1015 +
1016 +               IFX_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr);
1017 +               if (hprt0.b.prtpwr == 0 )
1018 +               {
1019 +                       hprt0.b.prtpwr = 1;
1020 +                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1021 +                       ifxusb_vbus_on(core_if);
1022 +               }
1023 +       }
1024 +       return 0;
1025 +}
1026 +
1027 +
1028 +/*!
1029 +   \brief Halts the IFXUSB  host mode operations in a clean manner. USB transfers are
1030 + stopped.
1031 + */
1032 +void ifxhcd_stop(struct usb_hcd *_syshcd)
1033 +{
1034 +       ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd(_syshcd);
1035 +       hprt0_data_t  hprt0 = { .d32=0 };
1036 +
1037 +       IFX_DEBUGPL(DBG_HCD, "IFX USB HCD STOP\n");
1038 +
1039 +       /* Turn off all interrupts. */
1040 +       ifxusb_disable_global_interrupts(&ifxhcd->core_if );
1041 +       ifxusb_host_disable_interrupts(&ifxhcd->core_if );
1042 +#ifdef __USE_TIMER_4_SOF__
1043 +       hrtimer_cancel(&ifxhcd->hr_timer);
1044 +#endif
1045 +       /*
1046 +        * The root hub should be disconnected before this function is called.
1047 +        * The disconnect will clear the URBD lists (via ..._hcd_urb_dequeue)
1048 +        * and the EPQH lists (via ..._hcd_endpoint_disable).
1049 +        */
1050 +
1051 +       /* Turn off the vbus power */
1052 +       IFX_PRINT("PortPower off\n");
1053 +
1054 +       ifxusb_vbus_off(&ifxhcd->core_if );
1055 +
1056 +       ifxusb_vbus_free(&ifxhcd->core_if );
1057 +
1058 +       hprt0.b.prtpwr = 0;
1059 +       ifxusb_wreg(ifxhcd->core_if.hprt0, hprt0.d32);
1060 +       return;
1061 +}
1062 +
1063 +/*!
1064 +   \brief Returns the current frame number
1065 + */
1066 +int ifxhcd_get_frame_number(struct usb_hcd *_syshcd)
1067 +{
1068 +       ifxhcd_hcd_t    *ifxhcd = syshcd_to_ifxhcd(_syshcd);
1069 +       hfnum_data_t hfnum;
1070 +
1071 +       hfnum.d32 = ifxusb_rreg(&ifxhcd->core_if.host_global_regs->hfnum);
1072 +
1073 +       return hfnum.b.frnum;
1074 +}
1075 +
1076 +/*!
1077 +   \brief Starts processing a USB transfer request specified by a USB Request Block
1078 +  (URB). mem_flags indicates the type of memory allocation to use while
1079 +  processing this URB.
1080 + */
1081 +int ifxhcd_urb_enqueue( struct usb_hcd           *_syshcd,
1082 +                        /*--- struct usb_host_endpoint *_sysep, Parameter im 2.6.28 entfallen ---*/
1083 +                        struct urb               *_urb,
1084 +                        gfp_t                     _mem_flags)
1085 +{
1086 +       int retval = 0;
1087 +       ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd);
1088 +       struct usb_host_endpoint *_sysep = ifxhcd_urb_to_endpoint(_urb);
1089 +       ifxhcd_epqh_t *epqh;
1090 +
1091 +       #ifdef __DEBUG__
1092 +               if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB))
1093 +                       dump_urb_info(_urb, "ifxusb_hcd_urb_enqueue");
1094 +       #endif //__DEBUG__
1095 +
1096 +       if (!ifxhcd->flags.b.port_connect_status)  /* No longer connected. */
1097 +               return -ENODEV;
1098 +
1099 +       #ifndef __EN_ISOC__
1100 +               if(usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS)
1101 +               {
1102 +                       IFX_ERROR("ISOC transfer not supported!!!\n");
1103 +                       return -ENODEV;
1104 +               }
1105 +       #endif
1106 +
1107 +       retval=ifxhcd_urbd_create (ifxhcd,_urb);
1108 +
1109 +       if (retval)
1110 +       {
1111 +               IFX_ERROR("IFXUSB HCD URB Enqueue failed creating URBD\n");
1112 +               return retval;
1113 +       }
1114 +       epqh = (ifxhcd_epqh_t *) _sysep->hcpriv;
1115 +       ifxhcd_epqh_ready(ifxhcd, epqh);
1116 +
1117 +       select_eps(ifxhcd);
1118 +       //enable_sof(ifxhcd);
1119 +       {
1120 +               gint_data_t gintsts;
1121 +               gintsts.d32=0;
1122 +               gintsts.b.sofintr = 1;
1123 +               ifxusb_mreg(&ifxhcd->core_if.core_global_regs->gintmsk, 0,gintsts.d32);
1124 +       }
1125 +
1126 +       return retval;
1127 +}
1128 +
1129 +/*!
1130 +   \brief Aborts/cancels a USB transfer request. Always returns 0 to indicate
1131 +  success.
1132 + */
1133 +int ifxhcd_urb_dequeue( struct usb_hcd *_syshcd,
1134 +                        struct urb *_urb, int status /* Parameter neu in 2.6.28 */)
1135 +{
1136 +       unsigned long flags;
1137 +       ifxhcd_hcd_t  *ifxhcd;
1138 +       ifxhcd_urbd_t *urbd;
1139 +       ifxhcd_epqh_t *epqh;
1140 +       int is_active=0;
1141 +       int rc;
1142 +
1143 +       struct usb_host_endpoint *_sysep;
1144 +
1145 +       IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD URB Dequeue\n");
1146 +
1147 +       #ifndef __EN_ISOC__
1148 +               if(usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS)
1149 +                       return 0;
1150 +       #endif
1151 +
1152 +       _sysep = ifxhcd_urb_to_endpoint(_urb);
1153 +
1154 +       ifxhcd = syshcd_to_ifxhcd(_syshcd);
1155 +
1156 +       SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags);
1157 +
1158 +       /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/
1159 +       rc = usb_hcd_check_unlink_urb(_syshcd, _urb, status);
1160 +       if (rc) {
1161 +               SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags);
1162 +               return rc;
1163 +       }
1164 +
1165 +       urbd = (ifxhcd_urbd_t *) _urb->hcpriv;
1166 +
1167 +       if(_sysep)
1168 +               epqh = (ifxhcd_epqh_t *) _sysep->hcpriv;
1169 +       else
1170 +               epqh = (ifxhcd_epqh_t *) urbd->epqh;
1171 +
1172 +       if(epqh!=urbd->epqh)
1173 +               IFX_ERROR("%s inconsistant epqh %p %p\n",__func__,epqh,urbd->epqh);
1174 +
1175 +       #ifdef __DEBUG__
1176 +               if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB))
1177 +               {
1178 +                       dump_urb_info(_urb, "ifxhcd_urb_dequeue");
1179 +                       if (epqh->is_active)
1180 +                               dump_channel_info(ifxhcd, epqh);
1181 +               }
1182 +       #endif //__DEBUG__
1183 +
1184 +       if(!epqh->hc)
1185 +               epqh->is_active=0;
1186 +       else if (!ifxhcd->flags.b.port_connect_status)
1187 +                       epqh->is_active=0;
1188 +       else if (epqh->is_active && urbd->is_active)
1189 +       {
1190 +               /*== AVM/WK 20100709 - halt channel only if really started ==*/
1191 +               //if (epqh->hc->xfer_started && !epqh->hc->wait_for_sof) {
1192 +               /*== AVM/WK 20101112 - halt channel if started ==*/
1193 +               if (epqh->hc->xfer_started) {
1194 +                       /*
1195 +                        * If still connected (i.e. in host mode), halt the
1196 +                        * channel so it can be used for other transfers. If
1197 +                        * no longer connected, the host registers can't be
1198 +                        * written to halt the channel since the core is in
1199 +                        * device mode.
1200 +                        */
1201 +                       /* == 20110803 AVM/WK FIX propagate status == */
1202 +                       if (_urb->status == -EINPROGRESS) {
1203 +                               _urb->status = status;
1204 +                       }
1205 +                       ifxhcd_hc_halt(&ifxhcd->core_if, epqh->hc, HC_XFER_URB_DEQUEUE);
1206 +                       epqh->hc = NULL;
1207 +                       is_active=1;
1208 +               }
1209 +       }
1210 +
1211 +       if(is_active)
1212 +       {
1213 +               SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags);
1214 +       }
1215 +       else
1216 +       {
1217 +               list_del_init(&urbd->urbd_list_entry);
1218 +               kfree (urbd);
1219 +
1220 +               /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/
1221 +               usb_hcd_unlink_urb_from_ep(_syshcd, _urb);
1222 +
1223 +               SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags);
1224 +               _urb->hcpriv = NULL;
1225 +//             usb_hcd_giveback_urb(_syshcd, _urb);
1226 +               usb_hcd_giveback_urb(_syshcd, _urb, status /* neu in 2.6.28 */);
1227 +               select_eps(ifxhcd);
1228 +       }
1229 +
1230 +       return 0;
1231 +}
1232 +
1233 +
1234 +
1235 +/*!
1236 +   \brief Frees resources in the IFXUSB controller related to a given endpoint. Also
1237 +  clears state in the HCD related to the endpoint. Any URBs for the endpoint
1238 +  must already be dequeued.
1239 + */
1240 +void ifxhcd_endpoint_disable( struct usb_hcd *_syshcd,
1241 +                              struct usb_host_endpoint *_sysep)
1242 +{
1243 +       ifxhcd_epqh_t *epqh;
1244 +       ifxhcd_hcd_t  *ifxhcd = syshcd_to_ifxhcd(_syshcd);
1245 +       unsigned long flags;
1246 +
1247 +       int retry = 0;
1248 +
1249 +       IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD EP DISABLE: _bEndpointAddress=0x%02x, "
1250 +           "endpoint=%d\n", _sysep->desc.bEndpointAddress,
1251 +                   ifxhcd_ep_addr_to_endpoint(_sysep->desc.bEndpointAddress));
1252 +
1253 +       SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags);
1254 +       if((uint32_t)_sysep>=0x80000000 && (uint32_t)_sysep->hcpriv>=(uint32_t)0x80000000)
1255 +       {
1256 +               epqh = (ifxhcd_epqh_t *)(_sysep->hcpriv);
1257 +               if (epqh && epqh->sysep==_sysep)
1258 +               {
1259 +
1260 +#if 1  /*== AVM/BC 20101111 CHG Option active: Kill URBs when disabling EP  ==*/
1261 +                       while (!list_empty(&epqh->urbd_list))
1262 +                       {
1263 +                               if (retry++ > 250)
1264 +                               {
1265 +                                       IFX_WARN("IFXUSB HCD EP DISABLE:"
1266 +                                                " URBD List for this endpoint is not empty\n");
1267 +                                       break;
1268 +                               }
1269 +                               kill_all_urbs_in_epqh(ifxhcd, epqh, -ETIMEDOUT);
1270 +                       }
1271 +#else
1272 +                       while (!list_empty(&epqh->urbd_list))
1273 +                       {
1274 +                               /** Check that the QTD list is really empty */
1275 +                               if (retry++ > 250)
1276 +                               {
1277 +                                       IFX_WARN("IFXUSB HCD EP DISABLE:"
1278 +                                                " URBD List for this endpoint is not empty\n");
1279 +                                       break;
1280 +                               }
1281 +                               SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags);
1282 +                               schedule_timeout_uninterruptible(1);
1283 +                               SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags);
1284 +                       }
1285 +#endif
1286 +
1287 +                       ifxhcd_epqh_free(epqh);
1288 +                       _sysep->hcpriv = NULL;
1289 +               }
1290 +       }
1291 +       SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags);
1292 +}
1293 +
1294 +
1295 +/*!
1296 +   \brief Handles host mode interrupts for the IFXUSB controller. Returns IRQ_NONE if
1297 + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
1298 + * interrupt.
1299 + *
1300 + * This function is called by the USB core when an interrupt occurs
1301 + */
1302 +irqreturn_t ifxhcd_irq(struct usb_hcd *_syshcd)
1303 +{
1304 +       ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd);
1305 +    int32_t retval=0;
1306 +
1307 +       //mask_and_ack_ifx_irq (ifxhcd->core_if.irq);
1308 +       retval = ifxhcd_handle_intr(ifxhcd);
1309 +       return IRQ_RETVAL(retval);
1310 +}
1311 +
1312 +
1313 +/*!
1314 +   \brief Handles host mode Over Current Interrupt
1315 + */
1316 +irqreturn_t ifxhcd_oc_irq(int _irq , void *_dev)
1317 +{
1318 +       ifxhcd_hcd_t *ifxhcd = _dev;
1319 +       int32_t retval=1;
1320 +
1321 +       ifxhcd->flags.b.port_over_current_change = 1;
1322 +       ifxusb_vbus_off(&ifxhcd->core_if);
1323 +       IFX_DEBUGP("OC INTERRUPT # %d\n",ifxhcd->core_if.core_no);
1324 +
1325 +       //mask_and_ack_ifx_irq (_irq);
1326 +       return IRQ_RETVAL(retval);
1327 +}
1328 +
1329 +/*!
1330 + \brief Creates Status Change bitmap for the root hub and root port. The bitmap is
1331 +  returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
1332 +  is the status change indicator for the single root port. Returns 1 if either
1333 +  change indicator is 1, otherwise returns 0.
1334 + */
1335 +int ifxhcd_hub_status_data(struct usb_hcd *_syshcd, char *_buf)
1336 +{
1337 +       ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd);
1338 +
1339 +       _buf[0] = 0;
1340 +       _buf[0] |= (ifxhcd->flags.b.port_connect_status_change ||
1341 +                   ifxhcd->flags.b.port_reset_change ||
1342 +                   ifxhcd->flags.b.port_enable_change ||
1343 +                   ifxhcd->flags.b.port_suspend_change ||
1344 +                   ifxhcd->flags.b.port_over_current_change) << 1;
1345 +
1346 +       #ifdef __DEBUG__
1347 +               if (_buf[0])
1348 +               {
1349 +                       IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD HUB STATUS DATA:"
1350 +                                   " Root port status changed\n");
1351 +                       IFX_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
1352 +                                   ifxhcd->flags.b.port_connect_status_change);
1353 +                       IFX_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
1354 +                                   ifxhcd->flags.b.port_reset_change);
1355 +                       IFX_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
1356 +                                   ifxhcd->flags.b.port_enable_change);
1357 +                       IFX_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
1358 +                                   ifxhcd->flags.b.port_suspend_change);
1359 +                       IFX_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
1360 +                                   ifxhcd->flags.b.port_over_current_change);
1361 +               }
1362 +       #endif //__DEBUG__
1363 +       return (_buf[0] != 0);
1364 +}
1365 +
1366 +#ifdef __WITH_HS_ELECT_TST__
1367 +       extern void do_setup(ifxusb_core_if_t *_core_if) ;
1368 +       extern void do_in_ack(ifxusb_core_if_t *_core_if);
1369 +#endif //__WITH_HS_ELECT_TST__
1370 +
1371 +/*!
1372 + \brief Handles hub class-specific requests.
1373 + */
1374 +int ifxhcd_hub_control( struct usb_hcd *_syshcd,
1375 +                        u16             _typeReq,
1376 +                        u16             _wValue,
1377 +                        u16             _wIndex,
1378 +                        char           *_buf,
1379 +                        u16             _wLength)
1380 +{
1381 +       int retval = 0;
1382 +
1383 +       ifxhcd_hcd_t              *ifxhcd  = syshcd_to_ifxhcd (_syshcd);
1384 +       ifxusb_core_if_t          *core_if = &ifxhcd->core_if;
1385 +       struct usb_hub_descriptor *desc;
1386 +       hprt0_data_t               hprt0 = {.d32 = 0};
1387 +
1388 +       uint32_t port_status;
1389 +
1390 +       switch (_typeReq)
1391 +       {
1392 +               case ClearHubFeature:
1393 +                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1394 +                                "ClearHubFeature 0x%x\n", _wValue);
1395 +                       switch (_wValue)
1396 +                       {
1397 +                               case C_HUB_LOCAL_POWER:
1398 +                               case C_HUB_OVER_CURRENT:
1399 +                                       /* Nothing required here */
1400 +                                       break;
1401 +                               default:
1402 +                                       retval = -EINVAL;
1403 +                                       IFX_ERROR ("IFXUSB HCD - "
1404 +                                                  "ClearHubFeature request %xh unknown\n", _wValue);
1405 +                       }
1406 +                       break;
1407 +               case ClearPortFeature:
1408 +                       if (!_wIndex || _wIndex > 1)
1409 +                               goto error;
1410 +
1411 +                       switch (_wValue)
1412 +                       {
1413 +                               case USB_PORT_FEAT_ENABLE:
1414 +                                       IFX_DEBUGPL (DBG_ANY, "IFXUSB HCD HUB CONTROL - "
1415 +                                                    "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1416 +                                       hprt0.d32 = ifxusb_read_hprt0 (core_if);
1417 +                                       hprt0.b.prtena = 1;
1418 +                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1419 +                                       break;
1420 +                               case USB_PORT_FEAT_SUSPEND:
1421 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1422 +                                                    "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1423 +                                       hprt0.d32 = ifxusb_read_hprt0 (core_if);
1424 +                                       hprt0.b.prtres = 1;
1425 +                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1426 +                                       /* Clear Resume bit */
1427 +                                       mdelay (100);
1428 +                                       hprt0.b.prtres = 0;
1429 +                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1430 +                                       break;
1431 +                               case USB_PORT_FEAT_POWER:
1432 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1433 +                                                    "ClearPortFeature USB_PORT_FEAT_POWER\n");
1434 +                                       #ifdef __IS_DUAL__
1435 +                                               ifxusb_vbus_off(core_if);
1436 +                                       #else
1437 +                                               ifxusb_vbus_off(core_if);
1438 +                                       #endif
1439 +                                       hprt0.d32 = ifxusb_read_hprt0 (core_if);
1440 +                                       hprt0.b.prtpwr = 0;
1441 +                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1442 +                                       break;
1443 +                               case USB_PORT_FEAT_INDICATOR:
1444 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1445 +                                                    "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1446 +                                       /* Port inidicator not supported */
1447 +                                       break;
1448 +                               case USB_PORT_FEAT_C_CONNECTION:
1449 +                                       /* Clears drivers internal connect status change
1450 +                                        * flag */
1451 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1452 +                                                    "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1453 +                                       ifxhcd->flags.b.port_connect_status_change = 0;
1454 +                                       break;
1455 +                               case USB_PORT_FEAT_C_RESET:
1456 +                                       /* Clears the driver's internal Port Reset Change
1457 +                                        * flag */
1458 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1459 +                                                    "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1460 +                                       ifxhcd->flags.b.port_reset_change = 0;
1461 +                                       break;
1462 +                               case USB_PORT_FEAT_C_ENABLE:
1463 +                                       /* Clears the driver's internal Port
1464 +                                        * Enable/Disable Change flag */
1465 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1466 +                                                    "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1467 +                                       ifxhcd->flags.b.port_enable_change = 0;
1468 +                                       break;
1469 +                               case USB_PORT_FEAT_C_SUSPEND:
1470 +                                       /* Clears the driver's internal Port Suspend
1471 +                                        * Change flag, which is set when resume signaling on
1472 +                                        * the host port is complete */
1473 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1474 +                                                    "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1475 +                                       ifxhcd->flags.b.port_suspend_change = 0;
1476 +                                       break;
1477 +                               case USB_PORT_FEAT_C_OVER_CURRENT:
1478 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1479 +                                                    "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1480 +                                       ifxhcd->flags.b.port_over_current_change = 0;
1481 +                                       break;
1482 +                               default:
1483 +                                       retval = -EINVAL;
1484 +                                       IFX_ERROR ("IFXUSB HCD - "
1485 +                                                "ClearPortFeature request %xh "
1486 +                                                "unknown or unsupported\n", _wValue);
1487 +                       }
1488 +                       break;
1489 +               case GetHubDescriptor:
1490 +                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1491 +                                "GetHubDescriptor\n");
1492 +                       desc = (struct usb_hub_descriptor *)_buf;
1493 +                       desc->bDescLength = 9;
1494 +                       desc->bDescriptorType = 0x29;
1495 +                       desc->bNbrPorts = 1;
1496 +                       desc->wHubCharacteristics = 0x08;
1497 +                       desc->bPwrOn2PwrGood = 1;
1498 +                       desc->bHubContrCurrent = 0;
1499 +//                     desc->bitmap[0] = 0;
1500 +//                     desc->bitmap[1] = 0xff;
1501 +                       break;
1502 +               case GetHubStatus:
1503 +                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1504 +                                "GetHubStatus\n");
1505 +                       memset (_buf, 0, 4);
1506 +                       break;
1507 +               case GetPortStatus:
1508 +                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1509 +                                "GetPortStatus\n");
1510 +                       if (!_wIndex || _wIndex > 1)
1511 +                               goto error;
1512 +
1513 +#              ifdef CONFIG_AVM_POWERMETER
1514 +                       {
1515 +                               /* first port only, but 2 Hosts */
1516 +                               static unsigned char ucOldPower1 = 255;
1517 +                               static unsigned char ucOldPower2 = 255;
1518 +
1519 +                               unsigned char ucNewPower = 0;
1520 +                               struct usb_device *childdev = _syshcd->self.root_hub->children[0];
1521 +
1522 +                               if (childdev != NULL) {
1523 +                                       ucNewPower = (childdev->actconfig != NULL)
1524 +                                                                       ? childdev->actconfig->desc.bMaxPower
1525 +                                                                       : 50;/* default: 50 means 100 mA*/
1526 +                               }
1527 +                               if (_syshcd->self.busnum == 1) {
1528 +                                       if (ucOldPower1 != ucNewPower) {
1529 +                                               ucOldPower1 = ucNewPower;
1530 +                                               printk (KERN_INFO "IFXHCD#1: AVM Powermeter changed to %u mA\n", ucNewPower*2);
1531 +                                               PowerManagmentRessourceInfo(powerdevice_usb_host, ucNewPower*2);
1532 +                                       }
1533 +                               } else {
1534 +                                       if (ucOldPower2 != ucNewPower) {
1535 +                                               ucOldPower2 = ucNewPower;
1536 +                                               printk (KERN_INFO "IFXHCD#2: AVM Powermeter changed to %u mA\n", ucNewPower*2);
1537 +                                               PowerManagmentRessourceInfo(powerdevice_usb_host2, ucNewPower*2);
1538 +                                       }
1539 +                               }
1540 +                       }
1541 +#              endif  /*--- #ifdef CONFIG_AVM_POWERMETER ---*/
1542 +
1543 +                       port_status = 0;
1544 +                       if (ifxhcd->flags.b.port_connect_status_change)
1545 +                               port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
1546 +                       if (ifxhcd->flags.b.port_enable_change)
1547 +                               port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
1548 +                       if (ifxhcd->flags.b.port_suspend_change)
1549 +                               port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
1550 +                       if (ifxhcd->flags.b.port_reset_change)
1551 +                               port_status |= (1 << USB_PORT_FEAT_C_RESET);
1552 +                       if (ifxhcd->flags.b.port_over_current_change)
1553 +                       {
1554 +                               IFX_ERROR("Device Not Supported\n");
1555 +                               port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
1556 +                       }
1557 +                       if (!ifxhcd->flags.b.port_connect_status)
1558 +                       {
1559 +                               /*
1560 +                                * The port is disconnected, which means the core is
1561 +                                * either in device mode or it soon will be. Just
1562 +                                * return 0's for the remainder of the port status
1563 +                                * since the port register can't be read if the core
1564 +                                * is in device mode.
1565 +                                */
1566 +                               *((u32 *) _buf) = cpu_to_le32(port_status);
1567 +                               break;
1568 +                       }
1569 +
1570 +                       hprt0.d32 = ifxusb_rreg(core_if->hprt0);
1571 +                       IFX_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
1572 +                       if (hprt0.b.prtconnsts)
1573 +                               port_status |= (1 << USB_PORT_FEAT_CONNECTION);
1574 +                       if (hprt0.b.prtena)
1575 +                               port_status |= (1 << USB_PORT_FEAT_ENABLE);
1576 +                       if (hprt0.b.prtsusp)
1577 +                               port_status |= (1 << USB_PORT_FEAT_SUSPEND);
1578 +                       if (hprt0.b.prtovrcurract)
1579 +                               port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
1580 +                       if (hprt0.b.prtrst)
1581 +                               port_status |= (1 << USB_PORT_FEAT_RESET);
1582 +                       if (hprt0.b.prtpwr)
1583 +                               port_status |= (1 << USB_PORT_FEAT_POWER);
1584 +/*                     if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED)
1585 +                               port_status |= (1 << USB_PORT_FEAT_HIGHSPEED);
1586 +                       else if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_LOW_SPEED)
1587 +                               port_status |= (1 << USB_PORT_FEAT_LOWSPEED);*/
1588 +                       if (hprt0.b.prttstctl)
1589 +                               port_status |= (1 << USB_PORT_FEAT_TEST);
1590 +                       /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1591 +                       *((u32 *) _buf) = cpu_to_le32(port_status);
1592 +                       break;
1593 +               case SetHubFeature:
1594 +                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1595 +                                "SetHubFeature\n");
1596 +                       /* No HUB features supported */
1597 +                       break;
1598 +               case SetPortFeature:
1599 +                       if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
1600 +                               goto error;
1601 +                       /*
1602 +                        * The port is disconnected, which means the core is
1603 +                        * either in device mode or it soon will be. Just
1604 +                        * return without doing anything since the port
1605 +                        * register can't be written if the core is in device
1606 +                        * mode.
1607 +                        */
1608 +                       if (!ifxhcd->flags.b.port_connect_status)
1609 +                               break;
1610 +                       switch (_wValue)
1611 +                       {
1612 +                               case USB_PORT_FEAT_SUSPEND:
1613 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1614 +                                                    "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1615 +                                       hprt0.d32 = ifxusb_read_hprt0 (core_if);
1616 +                                       hprt0.b.prtsusp = 1;
1617 +                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1618 +                                       //IFX_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
1619 +                                       /* Suspend the Phy Clock */
1620 +                                       {
1621 +                                               pcgcctl_data_t pcgcctl = {.d32=0};
1622 +                                               pcgcctl.b.stoppclk = 1;
1623 +                                               ifxusb_wreg(core_if->pcgcctl, pcgcctl.d32);
1624 +                                       }
1625 +                                       break;
1626 +                               case USB_PORT_FEAT_POWER:
1627 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1628 +                                            "SetPortFeature - USB_PORT_FEAT_POWER\n");
1629 +                                       ifxusb_vbus_on (core_if);
1630 +                                       hprt0.d32 = ifxusb_read_hprt0 (core_if);
1631 +                                       hprt0.b.prtpwr = 1;
1632 +                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1633 +                                       break;
1634 +                               case USB_PORT_FEAT_RESET:
1635 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1636 +                                                    "SetPortFeature - USB_PORT_FEAT_RESET\n");
1637 +                                       hprt0.d32 = ifxusb_read_hprt0 (core_if);
1638 +                                       hprt0.b.prtrst = 1;
1639 +                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1640 +                                       /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1641 +                                       MDELAY (60);
1642 +                                       hprt0.b.prtrst = 0;
1643 +                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1644 +                                       break;
1645 +                       #ifdef __WITH_HS_ELECT_TST__
1646 +                               case USB_PORT_FEAT_TEST:
1647 +                                       {
1648 +                                               uint32_t t;
1649 +                                               gint_data_t gintmsk;
1650 +                                               t = (_wIndex >> 8); /* MSB wIndex USB */
1651 +                                               IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1652 +                                                            "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
1653 +                                               warn("USB_PORT_FEAT_TEST %d\n", t);
1654 +                                               if (t < 6)
1655 +                                               {
1656 +                                                       hprt0.d32 = ifxusb_read_hprt0 (core_if);
1657 +                                                       hprt0.b.prttstctl = t;
1658 +                                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1659 +                                               }
1660 +                                               else if (t == 6)  /* HS_HOST_PORT_SUSPEND_RESUME */
1661 +                                               {
1662 +                                                       /* Save current interrupt mask */
1663 +                                                       gintmsk.d32 = ifxusb_rreg(&core_if->core_global_regs->gintmsk);
1664 +
1665 +                                                       /* Disable all interrupts while we muck with
1666 +                                                        * the hardware directly
1667 +                                                        */
1668 +                                                       ifxusb_wreg(&core_if->core_global_regs->gintmsk, 0);
1669 +
1670 +                                                       /* 15 second delay per the test spec */
1671 +                                                       mdelay(15000);
1672 +
1673 +                                                       /* Drive suspend on the root port */
1674 +                                                       hprt0.d32 = ifxusb_read_hprt0 (core_if);
1675 +                                                       hprt0.b.prtsusp = 1;
1676 +                                                       hprt0.b.prtres = 0;
1677 +                                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1678 +
1679 +                                                       /* 15 second delay per the test spec */
1680 +                                                       mdelay(15000);
1681 +
1682 +                                                       /* Drive resume on the root port */
1683 +                                                       hprt0.d32 = ifxusb_read_hprt0 (core_if);
1684 +                                                       hprt0.b.prtsusp = 0;
1685 +                                                       hprt0.b.prtres = 1;
1686 +                                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1687 +                                                       mdelay(100);
1688 +
1689 +                                                       /* Clear the resume bit */
1690 +                                                       hprt0.b.prtres = 0;
1691 +                                                       ifxusb_wreg(core_if->hprt0, hprt0.d32);
1692 +
1693 +                                                       /* Restore interrupts */
1694 +                                                       ifxusb_wreg(&core_if->core_global_regs->gintmsk, gintmsk.d32);
1695 +                                               }
1696 +                                               else if (t == 7)  /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
1697 +                                               {
1698 +                                                       /* Save current interrupt mask */
1699 +                                                       gintmsk.d32 = ifxusb_rreg(&core_if->core_global_regs->gintmsk);
1700 +
1701 +                                                       /* Disable all interrupts while we muck with
1702 +                                                        * the hardware directly
1703 +                                                        */
1704 +                                                       ifxusb_wreg(&core_if->core_global_regs->gintmsk, 0);
1705 +
1706 +                                                       /* 15 second delay per the test spec */
1707 +                                                       mdelay(15000);
1708 +
1709 +                                                       /* Send the Setup packet */
1710 +                                                       do_setup(core_if);
1711 +
1712 +                                                       /* 15 second delay so nothing else happens for awhile */
1713 +                                                       mdelay(15000);
1714 +
1715 +                                                       /* Restore interrupts */
1716 +                                                       ifxusb_wreg(&core_if->core_global_regs->gintmsk, gintmsk.d32);
1717 +                                               }
1718 +
1719 +                                               else if (t == 8)  /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
1720 +                                               {
1721 +                                                       /* Save current interrupt mask */
1722 +                                                       gintmsk.d32 = ifxusb_rreg(&core_if->core_global_regs->gintmsk);
1723 +
1724 +                                                       /* Disable all interrupts while we muck with
1725 +                                                        * the hardware directly
1726 +                                                        */
1727 +                                                       ifxusb_wreg(&core_if->core_global_regs->gintmsk, 0);
1728 +
1729 +                                                       /* Send the Setup packet */
1730 +                                                       do_setup(core_if);
1731 +
1732 +                                                       /* 15 second delay so nothing else happens for awhile */
1733 +                                                       mdelay(15000);
1734 +
1735 +                                                       /* Send the In and Ack packets */
1736 +                                                       do_in_ack(core_if);
1737 +
1738 +                                                       /* 15 second delay so nothing else happens for awhile */
1739 +                                                       mdelay(15000);
1740 +
1741 +                                                       /* Restore interrupts */
1742 +                                                       ifxusb_wreg(&core_if->core_global_regs->gintmsk, gintmsk.d32);
1743 +                                               }
1744 +                                       }
1745 +                                       break;
1746 +                       #endif //__WITH_HS_ELECT_TST__
1747 +                               case USB_PORT_FEAT_INDICATOR:
1748 +                                       IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - "
1749 +                                                    "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1750 +                                       /* Not supported */
1751 +                                       break;
1752 +                               default:
1753 +                                       retval = -EINVAL;
1754 +                                       IFX_ERROR ("IFXUSB HCD - "
1755 +                                                  "SetPortFeature request %xh "
1756 +                                                  "unknown or unsupported\n", _wValue);
1757 +                       }
1758 +                       break;
1759 +               default:
1760 +               error:
1761 +                       retval = -EINVAL;
1762 +                       IFX_WARN ("IFXUSB HCD - "
1763 +                                 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
1764 +                                 _typeReq, _wIndex, _wValue);
1765 +       }
1766 +       return retval;
1767 +}
1768 +
1769 +
1770 +/*!
1771 + \brief Assigns transactions from a URBD to a free host channel and initializes the
1772 + host channel to perform the transactions. The host channel is removed from
1773 + the free list.
1774 + \param _ifxhcd The HCD state structure.
1775 + \param _epqh Transactions from the first URBD for this EPQH are selected and assigned to a free host channel.
1776 + */
1777 +static int assign_and_init_hc(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
1778 +{
1779 +       ifxhcd_hc_t   *ifxhc;
1780 +       ifxhcd_urbd_t *urbd;
1781 +       struct urb    *urb;
1782 +
1783 +       IFX_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _ifxhcd, _epqh);
1784 +
1785 +       if(list_empty(&_epqh->urbd_list))
1786 +               return 0;
1787 +
1788 +       ifxhc = list_entry(_ifxhcd->free_hc_list.next, ifxhcd_hc_t, hc_list_entry);
1789 +       /* Remove the host channel from the free list. */
1790 +       list_del_init(&ifxhc->hc_list_entry);
1791 +
1792 +       urbd = list_entry(_epqh->urbd_list.next, ifxhcd_urbd_t, urbd_list_entry);
1793 +       urb  = urbd->urb;
1794 +
1795 +       _epqh->hc   = ifxhc;
1796 +       _epqh->urbd = urbd;
1797 +       ifxhc->epqh = _epqh;
1798 +
1799 +       urbd->is_active=1;
1800 +
1801 +       /*
1802 +        * Use usb_pipedevice to determine device address. This address is
1803 +        * 0 before the SET_ADDRESS command and the correct address afterward.
1804 +        */
1805 +       ifxhc->dev_addr = usb_pipedevice(urb->pipe);
1806 +       ifxhc->ep_num   = usb_pipeendpoint(urb->pipe);
1807 +
1808 +       ifxhc->xfer_started   = 0;
1809 +
1810 +       if      (urb->dev->speed == USB_SPEED_LOW)  ifxhc->speed = IFXUSB_EP_SPEED_LOW;
1811 +       else if (urb->dev->speed == USB_SPEED_FULL) ifxhc->speed = IFXUSB_EP_SPEED_FULL;
1812 +       else                                        ifxhc->speed = IFXUSB_EP_SPEED_HIGH;
1813 +
1814 +       ifxhc->mps         = _epqh->mps;
1815 +       ifxhc->halt_status = HC_XFER_NO_HALT_STATUS;
1816 +
1817 +       ifxhc->ep_type = _epqh->ep_type;
1818 +
1819 +       if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL)
1820 +       {
1821 +               ifxhc->control_phase=IFXHCD_CONTROL_SETUP;
1822 +               ifxhc->is_in          = 0;
1823 +               ifxhc->data_pid_start = IFXUSB_HC_PID_SETUP;
1824 +               ifxhc->xfer_buff      = urbd->setup_buff;
1825 +               ifxhc->xfer_len       = 8;
1826 +               ifxhc->xfer_count     = 0;
1827 +               ifxhc->short_rw       =(urb->transfer_flags & URB_ZERO_PACKET)?1:0;
1828 +       }
1829 +       else
1830 +       {
1831 +               ifxhc->is_in          = urbd->is_in;
1832 +               ifxhc->xfer_buff      = urbd->xfer_buff;
1833 +               ifxhc->xfer_len       = urbd->xfer_len;
1834 +               ifxhc->xfer_count     = 0;
1835 +               /* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/
1836 +               //ifxhc->data_pid_start = _epqh->data_toggle;
1837 +               ifxhc->data_pid_start = usb_gettoggle (urb->dev, usb_pipeendpoint(urb->pipe), usb_pipeout (urb->pipe))
1838 +                                                               ? IFXUSB_HC_PID_DATA1
1839 +                                                               : IFXUSB_HC_PID_DATA0;
1840 +               if(ifxhc->is_in)
1841 +                       ifxhc->short_rw       =0;
1842 +               else
1843 +                       ifxhc->short_rw       =(urb->transfer_flags & URB_ZERO_PACKET)?1:0;
1844 +
1845 +               #ifdef __EN_ISOC__
1846 +                       if(_epqh->ep_type==IFXUSB_EP_TYPE_ISOC)
1847 +                       {
1848 +                               struct usb_iso_packet_descriptor *frame_desc;
1849 +                               frame_desc = &urb->iso_frame_desc[urbd->isoc_frame_index];
1850 +                               ifxhc->xfer_buff += frame_desc->offset + urbd->isoc_split_offset;
1851 +                               ifxhc->xfer_len   = frame_desc->length - urbd->isoc_split_offset;
1852 +                               if (ifxhc->isoc_xact_pos == IFXUSB_HCSPLIT_XACTPOS_ALL)
1853 +                               {
1854 +                                       if (ifxhc->xfer_len <= 188)
1855 +                                               ifxhc->isoc_xact_pos = IFXUSB_HCSPLIT_XACTPOS_ALL;
1856 +                                       else
1857 +                                               ifxhc->isoc_xact_pos = IFXUSB_HCSPLIT_XACTPOS_BEGIN;
1858 +                               }
1859 +                       }
1860 +               #endif
1861 +       }
1862 +
1863 +       ifxhc->do_ping=0;
1864 +       if (_ifxhcd->core_if.snpsid < 0x4f54271a && ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
1865 +               ifxhc->do_ping=1;
1866 +
1867 +
1868 +       /* Set the split attributes */
1869 +       ifxhc->split = 0;
1870 +       if (_epqh->need_split) {
1871 +               ifxhc->split = 1;
1872 +               ifxhc->hub_addr       = urb->dev->tt->hub->devnum;
1873 +               ifxhc->port_addr      = urb->dev->ttport;
1874 +       }
1875 +
1876 +       //ifxhc->uint16_t pkt_count_limit
1877 +
1878 +       {
1879 +               hcint_data_t      hc_intr_mask;
1880 +               uint8_t           hc_num = ifxhc->hc_num;
1881 +               ifxusb_hc_regs_t *hc_regs = _ifxhcd->core_if.hc_regs[hc_num];
1882 +
1883 +               /* Clear old interrupt conditions for this host channel. */
1884 +               hc_intr_mask.d32 = 0xFFFFFFFF;
1885 +               hc_intr_mask.b.reserved = 0;
1886 +               ifxusb_wreg(&hc_regs->hcint, hc_intr_mask.d32);
1887 +
1888 +               /* Enable channel interrupts required for this transfer. */
1889 +               hc_intr_mask.d32 = 0;
1890 +               hc_intr_mask.b.chhltd = 1;
1891 +               hc_intr_mask.b.ahberr = 1;
1892 +
1893 +               ifxusb_wreg(&hc_regs->hcintmsk, hc_intr_mask.d32);
1894 +
1895 +               /* Enable the top level host channel interrupt. */
1896 +               {
1897 +                       uint32_t          intr_enable;
1898 +                       intr_enable = (1 << hc_num);
1899 +                       ifxusb_mreg(&_ifxhcd->core_if.host_global_regs->haintmsk, 0, intr_enable);
1900 +               }
1901 +
1902 +               /* Make sure host channel interrupts are enabled. */
1903 +               {
1904 +                       gint_data_t       gintmsk ={.d32 = 0};
1905 +                       gintmsk.b.hcintr = 1;
1906 +                       ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, 0, gintmsk.d32);
1907 +               }
1908 +
1909 +               /*
1910 +                * Program the HCCHARn register with the endpoint characteristics for
1911 +                * the current transfer.
1912 +                */
1913 +               {
1914 +                       hcchar_data_t     hcchar;
1915 +
1916 +                       hcchar.d32 = 0;
1917 +                       hcchar.b.devaddr   =  ifxhc->dev_addr;
1918 +                       hcchar.b.epnum     =  ifxhc->ep_num;
1919 +                       hcchar.b.lspddev   = (ifxhc->speed == IFXUSB_EP_SPEED_LOW);
1920 +                       hcchar.b.eptype    =  ifxhc->ep_type;
1921 +                       hcchar.b.mps       =  ifxhc->mps;
1922 +                       ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
1923 +
1924 +                       IFX_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, ifxhc->hc_num);
1925 +                       IFX_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n"    , hcchar.b.devaddr);
1926 +                       IFX_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n"      , hcchar.b.epnum);
1927 +                       IFX_DEBUGPL(DBG_HCDV, "  Is Low Speed: %d\n", hcchar.b.lspddev);
1928 +                       IFX_DEBUGPL(DBG_HCDV, "  Ep Type: %d\n"     , hcchar.b.eptype);
1929 +                       IFX_DEBUGPL(DBG_HCDV, "  Max Pkt: %d\n"     , hcchar.b.mps);
1930 +                       IFX_DEBUGPL(DBG_HCDV, "  Multi Cnt: %d\n"   , hcchar.b.multicnt);
1931 +               }
1932 +               /* Program the HCSPLIT register for SPLITs */
1933 +               {
1934 +                       hcsplt_data_t     hcsplt;
1935 +
1936 +                       hcsplt.d32 = 0;
1937 +                       if (ifxhc->split)
1938 +                       {
1939 +                               IFX_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", ifxhc->hc_num,
1940 +                                          (ifxhc->split==2) ? "CSPLIT" : "SSPLIT");
1941 +                               hcsplt.b.spltena  = 1;
1942 +                               hcsplt.b.compsplt = (ifxhc->split==2);
1943 +                               #ifdef __EN_ISOC__
1944 +                                       if(_epqh->ep_type==IFXUSB_EP_TYPE_ISOC)
1945 +                                               hcsplt.b.xactpos  = ifxhc->isoc_xact_pos;
1946 +                                       else
1947 +                               #endif
1948 +                                       hcsplt.b.xactpos  = IFXUSB_HCSPLIT_XACTPOS_ALL;
1949 +                               hcsplt.b.hubaddr  = ifxhc->hub_addr;
1950 +                               hcsplt.b.prtaddr  = ifxhc->port_addr;
1951 +                               IFX_DEBUGPL(DBG_HCDV, "   comp split %d\n" , hcsplt.b.compsplt);
1952 +                               IFX_DEBUGPL(DBG_HCDV, "   xact pos %d\n"   , hcsplt.b.xactpos);
1953 +                               IFX_DEBUGPL(DBG_HCDV, "   hub addr %d\n"   , hcsplt.b.hubaddr);
1954 +                               IFX_DEBUGPL(DBG_HCDV, "   port addr %d\n"  , hcsplt.b.prtaddr);
1955 +                               IFX_DEBUGPL(DBG_HCDV, "   is_in %d\n"      , ifxhc->is_in);
1956 +                               IFX_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n"   , ifxhc->mps);
1957 +                               IFX_DEBUGPL(DBG_HCDV, "   xferlen: %d\n"   , ifxhc->xfer_len);
1958 +                       }
1959 +                       ifxusb_wreg(&hc_regs->hcsplt, hcsplt.d32);
1960 +               }
1961 +       }
1962 +
1963 +       ifxhc->nak_retry_r=ifxhc->nak_retry=0;
1964 +       ifxhc->nak_countdown_r=ifxhc->nak_countdown=0;
1965 +
1966 +       if (ifxhc->split)
1967 +       {
1968 +               if(ifxhc->is_in)
1969 +               {
1970 +               }
1971 +               else
1972 +               {
1973 +               }
1974 +       }
1975 +       else if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL)
1976 +       {
1977 +               if(ifxhc->is_in)
1978 +               {
1979 +               }
1980 +               else
1981 +               {
1982 +               }
1983 +       }
1984 +       else if(_epqh->ep_type==IFXUSB_EP_TYPE_BULK)
1985 +       {
1986 +               if(ifxhc->is_in)
1987 +               {
1988 +//                     ifxhc->nak_retry_r=ifxhc->nak_retry=nak_retry_max;
1989 +//                     ifxhc->nak_countdown_r=ifxhc->nak_countdown=nak_countdown_max;
1990 +               }
1991 +               else
1992 +               {
1993 +               }
1994 +       }
1995 +       else if(_epqh->ep_type==IFXUSB_EP_TYPE_INTR)
1996 +       {
1997 +               if(ifxhc->is_in)
1998 +               {
1999 +               }
2000 +               else
2001 +               {
2002 +               }
2003 +       }
2004 +       else if(_epqh->ep_type==IFXUSB_EP_TYPE_ISOC)
2005 +       {
2006 +               if(ifxhc->is_in)
2007 +               {
2008 +               }
2009 +               else
2010 +               {
2011 +               }
2012 +       }
2013 +
2014 +       return 1;
2015 +}
2016 +
2017 +/*!
2018 + \brief This function selects transactions from the HCD transfer schedule and
2019 +  assigns them to available host channels. It is called from HCD interrupt
2020 +  handler functions.
2021 + */
2022 +static void select_eps_sub(ifxhcd_hcd_t *_ifxhcd)
2023 +{
2024 +       struct list_head *epqh_ptr;
2025 +       struct list_head *urbd_ptr;
2026 +       ifxhcd_epqh_t    *epqh;
2027 +       ifxhcd_urbd_t    *urbd;
2028 +       int               ret_val=0;
2029 +
2030 +       /*== AVM/BC 20101111 Function called with Lock ==*/
2031 +
2032 +//     #ifdef __DEBUG__
2033 +//             IFX_DEBUGPL(DBG_HCD, "  ifxhcd_select_ep\n");
2034 +//     #endif
2035 +
2036 +       /* Process entries in the periodic ready list. */
2037 +       #ifdef __EN_ISOC__
2038 +               epqh_ptr       = _ifxhcd->epqh_isoc_ready.next;
2039 +               while (epqh_ptr != &_ifxhcd->epqh_isoc_ready && !list_empty(&_ifxhcd->free_hc_list))
2040 +               {
2041 +                       epqh = list_entry(epqh_ptr, ifxhcd_epqh_t, epqh_list_entry);
2042 +                       epqh_ptr = epqh_ptr->next;
2043 +                       if(epqh->period_do)
2044 +                       {
2045 +                               if(assign_and_init_hc(_ifxhcd, epqh))
2046 +                               {
2047 +                                       IFX_DEBUGPL(DBG_HCD, "  select_eps ISOC\n");
2048 +                                       list_move_tail(&epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_active);
2049 +                                       epqh->is_active=1;
2050 +                                       ret_val=1;
2051 +                                       epqh->period_do=0;
2052 +                               }
2053 +                       }
2054 +               }
2055 +       #endif
2056 +
2057 +       epqh_ptr       = _ifxhcd->epqh_intr_ready.next;
2058 +       while (epqh_ptr != &_ifxhcd->epqh_intr_ready && !list_empty(&_ifxhcd->free_hc_list))
2059 +       {
2060 +               epqh = list_entry(epqh_ptr, ifxhcd_epqh_t, epqh_list_entry);
2061 +               epqh_ptr = epqh_ptr->next;
2062 +               if(epqh->period_do)
2063 +               {
2064 +                       if(assign_and_init_hc(_ifxhcd, epqh))
2065 +                       {
2066 +                               IFX_DEBUGPL(DBG_HCD, "  select_eps INTR\n");
2067 +                               list_move_tail(&epqh->epqh_list_entry, &_ifxhcd->epqh_intr_active);
2068 +                               epqh->is_active=1;
2069 +                               ret_val=1;
2070 +                               epqh->period_do=0;
2071 +                       }
2072 +               }
2073 +       }
2074 +
2075 +       epqh_ptr       = _ifxhcd->epqh_np_ready.next;
2076 +       while (epqh_ptr != &_ifxhcd->epqh_np_ready && !list_empty(&_ifxhcd->free_hc_list))  // may need to preserve at lease one for period
2077 +       {
2078 +               epqh = list_entry(epqh_ptr, ifxhcd_epqh_t, epqh_list_entry);
2079 +               epqh_ptr = epqh_ptr->next;
2080 +               if(assign_and_init_hc(_ifxhcd, epqh))
2081 +               {
2082 +                       IFX_DEBUGPL(DBG_HCD, "  select_eps CTRL/BULK\n");
2083 +                       list_move_tail(&epqh->epqh_list_entry, &_ifxhcd->epqh_np_active);
2084 +                       epqh->is_active=1;
2085 +                       ret_val=1;
2086 +               }
2087 +       }
2088 +       if(ret_val)
2089 +               /*== AVM/BC 20101111 Function called with Lock ==*/
2090 +               process_channels_sub(_ifxhcd);
2091 +
2092 +       /* AVM/BC 20101111 Urbds completion loop */
2093 +       while (!list_empty(&_ifxhcd->urbd_complete_list))
2094 +       {
2095 +               urbd_ptr = _ifxhcd->urbd_complete_list.next;
2096 +               list_del_init(urbd_ptr);
2097 +
2098 +               urbd = list_entry(urbd_ptr, ifxhcd_urbd_t, urbd_list_entry);
2099 +
2100 +               ifxhcd_complete_urb(_ifxhcd, urbd, urbd->status);
2101 +
2102 +       }
2103 +
2104 +}
2105 +
2106 +static void select_eps_func(unsigned long data)
2107 +{
2108 +       unsigned long flags;
2109 +
2110 +       ifxhcd_hcd_t *ifxhcd;
2111 +       ifxhcd=((ifxhcd_hcd_t *)data);
2112 +
2113 +       /* AVM/BC 20101111 select_eps_in_use flag removed */
2114 +
2115 +       SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags);
2116 +
2117 +       /*if(ifxhcd->select_eps_in_use){
2118 +               SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags);
2119 +               return;
2120 +       }
2121 +       ifxhcd->select_eps_in_use=1;
2122 +       */
2123 +
2124 +       select_eps_sub(ifxhcd);
2125 +
2126 +       //ifxhcd->select_eps_in_use=0;
2127 +
2128 +       SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags);
2129 +}
2130 +
2131 +void select_eps(ifxhcd_hcd_t *_ifxhcd)
2132 +{
2133 +       if(in_irq())
2134 +       {
2135 +               if(!_ifxhcd->select_eps.func)
2136 +               {
2137 +                       _ifxhcd->select_eps.next = NULL;
2138 +                       _ifxhcd->select_eps.state = 0;
2139 +                       atomic_set( &_ifxhcd->select_eps.count, 0);
2140 +                       _ifxhcd->select_eps.func = select_eps_func;
2141 +                       _ifxhcd->select_eps.data = (unsigned long)_ifxhcd;
2142 +               }
2143 +               tasklet_schedule(&_ifxhcd->select_eps);
2144 +       }
2145 +       else
2146 +       {
2147 +               unsigned long flags;
2148 +
2149 +               /* AVM/BC 20101111 select_eps_in_use flag removed */
2150 +
2151 +               SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
2152 +
2153 +               /*if(_ifxhcd->select_eps_in_use){
2154 +                       printk ("select_eps non_irq: busy\n");
2155 +                       SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
2156 +                       return;
2157 +               }
2158 +               _ifxhcd->select_eps_in_use=1;
2159 +               */
2160 +
2161 +               select_eps_sub(_ifxhcd);
2162 +
2163 +               //_ifxhcd->select_eps_in_use=0;
2164 +
2165 +               SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
2166 +       }
2167 +}
2168 +
2169 +/*!
2170 + \brief
2171 + */
2172 +static void process_unaligned( ifxhcd_epqh_t *_epqh)
2173 +{
2174 +       #if   defined(__UNALIGNED_BUFFER_ADJ__)
2175 +               if(!_epqh->aligned_checked)
2176 +               {
2177 +                       uint32_t xfer_len;
2178 +                       xfer_len=_epqh->urbd->xfer_len;
2179 +                       if(_epqh->urbd->is_in && xfer_len<_epqh->mps)
2180 +                               xfer_len = _epqh->mps;
2181 +                       _epqh->using_aligned_buf=0;
2182 +
2183 +                       if(xfer_len > 0 && ((unsigned long)_epqh->urbd->xfer_buff) & 3)
2184 +                       {
2185 +                               if(   _epqh->aligned_buf
2186 +                                  && _epqh->aligned_buf_len > 0
2187 +                                  && _epqh->aligned_buf_len < xfer_len
2188 +                                 )
2189 +                               {
2190 +                                       ifxusb_free_buf(_epqh->aligned_buf);
2191 +                                       _epqh->aligned_buf=NULL;
2192 +                                       _epqh->aligned_buf_len=0;
2193 +                               }
2194 +                               if(! _epqh->aligned_buf || ! _epqh->aligned_buf_len)
2195 +                               {
2196 +                                       _epqh->aligned_buf = ifxusb_alloc_buf(xfer_len, _epqh->urbd->is_in);
2197 +                                       if(_epqh->aligned_buf)
2198 +                                               _epqh->aligned_buf_len = xfer_len;
2199 +                               }
2200 +                               if(_epqh->aligned_buf)
2201 +                               {
2202 +                                       if(!_epqh->urbd->is_in)
2203 +                                               memcpy(_epqh->aligned_buf, _epqh->urbd->xfer_buff, xfer_len);
2204 +                                       _epqh->using_aligned_buf=1;
2205 +                                       _epqh->hc->xfer_buff = _epqh->aligned_buf;
2206 +                               }
2207 +                               else
2208 +                                       IFX_WARN("%s():%d\n",__func__,__LINE__);
2209 +                       }
2210 +                       if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL)
2211 +                       {
2212 +                               _epqh->using_aligned_setup=0;
2213 +                               if(((unsigned long)_epqh->urbd->setup_buff) & 3)
2214 +                               {
2215 +                                       if(! _epqh->aligned_setup)
2216 +                                               _epqh->aligned_setup = ifxusb_alloc_buf(8,0);
2217 +                                       if(_epqh->aligned_setup)
2218 +                                       {
2219 +                                               memcpy(_epqh->aligned_setup, _epqh->urbd->setup_buff, 8);
2220 +                                               _epqh->using_aligned_setup=1;
2221 +                                       }
2222 +                                       else
2223 +                                               IFX_WARN("%s():%d\n",__func__,__LINE__);
2224 +                                       _epqh->hc->xfer_buff = _epqh->aligned_setup;
2225 +                               }
2226 +                       }
2227 +               }
2228 +       #elif defined(__UNALIGNED_BUFFER_CHK__)
2229 +               if(!_epqh->aligned_checked)
2230 +               {
2231 +                       if(_epqh->urbd->is_in)
2232 +                       {
2233 +                               if(_epqh->urbd->xfer_len==0)
2234 +                                       IFX_WARN("%s():%d IN xfer while length is zero \n",__func__,__LINE__);
2235 +                               else{
2236 +                                       if(_epqh->urbd->xfer_len < _epqh->mps)
2237 +                                               IFX_WARN("%s():%d IN xfer while length < mps \n",__func__,__LINE__);
2238 +
2239 +                                       if(((unsigned long)_epqh->urbd->xfer_buff) & 3)
2240 +                                               IFX_WARN("%s():%d IN xfer Buffer UNALIGNED\n",__func__,__LINE__);
2241 +                               }
2242 +                       }
2243 +                       else
2244 +                       {
2245 +                               if(_epqh->urbd->xfer_len > 0 && (((unsigned long)_epqh->urbd->xfer_buff) & 3) )
2246 +                                       IFX_WARN("%s():%d OUT xfer Buffer UNALIGNED\n",__func__,__LINE__);
2247 +                       }
2248 +
2249 +                       if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL)
2250 +                       {
2251 +                               if(((unsigned long)_epqh->urbd->setup_buff) & 3)
2252 +                                       IFX_WARN("%s():%d SETUP xfer Buffer UNALIGNED\n",__func__,__LINE__);
2253 +                       }
2254 +               }
2255 +       #endif
2256 +       _epqh->aligned_checked=1;
2257 +}
2258 +
2259 +
2260 +/*!
2261 + \brief
2262 + */
2263 +void process_channels_sub(ifxhcd_hcd_t *_ifxhcd)
2264 +{
2265 +       ifxhcd_epqh_t    *epqh;
2266 +       struct list_head *epqh_item;
2267 +       struct ifxhcd_hc *hc;
2268 +
2269 +       #ifdef __EN_ISOC__
2270 +               if (!list_empty(&_ifxhcd->epqh_isoc_active))
2271 +               {
2272 +                       for (epqh_item  =  _ifxhcd->epqh_isoc_active.next;
2273 +                            epqh_item != &_ifxhcd->epqh_isoc_active;
2274 +                            )
2275 +                       {
2276 +                               epqh = list_entry(epqh_item, ifxhcd_epqh_t, epqh_list_entry);
2277 +                               epqh_item  =  epqh_item->next;
2278 +                               hc=epqh->hc;
2279 +                               if(hc && !hc->xfer_started && epqh->period_do)
2280 +                               {
2281 +                                       if(hc->split==0
2282 +                                           || hc->split==1
2283 +                                          )
2284 +                                       {
2285 +                                               //epqh->ping_state = 0;
2286 +                                               process_unaligned(epqh);
2287 +                                               hc->wait_for_sof=epqh->wait_for_sof;
2288 +                                               epqh->wait_for_sof=0;
2289 +                                               ifxhcd_hc_start(&_ifxhcd->core_if, hc);
2290 +                                               epqh->period_do=0;
2291 +                                               {
2292 +                                                       gint_data_t gintsts = {.d32 = 0};
2293 +                                                       gintsts.b.sofintr = 1;
2294 +                                                       ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk,0, gintsts.d32);
2295 +                                               }
2296 +                                       }
2297 +                               }
2298 +                       }
2299 +               }
2300 +       #endif
2301 +
2302 +       if (!list_empty(&_ifxhcd->epqh_intr_active))
2303 +       {
2304 +               for (epqh_item  =  _ifxhcd->epqh_intr_active.next;
2305 +                    epqh_item != &_ifxhcd->epqh_intr_active;
2306 +                    )
2307 +               {
2308 +                       epqh = list_entry(epqh_item, ifxhcd_epqh_t, epqh_list_entry);
2309 +                       epqh_item  =  epqh_item->next;
2310 +                       hc=epqh->hc;
2311 +                       if(hc && !hc->xfer_started && epqh->period_do)
2312 +                       {
2313 +                               if(hc->split==0
2314 +                                   || hc->split==1
2315 +                                  )
2316 +                               {
2317 +                                       //epqh->ping_state = 0;
2318 +                                       process_unaligned(epqh);
2319 +                                       hc->wait_for_sof=epqh->wait_for_sof;
2320 +                                       epqh->wait_for_sof=0;
2321 +                                       ifxhcd_hc_start(&_ifxhcd->core_if, hc);
2322 +                                       epqh->period_do=0;
2323 +#ifdef __USE_TIMER_4_SOF__
2324 +                                       /* AVM/WK change: let hc_start decide, if irq is needed */
2325 +#else
2326 +                                       {
2327 +                                               gint_data_t gintsts = {.d32 = 0};
2328 +                                               gintsts.b.sofintr = 1;
2329 +                                               ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk,0, gintsts.d32);
2330 +                                       }
2331 +#endif
2332 +                               }
2333 +                       }
2334 +
2335 +               }
2336 +       }
2337 +
2338 +       if (!list_empty(&_ifxhcd->epqh_np_active))
2339 +       {
2340 +               for (epqh_item  =  _ifxhcd->epqh_np_active.next;
2341 +                    epqh_item != &_ifxhcd->epqh_np_active;
2342 +                    )
2343 +               {
2344 +                       epqh = list_entry(epqh_item, ifxhcd_epqh_t, epqh_list_entry);
2345 +                       epqh_item  =  epqh_item->next;
2346 +                       hc=epqh->hc;
2347 +                       if(hc)
2348 +                       {
2349 +                               if(!hc->xfer_started)
2350 +                               {
2351 +                                       if(hc->split==0
2352 +                                           || hc->split==1
2353 +                                         //|| hc->split_counter == 0
2354 +                                          )
2355 +                                       {
2356 +                                               //epqh->ping_state = 0;
2357 +                                               process_unaligned(epqh);
2358 +                                               hc->wait_for_sof=epqh->wait_for_sof;
2359 +                                               epqh->wait_for_sof=0;
2360 +                                               ifxhcd_hc_start(&_ifxhcd->core_if, hc);
2361 +                                       }
2362 +                               }
2363 +                       }
2364 +               }
2365 +       }
2366 +}
2367 +
2368 +void process_channels(ifxhcd_hcd_t *_ifxhcd)
2369 +{
2370 +       unsigned long flags;
2371 +
2372 +       /* AVM/WK Fix: use spin_lock instead busy flag
2373 +       **/
2374 +       SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
2375 +
2376 +       //if(_ifxhcd->process_channels_in_use)
2377 +       //      return;
2378 +       //_ifxhcd->process_channels_in_use=1;
2379 +
2380 +       process_channels_sub(_ifxhcd);
2381 +       //_ifxhcd->process_channels_in_use=0;
2382 +       SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
2383 +}
2384 +
2385 +
2386 +#ifdef __HC_XFER_TIMEOUT__
2387 +       static void hc_xfer_timeout(unsigned long _ptr)
2388 +       {
2389 +               hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)_ptr;
2390 +               int hc_num = xfer_info->hc->hc_num;
2391 +               IFX_WARN("%s: timeout on channel %d\n", __func__, hc_num);
2392 +               IFX_WARN("  start_hcchar_val 0x%08x\n", xfer_info->hc->start_hcchar_val);
2393 +       }
2394 +#endif
2395 +
2396 +void ifxhcd_hc_dumb_rx(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc,uint8_t   *dump_buf)
2397 +{
2398 +       ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[_ifxhc->hc_num];
2399 +       hctsiz_data_t hctsiz= { .d32=0 };
2400 +       hcchar_data_t hcchar;
2401 +
2402 +
2403 +       _ifxhc->xfer_len = _ifxhc->mps;
2404 +       hctsiz.b.xfersize = _ifxhc->mps;
2405 +       hctsiz.b.pktcnt   = 0;
2406 +       hctsiz.b.pid      = _ifxhc->data_pid_start;
2407 +       ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
2408 +
2409 +       ifxusb_wreg(&hc_regs->hcdma, (uint32_t)(CPHYSADDR( ((uint32_t)(dump_buf)))));
2410 +
2411 +       {
2412 +               hcint_data_t hcint= { .d32=0 };
2413 +//             hcint.b.nak =1;
2414 +//             hcint.b.nyet=1;
2415 +//             hcint.b.ack =1;
2416 +               hcint.d32 =0xFFFFFFFF;
2417 +               ifxusb_wreg(&hc_regs->hcint, hcint.d32);
2418 +       }
2419 +
2420 +       /* Set host channel enable after all other setup is complete. */
2421 +       hcchar.b.chen  = 1;
2422 +       hcchar.b.chdis = 0;
2423 +       hcchar.b.epdir = 1;
2424 +       IFX_DEBUGPL(DBG_HCDV, "  HCCHART: 0x%08x\n", hcchar.d32);
2425 +       ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
2426 +}
2427 +
2428 +/*!
2429 +   \brief This function trigger a data transfer for a host channel and
2430 +  starts the transfer.
2431 +
2432 +  For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
2433 +  register along with a packet count of 1 and the channel is enabled. This
2434 +  causes a single PING transaction to occur. Other fields in HCTSIZ are
2435 +  simply set to 0 since no data transfer occurs in this case.
2436 +
2437 +  For a PING transfer in DMA mode, the HCTSIZ register is initialized with
2438 +  all the information required to perform the subsequent data transfer. In
2439 +  addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
2440 +  controller performs the entire PING protocol, then starts the data
2441 +  transfer.
2442 +  \param _core_if        Pointer of core_if structure
2443 +  \param _ifxhc Information needed to initialize the host channel. The xfer_len
2444 +  value may be reduced to accommodate the max widths of the XferSize and
2445 +  PktCnt fields in the HCTSIZn register. The multi_count value may be changed
2446 +  to reflect the final xfer_len value.
2447 + */
2448 +void ifxhcd_hc_start(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc)
2449 +{
2450 +       hctsiz_data_t hctsiz= { .d32=0 };
2451 +       hcchar_data_t hcchar;
2452 +       uint32_t max_hc_xfer_size = _core_if->params.max_transfer_size;
2453 +       uint16_t max_hc_pkt_count = _core_if->params.max_packet_count;
2454 +       ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[_ifxhc->hc_num];
2455 +       hfnum_data_t hfnum;
2456 +
2457 +       hctsiz.b.dopng = 0;
2458 +//     if(_ifxhc->do_ping && !_ifxhc->is_in) hctsiz.b.dopng = 1;
2459 +
2460 +       _ifxhc->nak_countdown=_ifxhc->nak_countdown_r;
2461 +
2462 +       /* AVM/BC 20101111 Workaround: Always PING if HI-Speed Out and xfer_len > 0 */
2463 +       if(/*_ifxhc->do_ping &&*/
2464 +               (!_ifxhc->is_in) &&
2465 +               (_ifxhc->speed == IFXUSB_EP_SPEED_HIGH) &&
2466 +               ((_ifxhc->ep_type == IFXUSB_EP_TYPE_BULK) || ((_ifxhc->ep_type == IFXUSB_EP_TYPE_CTRL) && (_ifxhc->control_phase != IFXHCD_CONTROL_SETUP))) &&
2467 +               _ifxhc->xfer_len
2468 +               )
2469 +               hctsiz.b.dopng = 1;
2470 +
2471 +       _ifxhc->xfer_started = 1;
2472 +
2473 +       if(_ifxhc->epqh->pkt_count_limit > 0 && _ifxhc->epqh->pkt_count_limit < max_hc_pkt_count )
2474 +       {
2475 +               max_hc_pkt_count=_ifxhc->epqh->pkt_count_limit;
2476 +               if(max_hc_pkt_count * _ifxhc->mps <  max_hc_xfer_size)
2477 +                       max_hc_xfer_size = max_hc_pkt_count * _ifxhc->mps;
2478 +       }
2479 +       if (_ifxhc->split > 0)
2480 +       {
2481 +               {
2482 +                       gint_data_t gintsts = {.d32 = 0};
2483 +                       gintsts.b.sofintr = 1;
2484 +                       ifxusb_mreg(&_core_if->core_global_regs->gintmsk,0, gintsts.d32);
2485 +               }
2486 +
2487 +               _ifxhc->start_pkt_count = 1;
2488 +               if(!_ifxhc->is_in && _ifxhc->split>1) // OUT CSPLIT
2489 +                       _ifxhc->xfer_len = 0;
2490 +               if (_ifxhc->xfer_len > _ifxhc->mps)
2491 +                       _ifxhc->xfer_len = _ifxhc->mps;
2492 +               if (_ifxhc->xfer_len > 188)
2493 +                       _ifxhc->xfer_len = 188;
2494 +       }
2495 +       else if(_ifxhc->is_in)
2496 +       {
2497 +               _ifxhc->short_rw = 0;
2498 +               if (_ifxhc->xfer_len > 0)
2499 +               {
2500 +                       if (_ifxhc->xfer_len > max_hc_xfer_size)
2501 +                               _ifxhc->xfer_len = max_hc_xfer_size - _ifxhc->mps + 1;
2502 +                       _ifxhc->start_pkt_count = (_ifxhc->xfer_len + _ifxhc->mps - 1) / _ifxhc->mps;
2503 +                       if (_ifxhc->start_pkt_count > max_hc_pkt_count)
2504 +                               _ifxhc->start_pkt_count = max_hc_pkt_count;
2505 +               }
2506 +               else /* Need 1 packet for transfer length of 0. */
2507 +                       _ifxhc->start_pkt_count = 1;
2508 +               _ifxhc->xfer_len = _ifxhc->start_pkt_count * _ifxhc->mps;
2509 +       }
2510 +       else //non-split out
2511 +       {
2512 +               if (_ifxhc->xfer_len == 0)
2513 +               {
2514 +                       /*== AVM/BC WK 20110421 ZERO PACKET Workaround: Is not an error ==*/
2515 +                       //if(_ifxhc->short_rw==0)
2516 +                       //      printk(KERN_INFO "%s() line %d: ZLP write without short_rw set!\n",__func__,__LINE__);
2517 +                       _ifxhc->start_pkt_count = 1;
2518 +               }
2519 +               else
2520 +               {
2521 +                       if (_ifxhc->xfer_len > max_hc_xfer_size)
2522 +                       {
2523 +                               _ifxhc->start_pkt_count = (max_hc_xfer_size / _ifxhc->mps);
2524 +                               _ifxhc->xfer_len = _ifxhc->start_pkt_count * _ifxhc->mps;
2525 +                       }
2526 +                       else
2527 +                       {
2528 +                               _ifxhc->start_pkt_count = (_ifxhc->xfer_len+_ifxhc->mps-1)  / _ifxhc->mps;
2529 +//                             if(_ifxhc->start_pkt_count * _ifxhc->mps == _ifxhc->xfer_len )
2530 +//                                     _ifxhc->start_pkt_count += _ifxhc->short_rw;
2531 +                               /*== AVM/BC WK 20110421 ZERO PACKET Workaround / check if short_rw is needed ==*/
2532 +                               if(_ifxhc->start_pkt_count * _ifxhc->mps != _ifxhc->xfer_len )
2533 +                                       _ifxhc->short_rw = 0;
2534 +                       }
2535 +               }
2536 +       }
2537 +
2538 +       #ifdef __EN_ISOC__
2539 +               if (_ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC)
2540 +               {
2541 +                       /* Set up the initial PID for the transfer. */
2542 +                       #if 1
2543 +                               _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0;
2544 +                       #else
2545 +                               if (_ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
2546 +                               {
2547 +                                       if (_ifxhc->is_in)
2548 +                                       {
2549 +                                               if      (_ifxhc->multi_count == 1)
2550 +                                                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0;
2551 +                                               else if (_ifxhc->multi_count == 2)
2552 +                                                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1;
2553 +                                               else
2554 +                                                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA2;
2555 +                                       }
2556 +                                       else
2557 +                                       {
2558 +                                               if (_ifxhc->multi_count == 1)
2559 +                                                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0;
2560 +                                               else
2561 +                                                       _ifxhc->data_pid_start = IFXUSB_HC_PID_MDATA;
2562 +                                       }
2563 +                               }
2564 +                               else
2565 +                                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0;
2566 +                       #endif
2567 +               }
2568 +       #endif
2569 +
2570 +       hctsiz.b.xfersize = _ifxhc->xfer_len;
2571 +       hctsiz.b.pktcnt   = _ifxhc->start_pkt_count;
2572 +       hctsiz.b.pid      = _ifxhc->data_pid_start;
2573 +
2574 +       ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
2575 +
2576 +
2577 +       IFX_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _ifxhc->hc_num);
2578 +       IFX_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
2579 +       IFX_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n" , hctsiz.b.pktcnt);
2580 +       IFX_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
2581 +       IFX_DEBUGPL(DBG_HCDV, "  DMA: 0x%08x\n", (uint32_t)(CPHYSADDR( ((uint32_t)(_ifxhc->xfer_buff))+ _ifxhc->xfer_count )));
2582 +       ifxusb_wreg(&hc_regs->hcdma, (uint32_t)(CPHYSADDR( ((uint32_t)(_ifxhc->xfer_buff))+ _ifxhc->xfer_count )));
2583 +
2584 +       /* Start the split */
2585 +       if (_ifxhc->split>0)
2586 +       {
2587 +               hcsplt_data_t hcsplt;
2588 +               hcsplt.d32 = ifxusb_rreg (&hc_regs->hcsplt);
2589 +               hcsplt.b.spltena = 1;
2590 +               if (_ifxhc->split>1)
2591 +                       hcsplt.b.compsplt = 1;
2592 +               else
2593 +                       hcsplt.b.compsplt = 0;
2594 +
2595 +               #ifdef __EN_ISOC__
2596 +                       if (_ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC)
2597 +                               hcsplt.b.xactpos = _ifxhc->isoc_xact_pos;
2598 +                       else
2599 +               #endif
2600 +               hcsplt.b.xactpos = IFXUSB_HCSPLIT_XACTPOS_ALL;// if not ISO
2601 +               ifxusb_wreg(&hc_regs->hcsplt, hcsplt.d32);
2602 +               IFX_DEBUGPL(DBG_HCDV, "  SPLIT: XACT_POS:0x%08x\n", hcsplt.d32);
2603 +       }
2604 +
2605 +       hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
2606 +//     hcchar.b.multicnt = _ifxhc->multi_count;
2607 +       hcchar.b.multicnt = 1;
2608 +
2609 +       #ifdef __DEBUG__
2610 +               _ifxhc->start_hcchar_val = hcchar.d32;
2611 +               if (hcchar.b.chdis)
2612 +                       IFX_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2613 +                                __func__, _ifxhc->hc_num, hcchar.d32);
2614 +       #endif
2615 +
2616 +       /* Set host channel enable after all other setup is complete. */
2617 +       hcchar.b.chen  = 1;
2618 +       hcchar.b.chdis = 0;
2619 +       hcchar.b.epdir =  _ifxhc->is_in;
2620 +       _ifxhc->hcchar=hcchar.d32;
2621 +
2622 +       IFX_DEBUGPL(DBG_HCDV, "  HCCHART: 0x%08x\n", _ifxhc->hcchar);
2623 +
2624 +       /* == 20110901 AVM/WK Fix: Clear IRQ flags in any case ==*/
2625 +       {
2626 +               hcint_data_t hcint= { .d32=0 };
2627 +               hcint.d32 =0xFFFFFFFF;
2628 +               ifxusb_wreg(&hc_regs->hcint, hcint.d32);
2629 +       }
2630 +
2631 +       if(_ifxhc->wait_for_sof==0)
2632 +       {
2633 +               hcint_data_t hcint;
2634 +
2635 +               hcint.d32=ifxusb_rreg(&hc_regs->hcintmsk);
2636 +
2637 +               hcint.b.nak =0;
2638 +               hcint.b.ack =0;
2639 +               /* == 20110901 AVM/WK Fix: We don't need NOT YET IRQ ==*/
2640 +               hcint.b.nyet=0;
2641 +               if(_ifxhc->nak_countdown_r)
2642 +                       hcint.b.nak =1;
2643 +               ifxusb_wreg(&hc_regs->hcintmsk, hcint.d32);
2644 +
2645 +               /* AVM WK / BC 20100827
2646 +                * MOVED. Oddframe updated inmediatly before write HCChar Register.
2647 +                */
2648 +               if (_ifxhc->ep_type == IFXUSB_EP_TYPE_INTR || _ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC)
2649 +               {
2650 +                       hfnum.d32 = ifxusb_rreg(&_core_if->host_global_regs->hfnum);
2651 +                       /* 1 if _next_ frame is odd, 0 if it's even */
2652 +                       hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
2653 +                       _ifxhc->hcchar=hcchar.d32;
2654 +               }
2655 +
2656 +               ifxusb_wreg(&hc_regs->hcchar, _ifxhc->hcchar);
2657 +#ifdef __USE_TIMER_4_SOF__
2658 +       } else {
2659 +               //activate SOF IRQ
2660 +               gint_data_t gintsts = {.d32 = 0};
2661 +               gintsts.b.sofintr = 1;
2662 +               ifxusb_mreg(&_core_if->core_global_regs->gintmsk,0, gintsts.d32);
2663 +#endif
2664 +       }
2665 +
2666 +       #ifdef __HC_XFER_TIMEOUT__
2667 +               /* Start a timer for this transfer. */
2668 +               init_timer(&_ifxhc->hc_xfer_timer);
2669 +               _ifxhc->hc_xfer_timer.function = hc_xfer_timeout;
2670 +               _ifxhc->hc_xfer_timer.core_if = _core_if;
2671 +               _ifxhc->hc_xfer_timer.hc = _ifxhc;
2672 +               _ifxhc->hc_xfer_timer.data = (unsigned long)(&_ifxhc->hc_xfer_info);
2673 +               _ifxhc->hc_xfer_timer.expires = jiffies + (HZ*10);
2674 +               add_timer(&_ifxhc->hc_xfer_timer);
2675 +       #endif
2676 +}
2677 +
2678 +/*!
2679 +   \brief Attempts to halt a host channel. This function should only be called
2680 +  to abort a transfer in DMA mode. Under normal circumstances in DMA mode, the
2681 +  controller halts the channel when the transfer is complete or a condition
2682 +  occurs that requires application intervention.
2683 +
2684 +  In DMA mode, always sets the Channel Enable and Channel Disable bits of the
2685 +  HCCHARn register. The controller ensures there is space in the request
2686 +  queue before submitting the halt request.
2687 +
2688 +  Some time may elapse before the core flushes any posted requests for this
2689 +  host channel and halts. The Channel Halted interrupt handler completes the
2690 +  deactivation of the host channel.
2691 + */
2692 +void ifxhcd_hc_halt(ifxusb_core_if_t *_core_if,
2693 +                    ifxhcd_hc_t *_ifxhc,
2694 +                    ifxhcd_halt_status_e _halt_status)
2695 +{
2696 +       hcchar_data_t   hcchar;
2697 +       ifxusb_hc_regs_t           *hc_regs;
2698 +
2699 +       hc_regs          = _core_if->hc_regs[_ifxhc->hc_num];
2700 +
2701 +       WARN_ON(_halt_status == HC_XFER_NO_HALT_STATUS);
2702 +
2703 +       if (_halt_status == HC_XFER_URB_DEQUEUE ||
2704 +           _halt_status == HC_XFER_AHB_ERR)
2705 +       {
2706 +               /*
2707 +                * Disable all channel interrupts except Ch Halted. The URBD
2708 +                * and EPQH state associated with this transfer has been cleared
2709 +                * (in the case of URB_DEQUEUE), so the channel needs to be
2710 +                * shut down carefully to prevent crashes.
2711 +                */
2712 +               hcint_data_t hcintmsk;
2713 +               hcintmsk.d32 = 0;
2714 +               hcintmsk.b.chhltd = 1;
2715 +               ifxusb_wreg(&hc_regs->hcintmsk, hcintmsk.d32);
2716 +
2717 +               /*
2718 +                * Make sure no other interrupts besides halt are currently
2719 +                * pending. Handling another interrupt could cause a crash due
2720 +                * to the URBD and EPQH state.
2721 +                */
2722 +               ifxusb_wreg(&hc_regs->hcint, ~hcintmsk.d32);
2723 +
2724 +               /*
2725 +                * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
2726 +                * even if the channel was already halted for some other
2727 +                * reason.
2728 +                */
2729 +               _ifxhc->halt_status = _halt_status;
2730 +
2731 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
2732 +               if (hcchar.b.chen == 0)
2733 +               {
2734 +                       /*
2735 +                        * The channel is either already halted or it hasn't
2736 +                        * started yet. In DMA mode, the transfer may halt if
2737 +                        * it finishes normally or a condition occurs that
2738 +                        * requires driver intervention. Don't want to halt
2739 +                        * the channel again. In either Slave or DMA mode,
2740 +                        * it's possible that the transfer has been assigned
2741 +                        * to a channel, but not started yet when an URB is
2742 +                        * dequeued. Don't want to halt a channel that hasn't
2743 +                        * started yet.
2744 +                        */
2745 +                       return;
2746 +               }
2747 +       }
2748 +
2749 +       if (_ifxhc->halting)
2750 +       {
2751 +               /*
2752 +                * A halt has already been issued for this channel. This might
2753 +                * happen when a transfer is aborted by a higher level in
2754 +                * the stack.
2755 +                */
2756 +               #ifdef __DEBUG__
2757 +                       IFX_PRINT("*** %s: Channel %d, _hc->halting already set ***\n",
2758 +                                 __func__, _ifxhc->hc_num);
2759 +               #endif
2760 +               //ifxusb_dump_global_registers(_core_if); */
2761 +               //ifxusb_dump_host_registers(_core_if); */
2762 +               return;
2763 +       }
2764 +       hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
2765 +       /* == AVM/WK 20100709 halt channel only if enabled ==*/
2766 +       if (hcchar.b.chen) {
2767 +               _ifxhc->halting = 1;
2768 +               hcchar.b.chdis = 1;
2769 +
2770 +               ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
2771 +               _ifxhc->halt_status = _halt_status;
2772 +       }
2773 +
2774 +       IFX_DEBUGPL(DBG_HCDV, "%s: Channel %d\n" , __func__, _ifxhc->hc_num);
2775 +       IFX_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n"   , hcchar.d32);
2776 +       IFX_DEBUGPL(DBG_HCDV, "  halting: %d\n" , _ifxhc->halting);
2777 +       IFX_DEBUGPL(DBG_HCDV, "  halt_status: %d\n"  , _ifxhc->halt_status);
2778 +
2779 +       return;
2780 +}
2781 +
2782 +/*!
2783 +   \brief Clears a host channel.
2784 + */
2785 +void ifxhcd_hc_cleanup(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc)
2786 +{
2787 +       ifxusb_hc_regs_t *hc_regs;
2788 +
2789 +       _ifxhc->xfer_started = 0;
2790 +       /*
2791 +        * Clear channel interrupt enables and any unhandled channel interrupt
2792 +        * conditions.
2793 +        */
2794 +       hc_regs = _core_if->hc_regs[_ifxhc->hc_num];
2795 +       ifxusb_wreg(&hc_regs->hcintmsk, 0);
2796 +       ifxusb_wreg(&hc_regs->hcint, 0xFFFFFFFF);
2797 +
2798 +       #ifdef __HC_XFER_TIMEOUT__
2799 +               del_timer(&_ifxhc->hc_xfer_timer);
2800 +       #endif
2801 +       #ifdef __DEBUG__
2802 +               {
2803 +                       hcchar_data_t hcchar;
2804 +                       hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
2805 +                       if (hcchar.b.chdis)
2806 +                               IFX_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", __func__, _ifxhc->hc_num, hcchar.d32);
2807 +               }
2808 +       #endif
2809 +}
2810 +
2811 +
2812 +
2813 +
2814 +
2815 +
2816 +
2817 +
2818 +#ifdef __DEBUG__
2819 +       static void dump_urb_info(struct urb *_urb, char* _fn_name)
2820 +       {
2821 +               IFX_PRINT("%s, urb %p\n"          , _fn_name, _urb);
2822 +               IFX_PRINT("  Device address: %d\n", usb_pipedevice(_urb->pipe));
2823 +               IFX_PRINT("  Endpoint: %d, %s\n"  , usb_pipeendpoint(_urb->pipe),
2824 +                                                   (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
2825 +               IFX_PRINT("  Endpoint type: %s\n",
2826 +                   ({  char *pipetype;
2827 +                       switch (usb_pipetype(_urb->pipe)) {
2828 +                               case PIPE_CONTROL:     pipetype = "CONTROL"; break;
2829 +                               case PIPE_BULK:        pipetype = "BULK"; break;
2830 +                               case PIPE_INTERRUPT:   pipetype = "INTERRUPT"; break;
2831 +                               case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
2832 +                               default:               pipetype = "UNKNOWN"; break;
2833 +                       };
2834 +                       pipetype;
2835 +                   }));
2836 +               IFX_PRINT("  Speed: %s\n",
2837 +                   ({  char *speed;
2838 +                       switch (_urb->dev->speed) {
2839 +                               case USB_SPEED_HIGH: speed = "HIGH"; break;
2840 +                               case USB_SPEED_FULL: speed = "FULL"; break;
2841 +                               case USB_SPEED_LOW:  speed = "LOW"; break;
2842 +                               default:             speed = "UNKNOWN"; break;
2843 +                       };
2844 +                       speed;
2845 +                   }));
2846 +               IFX_PRINT("  Max packet size: %d\n",
2847 +                         usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
2848 +               IFX_PRINT("  Data buffer length: %d\n", _urb->transfer_buffer_length);
2849 +               IFX_PRINT("  Transfer buffer: %p, Transfer DMA: %p\n",
2850 +                         _urb->transfer_buffer, (void *)_urb->transfer_dma);
2851 +               IFX_PRINT("  Setup buffer: %p, Setup DMA: %p\n",
2852 +                         _urb->setup_packet, (void *)_urb->setup_dma);
2853 +               IFX_PRINT("  Interval: %d\n", _urb->interval);
2854 +               if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS)
2855 +               {
2856 +                       int i;
2857 +                       for (i = 0; i < _urb->number_of_packets;  i++)
2858 +                       {
2859 +                               IFX_PRINT("  ISO Desc %d:\n", i);
2860 +                               IFX_PRINT("    offset: %d, length %d\n",
2861 +                                   _urb->iso_frame_desc[i].offset,
2862 +                                   _urb->iso_frame_desc[i].length);
2863 +                       }
2864 +               }
2865 +       }
2866 +
2867 +       static void dump_channel_info(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
2868 +       {
2869 +               if (_epqh->hc != NULL)
2870 +               {
2871 +                       ifxhcd_hc_t      *hc = _epqh->hc;
2872 +                       struct list_head *item;
2873 +                       ifxhcd_epqh_t      *epqh_item;
2874 +
2875 +                       ifxusb_hc_regs_t *hc_regs;
2876 +
2877 +                       hcchar_data_t  hcchar;
2878 +                       hcsplt_data_t  hcsplt;
2879 +                       hctsiz_data_t  hctsiz;
2880 +                       uint32_t       hcdma;
2881 +
2882 +                       hc_regs = _ifxhcd->core_if.hc_regs[hc->hc_num];
2883 +                       hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
2884 +                       hcsplt.d32 = ifxusb_rreg(&hc_regs->hcsplt);
2885 +                       hctsiz.d32 = ifxusb_rreg(&hc_regs->hctsiz);
2886 +                       hcdma      = ifxusb_rreg(&hc_regs->hcdma);
2887 +
2888 +                       IFX_PRINT("  Assigned to channel %d:\n"       , hc->hc_num);
2889 +                       IFX_PRINT("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
2890 +                       IFX_PRINT("    hctsiz 0x%08x, hcdma 0x%08x\n" , hctsiz.d32, hcdma);
2891 +                       IFX_PRINT("    dev_addr: %d, ep_num: %d, is_in: %d\n",
2892 +                          hc->dev_addr, hc->ep_num, hc->is_in);
2893 +                       IFX_PRINT("    ep_type: %d\n"        , hc->ep_type);
2894 +                       IFX_PRINT("    max_packet_size: %d\n", hc->mps);
2895 +                       IFX_PRINT("    data_pid_start: %d\n" , hc->data_pid_start);
2896 +                       IFX_PRINT("    xfer_started: %d\n"   , hc->xfer_started);
2897 +                       IFX_PRINT("    halt_status: %d\n"    , hc->halt_status);
2898 +                       IFX_PRINT("    xfer_buff: %p\n"      , hc->xfer_buff);
2899 +                       IFX_PRINT("    xfer_len: %d\n"       , hc->xfer_len);
2900 +                       IFX_PRINT("    epqh: %p\n"           , hc->epqh);
2901 +                       IFX_PRINT("  NP Active:\n");
2902 +                       list_for_each(item, &_ifxhcd->epqh_np_active)
2903 +                       {
2904 +                               epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry);
2905 +                               IFX_PRINT("    %p\n", epqh_item);
2906 +                       }
2907 +                       IFX_PRINT("  NP Ready:\n");
2908 +                       list_for_each(item, &_ifxhcd->epqh_np_ready)
2909 +                       {
2910 +                               epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry);
2911 +                               IFX_PRINT("    %p\n", epqh_item);
2912 +                       }
2913 +                       IFX_PRINT("  INTR Active:\n");
2914 +                       list_for_each(item, &_ifxhcd->epqh_intr_active)
2915 +                       {
2916 +                               epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry);
2917 +                               IFX_PRINT("    %p\n", epqh_item);
2918 +                       }
2919 +                       IFX_PRINT("  INTR Ready:\n");
2920 +                       list_for_each(item, &_ifxhcd->epqh_intr_ready)
2921 +                       {
2922 +                               epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry);
2923 +                               IFX_PRINT("    %p\n", epqh_item);
2924 +                       }
2925 +                       #ifdef __EN_ISOC__
2926 +                               IFX_PRINT("  ISOC Active:\n");
2927 +                               list_for_each(item, &_ifxhcd->epqh_isoc_active)
2928 +                               {
2929 +                                       epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry);
2930 +                                       IFX_PRINT("    %p\n", epqh_item);
2931 +                               }
2932 +                               IFX_PRINT("  ISOC Ready:\n");
2933 +                               list_for_each(item, &_ifxhcd->epqh_isoc_ready)
2934 +                               {
2935 +                                       epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry);
2936 +                                       IFX_PRINT("    %p\n", epqh_item);
2937 +                               }
2938 +                       #endif
2939 +                       IFX_PRINT("  Standby:\n");
2940 +                       list_for_each(item, &_ifxhcd->epqh_stdby)
2941 +                       {
2942 +                               epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry);
2943 +                               IFX_PRINT("    %p\n", epqh_item);
2944 +                       }
2945 +               }
2946 +       }
2947 +#endif //__DEBUG__
2948 +
2949 +
2950 +/*!
2951 +   \brief This function writes a packet into the Tx FIFO associated with the Host
2952 +  Channel. For a channel associated with a non-periodic EP, the non-periodic
2953 +  Tx FIFO is written. For a channel associated with a periodic EP, the
2954 +  periodic Tx FIFO is written. This function should only be called in Slave
2955 +  mode.
2956 +
2957 +  Upon return the xfer_buff and xfer_count fields in _hc are incremented by
2958 +  then number of bytes written to the Tx FIFO.
2959 + */
2960 +
2961 +#ifdef __ENABLE_DUMP__
2962 +       void ifxhcd_dump_state(ifxhcd_hcd_t *_ifxhcd)
2963 +       {
2964 +               int num_channels;
2965 +               int i;
2966 +               num_channels = _ifxhcd->core_if.params.host_channels;
2967 +               IFX_PRINT("\n");
2968 +               IFX_PRINT("************************************************************\n");
2969 +               IFX_PRINT("HCD State:\n");
2970 +               IFX_PRINT("  Num channels: %d\n", num_channels);
2971 +               for (i = 0; i < num_channels; i++) {
2972 +                       ifxhcd_hc_t *hc = &_ifxhcd->ifxhc[i];
2973 +                       IFX_PRINT("  Channel %d:\n", hc->hc_num);
2974 +                       IFX_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
2975 +                                 hc->dev_addr, hc->ep_num, hc->is_in);
2976 +                       IFX_PRINT("    speed: %d\n"          , hc->speed);
2977 +                       IFX_PRINT("    ep_type: %d\n"        , hc->ep_type);
2978 +                       IFX_PRINT("    mps: %d\n", hc->mps);
2979 +                       IFX_PRINT("    data_pid_start: %d\n" , hc->data_pid_start);
2980 +                       IFX_PRINT("    xfer_started: %d\n"   , hc->xfer_started);
2981 +                       IFX_PRINT("    xfer_buff: %p\n"      , hc->xfer_buff);
2982 +                       IFX_PRINT("    xfer_len: %d\n"       , hc->xfer_len);
2983 +                       IFX_PRINT("    xfer_count: %d\n"     , hc->xfer_count);
2984 +                       IFX_PRINT("    halting: %d\n"   , hc->halting);
2985 +                       IFX_PRINT("    halt_status: %d\n"    , hc->halt_status);
2986 +                       IFX_PRINT("    split: %d\n"          , hc->split);
2987 +                       IFX_PRINT("    hub_addr: %d\n"       , hc->hub_addr);
2988 +                       IFX_PRINT("    port_addr: %d\n"      , hc->port_addr);
2989 +                       #ifdef __EN_ISOC__
2990 +                               IFX_PRINT("    isoc_xact_pos: %d\n"       , hc->isoc_xact_pos);
2991 +                       #endif
2992 +                       IFX_PRINT("    epqh: %p\n"           , hc->epqh);
2993 +                       IFX_PRINT("    short_rw: %d\n"       , hc->short_rw);
2994 +                       IFX_PRINT("    do_ping: %d\n"        , hc->do_ping);
2995 +                       IFX_PRINT("    control_phase: %d\n"  , hc->control_phase);
2996 +                       IFX_PRINT("    pkt_count_limit: %d\n", hc->epqh->pkt_count_limit);
2997 +                       IFX_PRINT("    start_pkt_count: %d\n"       , hc->start_pkt_count);
2998 +               }
2999 +               IFX_PRINT("************************************************************\n");
3000 +               IFX_PRINT("\n");
3001 +       }
3002 +#endif //__ENABLE_DUMP__
3003 +
3004 --- /dev/null
3005 +++ b/drivers/usb/ifxhcd/ifxhcd.h
3006 @@ -0,0 +1,628 @@
3007 +/*****************************************************************************
3008 + **   FILE NAME       : ifxhcd.h
3009 + **   PROJECT         : IFX USB sub-system V3
3010 + **   MODULES         : IFX USB sub-system Host and Device driver
3011 + **   SRC VERSION     : 1.0
3012 + **   DATE            : 1/Jan/2009
3013 + **   AUTHOR          : Chen, Howard
3014 + **   DESCRIPTION     : This file contains the structures, constants, and interfaces for
3015 + **                     the Host Contoller Driver (HCD).
3016 + **
3017 + **                     The Host Controller Driver (HCD) is responsible for translating requests
3018 + **                     from the USB Driver into the appropriate actions on the IFXUSB controller.
3019 + **                     It isolates the USBD from the specifics of the controller by providing an
3020 + **                     API to the USBD.
3021 + **   FUNCTIONS       :
3022 + **   COMPILER        : gcc
3023 + **   REFERENCE       : Synopsys DWC-OTG Driver 2.7
3024 + **   COPYRIGHT       :
3025 + **  Version Control Section  **
3026 + **   $Author$
3027 + **   $Date$
3028 + **   $Revisions$
3029 + **   $Log$       Revision history
3030 +*****************************************************************************/
3031 +
3032 +/*!
3033 +  \defgroup IFXUSB_HCD HCD Interface
3034 +  \ingroup IFXUSB_DRIVER_V3
3035 +  \brief  The Host Controller Driver (HCD) is responsible for translating requests
3036 + from the USB Driver into the appropriate actions on the IFXUSB controller.
3037 + It isolates the USBD from the specifics of the controller by providing an
3038 + API to the USBD.
3039 + */
3040 +
3041 +
3042 +/*!
3043 +  \file ifxhcd.h
3044 +  \ingroup IFXUSB_DRIVER_V3
3045 +  \brief This file contains the structures, constants, and interfaces for
3046 + the Host Contoller Driver (HCD).
3047 + */
3048 +
3049 +#if !defined(__IFXHCD_H__)
3050 +#define __IFXHCD_H__
3051 +
3052 +#include <linux/list.h>
3053 +#include <linux/usb.h>
3054 +
3055 +#ifdef __USE_TIMER_4_SOF__
3056 +#include <linux/hrtimer.h>
3057 +#endif
3058 +#include <linux/usb/hcd.h>
3059 +
3060 +#include "ifxusb_cif.h"
3061 +#include "ifxusb_plat.h"
3062 +
3063 +
3064 +
3065 +/*!
3066 +  \addtogroup IFXUSB_HCD
3067 + */
3068 +/*@{*/
3069 +
3070 +/* Phases for control transfers.*/
3071 +typedef enum ifxhcd_control_phase {
3072 +       IFXHCD_CONTROL_SETUP,
3073 +       IFXHCD_CONTROL_DATA,
3074 +       IFXHCD_CONTROL_STATUS
3075 +} ifxhcd_control_phase_e;
3076 +
3077 +/* Reasons for halting a host channel. */
3078 +typedef enum ifxhcd_halt_status
3079 +{
3080 +       HC_XFER_NO_HALT_STATUS,         // Initial
3081 +       HC_XFER_COMPLETE,               // Xact complete without error, upward
3082 +       HC_XFER_URB_COMPLETE,           // Xfer complete without error, short upward
3083 +       HC_XFER_STALL,                  // HC stopped abnormally, upward/downward
3084 +       HC_XFER_XACT_ERR,               // HC stopped abnormally, upward
3085 +       HC_XFER_FRAME_OVERRUN,          // HC stopped abnormally, upward
3086 +       HC_XFER_BABBLE_ERR,             // HC stopped abnormally, upward
3087 +       HC_XFER_AHB_ERR,                // HC stopped abnormally, upward
3088 +       HC_XFER_DATA_TOGGLE_ERR,
3089 +       HC_XFER_URB_DEQUEUE,            // HC stopper manually, downward
3090 +       HC_XFER_NAK                     // HC stopped by nak monitor, downward
3091 +} ifxhcd_halt_status_e;
3092 +
3093 +struct ifxhcd_urbd;
3094 +struct ifxhcd_hc ;
3095 +struct ifxhcd_epqh ;
3096 +struct ifxhcd_hcd;
3097 +
3098 +/*!
3099 + \brief A URB Descriptor (URBD) holds the state of a bulk, control,
3100 +  interrupt, or isochronous transfer. A single URBD is created for each URB
3101 +  (of one of these types) submitted to the HCD. The transfer associated with
3102 +  a URBD may require one or multiple transactions.
3103 +
3104 +  A URBD is linked to a EP Queue Head, which is entered in either the
3105 +  isoc, intr or non-periodic schedule for execution. When a URBD is chosen for
3106 +  execution, some or all of its transactions may be executed. After
3107 +  execution, the state of the URBD is updated. The URBD may be retired if all
3108 +  its transactions are complete or if an error occurred. Otherwise, it
3109 +  remains in the schedule so more transactions can be executed later.
3110 + */
3111 +typedef struct ifxhcd_urbd {
3112 +       struct list_head          urbd_list_entry;  // Hook for EPQH->urbd_list and ifxhcd->urbd_complete_list
3113 +       struct urb               *urb;              /*!< URB for this transfer */
3114 +                                                   //struct urb {
3115 +                                                   //  struct list_head urb_list;
3116 +                                                   //  struct list_head anchor_list;
3117 +                                                   //  struct usb_anchor * anchor;
3118 +                                                   //  struct usb_device * dev;
3119 +                                                   //  struct usb_host_endpoint * ep;
3120 +                                                   //  unsigned int pipe;
3121 +                                                   //  int status;
3122 +                                                   //  unsigned int transfer_flags;
3123 +                                                   //  void * transfer_buffer;
3124 +                                                   //  dma_addr_t transfer_dma;
3125 +                                                   //  u32 transfer_buffer_length;
3126 +                                                   //  u32 actual_length;
3127 +                                                   //  unsigned char * setup_packet;
3128 +                                                   //  dma_addr_t setup_dma;
3129 +                                                   //  int start_frame;
3130 +                                                   //  int number_of_packets;
3131 +                                                   //  int interval;
3132 +                                                   //  int error_count;
3133 +                                                   //  void * context;
3134 +                                                   //  usb_complete_t complete;
3135 +                                                   //  struct usb_iso_packet_descriptor iso_frame_desc[0];
3136 +                                                   //};
3137 +                                                   //urb_list         For use by current owner of the URB.
3138 +                                                   //anchor_list      membership in the list of an anchor
3139 +                                                   //anchor           to anchor URBs to a common mooring
3140 +                                                   //dev              Identifies the USB device to perform the request.
3141 +                                                   //ep               Points to the endpoint's data structure. Will
3142 +                                                   //                 eventually replace pipe.
3143 +                                                   //pipe             Holds endpoint number, direction, type, and more.
3144 +                                                   //                 Create these values with the eight macros available; u
3145 +                                                   //                 sb_{snd,rcv}TYPEpipe(dev,endpoint), where the TYPE is
3146 +                                                   //                  "ctrl", "bulk", "int" or "iso". For example
3147 +                                                   //                 usb_sndbulkpipe or usb_rcvintpipe. Endpoint numbers
3148 +                                                   //                 range from zero to fifteen. Note that "in" endpoint two
3149 +                                                   //                 is a different endpoint (and pipe) from "out" endpoint
3150 +                                                   //                 two. The current configuration controls the existence,
3151 +                                                   //                 type, and maximum packet size of any given endpoint.
3152 +                                                   //status           This is read in non-iso completion functions to get
3153 +                                                   //                 the status of the particular request. ISO requests
3154 +                                                   //                 only use it to tell whether the URB was unlinked;
3155 +                                                   //                 detailed status for each frame is in the fields of
3156 +                                                   //                 the iso_frame-desc.
3157 +                                                   //transfer_flags   A variety of flags may be used to affect how URB
3158 +                                                   //                 submission, unlinking, or operation are handled.
3159 +                                                   //                 Different kinds of URB can use different flags.
3160 +                                                   //                      URB_SHORT_NOT_OK
3161 +                                                   //                      URB_ISO_ASAP
3162 +                                                   //                      URB_NO_TRANSFER_DMA_MAP
3163 +                                                   //                      URB_NO_SETUP_DMA_MAP
3164 +                                                   //                      URB_NO_FSBR
3165 +                                                   //                      URB_ZERO_PACKET
3166 +                                                   //                      URB_NO_INTERRUPT
3167 +                                                   //transfer_buffer  This identifies the buffer to (or from) which the I/O
3168 +                                                   //                 request will be performed (unless URB_NO_TRANSFER_DMA_MAP
3169 +                                                   //                 is set). This buffer must be suitable for DMA; allocate it
3170 +                                                   //                 with kmalloc or equivalent. For transfers to "in"
3171 +                                                   //                 endpoints, contents of this buffer will be modified. This
3172 +                                                   //                 buffer is used for the data stage of control transfers.
3173 +                                                   //transfer_dma     When transfer_flags includes URB_NO_TRANSFER_DMA_MAP, the
3174 +                                                   //                 device driver is saying that it provided this DMA address,
3175 +                                                   //                 which the host controller driver should use in preference
3176 +                                                   //                 to the transfer_buffer.
3177 +                                                   //transfer_buffer_length How big is transfer_buffer. The transfer may be broken
3178 +                                                   //                 up into chunks according to the current maximum packet size
3179 +                                                   //                 for the endpoint, which is a function of the configuration
3180 +                                                   //                 and is encoded in the pipe. When the length is zero, neither
3181 +                                                   //                 transfer_buffer nor transfer_dma is used.
3182 +                                                   //actual_length    This is read in non-iso completion functions, and it tells
3183 +                                                   //                 how many bytes (out of transfer_buffer_length) were transferred.
3184 +                                                   //                 It will normally be the same as requested, unless either an error
3185 +                                                   //                 was reported or a short read was performed. The URB_SHORT_NOT_OK
3186 +                                                   //                 transfer flag may be used to make such short reads be reported
3187 +                                                   //                 as errors.
3188 +                                                   //setup_packet     Only used for control transfers, this points to eight bytes of
3189 +                                                   //                 setup data. Control transfers always start by sending this data
3190 +                                                   //                 to the device. Then transfer_buffer is read or written, if needed.
3191 +                                                   //setup_dma        For control transfers with URB_NO_SETUP_DMA_MAP set, the device
3192 +                                                   //                 driver has provided this DMA address for the setup packet. The
3193 +                                                   //                 host controller driver should use this in preference to setup_packet.
3194 +                                                   //start_frame      Returns the initial frame for isochronous transfers.
3195 +                                                   //number_of_packets Lists the number of ISO transfer buffers.
3196 +                                                   //interval         Specifies the polling interval for interrupt or isochronous transfers.
3197 +                                                   //                 The units are frames (milliseconds) for for full and low speed devices,
3198 +                                                   //                 and microframes (1/8 millisecond) for highspeed ones.
3199 +                                                   //error_count      Returns the number of ISO transfers that reported errors.
3200 +                                                   //context          For use in completion functions. This normally points to request-specific
3201 +                                                   //                 driver context.
3202 +                                                   //complete         Completion handler. This URB is passed as the parameter to the completion
3203 +                                                   //                 function. The completion function may then do what it likes with the URB,
3204 +                                                   //                 including resubmitting or freeing it.
3205 +                                                   //iso_frame_desc[0] Used to provide arrays of ISO transfer buffers and to collect the transfer
3206 +                                                   //                 status for each buffer.
3207 +
3208 +       struct ifxhcd_epqh       *epqh;
3209 +                                                // Actual data portion, not SETUP or STATUS in case of CTRL XFER
3210 +                                                // DMA adjusted
3211 +       uint8_t                  *setup_buff;       /*!< Pointer to the entire transfer buffer. (CPU accessable)*/
3212 +       uint8_t                  *xfer_buff;        /*!< Pointer to the entire transfer buffer. (CPU accessable)*/
3213 +       uint32_t                  xfer_len;         /*!< Total number of bytes to transfer in this xfer. */
3214 +       unsigned                  is_in    :1;
3215 +       unsigned                  is_active:1;
3216 +
3217 +                                 // For ALL XFER
3218 +       uint8_t                   error_count;    /*!< Holds the number of bus errors that have occurred for a transaction
3219 +                                                      within this transfer.
3220 +                                                  */
3221 +       /*== AVM/BC 20101111  Needed for URB Complete List ==*/
3222 +       int                                       status;
3223 +                                 // For ISOC XFER only
3224 +       #ifdef __EN_ISOC__
3225 +               int                       isoc_frame_index; /*!< Index of the next frame descriptor for an isochronous transfer. A
3226 +                                                                frame descriptor describes the buffer position and length of the
3227 +                                                                data to be transferred in the next scheduled (micro)frame of an
3228 +                                                                isochronous transfer. It also holds status for that transaction.
3229 +                                                                The frame index starts at 0.
3230 +                                                            */
3231 +                                         // For SPLITed ISOC XFER only
3232 +               uint8_t                   isoc_split_pos;   /*!< Position of the ISOC split on full/low speed */
3233 +               uint16_t                  isoc_split_offset;/*!< Position of the ISOC split in the buffer for the current frame */
3234 +       #endif
3235 +} ifxhcd_urbd_t;
3236 +
3237 +/*!
3238 + \brief A EP Queue Head (EPQH) holds the static characteristics of an endpoint and
3239 + maintains a list of transfers (URBDs) for that endpoint. A EPQH structure may
3240 + be entered in either the isoc, intr or non-periodic schedule.
3241 + */
3242 +
3243 +typedef struct ifxhcd_epqh {
3244 +       struct list_head     epqh_list_entry;   // Hook for EP Queues
3245 +       struct list_head     urbd_list;         /*!< List of URBDs for this EPQH. */
3246 +       struct ifxhcd_hc    *hc;                /*!< Host channel currently processing transfers for this EPQH. */
3247 +       struct ifxhcd_urbd  *urbd;              /*!< URBD currently assigned to a host channel for this EPQH. */
3248 +       struct usb_host_endpoint *sysep;
3249 +       uint8_t              ep_type;           /*!< Endpoint type. One of the following values:
3250 +                                                    - IFXUSB_EP_TYPE_CTRL
3251 +                                                    - IFXUSB_EP_TYPE_ISOC
3252 +                                                    - IFXUSB_EP_TYPE_BULK
3253 +                                                    - IFXUSB_EP_TYPE_INTR
3254 +                                                */
3255 +       uint16_t             mps;               /*!< wMaxPacketSize Field of Endpoint Descriptor. */
3256 +
3257 +       /* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/
3258 +       /*uint8_t              data_toggle;*/     /*!< Determines the PID of the next data packet
3259 +                                                    One of the following values:
3260 +                                                    - IFXHCD_HC_PID_DATA0
3261 +                                                    - IFXHCD_HC_PID_DATA1
3262 +                                                */
3263 +       uint8_t              is_active;
3264 +
3265 +       uint8_t              pkt_count_limit;
3266 +       #ifdef __EPQD_DESTROY_TIMEOUT__
3267 +               struct timer_list destroy_timer;
3268 +       #endif
3269 +
3270 +       uint16_t             wait_for_sof;
3271 +       uint8_t              need_split;        /*!< Full/low speed endpoint on high-speed hub requires split. */
3272 +       uint16_t             interval;          /*!< Interval between transfers in (micro)frames. (for INTR)*/
3273 +
3274 +       uint16_t             period_counter;    /*!< Interval between transfers in (micro)frames. */
3275 +       uint8_t              period_do;
3276 +
3277 +       uint8_t aligned_checked;
3278 +
3279 +       #if   defined(__UNALIGNED_BUFFER_ADJ__)
3280 +               uint8_t using_aligned_setup;
3281 +               uint8_t *aligned_setup;
3282 +               uint8_t using_aligned_buf;
3283 +               uint8_t *aligned_buf;
3284 +               unsigned aligned_buf_len : 19;
3285 +       #endif
3286 +
3287 +       uint8_t   *dump_buf;
3288 +} ifxhcd_epqh_t;
3289 +
3290 +
3291 +#if defined(__HC_XFER_TIMEOUT__)
3292 +       struct ifxusb_core_if;
3293 +       struct ifxhcd_hc;
3294 +       typedef struct hc_xfer_info
3295 +       {
3296 +               struct ifxusb_core_if *core_if;
3297 +               struct ifxhcd_hc      *hc;
3298 +       } hc_xfer_info_t;
3299 +#endif //defined(__HC_XFER_TIMEOUT__)
3300 +
3301 +
3302 +/*!
3303 + \brief Host channel descriptor. This structure represents the state of a single
3304 + host channel when acting in host mode. It contains the data items needed to
3305 + transfer packets to an endpoint via a host channel.
3306 + */
3307 +typedef struct ifxhcd_hc
3308 +{
3309 +       struct list_head hc_list_entry  ; // Hook to free hc
3310 +       struct ifxhcd_epqh *epqh        ; /*!< EP Queue Head for the transfer being processed by this channel. */
3311 +
3312 +       uint8_t  hc_num                 ; /*!< Host channel number used for register address lookup */
3313 +       uint8_t *xfer_buff              ; /*!< Pointer to the entire transfer buffer. */
3314 +       uint32_t xfer_count             ; /*!< Number of bytes transferred so far. The offset of the begin of the buf */
3315 +       uint32_t xfer_len               ; /*!< Total number of bytes to transfer in this xfer. */
3316 +       uint16_t start_pkt_count        ; /*!< Packet count at start of transfer. Used to calculate the actual xfer size*/
3317 +       ifxhcd_halt_status_e halt_status; /*!< Reason for halting the host channel. */
3318 +
3319 +       unsigned dev_addr       : 7; /*!< Device to access */
3320 +       unsigned ep_num         : 4; /*!< EP to access */
3321 +       unsigned is_in          : 1; /*!< EP direction. 0: OUT, 1: IN */
3322 +       unsigned speed          : 2; /*!< EP speed. */
3323 +       unsigned ep_type        : 2; /*!< Endpoint type. */
3324 +       unsigned mps            :11; /*!< Max packet size in bytes */
3325 +       unsigned data_pid_start : 2; /*!< PID for initial transaction. */
3326 +       unsigned do_ping        : 1; /*!< Set to 1 to indicate that a PING request should be issued on this
3327 +                                         channel. If 0, process normally.
3328 +                                     */
3329 +
3330 +       unsigned xfer_started   : 1; /*!< Flag to indicate whether the transfer has been started. Set to 1 if
3331 +                                         it has been started, 0 otherwise.
3332 +                                     */
3333 +       unsigned halting        : 1; /*!< Set to 1 if the host channel has been halted, but the core is not
3334 +                                         finished flushing queued requests. Otherwise 0.
3335 +                                     */
3336 +       unsigned short_rw       : 1; /*!< When Tx, means termination needed.
3337 +                                         When Rx, indicate Short Read  */
3338 +       /* Split settings for the host channel */
3339 +       unsigned split          : 2; /*!< Split: 0-Non Split, 1-SSPLIT, 2&3 CSPLIT */
3340 +
3341 +       /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/
3342 +       unsigned nyet_count;
3343 +
3344 +       /* nak monitor */
3345 +       unsigned nak_retry_r    : 16;
3346 +       unsigned nak_retry      : 16;
3347 +               #define nak_retry_max     40000
3348 +       unsigned nak_countdown  : 8;
3349 +       unsigned nak_countdown_r: 8;
3350 +               #define nak_countdown_max 1
3351 +
3352 +       uint16_t                  wait_for_sof;
3353 +       ifxhcd_control_phase_e    control_phase;  /*!< Current phase for control transfers (Setup, Data, or Status). */
3354 +       uint32_t ssplit_out_xfer_count; /*!< How many bytes transferred during SSPLIT OUT */
3355 +       #ifdef __DEBUG__
3356 +               uint32_t          start_hcchar_val;
3357 +       #endif
3358 +       #ifdef __HC_XFER_TIMEOUT__
3359 +               hc_xfer_info_t    hc_xfer_info;
3360 +               struct timer_list hc_xfer_timer;
3361 +       #endif
3362 +       uint32_t hcchar;
3363 +
3364 +       /* Split settings for the host channel */
3365 +       uint8_t hub_addr;          /*!< Address of high speed hub */
3366 +       uint8_t port_addr;         /*!< Port of the low/full speed device */
3367 +       #ifdef __EN_ISOC__
3368 +               uint8_t isoc_xact_pos;          /*!< Split transaction position */
3369 +       #endif
3370 +} ifxhcd_hc_t;
3371 +
3372 +
3373 +/*!
3374 + \brief This structure holds the state of the HCD, including the non-periodic and
3375 + periodic schedules.
3376 + */
3377 +typedef struct ifxhcd_hcd
3378 +{
3379 +       struct device *dev;
3380 +       struct hc_driver hc_driver;
3381 +       ifxusb_core_if_t core_if;   /*!< Pointer to the core interface structure. */
3382 +       struct usb_hcd *syshcd;
3383 +
3384 +       volatile union ifxhcd_internal_flags
3385 +       {
3386 +               uint32_t d32;
3387 +               struct
3388 +               {
3389 +                       unsigned port_connect_status_change : 1;
3390 +                       unsigned port_connect_status        : 1;
3391 +                       unsigned port_reset_change          : 1;
3392 +                       unsigned port_enable_change         : 1;
3393 +                       unsigned port_suspend_change        : 1;
3394 +                       unsigned port_over_current_change   : 1;
3395 +                       unsigned reserved                   : 27;
3396 +               } b;
3397 +       } flags; /*!< Internal HCD Flags */
3398 +
3399 +       struct ifxhcd_hc ifxhc[MAX_EPS_CHANNELS];         /*!< Array of pointers to the host channel descriptors. Allows accessing
3400 +                                                              a host channel descriptor given the host channel number. This is
3401 +                                                              useful in interrupt handlers.
3402 +                                                          */
3403 +       struct list_head free_hc_list;                    /*!< Free host channels in the controller. This is a list of ifxhcd_hc_t items. */
3404 +       uint8_t   *status_buf;                            /*!< Buffer to use for any data received during the status phase of a
3405 +                                                              control transfer. Normally no data is transferred during the status
3406 +                                                              phase. This buffer is used as a bit bucket.
3407 +                                                          */
3408 +               #define IFXHCD_STATUS_BUF_SIZE 64
3409 +
3410 +       struct list_head epqh_np_active;    // with URBD, with HC
3411 +       struct list_head epqh_np_ready;     // with URBD, No HC
3412 +
3413 +       struct list_head epqh_intr_active;  // with URBD, with HC
3414 +       struct list_head epqh_intr_ready;   // with URBD, no pass, No HC
3415 +
3416 +       #ifdef __EN_ISOC__
3417 +               struct list_head epqh_isoc_active;  // with URBD, with HC
3418 +               struct list_head epqh_isoc_ready;   // with URBD, no pass, No HC
3419 +       #endif
3420 +
3421 +       /*== AVM/BC 20101111  URB Complete List ==*/
3422 +       struct list_head urbd_complete_list;
3423 +
3424 +       struct list_head epqh_stdby;
3425 +
3426 +       /* AVM/BC 20101111 flags removed */
3427 +       //unsigned process_channels_in_use  : 1;
3428 +       //unsigned select_eps_in_use        : 1;
3429 +
3430 +       struct tasklet_struct  select_eps;                /*!<  Tasket to do a reset */
3431 +       uint32_t lastframe;
3432 +       spinlock_t      lock;
3433 +#ifdef __USE_TIMER_4_SOF__
3434 +       struct hrtimer hr_timer;
3435 +#endif
3436 +} ifxhcd_hcd_t;
3437 +
3438 +/* Gets the ifxhcd_hcd from a struct usb_hcd */
3439 +static inline ifxhcd_hcd_t *syshcd_to_ifxhcd(struct usb_hcd *syshcd)
3440 +{
3441 +       return (ifxhcd_hcd_t *)(syshcd->hcd_priv[0]);
3442 +}
3443 +
3444 +/* Gets the struct usb_hcd that contains a ifxhcd_hcd_t. */
3445 +static inline struct usb_hcd *ifxhcd_to_syshcd(ifxhcd_hcd_t *ifxhcd)
3446 +{
3447 +       return (struct usb_hcd *)(ifxhcd->syshcd);
3448 +}
3449 +
3450 +/*! \brief HCD Create/Destroy Functions */
3451 +/*@{*/
3452 +       extern int  ifxhcd_init  (ifxhcd_hcd_t *_ifxhcd);
3453 +       extern void ifxhcd_remove(ifxhcd_hcd_t *_ifxhcd);
3454 +/*@}*/
3455 +
3456 +/*! \brief Linux HC Driver API Functions */
3457 +/*@{*/
3458 +extern int  ifxhcd_start(struct usb_hcd *hcd);
3459 +extern void ifxhcd_stop (struct usb_hcd *hcd);
3460 +extern int  ifxhcd_get_frame_number(struct usb_hcd *hcd);
3461 +
3462 +
3463 +/*!
3464 +   \brief This function does the setup for a data transfer for a host channel and
3465 +  starts the transfer. May be called in either Slave mode or DMA mode. In
3466 +  Slave mode, the caller must ensure that there is sufficient space in the
3467 +  request queue and Tx Data FIFO.
3468 +
3469 +  For an OUT transfer in Slave mode, it loads a data packet into the
3470 +  appropriate FIFO. If necessary, additional data packets will be loaded in
3471 +  the Host ISR.
3472 +
3473 +  For an IN transfer in Slave mode, a data packet is requested. The data
3474 +  packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
3475 +  additional data packets are requested in the Host ISR.
3476 +
3477 +  For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
3478 +  register along with a packet count of 1 and the channel is enabled. This
3479 +  causes a single PING transaction to occur. Other fields in HCTSIZ are
3480 +  simply set to 0 since no data transfer occurs in this case.
3481 +
3482 +  For a PING transfer in DMA mode, the HCTSIZ register is initialized with
3483 +  all the information required to perform the subsequent data transfer. In
3484 +  addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
3485 +  controller performs the entire PING protocol, then starts the data
3486 +  transfer.
3487 +
3488 +  @param _ifxhc Information needed to initialize the host channel. The xfer_len
3489 +  value may be reduced to accommodate the max widths of the XferSize and
3490 +  PktCnt fields in the HCTSIZn register. The multi_count value may be changed
3491 +  to reflect the final xfer_len value.
3492 + */
3493 +extern void ifxhcd_hc_start(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
3494 +
3495 +//extern int ifxhcd_urb_enqueue(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep, struct urb *_urb, gfp_t mem_flags);
3496 +//extern int ifxhcd_urb_dequeue(struct usb_hcd *_syshcd, struct urb *_urb);
3497 +extern irqreturn_t ifxhcd_irq(struct usb_hcd *_syshcd);
3498 +int ifxhcd_urb_enqueue( struct usb_hcd           *_syshcd,
3499 +                        /*--- struct usb_host_endpoint *_sysep, Parameter im 2.6.28 entfallen ---*/
3500 +                        struct urb               *_urb,
3501 +                        gfp_t                     _mem_flags);
3502 +int ifxhcd_urb_dequeue( struct usb_hcd *_syshcd,
3503 +                        struct urb *_urb, int status /* Parameter neu in 2.6.28 */);
3504 +
3505 +extern void ifxhcd_endpoint_disable(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep);
3506 +
3507 +extern int ifxhcd_hub_status_data(struct usb_hcd *_syshcd, char *_buf);
3508 +extern int ifxhcd_hub_control( struct usb_hcd *_syshcd,
3509 +                               u16             _typeReq,
3510 +                               u16             _wValue,
3511 +                               u16             _wIndex,
3512 +                               char           *_buf,
3513 +                               u16             _wLength);
3514 +
3515 +/*@}*/
3516 +
3517 +/*! \brief Transaction Execution Functions */
3518 +/*@{*/
3519 +extern void                      ifxhcd_complete_urb       (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd,  int _status);
3520 +
3521 +/*@}*/
3522 +
3523 +/*! \brief Deferred Transaction Execution Functions */
3524 +/*@{*/
3525 +
3526 +/*== AVM/BC 20101111  URB Complete List ==*/
3527 +extern void                      defer_ifxhcd_complete_urb       (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd,  int _status);
3528 +
3529 +/*!
3530 +   \brief Clears the transfer state for a host channel. This function is normally
3531 +  called after a transfer is done and the host channel is being released.
3532 + */
3533 +extern void ifxhcd_hc_cleanup(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
3534 +
3535 +/*!
3536 +   \brief Attempts to halt a host channel. This function should only be called in
3537 +  Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
3538 +  normal circumstances in DMA mode, the controller halts the channel when the
3539 +  transfer is complete or a condition occurs that requires application
3540 +  intervention.
3541 +
3542 +  In slave mode, checks for a free request queue entry, then sets the Channel
3543 +  Enable and Channel Disable bits of the Host Channel Characteristics
3544 +  register of the specified channel to intiate the halt. If there is no free
3545 +  request queue entry, sets only the Channel Disable bit of the HCCHARn
3546 +  register to flush requests for this channel. In the latter case, sets a
3547 +  flag to indicate that the host channel needs to be halted when a request
3548 +  queue slot is open.
3549 +
3550 +  In DMA mode, always sets the Channel Enable and Channel Disable bits of the
3551 +  HCCHARn register. The controller ensures there is space in the request
3552 +  queue before submitting the halt request.
3553 +
3554 +  Some time may elapse before the core flushes any posted requests for this
3555 +  host channel and halts. The Channel Halted interrupt handler completes the
3556 +  deactivation of the host channel.
3557 + */
3558 +extern void ifxhcd_hc_halt(ifxusb_core_if_t *_core_if,
3559 +                    ifxhcd_hc_t *_ifxhc,
3560 +                    ifxhcd_halt_status_e _halt_status);
3561 +
3562 +/*!
3563 +   \brief Prepares a host channel for transferring packets to/from a specific
3564 +  endpoint. The HCCHARn register is set up with the characteristics specified
3565 +  in _ifxhc. Host channel interrupts that may need to be serviced while this
3566 +  transfer is in progress are enabled.
3567 + */
3568 +extern void ifxhcd_hc_init(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
3569 +
3570 +/*!
3571 +   \brief This function is called to handle the disconnection of host port.
3572 + */
3573 +int32_t ifxhcd_disconnect(ifxhcd_hcd_t *_ifxhcd);
3574 +/*@}*/
3575 +
3576 +/*!  \brief Interrupt Handler Functions */
3577 +/*@{*/
3578 +extern irqreturn_t ifxhcd_oc_irq(int _irq, void *_dev);
3579 +
3580 +extern int32_t ifxhcd_handle_oc_intr(ifxhcd_hcd_t *_ifxhcd);
3581 +extern int32_t ifxhcd_handle_intr   (ifxhcd_hcd_t *_ifxhcd);
3582 +/*@}*/
3583 +
3584 +
3585 +/*! \brief Schedule Queue Functions */
3586 +/*@{*/
3587 +extern ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb);
3588 +extern void           ifxhcd_epqh_free   (                       ifxhcd_epqh_t *_epqh);
3589 +extern void           select_eps      (ifxhcd_hcd_t *_ifxhcd);
3590 +extern void           process_channels(ifxhcd_hcd_t *_ifxhcd);
3591 +extern void           process_channels_sub(ifxhcd_hcd_t *_ifxhcd);
3592 +extern void              complete_channel(ifxhcd_hcd_t *_ifxhcd, ifxhcd_hc_t *_ifxhc, ifxhcd_urbd_t *_urbd);
3593 +extern void           ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
3594 +extern void           ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
3595 +extern void           ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
3596 +extern void           ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh);
3597 +extern int            ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb);
3598 +/*@}*/
3599 +
3600 +/*! \brief Gets the usb_host_endpoint associated with an URB. */
3601 +static inline struct usb_host_endpoint *ifxhcd_urb_to_endpoint(struct urb *_urb)
3602 +{
3603 +       struct usb_device *dev = _urb->dev;
3604 +       int    ep_num = usb_pipeendpoint(_urb->pipe);
3605 +
3606 +       return (usb_pipein(_urb->pipe))?(dev->ep_in[ep_num]):(dev->ep_out[ep_num]);
3607 +}
3608 +
3609 +/*!
3610 + * \brief Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
3611 + * qualified with its direction (possible 32 endpoints per device).
3612 + */
3613 +#define ifxhcd_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
3614 +                                                       ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
3615 +
3616 +
3617 +/* AVM/WK: not needed?
3618 +
3619 +extern struct usb_device *usb_alloc_dev  (struct usb_device *parent, struct usb_bus *, unsigned port);
3620 +extern int                usb_add_hcd    (struct usb_hcd *syshcd, unsigned int irqnum, unsigned long irqflags);
3621 +extern void               usb_remove_hcd (struct usb_hcd *syshcd);
3622 +extern struct usb_hcd    *usb_create_hcd (const struct hc_driver *driver, struct device *dev, char *bus_name);
3623 +extern void               usb_hcd_giveback_urb (struct usb_hcd *syshcd, struct urb *urb);
3624 +extern void               usb_put_hcd       (struct usb_hcd *syshcd);
3625 +extern long               usb_calc_bus_time (int speed, int is_input, int isoc, int bytecount);
3626 +
3627 +*/
3628 +/** Internal Functions */
3629 +void         ifxhcd_dump_state(ifxhcd_hcd_t *_ifxhcd);
3630 +extern char *syserr(int errno);
3631 +
3632 +/*@}*//*IFXUSB_HCD*/
3633 +
3634 +#endif // __IFXHCD_H__
3635 --- /dev/null
3636 +++ b/drivers/usb/ifxhcd/ifxhcd_es.c
3637 @@ -0,0 +1,549 @@
3638 +/*****************************************************************************
3639 + **   FILE NAME       : ifxhcd_es.c
3640 + **   PROJECT         : IFX USB sub-system V3
3641 + **   MODULES         : IFX USB sub-system Host and Device driver
3642 + **   SRC VERSION     : 1.0
3643 + **   DATE            : 1/Jan/2009
3644 + **   AUTHOR          : Chen, Howard
3645 + **   DESCRIPTION     : The file contain function to enable host mode USB-IF Electrical Test function.
3646 + *****************************************************************************/
3647 +
3648 +/*!
3649 + \file ifxhcd_es.c
3650 + \ingroup IFXUSB_DRIVER_V3
3651 + \brief The file contain function to enable host mode USB-IF Electrical Test function.
3652 +*/
3653 +
3654 +#include <linux/version.h>
3655 +#include "ifxusb_version.h"
3656 +
3657 +#include <linux/kernel.h>
3658 +
3659 +#include <linux/errno.h>
3660 +
3661 +#include <linux/dma-mapping.h>
3662 +
3663 +#include "ifxusb_plat.h"
3664 +#include "ifxusb_regs.h"
3665 +#include "ifxusb_cif.h"
3666 +#include "ifxhcd.h"
3667 +
3668 +
3669 +#ifdef __WITH_HS_ELECT_TST__
3670 +       /*
3671 +        * Quick and dirty hack to implement the HS Electrical Test
3672 +        * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
3673 +        *
3674 +        * This code was copied from our userspace app "hset". It sends a
3675 +        * Get Device Descriptor control sequence in two parts, first the
3676 +        * Setup packet by itself, followed some time later by the In and
3677 +        * Ack packets. Rather than trying to figure out how to add this
3678 +        * functionality to the normal driver code, we just hijack the
3679 +        * hardware, using these two function to drive the hardware
3680 +        * directly.
3681 +        */
3682 +
3683 +
3684 +       void do_setup(ifxusb_core_if_t *_core_if)
3685 +       {
3686 +
3687 +               ifxusb_core_global_regs_t *global_regs    = _core_if->core_global_regs;
3688 +               ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs;
3689 +               ifxusb_hc_regs_t          *hc_regs        = _core_if->hc_regs[0];
3690 +               uint32_t                  *data_fifo      = _core_if->data_fifo[0];
3691 +
3692 +               gint_data_t    gintsts;
3693 +               hctsiz_data_t  hctsiz;
3694 +               hcchar_data_t  hcchar;
3695 +               haint_data_t   haint;
3696 +               hcint_data_t   hcint;
3697 +
3698 +
3699 +               /* Enable HAINTs */
3700 +               ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001);
3701 +
3702 +               /* Enable HCINTs */
3703 +               ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3);
3704 +
3705 +               /* Read GINTSTS */
3706 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3707 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
3708 +
3709 +               /* Read HAINT */
3710 +               haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
3711 +               //fprintf(stderr, "HAINT: %08x\n", haint.d32);
3712 +
3713 +               /* Read HCINT */
3714 +               hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
3715 +               //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
3716 +
3717 +               /* Read HCCHAR */
3718 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3719 +               //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
3720 +
3721 +               /* Clear HCINT */
3722 +               ifxusb_wreg(&hc_regs->hcint, hcint.d32);
3723 +
3724 +               /* Clear HAINT */
3725 +               ifxusb_wreg(&hc_global_regs->haint, haint.d32);
3726 +
3727 +               /* Clear GINTSTS */
3728 +               ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
3729 +
3730 +               /* Read GINTSTS */
3731 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3732 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
3733 +
3734 +               /*
3735 +                * Send Setup packet (Get Device Descriptor)
3736 +                */
3737 +
3738 +               /* Make sure channel is disabled */
3739 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3740 +               if (hcchar.b.chen) {
3741 +                       //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
3742 +                       hcchar.b.chdis = 1;
3743 +       //              hcchar.b.chen = 1;
3744 +                       ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
3745 +                       //sleep(1);
3746 +                       mdelay(1000);
3747 +
3748 +                       /* Read GINTSTS */
3749 +                       gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3750 +                       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
3751 +
3752 +                       /* Read HAINT */
3753 +                       haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
3754 +                       //fprintf(stderr, "HAINT: %08x\n", haint.d32);
3755 +
3756 +                       /* Read HCINT */
3757 +                       hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
3758 +                       //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
3759 +
3760 +                       /* Read HCCHAR */
3761 +                       hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3762 +                       //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
3763 +
3764 +                       /* Clear HCINT */
3765 +                       ifxusb_wreg(&hc_regs->hcint, hcint.d32);
3766 +
3767 +                       /* Clear HAINT */
3768 +                       ifxusb_wreg(&hc_global_regs->haint, haint.d32);
3769 +
3770 +                       /* Clear GINTSTS */
3771 +                       ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
3772 +
3773 +                       hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3774 +                       //if (hcchar.b.chen) {
3775 +                       //      fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
3776 +                       //}
3777 +               }
3778 +
3779 +               /* Set HCTSIZ */
3780 +               hctsiz.d32 = 0;
3781 +               hctsiz.b.xfersize = 8;
3782 +               hctsiz.b.pktcnt = 1;
3783 +               hctsiz.b.pid = IFXUSB_HC_PID_SETUP;
3784 +               ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
3785 +
3786 +               /* Set HCCHAR */
3787 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3788 +               hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
3789 +               hcchar.b.epdir = 0;
3790 +               hcchar.b.epnum = 0;
3791 +               hcchar.b.mps = 8;
3792 +               hcchar.b.chen = 1;
3793 +               ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
3794 +
3795 +               /* Fill FIFO with Setup data for Get Device Descriptor */
3796 +               ifxusb_wreg(data_fifo++, 0x01000680);
3797 +               ifxusb_wreg(data_fifo++, 0x00080000);
3798 +
3799 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3800 +               //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
3801 +
3802 +               /* Wait for host channel interrupt */
3803 +               do {
3804 +                       gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3805 +               } while (gintsts.b.hcintr == 0);
3806 +
3807 +               //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
3808 +
3809 +               /* Disable HCINTs */
3810 +               ifxusb_wreg(&hc_regs->hcintmsk, 0x0000);
3811 +
3812 +               /* Disable HAINTs */
3813 +               ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000);
3814 +
3815 +               /* Read HAINT */
3816 +               haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
3817 +               //fprintf(stderr, "HAINT: %08x\n", haint.d32);
3818 +
3819 +               /* Read HCINT */
3820 +               hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
3821 +               //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
3822 +
3823 +               /* Read HCCHAR */
3824 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3825 +               //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
3826 +
3827 +               /* Clear HCINT */
3828 +               ifxusb_wreg(&hc_regs->hcint, hcint.d32);
3829 +
3830 +               /* Clear HAINT */
3831 +               ifxusb_wreg(&hc_global_regs->haint, haint.d32);
3832 +
3833 +               /* Clear GINTSTS */
3834 +               ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
3835 +
3836 +               /* Read GINTSTS */
3837 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3838 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
3839 +       }
3840 +
3841 +       void do_in_ack(ifxusb_core_if_t *_core_if)
3842 +       {
3843 +
3844 +               ifxusb_core_global_regs_t *global_regs    = _core_if->core_global_regs;
3845 +               ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs;
3846 +               ifxusb_hc_regs_t          *hc_regs        = _core_if->hc_regs[0];
3847 +               uint32_t                  *data_fifo      = _core_if->data_fifo[0];
3848 +
3849 +               gint_data_t        gintsts;
3850 +               hctsiz_data_t      hctsiz;
3851 +               hcchar_data_t      hcchar;
3852 +               haint_data_t       haint;
3853 +               hcint_data_t       hcint;
3854 +               grxsts_data_t      grxsts;
3855 +
3856 +               /* Enable HAINTs */
3857 +               ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001);
3858 +
3859 +               /* Enable HCINTs */
3860 +               ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3);
3861 +
3862 +               /* Read GINTSTS */
3863 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3864 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
3865 +
3866 +               /* Read HAINT */
3867 +               haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
3868 +               //fprintf(stderr, "HAINT: %08x\n", haint.d32);
3869 +
3870 +               /* Read HCINT */
3871 +               hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
3872 +               //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
3873 +
3874 +               /* Read HCCHAR */
3875 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3876 +               //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
3877 +
3878 +               /* Clear HCINT */
3879 +               ifxusb_wreg(&hc_regs->hcint, hcint.d32);
3880 +
3881 +               /* Clear HAINT */
3882 +               ifxusb_wreg(&hc_global_regs->haint, haint.d32);
3883 +
3884 +               /* Clear GINTSTS */
3885 +               ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
3886 +
3887 +               /* Read GINTSTS */
3888 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3889 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
3890 +
3891 +               /*
3892 +                * Receive Control In packet
3893 +                */
3894 +
3895 +               /* Make sure channel is disabled */
3896 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3897 +               if (hcchar.b.chen) {
3898 +                       //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
3899 +                       hcchar.b.chdis = 1;
3900 +                       hcchar.b.chen = 1;
3901 +                       ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
3902 +                       //sleep(1);
3903 +                       mdelay(1000);
3904 +
3905 +                       /* Read GINTSTS */
3906 +                       gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3907 +                       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
3908 +
3909 +                       /* Read HAINT */
3910 +                       haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
3911 +                       //fprintf(stderr, "HAINT: %08x\n", haint.d32);
3912 +
3913 +                       /* Read HCINT */
3914 +                       hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
3915 +                       //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
3916 +
3917 +                       /* Read HCCHAR */
3918 +                       hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3919 +                       //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
3920 +
3921 +                       /* Clear HCINT */
3922 +                       ifxusb_wreg(&hc_regs->hcint, hcint.d32);
3923 +
3924 +                       /* Clear HAINT */
3925 +                       ifxusb_wreg(&hc_global_regs->haint, haint.d32);
3926 +
3927 +                       /* Clear GINTSTS */
3928 +                       ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
3929 +
3930 +                       hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3931 +                       //if (hcchar.b.chen) {
3932 +                       //      fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
3933 +                       //}
3934 +               }
3935 +
3936 +               /* Set HCTSIZ */
3937 +               hctsiz.d32 = 0;
3938 +               hctsiz.b.xfersize = 8;
3939 +               hctsiz.b.pktcnt = 1;
3940 +               hctsiz.b.pid = IFXUSB_HC_PID_DATA1;
3941 +               ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
3942 +
3943 +               /* Set HCCHAR */
3944 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
3945 +               hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
3946 +               hcchar.b.epdir = 1;
3947 +               hcchar.b.epnum = 0;
3948 +               hcchar.b.mps = 8;
3949 +               hcchar.b.chen = 1;
3950 +               ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
3951 +
3952 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3953 +               //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
3954 +
3955 +               /* Wait for receive status queue interrupt */
3956 +               do {
3957 +                       gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3958 +               } while (gintsts.b.rxstsqlvl == 0);
3959 +
3960 +               //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
3961 +
3962 +               /* Read RXSTS */
3963 +               grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp);
3964 +               //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
3965 +
3966 +               /* Clear RXSTSQLVL in GINTSTS */
3967 +               gintsts.d32 = 0;
3968 +               gintsts.b.rxstsqlvl = 1;
3969 +               ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
3970 +
3971 +               switch (grxsts.hb.pktsts) {
3972 +                       case IFXUSB_HSTS_DATA_UPDT:
3973 +                               /* Read the data into the host buffer */
3974 +                               if (grxsts.hb.bcnt > 0) {
3975 +                                       int i;
3976 +                                       int word_count = (grxsts.hb.bcnt + 3) / 4;
3977 +
3978 +                                       for (i = 0; i < word_count; i++) {
3979 +                                               (void)ifxusb_rreg(data_fifo++);
3980 +                                       }
3981 +                               }
3982 +
3983 +                               //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.hb.bcnt);
3984 +                               break;
3985 +
3986 +                       default:
3987 +                               //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
3988 +                               break;
3989 +               }
3990 +
3991 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3992 +               //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
3993 +
3994 +               /* Wait for receive status queue interrupt */
3995 +               do {
3996 +                       gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
3997 +               } while (gintsts.b.rxstsqlvl == 0);
3998 +
3999 +               //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
4000 +
4001 +               /* Read RXSTS */
4002 +               grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp);
4003 +               //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
4004 +
4005 +               /* Clear RXSTSQLVL in GINTSTS */
4006 +               gintsts.d32 = 0;
4007 +               gintsts.b.rxstsqlvl = 1;
4008 +               ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
4009 +
4010 +               switch (grxsts.hb.pktsts) {
4011 +                       case IFXUSB_HSTS_XFER_COMP:
4012 +                               break;
4013 +
4014 +                       default:
4015 +                               //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
4016 +                               break;
4017 +               }
4018 +
4019 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
4020 +               //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
4021 +
4022 +               /* Wait for host channel interrupt */
4023 +               do {
4024 +                       gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
4025 +               } while (gintsts.b.hcintr == 0);
4026 +
4027 +               //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
4028 +
4029 +               /* Read HAINT */
4030 +               haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
4031 +               //fprintf(stderr, "HAINT: %08x\n", haint.d32);
4032 +
4033 +               /* Read HCINT */
4034 +               hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
4035 +               //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
4036 +
4037 +               /* Read HCCHAR */
4038 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
4039 +               //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
4040 +
4041 +               /* Clear HCINT */
4042 +               ifxusb_wreg(&hc_regs->hcint, hcint.d32);
4043 +
4044 +               /* Clear HAINT */
4045 +               ifxusb_wreg(&hc_global_regs->haint, haint.d32);
4046 +
4047 +               /* Clear GINTSTS */
4048 +               ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
4049 +
4050 +               /* Read GINTSTS */
4051 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
4052 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
4053 +
4054 +       //      usleep(100000);
4055 +       //      mdelay(100);
4056 +               mdelay(1);
4057 +
4058 +               /*
4059 +                * Send handshake packet
4060 +                */
4061 +
4062 +               /* Read HAINT */
4063 +               haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
4064 +               //fprintf(stderr, "HAINT: %08x\n", haint.d32);
4065 +
4066 +               /* Read HCINT */
4067 +               hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
4068 +               //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
4069 +
4070 +               /* Read HCCHAR */
4071 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
4072 +               //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
4073 +
4074 +               /* Clear HCINT */
4075 +               ifxusb_wreg(&hc_regs->hcint, hcint.d32);
4076 +
4077 +               /* Clear HAINT */
4078 +               ifxusb_wreg(&hc_global_regs->haint, haint.d32);
4079 +
4080 +               /* Clear GINTSTS */
4081 +               ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
4082 +
4083 +               /* Read GINTSTS */
4084 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
4085 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
4086 +
4087 +               /* Make sure channel is disabled */
4088 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
4089 +               if (hcchar.b.chen) {
4090 +                       //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
4091 +                       hcchar.b.chdis = 1;
4092 +                       hcchar.b.chen = 1;
4093 +                       ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
4094 +                       //sleep(1);
4095 +                       mdelay(1000);
4096 +
4097 +                       /* Read GINTSTS */
4098 +                       gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
4099 +                       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
4100 +
4101 +                       /* Read HAINT */
4102 +                       haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
4103 +                       //fprintf(stderr, "HAINT: %08x\n", haint.d32);
4104 +
4105 +                       /* Read HCINT */
4106 +                       hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
4107 +                       //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
4108 +
4109 +                       /* Read HCCHAR */
4110 +                       hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
4111 +                       //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
4112 +
4113 +                       /* Clear HCINT */
4114 +                       ifxusb_wreg(&hc_regs->hcint, hcint.d32);
4115 +
4116 +                       /* Clear HAINT */
4117 +                       ifxusb_wreg(&hc_global_regs->haint, haint.d32);
4118 +
4119 +                       /* Clear GINTSTS */
4120 +                       ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
4121 +
4122 +                       hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
4123 +                       //if (hcchar.b.chen) {
4124 +                       //      fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
4125 +                       //}
4126 +               }
4127 +
4128 +               /* Set HCTSIZ */
4129 +               hctsiz.d32 = 0;
4130 +               hctsiz.b.xfersize = 0;
4131 +               hctsiz.b.pktcnt = 1;
4132 +               hctsiz.b.pid = IFXUSB_HC_PID_DATA1;
4133 +               ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
4134 +
4135 +               /* Set HCCHAR */
4136 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
4137 +               hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
4138 +               hcchar.b.epdir = 0;
4139 +               hcchar.b.epnum = 0;
4140 +               hcchar.b.mps = 8;
4141 +               hcchar.b.chen = 1;
4142 +               ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
4143 +
4144 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
4145 +               //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
4146 +
4147 +               /* Wait for host channel interrupt */
4148 +               do {
4149 +                       gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
4150 +               } while (gintsts.b.hcintr == 0);
4151 +
4152 +               //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
4153 +
4154 +               /* Disable HCINTs */
4155 +               ifxusb_wreg(&hc_regs->hcintmsk, 0x0000);
4156 +
4157 +               /* Disable HAINTs */
4158 +               ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000);
4159 +
4160 +               /* Read HAINT */
4161 +               haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
4162 +               //fprintf(stderr, "HAINT: %08x\n", haint.d32);
4163 +
4164 +               /* Read HCINT */
4165 +               hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
4166 +               //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
4167 +
4168 +               /* Read HCCHAR */
4169 +               hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
4170 +               //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
4171 +
4172 +               /* Clear HCINT */
4173 +               ifxusb_wreg(&hc_regs->hcint, hcint.d32);
4174 +
4175 +               /* Clear HAINT */
4176 +               ifxusb_wreg(&hc_global_regs->haint, haint.d32);
4177 +
4178 +               /* Clear GINTSTS */
4179 +               ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
4180 +
4181 +               /* Read GINTSTS */
4182 +               gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
4183 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
4184 +       }
4185 +#endif //__WITH_HS_ELECT_TST__
4186 +
4187 --- /dev/null
4188 +++ b/drivers/usb/ifxhcd/ifxhcd_intr.c
4189 @@ -0,0 +1,3742 @@
4190 +/*****************************************************************************
4191 + **   FILE NAME       : ifxhcd_intr.c
4192 + **   PROJECT         : IFX USB sub-system V3
4193 + **   MODULES         : IFX USB sub-system Host and Device driver
4194 + **   SRC VERSION     : 1.0
4195 + **   DATE            : 1/Jan/2009
4196 + **   AUTHOR          : Chen, Howard
4197 + **   DESCRIPTION     : This file contains the implementation of the HCD Interrupt handlers.
4198 + *****************************************************************************/
4199 +
4200 +/*!
4201 + \file ifxhcd_intr.c
4202 + \ingroup IFXUSB_DRIVER_V3
4203 + \brief This file contains the implementation of the HCD Interrupt handlers.
4204 +*/
4205 +
4206 +
4207 +#include <linux/version.h>
4208 +#include "ifxusb_version.h"
4209 +
4210 +#include "ifxusb_plat.h"
4211 +#include "ifxusb_regs.h"
4212 +#include "ifxusb_cif.h"
4213 +
4214 +#include "ifxhcd.h"
4215 +
4216 +/* AVM/WK 20100520*/
4217 +#ifdef __EN_ISOC__
4218 +#error AVM/WK: CONFIG_USB_HOST_IFX_WITH_ISO currently not supported!
4219 +#endif
4220 +
4221 +/* Macro used to clear one channel interrupt */
4222 +#define clear_hc_int(_hc_regs_,_intr_) \
4223 +       do { \
4224 +               hcint_data_t hcint_clear = {.d32 = 0}; \
4225 +               hcint_clear.b._intr_ = 1; \
4226 +               ifxusb_wreg(&((_hc_regs_)->hcint), hcint_clear.d32); \
4227 +       } while (0)
4228 +
4229 +/*
4230 + * Macro used to disable one channel interrupt. Channel interrupts are
4231 + * disabled when the channel is halted or released by the interrupt handler.
4232 + * There is no need to handle further interrupts of that type until the
4233 + * channel is re-assigned. In fact, subsequent handling may cause crashes
4234 + * because the channel structures are cleaned up when the channel is released.
4235 + */
4236 +#define disable_hc_int(_hc_regs_,_intr_) \
4237 +       do { \
4238 +               hcint_data_t hcintmsk = {.d32 = 0}; \
4239 +               hcintmsk.b._intr_ = 1; \
4240 +               ifxusb_mreg(&((_hc_regs_)->hcintmsk), hcintmsk.d32, 0); \
4241 +       } while (0)
4242 +
4243 +#define enable_hc_int(_hc_regs_,_intr_) \
4244 +       do { \
4245 +               hcint_data_t hcintmsk = {.d32 = 0}; \
4246 +               hcintmsk.b._intr_ = 1; \
4247 +               ifxusb_mreg(&((_hc_regs_)->hcintmsk),0, hcintmsk.d32); \
4248 +       } while (0)
4249 +
4250 +/*
4251 + * Save the starting data toggle for the next transfer. The data toggle is
4252 + * saved in the QH for non-control transfers and it's saved in the QTD for
4253 + * control transfers.
4254 + */
4255 +uint8_t read_data_toggle(ifxusb_hc_regs_t *_hc_regs)
4256 +{
4257 +       hctsiz_data_t hctsiz;
4258 +       hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz);
4259 +       return(hctsiz.b.pid);
4260 +}
4261 +
4262 +
4263 +static void release_channel_dump(ifxhcd_hc_t      *ifxhc,
4264 +                               struct urb       *urb,
4265 +                               ifxhcd_epqh_t    *epqh,
4266 +                               ifxhcd_urbd_t    *urbd,
4267 +                               ifxhcd_halt_status_e  halt_status)
4268 +{
4269 +       #ifdef __DEBUG__
4270 +               printk(KERN_INFO);
4271 +               switch (halt_status)
4272 +               {
4273 +                       case HC_XFER_NO_HALT_STATUS:
4274 +                               printk("HC_XFER_NO_HALT_STATUS");break;
4275 +                       case HC_XFER_URB_COMPLETE:
4276 +                               printk("HC_XFER_URB_COMPLETE");break;
4277 +                       case HC_XFER_AHB_ERR:
4278 +                               printk("HC_XFER_AHB_ERR");break;
4279 +                       case HC_XFER_STALL:
4280 +                               printk("HC_XFER_STALL");break;
4281 +                       case HC_XFER_BABBLE_ERR:
4282 +                               printk("HC_XFER_BABBLE_ERR");break;
4283 +                       case HC_XFER_XACT_ERR:
4284 +                               printk("HC_XFER_XACT_ERR");break;
4285 +                       case HC_XFER_URB_DEQUEUE:
4286 +                               printk("HC_XFER_URB_DEQUEUE");break;
4287 +                       case HC_XFER_FRAME_OVERRUN:
4288 +                               printk("HC_XFER_FRAME_OVERRUN");break;
4289 +                       case HC_XFER_DATA_TOGGLE_ERR:
4290 +                               printk("HC_XFER_DATA_TOGGLE_ERR");break;
4291 +                       case HC_XFER_NAK:
4292 +                               printk("HC_XFER_NAK");break;
4293 +                       case HC_XFER_COMPLETE:
4294 +                               printk("HC_XFER_COMPLETE");break;
4295 +                       default:
4296 +                               printk("KNOWN");break;
4297 +               }
4298 +               if(ifxhc)
4299 +                       printk("Ch %d %s%s S%d " , ifxhc->hc_num
4300 +                               ,(ifxhc->ep_type == IFXUSB_EP_TYPE_CTRL)?"CTRL-":
4301 +                                  ((ifxhc->ep_type == IFXUSB_EP_TYPE_BULK)?"BULK-":
4302 +                                    ((ifxhc->ep_type == IFXUSB_EP_TYPE_INTR)?"INTR-":
4303 +                                      ((ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC)?"ISOC-":"????"
4304 +                                      )
4305 +                                    )
4306 +                                  )
4307 +                               ,(ifxhc->is_in)?"IN":"OUT"
4308 +                               ,(ifxhc->split)
4309 +                               );
4310 +               else
4311 +                       printk(" [NULL HC] ");
4312 +               printk("urb=%p epqh=%p urbd=%p\n",urb,epqh,urbd);
4313 +
4314 +               if(urb)
4315 +               {
4316 +                       printk(KERN_INFO "  Device address: %d\n", usb_pipedevice(urb->pipe));
4317 +                       printk(KERN_INFO "  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
4318 +                                   (usb_pipein(urb->pipe) ? "IN" : "OUT"));
4319 +                       printk(KERN_INFO "  Endpoint type: %s\n",
4320 +                                   ({char *pipetype;
4321 +                                   switch (usb_pipetype(urb->pipe)) {
4322 +                                           case PIPE_CONTROL: pipetype = "CTRL"; break;
4323 +                                           case PIPE_BULK: pipetype = "BULK"; break;
4324 +                                           case PIPE_INTERRUPT: pipetype = "INTR"; break;
4325 +                                           case PIPE_ISOCHRONOUS: pipetype = "ISOC"; break;
4326 +                                           default: pipetype = "????"; break;
4327 +                                   }; pipetype;}));
4328 +                       printk(KERN_INFO "  Speed: %s\n",
4329 +                                   ({char *speed;
4330 +                                   switch (urb->dev->speed) {
4331 +                                           case USB_SPEED_HIGH: speed = "HS"; break;
4332 +                                           case USB_SPEED_FULL: speed = "FS"; break;
4333 +                                           case USB_SPEED_LOW: speed = "LS"; break;
4334 +                                       default: speed = "????"; break;
4335 +                                   }; speed;}));
4336 +                       printk(KERN_INFO "  Max packet size: %d\n",
4337 +                                   usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4338 +                       printk(KERN_INFO "  Data buffer length: %d\n", urb->transfer_buffer_length);
4339 +                       printk(KERN_INFO "  Transfer buffer: %p, Transfer DMA: %p\n",
4340 +                                   urb->transfer_buffer, (void *)urb->transfer_dma);
4341 +                       printk(KERN_INFO "  Setup buffer: %p, Setup DMA: %p\n",
4342 +                                   urb->setup_packet, (void *)urb->setup_dma);
4343 +                       printk(KERN_INFO "  Interval: %d\n", urb->interval);
4344 +                       switch (urb->status)
4345 +                       {
4346 +                               case HC_XFER_NO_HALT_STATUS:
4347 +                                       printk(KERN_INFO "  STATUS:HC_XFER_NO_HALT_STATUS\n");break;
4348 +                               case HC_XFER_URB_COMPLETE:
4349 +                                       printk(KERN_INFO "  STATUS:HC_XFER_URB_COMPLETE\n");break;
4350 +                               case HC_XFER_AHB_ERR:
4351 +                                       printk(KERN_INFO "  STATUS:HC_XFER_AHB_ERR\n");break;
4352 +                               case HC_XFER_STALL:
4353 +                                       printk(KERN_INFO "  STATUS:HC_XFER_STALL\n");break;
4354 +                               case HC_XFER_BABBLE_ERR:
4355 +                                       printk(KERN_INFO "  STATUS:HC_XFER_BABBLE_ERR\n");break;
4356 +                               case HC_XFER_XACT_ERR:
4357 +                                       printk(KERN_INFO "  STATUS:HC_XFER_XACT_ERR\n");break;
4358 +                               case HC_XFER_URB_DEQUEUE:
4359 +                                       printk(KERN_INFO "  STATUS:HC_XFER_URB_DEQUEUE\n");break;
4360 +                               case HC_XFER_FRAME_OVERRUN:
4361 +                                       printk(KERN_INFO "  STATUS:HC_XFER_FRAME_OVERRUN\n");break;
4362 +                               case HC_XFER_DATA_TOGGLE_ERR:
4363 +                                       printk(KERN_INFO "  STATUS:HC_XFER_DATA_TOGGLE_ERR\n");break;
4364 +                               case HC_XFER_COMPLETE:
4365 +                                       printk(KERN_INFO "  STATUS:HC_XFER_COMPLETE\n");break;
4366 +                               default:
4367 +                                       printk(KERN_INFO "  STATUS:KNOWN\n");break;
4368 +                       }
4369 +               }
4370 +       #endif
4371 +}
4372 +
4373 +
4374 +static void release_channel(ifxhcd_hcd_t          *_ifxhcd,
4375 +                            ifxhcd_hc_t           *_ifxhc,
4376 +                            ifxhcd_halt_status_e  _halt_status)
4377 +{
4378 +       ifxusb_hc_regs_t *hc_regs = _ifxhcd->core_if.hc_regs[_ifxhc->hc_num];
4379 +       struct urb       *urb     = NULL;
4380 +       ifxhcd_epqh_t    *epqh    = NULL;
4381 +       ifxhcd_urbd_t    *urbd    = NULL;
4382 +
4383 +       IFX_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
4384 +                   __func__, _ifxhc->hc_num, _halt_status);
4385 +
4386 +       epqh=_ifxhc->epqh;
4387 +
4388 +       if(!epqh)
4389 +               IFX_ERROR("%s epqh=null\n",__func__);
4390 +       else
4391 +       {
4392 +               urbd=epqh->urbd;
4393 +               if(!urbd)
4394 +                       IFX_ERROR("%s urbd=null\n",__func__);
4395 +               else
4396 +               {
4397 +                       urb=urbd->urb;
4398 +                       if(!urb)
4399 +                               IFX_ERROR("%s urb =null\n",__func__);
4400 +                       else {
4401 +                               /* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/
4402 +                               unsigned toggle = (read_data_toggle(hc_regs) == IFXUSB_HC_PID_DATA0)? 0: 1;
4403 +                               usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), usb_pipeout(urb->pipe), toggle);
4404 +                       }
4405 +               }
4406 +               //epqh->data_toggle = read_data_toggle(hc_regs);
4407 +
4408 +       }
4409 +
4410 +       switch (_halt_status)
4411 +       {
4412 +               case HC_XFER_NO_HALT_STATUS:
4413 +                       IFX_ERROR("%s: No halt_status, channel %d\n", __func__, _ifxhc->hc_num);
4414 +                       break;
4415 +               case HC_XFER_COMPLETE:
4416 +                       IFX_ERROR("%s: Inavalid halt_status HC_XFER_COMPLETE, channel %d\n", __func__, _ifxhc->hc_num);
4417 +                       break;
4418 +               case HC_XFER_URB_COMPLETE:
4419 +               case HC_XFER_URB_DEQUEUE:
4420 +               case HC_XFER_AHB_ERR:
4421 +               case HC_XFER_XACT_ERR:
4422 +               case HC_XFER_FRAME_OVERRUN:
4423 +                       if(urbd && urb) {
4424 +                               /* == 20110803 AVM/WK FIX set status, if still in progress == */
4425 +                               if (urb->status == -EINPROGRESS) {
4426 +                                       switch (_halt_status) {
4427 +                                       case HC_XFER_URB_COMPLETE:
4428 +                                               urb->status = 0;
4429 +                                               break;
4430 +                                       case HC_XFER_URB_DEQUEUE:
4431 +                                               urb->status = -ECONNRESET;
4432 +                                               break;
4433 +                                       case HC_XFER_AHB_ERR:
4434 +                                       case HC_XFER_XACT_ERR:
4435 +                                       case HC_XFER_FRAME_OVERRUN:
4436 +                                               urb->status = -EPROTO;
4437 +                                               break;
4438 +                                       default:
4439 +                                               break;
4440 +                                       }
4441 +                               }
4442 +                               /*== AVM/BC 20101111 Deferred Complete ==*/
4443 +                               defer_ifxhcd_complete_urb(_ifxhcd, urbd, urb->status);
4444 +                       }
4445 +                       else
4446 +                       {
4447 +                               IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb);
4448 +                               release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status);
4449 +                       }
4450 +                       if(epqh)
4451 +                               ifxhcd_epqh_idle(_ifxhcd, epqh);
4452 +                       else
4453 +                       {
4454 +                               IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh);
4455 +                               release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status);
4456 +                       }
4457 +
4458 +                       list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list);
4459 +                       ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc);
4460 +                       break;
4461 +               case HC_XFER_STALL:
4462 +                       release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status);
4463 +                       if(urbd)
4464 +                               /*== AVM/BC 20101111 Deferred Complete ==*/
4465 +                               defer_ifxhcd_complete_urb(_ifxhcd, urbd, -EPIPE);
4466 +                       else
4467 +                               IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb);
4468 +                       if(epqh)
4469 +                       {
4470 +//                             epqh->data_toggle = 0;
4471 +                               ifxhcd_epqh_idle(_ifxhcd, epqh);
4472 +                       }
4473 +                       else
4474 +                               IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh);
4475 +                       list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list);
4476 +                       ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc);
4477 +                       break;
4478 +               case HC_XFER_NAK:
4479 +                       release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status);
4480 +                       if(urbd)
4481 +                       {
4482 +                               //ifxhcd_complete_urb(_ifxhcd, urbd, -ETIMEDOUT);
4483 +                               urb->status = 0;
4484 +                               /*== AVM/BC 20101111 Deferred Complete ==*/
4485 +                               defer_ifxhcd_complete_urb(_ifxhcd, urbd, urb->status);
4486 +                       }
4487 +                       else
4488 +                               IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb);
4489 +                       if(epqh)
4490 +                               ifxhcd_epqh_idle(_ifxhcd, epqh);
4491 +                       else
4492 +                               IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh);
4493 +                       list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list);
4494 +                       ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc);
4495 +                       break;
4496 +               case HC_XFER_BABBLE_ERR:
4497 +               case HC_XFER_DATA_TOGGLE_ERR:
4498 +                       release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status);
4499 +                       if(urbd)
4500 +                               /*== AVM/BC 20101111 Deferred Complete ==*/
4501 +                               defer_ifxhcd_complete_urb(_ifxhcd, urbd, -EOVERFLOW);
4502 +                       else
4503 +                               IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb);
4504 +                       if(epqh)
4505 +                               ifxhcd_epqh_idle(_ifxhcd, epqh);
4506 +                       else
4507 +                               IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh);
4508 +                       list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list);
4509 +                       ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc);
4510 +                       break;
4511 +       }
4512 +       select_eps(_ifxhcd);
4513 +}
4514 +
4515 +/*
4516 + * Updates the state of the URB after a Transfer Complete interrupt on the
4517 + * host channel. Updates the actual_length field of the URB based on the
4518 + * number of bytes transferred via the host channel. Sets the URB status
4519 + * if the data transfer is finished.
4520 + *
4521 + * @return 1 if the data transfer specified by the URB is completely finished,
4522 + * 0 otherwise.
4523 + */
4524 +static int update_urb_state_xfer_comp(ifxhcd_hc_t       *_ifxhc,
4525 +                                      ifxusb_hc_regs_t  *_hc_regs,
4526 +                                      struct urb        *_urb,
4527 +                                      ifxhcd_urbd_t      *_urbd)
4528 +{
4529 +       int xfer_done  = 0;
4530 +
4531 +       if (_ifxhc->is_in)
4532 +       {
4533 +               hctsiz_data_t hctsiz;
4534 +               hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz);
4535 +               _urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
4536 +               if ((hctsiz.b.xfersize != 0) || (_urb->actual_length >= _urb->transfer_buffer_length))
4537 +               {
4538 +                       xfer_done = 1;
4539 +                       _urb->status = 0;
4540 +                       /* 20110805 AVM/WK Workaround: catch overflow error here, hardware does not */
4541 +                       if (_urb->actual_length > _urb->transfer_buffer_length) {
4542 +                               _urb->status = -EOVERFLOW;
4543 +                       }
4544 +                       #if 0
4545 +                               if (_urb->actual_length < _urb->transfer_buffer_length && _urb->transfer_flags & URB_SHORT_NOT_OK)
4546 +                               _urb->status = -EREMOTEIO;
4547 +                       #endif
4548 +               }
4549 +
4550 +       }
4551 +       else
4552 +       {
4553 +               if (_ifxhc->split)
4554 +                       _urb->actual_length +=  _ifxhc->ssplit_out_xfer_count;
4555 +               else
4556 +                       _urb->actual_length +=  _ifxhc->xfer_len;
4557 +
4558 +               if (_urb->actual_length >= _urb->transfer_buffer_length)
4559 +               {
4560 +                       /*== AVM/BC WK 20110421 ZERO PACKET Workaround ==*/
4561 +                       if ((_ifxhc->short_rw == 1) && ( _ifxhc->xfer_len > 0) && ( _ifxhc->xfer_len % _ifxhc->mps == 0 ))
4562 +                       {
4563 +                               _ifxhc->short_rw = 0;
4564 +                               //Transfer not finished. Another iteration for ZLP.
4565 +                       }
4566 +                       else
4567 +                       {
4568 +                               xfer_done = 1;
4569 +                       }
4570 +                       _urb->status = 0;
4571 +               }
4572 +       }
4573 +
4574 +       #ifdef __DEBUG__
4575 +               {
4576 +                       hctsiz_data_t   hctsiz;
4577 +                       hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz);
4578 +                       IFX_DEBUGPL(DBG_HCDV, "IFXUSB: %s: %s, channel %d\n",
4579 +                                   __func__, (_ifxhc->is_in ? "IN" : "OUT"), _ifxhc->hc_num);
4580 +                       IFX_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", _ifxhc->xfer_len);
4581 +                       IFX_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n", hctsiz.b.xfersize);
4582 +                       IFX_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
4583 +                                   _urb->transfer_buffer_length);
4584 +                       IFX_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n", _urb->actual_length);
4585 +               }
4586 +       #endif
4587 +       return xfer_done;
4588 +}
4589 +
4590 +/*== AVM/BC 20101111 Function called with Lock ==*/
4591 +
4592 +void complete_channel(ifxhcd_hcd_t        *_ifxhcd,
4593 +                            ifxhcd_hc_t          *_ifxhc,
4594 +                            ifxhcd_urbd_t        *_urbd)
4595 +{
4596 +       ifxusb_hc_regs_t *hc_regs = _ifxhcd->core_if.hc_regs[_ifxhc->hc_num];
4597 +       struct urb    *urb  = NULL;
4598 +       ifxhcd_epqh_t *epqh = NULL;
4599 +       int urb_xfer_done;
4600 +
4601 +       IFX_DEBUGPL(DBG_HCD, "--Complete Channel %d : \n", _ifxhc->hc_num);
4602 +
4603 +       if(!_urbd)
4604 +       {
4605 +               IFX_ERROR("ERROR %s():%d urbd=%p\n",__func__,__LINE__,_urbd);
4606 +               return;
4607 +       }
4608 +
4609 +       urb  = _urbd->urb;
4610 +       epqh = _urbd->epqh;
4611 +
4612 +       if(!urb || !epqh)
4613 +       {
4614 +               IFX_ERROR("ERROR %s():%d urb=%p epqh=%p\n",__func__,__LINE__,urb,epqh);
4615 +               return;
4616 +       }
4617 +
4618 +       _ifxhc->do_ping=0;
4619 +
4620 +       if (_ifxhc->split)
4621 +               _ifxhc->split = 1;
4622 +
4623 +       switch (epqh->ep_type)
4624 +       {
4625 +               case IFXUSB_EP_TYPE_CTRL:
4626 +                       switch (_ifxhc->control_phase)
4627 +                       {
4628 +                               case IFXHCD_CONTROL_SETUP:
4629 +                                       IFX_DEBUGPL(DBG_HCDV, "  Control setup transaction done\n");
4630 +                                       if (_urbd->xfer_len > 0)
4631 +                                       {
4632 +                                               _ifxhc->control_phase = IFXHCD_CONTROL_DATA;
4633 +                                               _ifxhc->is_in         = _urbd->is_in;
4634 +                                               _ifxhc->xfer_len      = _urbd->xfer_len;
4635 +                                               #if   defined(__UNALIGNED_BUFFER_ADJ__)
4636 +                                                       if(epqh->using_aligned_buf)
4637 +                                                               _ifxhc->xfer_buff      = epqh->aligned_buf;
4638 +                                                       else
4639 +                                               #endif
4640 +                                                               _ifxhc->xfer_buff      = _urbd->xfer_buff;
4641 +                                       }
4642 +                                       else
4643 +                                       {
4644 +                                               _ifxhc->control_phase = IFXHCD_CONTROL_STATUS;
4645 +                                               _ifxhc->is_in          = 1;
4646 +                                               _ifxhc->xfer_len       = 0;
4647 +                                               _ifxhc->xfer_buff      = _ifxhcd->status_buf;
4648 +                                       }
4649 +                                       if(_ifxhc->is_in)
4650 +                                               _ifxhc->short_rw       =0;
4651 +                                       else
4652 +                                               _ifxhc->short_rw       =(urb->transfer_flags & URB_ZERO_PACKET)?1:0;
4653 +                                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1;
4654 +                                       _ifxhc->xfer_count     = 0;
4655 +                                       _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
4656 +                                       /*== AVM/BC 20101111 Lock not needed ==*/
4657 +                                       process_channels_sub(_ifxhcd);
4658 +                                       break;
4659 +                               case IFXHCD_CONTROL_DATA:
4660 +                                       urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd);
4661 +                                       if (urb_xfer_done)
4662 +                                       {
4663 +                                               _ifxhc->control_phase  = IFXHCD_CONTROL_STATUS;
4664 +                                               _ifxhc->is_in          = (_urbd->is_in)?0:1;
4665 +                                               _ifxhc->xfer_len       = 0;
4666 +                                               _ifxhc->xfer_count     = 0;
4667 +                                               _ifxhc->xfer_buff      = _ifxhcd->status_buf;
4668 +                                               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
4669 +                                               _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1;
4670 +                                               if(_ifxhc->is_in)
4671 +                                                       _ifxhc->short_rw       =0;
4672 +                                               else
4673 +                                                       _ifxhc->short_rw       =1;
4674 +                                       }
4675 +                                       else // continue
4676 +                                       {
4677 +                                               _ifxhc->xfer_len       = _urbd->xfer_len - urb->actual_length;
4678 +                                               _ifxhc->xfer_count     = urb->actual_length;
4679 +                                               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
4680 +                                               _ifxhc->data_pid_start = read_data_toggle(hc_regs);
4681 +                                       }
4682 +                                       /*== AVM/BC 20101111 Lock not needed ==*/
4683 +                                       process_channels_sub(_ifxhcd);
4684 +                                       break;
4685 +                               case IFXHCD_CONTROL_STATUS:
4686 +                                       if (urb->status == -EINPROGRESS)
4687 +                                               urb->status = 0;
4688 +                                       release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE);
4689 +                                       break;
4690 +                       }
4691 +                       break;
4692 +               case IFXUSB_EP_TYPE_BULK:
4693 +                       IFX_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
4694 +                       urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd);
4695 +                       if (urb_xfer_done)
4696 +                               release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE);
4697 +                       else
4698 +                       {
4699 +                               _ifxhc->xfer_len       = _urbd->xfer_len - urb->actual_length;
4700 +                               _ifxhc->xfer_count     = urb->actual_length;
4701 +                               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
4702 +                               _ifxhc->data_pid_start = read_data_toggle(hc_regs);
4703 +                               /*== AVM/BC 20101111 Lock not needed ==*/
4704 +                               process_channels_sub(_ifxhcd);
4705 +                       }
4706 +                       break;
4707 +               case IFXUSB_EP_TYPE_INTR:
4708 +                       urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd);
4709 +                       release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE);
4710 +                       break;
4711 +               case IFXUSB_EP_TYPE_ISOC:
4712 +//                     if (_urbd->isoc_split_pos == IFXUSB_HCSPLIT_XACTPOS_ALL)
4713 +//                             halt_status = update_isoc_urb_state(_ifxhcd, _ifxhc, hc_regs, _urbd, HC_XFER_COMPLETE);
4714 +//                     complete_periodic_xfer(_ifxhcd, _ifxhc, hc_regs, _urbd, halt_status);
4715 +                       urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd);
4716 +                       release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE);
4717 +                       break;
4718 +       }
4719 +}
4720 +
4721 +
4722 +
4723 +void showint(uint32_t val_hcint
4724 +            ,uint32_t val_hcintmsk
4725 +            ,uint32_t val_hctsiz)
4726 +{
4727 +#ifdef __DEBUG__
4728 +       hcint_data_t  hcint    = {.d32 = val_hcint};
4729 +       hcint_data_t  hcintmsk = {.d32 = val_hcintmsk};
4730 +
4731 +       printk(KERN_INFO "   WITH FLAG: Sz:%08x I:%08X/M:%08X %s%s%s%s%s%s%s%s%s%s\n"
4732 +               ,val_hctsiz,hcint.d32 ,hcintmsk.d32
4733 +               ,(hcint.b.datatglerr || hcintmsk.b.datatglerr)?
4734 +                (
4735 +                  (hcint.b.datatglerr && hcintmsk.b.datatglerr)?"datatglerr[*/*] ":
4736 +                   (
4737 +                     (hcint.b.datatglerr)?"datatglerr[*/] ":"datatglerr[/*] "
4738 +                   )
4739 +                )
4740 +                :""
4741 +               ,(hcint.b.frmovrun || hcintmsk.b.frmovrun)?
4742 +                (
4743 +                  (hcint.b.frmovrun && hcintmsk.b.frmovrun)?"frmovrun[*/*] ":
4744 +                   (
4745 +                     (hcint.b.frmovrun)?"frmovrun[*/] ":"frmovrun[/*] "
4746 +                   )
4747 +                )
4748 +                :""
4749 +               ,(hcint.b.bblerr || hcintmsk.b.bblerr)?
4750 +                (
4751 +                  (hcint.b.bblerr && hcintmsk.b.bblerr)?"bblerr[*/*] ":
4752 +                   (
4753 +                     (hcint.b.bblerr)?"bblerr[*/] ":"bblerr[/*] "
4754 +                   )
4755 +                )
4756 +                :""
4757 +               ,(hcint.b.xacterr || hcintmsk.b.xacterr)?
4758 +                (
4759 +                  (hcint.b.xacterr && hcintmsk.b.xacterr)?"xacterr[*/*] ":
4760 +                   (
4761 +                     (hcint.b.xacterr)?"xacterr[*/] ":"xacterr[/*] "
4762 +                   )
4763 +                )
4764 +                :""
4765 +               ,(hcint.b.nyet || hcintmsk.b.nyet)?
4766 +                (
4767 +                  (hcint.b.nyet && hcintmsk.b.nyet)?"nyet[*/*] ":
4768 +                   (
4769 +                     (hcint.b.nyet)?"nyet[*/] ":"nyet[/*] "
4770 +                   )
4771 +                )
4772 +                :""
4773 +               ,(hcint.b.nak || hcintmsk.b.nak)?
4774 +                (
4775 +                  (hcint.b.nak && hcintmsk.b.nak)?"nak[*/*] ":
4776 +                   (
4777 +                     (hcint.b.nak)?"nak[*/] ":"nak[/*] "
4778 +                   )
4779 +                )
4780 +                :""
4781 +               ,(hcint.b.ack || hcintmsk.b.ack)?
4782 +                (
4783 +                  (hcint.b.ack && hcintmsk.b.ack)?"ack[*/*] ":
4784 +                   (
4785 +                     (hcint.b.ack)?"ack[*/] ":"ack[/*] "
4786 +                   )
4787 +                )
4788 +                :""
4789 +               ,(hcint.b.stall || hcintmsk.b.stall)?
4790 +                (
4791 +                  (hcint.b.stall && hcintmsk.b.stall)?"stall[*/*] ":
4792 +                   (
4793 +                     (hcint.b.stall)?"stall[*/] ":"stall[/*] "
4794 +                   )
4795 +                )
4796 +                :""
4797 +               ,(hcint.b.ahberr || hcintmsk.b.ahberr)?
4798 +                (
4799 +                  (hcint.b.ahberr && hcintmsk.b.ahberr)?"ahberr[*/*] ":
4800 +                   (
4801 +                     (hcint.b.ahberr)?"ahberr[*/] ":"ahberr[/*] "
4802 +                   )
4803 +                )
4804 +                :""
4805 +               ,(hcint.b.xfercomp || hcintmsk.b.xfercomp)?
4806 +                (
4807 +                  (hcint.b.xfercomp && hcintmsk.b.xfercomp)?"xfercomp[*/*] ":
4808 +                   (
4809 +                     (hcint.b.xfercomp)?"xfercomp[*/] ":"xfercomp[/*] "
4810 +                   )
4811 +                )
4812 +                :""
4813 +       );
4814 +#endif
4815 +}
4816 +
4817 +
4818 +extern void ifxhcd_hc_dumb_rx(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc,uint8_t   *dump_buf);
4819 +
4820 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
4821 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
4822 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
4823 +static int32_t chhltd_ctrlbulk_rx_nonsplit(ifxhcd_hcd_t      *_ifxhcd,
4824 +                                        ifxhcd_hc_t       *_ifxhc,
4825 +                                        ifxusb_hc_regs_t  *_hc_regs,
4826 +                                        ifxhcd_urbd_t     *_urbd)
4827 +{
4828 +       hcint_data_t  hcint;
4829 +       hcint_data_t  hcintmsk;
4830 +       hctsiz_data_t hctsiz;
4831 +
4832 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
4833 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
4834 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
4835 +
4836 +       disable_hc_int(_hc_regs,ack);
4837 +       disable_hc_int(_hc_regs,nak);
4838 +       disable_hc_int(_hc_regs,nyet);
4839 +       _ifxhc->do_ping        = 0;
4840 +
4841 +       if(_ifxhc->halt_status == HC_XFER_NAK)
4842 +       {
4843 +               if(_ifxhc->nak_retry_r)
4844 +               {
4845 +                       _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
4846 +                       _ifxhc->nak_retry--;
4847 +                       if(_ifxhc->nak_retry)
4848 +                       {
4849 +                               _ifxhc->xfer_len           = _urbd->xfer_len - _urbd->urb->actual_length;
4850 +                               _ifxhc->xfer_count         = _urbd->urb->actual_length;
4851 +                               _ifxhc->data_pid_start     = read_data_toggle(_hc_regs);
4852 +                               _ifxhc->wait_for_sof   = 1;
4853 +                               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
4854 +                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
4855 +                       }
4856 +                       else
4857 +                       {
4858 +                               _ifxhc->wait_for_sof   = 0;
4859 +                               release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status);
4860 +                       }
4861 +               }
4862 +               else
4863 +               {
4864 +                       _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
4865 +                       _ifxhc->xfer_len           = _urbd->xfer_len - _urbd->urb->actual_length;
4866 +                       _ifxhc->xfer_count         = _urbd->urb->actual_length;
4867 +                       _ifxhc->data_pid_start     = read_data_toggle(_hc_regs);
4868 +                       _ifxhc->wait_for_sof   = 1;
4869 +                       _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
4870 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
4871 +               }
4872 +               return 1;
4873 +       }
4874 +
4875 +       if (hcint.b.xfercomp)
4876 +       {
4877 +               _urbd->error_count     =0;
4878 +               _ifxhc->wait_for_sof   =0;
4879 +               complete_channel(_ifxhcd, _ifxhc, _urbd);
4880 +               return 1;
4881 +       }
4882 +       else if (hcint.b.stall)
4883 +       {
4884 +               _urbd->error_count     =0;
4885 +               _ifxhc->wait_for_sof   =0;
4886 +               // ZLP shortcut
4887 +               #if 0
4888 +               if(hctsiz.b.pktcnt==0)
4889 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
4890 +               else
4891 +               #endif
4892 +               {
4893 +               // Stall FIFO compensation.
4894 +               #if 0
4895 +                       int sz1,sz2;
4896 +                       sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt;
4897 +                       sz2*=_ifxhc->mps;
4898 +                       sz1=_ifxhc->xfer_len - hctsiz.b.xfersize;
4899 +                       sz2-=sz1;
4900 +                       if(sz2)
4901 +                               ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf);
4902 +               #endif
4903 +                       _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
4904 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
4905 +               }
4906 +               return 1;
4907 +       }
4908 +       else if (hcint.b.bblerr)
4909 +       {
4910 +               _urbd->error_count     =0;
4911 +               _ifxhc->wait_for_sof   =0;
4912 +
4913 +               // ZLP shortcut
4914 +               #if 0
4915 +               if(hctsiz.b.pktcnt==0)
4916 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
4917 +               else
4918 +               #endif
4919 +               _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
4920 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
4921 +               return 1;
4922 +       }
4923 +       else if (hcint.b.xacterr)
4924 +       {
4925 +               // ZLP shortcut
4926 +               #if 1
4927 +               if(hctsiz.b.pktcnt==0)
4928 +               {
4929 +                       _urbd->error_count     =0;
4930 +                       _ifxhc->wait_for_sof   =0;
4931 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
4932 +               }
4933 +               else
4934 +               #endif
4935 +               {
4936 +                       _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
4937 +                       _ifxhc->xfer_len           = _urbd->xfer_len - _urbd->urb->actual_length;
4938 +                       _ifxhc->xfer_count         = _urbd->urb->actual_length;
4939 +                       _ifxhc->data_pid_start     = read_data_toggle(_hc_regs);
4940 +
4941 +                       /* 20110803 AVM/WK FIX: Reset error count on any handshake */
4942 +                       if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) {
4943 +                               _urbd->error_count = 1;
4944 +                       } else {
4945 +                               _urbd->error_count++;
4946 +                       }
4947 +
4948 +                       if (_urbd->error_count >= 3)
4949 +                       {
4950 +                               _urbd->error_count     =0;
4951 +                               _ifxhc->wait_for_sof   =0;
4952 +                               release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
4953 +                       }
4954 +                       else
4955 +                       {
4956 +                               _ifxhc->wait_for_sof   = 1;
4957 +                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
4958 +                       }
4959 +               }
4960 +               return 1;
4961 +       }
4962 +       else if(hcint.b.datatglerr )
4963 +       {
4964 +               _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
4965 +               #if 1
4966 +                       if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0)
4967 +                               _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1;
4968 +                       else
4969 +                               _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0;
4970 +                       _ifxhc->wait_for_sof   = 1;
4971 +                       _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
4972 +                       _ifxhc->xfer_count     = _urbd->urb->actual_length;
4973 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
4974 +               #else
4975 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR);
4976 +               #endif
4977 +               return 1;
4978 +       }
4979 +       else if(hcint.b.frmovrun   )
4980 +       {
4981 +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT0 FRMOVRUN [should be Period only]\n",__func__,__LINE__);
4982 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
4983 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN);
4984 +               return 1;
4985 +       }
4986 +       else if(hcint.b.nyet   )
4987 +       {
4988 +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT0 NYET  [should be Out only]\n",__func__,__LINE__);
4989 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
4990 +       }
4991 +       return 0;
4992 +}
4993 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
4994 +static int32_t chhltd_ctrlbulk_tx_nonsplit(ifxhcd_hcd_t      *_ifxhcd,
4995 +                                        ifxhcd_hc_t       *_ifxhc,
4996 +                                        ifxusb_hc_regs_t  *_hc_regs,
4997 +                                        ifxhcd_urbd_t     *_urbd)
4998 +{
4999 +       hcint_data_t  hcint;
5000 +       hcint_data_t  hcintmsk;
5001 +       hctsiz_data_t hctsiz;
5002 +       int out_nak_enh = 0;
5003 +
5004 +#ifdef __DEBUG__
5005 +static int first=0;
5006 +#endif
5007 +
5008 +       if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
5009 +               out_nak_enh = 1;
5010 +
5011 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
5012 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
5013 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
5014 +
5015 +#ifdef __DEBUG__
5016 +if(!first&& _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK
5017 +   &&(hcint.b.stall || hcint.b.datatglerr || hcint.b.frmovrun || hcint.b.bblerr || hcint.b.xacterr) && !hcint.b.ack)
5018 +{
5019 +       showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5020 +       first=1;
5021 +       printk(KERN_INFO "   [%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X] \n"
5022 +       ,*(_ifxhc->xfer_buff+ 0),*(_ifxhc->xfer_buff+ 1),*(_ifxhc->xfer_buff+ 2),*(_ifxhc->xfer_buff+ 3)
5023 +       ,*(_ifxhc->xfer_buff+ 4),*(_ifxhc->xfer_buff+ 5),*(_ifxhc->xfer_buff+ 6),*(_ifxhc->xfer_buff+ 7)
5024 +       ,*(_ifxhc->xfer_buff+ 8),*(_ifxhc->xfer_buff+ 9),*(_ifxhc->xfer_buff+10),*(_ifxhc->xfer_buff+11)
5025 +       ,*(_ifxhc->xfer_buff+12),*(_ifxhc->xfer_buff+13),*(_ifxhc->xfer_buff+14),*(_ifxhc->xfer_buff+15));
5026 +
5027 +       printk(KERN_INFO "   [_urbd->urb->actual_length:%08X _ifxhc->start_pkt_count:%08X hctsiz.b.pktcnt:%08X ,_urbd->xfer_len:%08x] \n"
5028 +       ,_urbd->urb->actual_length
5029 +       ,_ifxhc->start_pkt_count
5030 +       ,hctsiz.b.pktcnt
5031 +       ,_urbd->xfer_len);
5032 +}
5033 +#endif
5034 +
5035 +       if(_ifxhc->halt_status == HC_XFER_NAK)
5036 +       {
5037 +               if(_ifxhc->nak_retry_r)
5038 +               {
5039 +                       _ifxhc->nak_retry--;
5040 +                       if(_ifxhc->nak_retry)
5041 +                       {
5042 +                               if(_ifxhc->xfer_len!=0)
5043 +                                       _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5044 +                               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
5045 +                               _ifxhc->xfer_count     = _urbd->urb->actual_length;
5046 +                               _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5047 +                               _ifxhc->wait_for_sof   = 1;
5048 +                               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
5049 +                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5050 +                       }
5051 +                       else
5052 +                       {
5053 +                               _ifxhc->wait_for_sof   = 0;
5054 +                               release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status);
5055 +                       }
5056 +               }
5057 +               else
5058 +               {
5059 +                       if(_ifxhc->xfer_len!=0)
5060 +                               _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5061 +                       _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
5062 +                       _ifxhc->xfer_count     = _urbd->urb->actual_length;
5063 +                       _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5064 +                       _ifxhc->wait_for_sof   = 1;
5065 +                       _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
5066 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5067 +               }
5068 +               return 1;
5069 +       }
5070 +
5071 +       if (hcint.b.xfercomp)
5072 +       {
5073 +               disable_hc_int(_hc_regs,ack);
5074 +               disable_hc_int(_hc_regs,nak);
5075 +               disable_hc_int(_hc_regs,nyet);
5076 +               _urbd->error_count     =0;
5077 +               if(_ifxhc->xfer_len==0 && !hcint.b.ack && hcint.b.nak)
5078 +               {
5079 +                       // Walkaround: When sending ZLP and receive NAK but also issue CMPT intr
5080 +                       // Solution:   NoSplit: Resend at next SOF
5081 +                       //             Split  : Resend at next SOF with SSPLIT
5082 +                       if(hcint.b.nyet && !out_nak_enh)
5083 +                               _ifxhc->do_ping        = 1;
5084 +                       else
5085 +                               _ifxhc->do_ping        = 0;
5086 +                       _ifxhc->xfer_len       = 0;
5087 +                       _ifxhc->xfer_count     = 0;
5088 +                       _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
5089 +                       _ifxhc->wait_for_sof   = 1;
5090 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5091 +               }
5092 +               else
5093 +               {
5094 +                       _ifxhc->wait_for_sof   = 0;
5095 +                       _ifxhc->do_ping        = 0;
5096 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5097 +               }
5098 +               return 1;
5099 +       }
5100 +       else if (hcint.b.stall)
5101 +       {
5102 +               disable_hc_int(_hc_regs,ack);
5103 +               disable_hc_int(_hc_regs,nak);
5104 +               disable_hc_int(_hc_regs,nyet);
5105 +               _urbd->error_count     =0;
5106 +               _ifxhc->wait_for_sof   =0;
5107 +               _ifxhc->do_ping        =0;
5108 +
5109 +               // ZLP shortcut
5110 +               #if 1
5111 +               if(hctsiz.b.pktcnt==0)
5112 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5113 +               else
5114 +               #endif
5115 +               {
5116 +                       if(_ifxhc->xfer_len!=0)
5117 +                               _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5118 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
5119 +               }
5120 +               return 1;
5121 +       }
5122 +       else if (hcint.b.xacterr)
5123 +       {
5124 +               // ZLP shortcut
5125 +               #if 1
5126 +               if(hctsiz.b.pktcnt==0)
5127 +               {
5128 +                       disable_hc_int(_hc_regs,ack);
5129 +                       disable_hc_int(_hc_regs,nak);
5130 +                       disable_hc_int(_hc_regs,nyet);
5131 +                       _urbd->error_count     =0;
5132 +                       _ifxhc->wait_for_sof   =0;
5133 +                       _ifxhc->do_ping        =0;
5134 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5135 +               }
5136 +               else
5137 +               #endif
5138 +               {
5139 +                       if(_ifxhc->xfer_len!=0)
5140 +                               _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5141 +                       _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
5142 +                       _ifxhc->xfer_count     = _urbd->urb->actual_length;
5143 +                       _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5144 +
5145 +                       if (hcint.b.nak || hcint.b.nyet || hcint.b.ack)
5146 +                       {
5147 +                               _urbd->error_count     =0;
5148 +                               _ifxhc->wait_for_sof   =1;
5149 +                               enable_hc_int(_hc_regs,ack);
5150 +                               enable_hc_int(_hc_regs,nak);
5151 +                               enable_hc_int(_hc_regs,nyet);
5152 +                               if(!out_nak_enh)
5153 +                                       _ifxhc->do_ping        =1;
5154 +                               else
5155 +                                       _ifxhc->do_ping        =0;
5156 +                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5157 +                       }
5158 +                       else
5159 +                       {
5160 +                               _urbd->error_count ++ ;
5161 +                               if (_urbd->error_count == 3)
5162 +                               {
5163 +                                       disable_hc_int(_hc_regs,ack);
5164 +                                       disable_hc_int(_hc_regs,nak);
5165 +                                       disable_hc_int(_hc_regs,nyet);
5166 +                                       _urbd->error_count     =0;
5167 +                                       _ifxhc->wait_for_sof   =0;
5168 +                                       _ifxhc->do_ping        =0;
5169 +                                       release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
5170 +                               }
5171 +                               else
5172 +                               {
5173 +                                       enable_hc_int(_hc_regs,ack);
5174 +                                       enable_hc_int(_hc_regs,nak);
5175 +                                       enable_hc_int(_hc_regs,nyet);
5176 +                                       _ifxhc->wait_for_sof   =1;
5177 +                                       if(!out_nak_enh)
5178 +                                               _ifxhc->do_ping        =1;
5179 +                                       else
5180 +                                               _ifxhc->do_ping        =0;
5181 +                                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5182 +                               }
5183 +                       }
5184 +               }
5185 +               return 1;
5186 +       }
5187 +       else if(hcint.b.bblerr     )
5188 +       {
5189 +IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT0 BABBLE [should be IN only]\n",__func__,__LINE__);
5190 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5191 +               _ifxhc->do_ping        = 0;
5192 +               if(_ifxhc->xfer_len!=0)
5193 +                       _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5194 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
5195 +               return 1;
5196 +       }
5197 +       else if(hcint.b.nak || hcint.b.nyet)
5198 +       {
5199 +               if(!out_nak_enh)
5200 +               {
5201 +                       // ZLP shortcut
5202 +                       #if 1
5203 +                       if(hctsiz.b.pktcnt==0)
5204 +                       {
5205 +                               _urbd->error_count     =0;
5206 +                               _ifxhc->wait_for_sof   =0;
5207 +                               _ifxhc->do_ping        =0;
5208 +                               complete_channel(_ifxhcd, _ifxhc, _urbd);
5209 +                       }
5210 +                       else
5211 +                       #endif
5212 +                       {
5213 +                               if(!out_nak_enh)
5214 +                                       _ifxhc->do_ping        =1;
5215 +                               else
5216 +                                       _ifxhc->do_ping        =0;
5217 +                               if(_ifxhc->xfer_len!=0)
5218 +                               {
5219 +                                       _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5220 +                                       _ifxhc->xfer_len           = _urbd->xfer_len - _urbd->urb->actual_length;
5221 +                                       _ifxhc->xfer_count         = _urbd->urb->actual_length;
5222 +                               }
5223 +                               _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5224 +                               _ifxhc->wait_for_sof   = 1;
5225 +                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5226 +                       }
5227 +                       return 1;
5228 +               }
5229 +       }
5230 +       else if(hcint.b.datatglerr )
5231 +       {
5232 +IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT0 DATATGLERR [should be IN only]\n",__func__,__LINE__);
5233 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5234 +               _urbd->error_count     =0;
5235 +               _ifxhc->wait_for_sof   =0;
5236 +               _ifxhc->do_ping        =0;
5237 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR);
5238 +               return 1;
5239 +       }
5240 +       else if(hcint.b.frmovrun   )
5241 +       {
5242 +IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT0 FRMOVRUN [should be PERIODIC only]\n",__func__,__LINE__);
5243 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5244 +               _urbd->error_count     =0;
5245 +               _ifxhc->wait_for_sof   =0;
5246 +               _ifxhc->do_ping        =0;
5247 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN);
5248 +               return 1;
5249 +       }
5250 +       return 0;
5251 +}
5252 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
5253 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
5254 +static int32_t chhltd_intr_rx_nonsplit(ifxhcd_hcd_t      *_ifxhcd,
5255 +                                    ifxhcd_hc_t       *_ifxhc,
5256 +                                    ifxusb_hc_regs_t  *_hc_regs,
5257 +                                    ifxhcd_urbd_t     *_urbd)
5258 +{
5259 +       hcint_data_t  hcint;
5260 +       hcint_data_t  hcintmsk;
5261 +       hctsiz_data_t hctsiz;
5262 +
5263 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
5264 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
5265 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
5266 +       disable_hc_int(_hc_regs,ack);
5267 +       disable_hc_int(_hc_regs,nak);
5268 +       disable_hc_int(_hc_regs,nyet);
5269 +       _ifxhc->do_ping        =0;
5270 +
5271 +       if(_ifxhc->halt_status == HC_XFER_NAK)
5272 +       {
5273 +               if(_ifxhc->nak_retry_r)
5274 +               {
5275 +                       _ifxhc->nak_retry--;
5276 +                       if(_ifxhc->nak_retry)
5277 +                       {
5278 +                               if(_ifxhc->xfer_len!=0)
5279 +                                       _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5280 +                               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
5281 +                               _ifxhc->xfer_count     = _urbd->urb->actual_length;
5282 +                               _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5283 +                               _ifxhc->wait_for_sof   = 1;
5284 +                               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
5285 +                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5286 +                       }
5287 +                       else
5288 +                       {
5289 +                               _ifxhc->wait_for_sof   = 0;
5290 +                               release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status);
5291 +                       }
5292 +               }
5293 +               else
5294 +               {
5295 +                       if(_ifxhc->xfer_len!=0)
5296 +                               _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5297 +                       _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
5298 +                       _ifxhc->xfer_count     = _urbd->urb->actual_length;
5299 +                       _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5300 +                       _ifxhc->wait_for_sof   = 1;
5301 +                       _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
5302 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5303 +               }
5304 +               return 1;
5305 +       }
5306 +
5307 +       if(hcint.b.xfercomp   )
5308 +       {
5309 +               _urbd->error_count   =0;
5310 +               //restart INTR immediately
5311 +               #if 1
5312 +               if(hctsiz.b.pktcnt>0)
5313 +               {
5314 +                       // TODO Re-initialize Channel (in next b_interval - 1 uF/F)
5315 +                       _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
5316 +                       if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
5317 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5318 +               }
5319 +               else
5320 +               #endif
5321 +               {
5322 +                       _ifxhc->wait_for_sof =0;
5323 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5324 +               }
5325 +               return 1;
5326 +       }
5327 +       else if (hcint.b.stall)
5328 +       {
5329 +               _urbd->error_count   =0;
5330 +               _ifxhc->wait_for_sof =0;
5331 +
5332 +               // Don't care shortcut
5333 +               #if 0
5334 +               if(hctsiz.b.pktcnt==0)
5335 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5336 +               else
5337 +               #endif
5338 +               {
5339 +                       // Stall FIFO compensation.
5340 +                       #if 0
5341 +                               int sz1,sz2;
5342 +                               sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt;
5343 +                               sz2*=_ifxhc->mps;
5344 +                               sz1=_ifxhc->xfer_len - hctsiz.b.xfersize;
5345 +                               sz2-=sz1;
5346 +                               if(sz2)
5347 +                                       ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf);
5348 +                       #endif
5349 +                       _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
5350 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
5351 +               }
5352 +               return 1;
5353 +       }
5354 +
5355 +
5356 +       else if (hcint.b.bblerr)
5357 +       {
5358 +               _urbd->error_count   =0;
5359 +               _ifxhc->wait_for_sof =0;
5360 +
5361 +               // Don't care shortcut
5362 +               #if 0
5363 +               if(hctsiz.b.pktcnt==0)
5364 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5365 +               else
5366 +               #endif
5367 +               {
5368 +                       _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
5369 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
5370 +               }
5371 +               return 1;
5372 +       }
5373 +       else if (hcint.b.nak || hcint.b.datatglerr || hcint.b.frmovrun)
5374 +       {
5375 +               _urbd->error_count   =0;
5376 +               //restart INTR immediately
5377 +               #if 1
5378 +               if(hctsiz.b.pktcnt>0)
5379 +               {
5380 +                       // TODO Re-initialize Channel (in next b_interval - 1 uF/F)
5381 +                       _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
5382 +                       if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
5383 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5384 +               }
5385 +               else
5386 +               #endif
5387 +               {
5388 +                       _ifxhc->wait_for_sof =0;
5389 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5390 +               }
5391 +               return 1;
5392 +       }
5393 +       else if (hcint.b.xacterr)
5394 +       {
5395 +               // ZLP shortcut
5396 +               #if 1
5397 +               if(hctsiz.b.pktcnt==0)
5398 +               {
5399 +                       _urbd->error_count     =0;
5400 +                       _ifxhc->wait_for_sof   =0;
5401 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5402 +               }
5403 +               else
5404 +               #endif
5405 +               {
5406 +                       /* 20110803 AVM/WK FIX: Reset error count on any handshake */
5407 +                       if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) {
5408 +                               _urbd->error_count = 1;
5409 +                       } else {
5410 +                               _urbd->error_count++;
5411 +                       }
5412 +
5413 +                       if(_urbd->error_count>=3)
5414 +                       {
5415 +                               _urbd->error_count     =0;
5416 +                               _ifxhc->wait_for_sof   =0;
5417 +                               release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
5418 +                       }
5419 +                       else
5420 +                       {
5421 +                               _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
5422 +                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5423 +                       }
5424 +               }
5425 +               return 1;
5426 +       }
5427 +       else if(hcint.b.nyet   )
5428 +       {
5429 +IFX_WARN("%s() %d Warning INTR IN SPLIT0 NYET [should be OUT only]\n",__func__,__LINE__);
5430 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5431 +               return 1;
5432 +       }
5433 +       return 0;
5434 +}
5435 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
5436 +static int32_t chhltd_intr_tx_nonsplit(ifxhcd_hcd_t      *_ifxhcd,
5437 +                                    ifxhcd_hc_t       *_ifxhc,
5438 +                                    ifxusb_hc_regs_t  *_hc_regs,
5439 +                                    ifxhcd_urbd_t     *_urbd)
5440 +{
5441 +       hcint_data_t  hcint;
5442 +       hcint_data_t  hcintmsk;
5443 +       hctsiz_data_t hctsiz;
5444 +       int out_nak_enh = 0;
5445 +
5446 +       if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
5447 +               out_nak_enh = 1;
5448 +
5449 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
5450 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
5451 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
5452 +
5453 +       if(_ifxhc->halt_status == HC_XFER_NAK)
5454 +       {
5455 +               if(_ifxhc->nak_retry_r)
5456 +               {
5457 +                       _ifxhc->nak_retry--;
5458 +                       if(_ifxhc->nak_retry)
5459 +                       {
5460 +                               if(_ifxhc->xfer_len!=0)
5461 +                                       _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5462 +                               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
5463 +                               _ifxhc->xfer_count     = _urbd->urb->actual_length;
5464 +                               _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5465 +                               _ifxhc->wait_for_sof   = 1;
5466 +                               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
5467 +                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5468 +                       }
5469 +                       else
5470 +                       {
5471 +                               _ifxhc->wait_for_sof   = 0;
5472 +                               release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status);
5473 +                       }
5474 +               }
5475 +               else
5476 +               {
5477 +                       if(_ifxhc->xfer_len!=0)
5478 +                               _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5479 +                       _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
5480 +                       _ifxhc->xfer_count     = _urbd->urb->actual_length;
5481 +                       _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5482 +                       _ifxhc->wait_for_sof   = 1;
5483 +                       _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
5484 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5485 +               }
5486 +               return 1;
5487 +       }
5488 +
5489 +       if(hcint.b.xfercomp   )
5490 +       {
5491 +               disable_hc_int(_hc_regs,ack);
5492 +               disable_hc_int(_hc_regs,nak);
5493 +               disable_hc_int(_hc_regs,nyet);
5494 +               _urbd->error_count   =0;
5495 +               //restart INTR immediately
5496 +               #if 0
5497 +               if(hctsiz.b.pktcnt>0)
5498 +               {
5499 +                       // TODO Re-initialize Channel (in next b_interval - 1 uF/F)
5500 +                       _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
5501 +                       if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
5502 +                       if(hcint.b.nyet && !out_nak_enh  )
5503 +                               _ifxhc->do_ping        =1;
5504 +                       else
5505 +                               _ifxhc->do_ping        =0;
5506 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5507 +               }
5508 +               else
5509 +               #endif
5510 +               {
5511 +                       _ifxhc->wait_for_sof =0;
5512 +                       _ifxhc->do_ping      =0;
5513 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5514 +               }
5515 +               return 1;
5516 +       }
5517 +       else if (hcint.b.stall)
5518 +       {
5519 +               disable_hc_int(_hc_regs,ack);
5520 +               disable_hc_int(_hc_regs,nyet);
5521 +               disable_hc_int(_hc_regs,nak);
5522 +               _urbd->error_count   =0;
5523 +               _ifxhc->wait_for_sof =0;
5524 +               _ifxhc->do_ping      =0;
5525 +
5526 +               // Don't care shortcut
5527 +               #if 0
5528 +               if(hctsiz.b.pktcnt==0)
5529 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5530 +               else
5531 +               #endif
5532 +               {
5533 +                       if(_ifxhc->xfer_len!=0)// !_ifxhc->is_in
5534 +                               _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps);
5535 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
5536 +               }
5537 +               return 1;
5538 +       }
5539 +       else if(hcint.b.nak || hcint.b.frmovrun )
5540 +       {
5541 +               disable_hc_int(_hc_regs,ack);
5542 +               disable_hc_int(_hc_regs,nyet);
5543 +               disable_hc_int(_hc_regs,nak);
5544 +               _urbd->error_count   =0;
5545 +               //restart INTR immediately
5546 +               #if 0
5547 +               if(hctsiz.b.pktcnt>0)
5548 +               {
5549 +                       // TODO Re-initialize Channel (in next b_interval - 1 uF/F)
5550 +                       _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
5551 +                       if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
5552 +                       if(!out_nak_enh  )
5553 +                               _ifxhc->do_ping        =1;
5554 +                       else
5555 +                               _ifxhc->do_ping        =0;
5556 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5557 +               }
5558 +               else
5559 +               #endif
5560 +               {
5561 +                       _ifxhc->wait_for_sof =0;
5562 +                       _ifxhc->do_ping      =0;
5563 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5564 +               }
5565 +               return 1;
5566 +       }
5567 +       else if(hcint.b.xacterr    )
5568 +       {
5569 +               // ZLP shortcut
5570 +               #if 1
5571 +               if(hctsiz.b.pktcnt==0)
5572 +               {
5573 +                       _urbd->error_count     =0;
5574 +                       _ifxhc->wait_for_sof   =0;
5575 +                       _ifxhc->do_ping        =0;
5576 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5577 +               }
5578 +               else
5579 +               #endif
5580 +               {
5581 +                       /* 20110803 AVM/WK FIX: Reset error count on any handshake */
5582 +                       if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) {
5583 +                               _urbd->error_count = 1;
5584 +                       } else {
5585 +                               _urbd->error_count++;
5586 +                       }
5587 +
5588 +                       if(_urbd->error_count>=3)
5589 +                       {
5590 +                               _urbd->error_count     =0;
5591 +                               _ifxhc->wait_for_sof   =0;
5592 +                               _ifxhc->do_ping        =0;
5593 +                               release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
5594 +                       }
5595 +                       else
5596 +                       {
5597 +                               //_ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
5598 +                               //if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
5599 +                               _ifxhc->wait_for_sof=1;
5600 +                               if(!out_nak_enh  )
5601 +                                       _ifxhc->do_ping        =1;
5602 +                               else
5603 +                                       _ifxhc->do_ping        =0;
5604 +
5605 +                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5606 +                       }
5607 +               }
5608 +               return 1;
5609 +       }
5610 +       else if(hcint.b.bblerr     )
5611 +       {
5612 +IFX_WARN("%s() %d Warning INTR OUT SPLIT0 BABBLEERR  [should be IN only]\n",__func__,__LINE__);
5613 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5614 +               _urbd->error_count     =0;
5615 +               _ifxhc->wait_for_sof   =0;
5616 +               _ifxhc->do_ping        =0;
5617 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
5618 +               return 1;
5619 +       }
5620 +       else if(hcint.b.datatglerr )
5621 +       {
5622 +IFX_WARN("%s() %d Warning INTR OUT SPLIT0 DATATGLERR\n",__func__,__LINE__);
5623 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5624 +               _urbd->error_count     =0;
5625 +               _ifxhc->wait_for_sof   =0;
5626 +               _ifxhc->do_ping        =0;
5627 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR);
5628 +               return 1;
5629 +       }
5630 +       return 0;
5631 +}
5632 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
5633 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
5634 +static int32_t chhltd_isoc_rx_nonsplit(ifxhcd_hcd_t      *_ifxhcd,
5635 +                                    ifxhcd_hc_t       *_ifxhc,
5636 +                                    ifxusb_hc_regs_t  *_hc_regs,
5637 +                                    ifxhcd_urbd_t     *_urbd)
5638 +{
5639 +       #if defined(__EN_ISOC__)
5640 +               hcint_data_t  hcint;
5641 +               hcint_data_t  hcintmsk;
5642 +               hctsiz_data_t hctsiz;
5643 +
5644 +               hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
5645 +               hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
5646 +               hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
5647 +
5648 +               if (hcint.b.xfercomp || hcint.b.frmovrun)
5649 +               {
5650 +                       _urbd->error_count=0;
5651 +                       disable_hc_int(_hc_regs,ack);
5652 +                       disable_hc_int(_hc_regs,nak);
5653 +                       disable_hc_int(_hc_regs,nyet);
5654 +                       _ifxhc->wait_for_sof   = 0;
5655 +                       if (hcint.b.xfercomp)
5656 +                               complete_channel(_ifxhcd, _ifxhc, _urbd);
5657 +                       else
5658 +                               release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN);
5659 +               }
5660 +               else if (hcint.b.xacterr || hcint.b.bblerr)
5661 +               {
5662 +                       #ifndef VR9Skip
5663 +                               if(hctsiz.b.pktcnt==0)
5664 +                               {
5665 +                                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5666 +                               }
5667 +                               else
5668 +                               {
5669 +                                       int sz1,sz2;
5670 +                                       sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt;
5671 +                                       sz2*=_ifxhc->mps;
5672 +                                       sz1=_ifxhc->xfer_len - hctsiz.b.xfersize;
5673 +                                       sz2-=sz1;
5674 +                                       if(sz2)
5675 +                                               ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf);
5676 +                                       _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
5677 +                                       _ifxhc->xfer_len           = _urbd->xfer_len - _urbd->urb->actual_length;
5678 +                                       _ifxhc->xfer_count         = _urbd->urb->actual_length;
5679 +                                       _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5680 +                                       _urbd->error_count++;
5681 +                                       if(_urbd->error_count>=3)
5682 +                                       {
5683 +                                               _urbd->error_count=0;
5684 +                                               _ifxhc->wait_for_sof   = 0;
5685 +                                               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
5686 +                                               release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
5687 +                                       }
5688 +                                       else
5689 +                                       {
5690 +                                               _ifxhc->wait_for_sof   = 1;
5691 +                                               enable_hc_int(_hc_regs,ack);
5692 +                                               enable_hc_int(_hc_regs,nak);
5693 +                                               enable_hc_int(_hc_regs,nyet);
5694 +                                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5695 +                                       }
5696 +                               }
5697 +                       #endif
5698 +               }
5699 +               else if(hcint.b.datatglerr )
5700 +               {
5701 +                       warning
5702 +               }
5703 +               else if(hcint.b.stall      )
5704 +               {
5705 +                       warning
5706 +               }
5707 +       #else
5708 +       #endif
5709 +       return 0;
5710 +}
5711 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
5712 +static int32_t chhltd_isoc_tx_nonsplit(ifxhcd_hcd_t      *_ifxhcd,
5713 +                                    ifxhcd_hc_t       *_ifxhc,
5714 +                                    ifxusb_hc_regs_t  *_hc_regs,
5715 +                                    ifxhcd_urbd_t     *_urbd)
5716 +{
5717 +       #if defined(__EN_ISOC__)
5718 +               hcint_data_t  hcint;
5719 +               hcint_data_t  hcintmsk;
5720 +               hctsiz_data_t hctsiz;
5721 +               int out_nak_enh = 0;
5722 +
5723 +               if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
5724 +                       out_nak_enh = 1;
5725 +
5726 +               hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
5727 +               hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
5728 +               hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
5729 +
5730 +               if (hcint.b.xfercomp)
5731 +               {
5732 +                       _urbd->error_count=0;
5733 +                       disable_hc_int(_hc_regs,ack);
5734 +                       disable_hc_int(_hc_regs,nak);
5735 +                       disable_hc_int(_hc_regs,nyet);
5736 +                       _ifxhc->wait_for_sof   = 0;
5737 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5738 +                       return 1;
5739 +               }
5740 +               else if (hcint.b.frmovrun)
5741 +               {
5742 +                       #ifndef VR9Skip
5743 +                               _urbd->error_count=0;
5744 +                               disable_hc_int(_hc_regs,ack);
5745 +                               disable_hc_int(_hc_regs,nak);
5746 +                               disable_hc_int(_hc_regs,nyet);
5747 +                               _ifxhc->wait_for_sof   = 0;
5748 +                               release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN);
5749 +                       #endif
5750 +               }
5751 +               else if(hcint.b.datatglerr )
5752 +               {
5753 +                       warning
5754 +               }
5755 +               else if(hcint.b.bblerr     )
5756 +               {
5757 +                       #ifndef VR9Skip
5758 +                               if(hctsiz.b.pktcnt==0)
5759 +                               {
5760 +                                       complete_channel(_ifxhcd, _ifxhc, _urbd);
5761 +                               }
5762 +                               else
5763 +                               {
5764 +                                       int sz1,sz2;
5765 +                                       sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt;
5766 +                                       sz2*=_ifxhc->mps;
5767 +                                       sz1=_ifxhc->xfer_len - hctsiz.b.xfersize;
5768 +                                       sz2-=sz1;
5769 +                                               if(sz2)
5770 +                                                       ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf);
5771 +                                               _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
5772 +                                       _ifxhc->xfer_len           = _urbd->xfer_len - _urbd->urb->actual_length;
5773 +                                       _ifxhc->xfer_count         = _urbd->urb->actual_length;
5774 +                                       _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5775 +                                       _urbd->error_count++;
5776 +                                       if(_urbd->error_count>=3)
5777 +                                       {
5778 +                                               _urbd->error_count=0;
5779 +                                               _ifxhc->wait_for_sof   = 0;
5780 +                                               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
5781 +                                       }
5782 +                                       else
5783 +                                       {
5784 +                                               _ifxhc->wait_for_sof   = 1;
5785 +                                               enable_hc_int(_hc_regs,ack);
5786 +                                               enable_hc_int(_hc_regs,nak);
5787 +                                               enable_hc_int(_hc_regs,nyet);
5788 +                                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5789 +                                       }
5790 +                               }
5791 +                       #endif
5792 +               }
5793 +               else if(hcint.b.xacterr    )
5794 +               {
5795 +                       if(hctsiz.b.pktcnt==0)
5796 +                       {
5797 +                               complete_channel(_ifxhcd, _ifxhc, _urbd);
5798 +                               return 1;
5799 +                       }
5800 +                       _urbd->error_count++;
5801 +                       if(_urbd->error_count>=3)
5802 +                       {
5803 +                               _urbd->error_count=0;
5804 +                               _ifxhc->wait_for_sof   = 0;
5805 +                               release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
5806 +                       }
5807 +                       else
5808 +                       {
5809 +                               _ifxhc->wait_for_sof   = 1;
5810 +                               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5811 +                       }
5812 +                       return 1;
5813 +               }
5814 +               else if(hcint.b.stall      )
5815 +               {
5816 +                               warning
5817 +               }
5818 +       #else
5819 +       #endif
5820 +       return 0;
5821 +}
5822 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
5823 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
5824 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
5825 +static int32_t chhltd_ctrlbulk_rx_ssplit(ifxhcd_hcd_t      *_ifxhcd,
5826 +                                      ifxhcd_hc_t       *_ifxhc,
5827 +                                      ifxusb_hc_regs_t  *_hc_regs,
5828 +                                      ifxhcd_urbd_t     *_urbd)
5829 +{
5830 +       hcint_data_t  hcint;
5831 +       hcint_data_t  hcintmsk;
5832 +       hctsiz_data_t hctsiz;
5833 +
5834 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
5835 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
5836 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
5837 +
5838 +       disable_hc_int(_hc_regs,ack);
5839 +       disable_hc_int(_hc_regs,nak);
5840 +       disable_hc_int(_hc_regs,nyet);
5841 +
5842 +       _ifxhc->do_ping        =0;
5843 +
5844 +       if (hcint.b.ack)
5845 +       {
5846 +               _urbd->error_count=0;
5847 +               _ifxhc->split=2;
5848 +               _ifxhc->wait_for_sof   = 8;
5849 +               _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
5850 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5851 +               return 1;
5852 +       }
5853 +       else if (hcint.b.nak)
5854 +       {
5855 +               _ifxhc->wait_for_sof   = 1;
5856 +               _urbd->error_count     = 0;
5857 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5858 +               return 1;
5859 +       }
5860 +       else if (hcint.b.xacterr)
5861 +       {
5862 +               _urbd->error_count++;
5863 +               if(_urbd->error_count>=3)
5864 +               {
5865 +                       _urbd->error_count=0;
5866 +                       _ifxhc->wait_for_sof =0;
5867 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
5868 +               }
5869 +               else
5870 +               {
5871 +                       _ifxhc->wait_for_sof =1;
5872 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5873 +               }
5874 +               return 1;
5875 +       }
5876 +       else if(hcint.b.bblerr     )
5877 +       {
5878 +               _urbd->error_count   =0;
5879 +               _ifxhc->wait_for_sof =0;
5880 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
5881 +               return 1;
5882 +       }
5883 +       else if(hcint.b.stall      )
5884 +       {
5885 +               _urbd->error_count   =0;
5886 +               _ifxhc->wait_for_sof =0;
5887 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
5888 +               return 1;
5889 +       }
5890 +       else if(hcint.b.datatglerr )
5891 +       {
5892 +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 HC_XFER_DATA_TOGGLE_ERR\n",__func__,__LINE__);
5893 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5894 +               _urbd->error_count   =0;
5895 +               _ifxhc->wait_for_sof =0;
5896 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR);
5897 +               return 1;
5898 +       }
5899 +       else if(hcint.b.frmovrun   )
5900 +       {
5901 +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 HC_XFER_FRAME_OVERRUN\n",__func__,__LINE__);
5902 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5903 +               _urbd->error_count   =0;
5904 +               _ifxhc->wait_for_sof =0;
5905 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN);
5906 +               return 1;
5907 +       }
5908 +       else if(hcint.b.nyet   )
5909 +       {
5910 +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 NYET\n",__func__,__LINE__);
5911 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5912 +       }
5913 +       else if(hcint.b.xfercomp   )
5914 +       {
5915 +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 COMPLETE\n",__func__,__LINE__);
5916 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5917 +       }
5918 +       return 0;
5919 +}
5920 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
5921 +static int32_t chhltd_ctrlbulk_tx_ssplit(ifxhcd_hcd_t      *_ifxhcd,
5922 +                                      ifxhcd_hc_t       *_ifxhc,
5923 +                                      ifxusb_hc_regs_t  *_hc_regs,
5924 +                                      ifxhcd_urbd_t     *_urbd)
5925 +{
5926 +       hcint_data_t  hcint;
5927 +       hcint_data_t  hcintmsk;
5928 +       hctsiz_data_t hctsiz;
5929 +       int out_nak_enh = 0;
5930 +
5931 +#ifdef __DEBUG__
5932 +static int first=0;
5933 +#endif
5934 +
5935 +       if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
5936 +               out_nak_enh = 1;
5937 +
5938 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
5939 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
5940 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
5941 +       disable_hc_int(_hc_regs,ack);
5942 +       disable_hc_int(_hc_regs,nak);
5943 +       disable_hc_int(_hc_regs,nyet);
5944 +
5945 +#ifdef __DEBUG__
5946 +       if(!first&& _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK
5947 +          &&(hcint.b.stall || hcint.b.datatglerr || hcint.b.frmovrun || hcint.b.bblerr || hcint.b.xacterr) && !hcint.b.ack)
5948 +       {
5949 +               showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5950 +               first=1;
5951 +               printk(KERN_INFO "   [%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X] \n"
5952 +               ,*(_ifxhc->xfer_buff+ 0),*(_ifxhc->xfer_buff+ 1),*(_ifxhc->xfer_buff+ 2),*(_ifxhc->xfer_buff+ 3)
5953 +               ,*(_ifxhc->xfer_buff+ 4),*(_ifxhc->xfer_buff+ 5),*(_ifxhc->xfer_buff+ 6),*(_ifxhc->xfer_buff+ 7)
5954 +               ,*(_ifxhc->xfer_buff+ 8),*(_ifxhc->xfer_buff+ 9),*(_ifxhc->xfer_buff+10),*(_ifxhc->xfer_buff+11)
5955 +               ,*(_ifxhc->xfer_buff+12),*(_ifxhc->xfer_buff+13),*(_ifxhc->xfer_buff+14),*(_ifxhc->xfer_buff+15));
5956 +
5957 +               printk(KERN_INFO "   [_urbd->urb->actual_length:%08X _ifxhc->start_pkt_count:%08X hctsiz.b.pktcnt:%08X ,_urbd->xfer_len:%08x] \n"
5958 +               ,_urbd->urb->actual_length
5959 +               ,_ifxhc->start_pkt_count
5960 +               ,hctsiz.b.pktcnt
5961 +               ,_urbd->xfer_len);
5962 +       }
5963 +#endif
5964 +
5965 +       if     (hcint.b.ack )
5966 +       {
5967 +               _urbd->error_count=0;
5968 +               if (_ifxhc->ep_type == IFXUSB_EP_TYPE_BULK || _ifxhc->control_phase != IFXHCD_CONTROL_SETUP)
5969 +                       _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len;
5970 +               _ifxhc->split=2;
5971 +               _ifxhc->wait_for_sof   =8;
5972 +               _ifxhc->data_pid_start =read_data_toggle(_hc_regs);
5973 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5974 +               return 1;
5975 +       }
5976 +       else if(hcint.b.nyet)
5977 +       {
5978 +IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT1 NYET\n",__func__,__LINE__);
5979 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
5980 +               _urbd->error_count=0;
5981 +               if (_ifxhc->ep_type == IFXUSB_EP_TYPE_BULK || _ifxhc->control_phase != IFXHCD_CONTROL_SETUP)
5982 +                       _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len;
5983 +               _ifxhc->split=2;
5984 +               _ifxhc->wait_for_sof   =1;
5985 +               _ifxhc->data_pid_start =read_data_toggle(_hc_regs);
5986 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5987 +               return 1;
5988 +       }
5989 +       else if(hcint.b.nak        )
5990 +       {
5991 +               _ifxhc->wait_for_sof  =1;
5992 +               if(!out_nak_enh  )
5993 +                       _ifxhc->do_ping        =1;
5994 +               else
5995 +                       _ifxhc->do_ping        =0;
5996 +               _urbd->error_count    =0;
5997 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
5998 +               return 1;
5999 +       }
6000 +       else if(hcint.b.xacterr    )
6001 +       {
6002 +               _urbd->error_count++;
6003 +               if(_urbd->error_count>=3)
6004 +               {
6005 +                       _urbd->error_count=0;
6006 +                       _ifxhc->wait_for_sof  =0;
6007 +                       _ifxhc->do_ping       =0;
6008 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
6009 +               }
6010 +               else
6011 +               {
6012 +                       _ifxhc->wait_for_sof  =1;
6013 +                       _ifxhc->do_ping       =1;
6014 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6015 +               }
6016 +               return 1;
6017 +       }
6018 +       else if(hcint.b.datatglerr )
6019 +       {
6020 +               _urbd->error_count   =0;
6021 +               _ifxhc->wait_for_sof =0;
6022 +               _ifxhc->do_ping      =0;
6023 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR);
6024 +               return 1;
6025 +       }
6026 +       else if(hcint.b.bblerr     )
6027 +       {
6028 +               _urbd->error_count   =0;
6029 +               _ifxhc->wait_for_sof =0;
6030 +               _ifxhc->do_ping      =0;
6031 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
6032 +               return 1;
6033 +       }
6034 +       else if(hcint.b.stall      )
6035 +       {
6036 +               _urbd->error_count   =0;
6037 +               _ifxhc->wait_for_sof =0;
6038 +               _ifxhc->do_ping      =0;
6039 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
6040 +               return 1;
6041 +       }
6042 +       else if(hcint.b.frmovrun   )
6043 +       {
6044 +IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT1 HC_XFER_FRAME_OVERRUN\n",__func__,__LINE__);
6045 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
6046 +               _urbd->error_count   =0;
6047 +               _ifxhc->wait_for_sof =0;
6048 +               _ifxhc->do_ping      =0;
6049 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN);
6050 +               return 1;
6051 +       }
6052 +       else if(hcint.b.xfercomp   )
6053 +       {
6054 +               printk(KERN_INFO "%s() %d Warning CTRLBULK OUT SPLIT1 COMPLETE\n",__func__,__LINE__);
6055 +       }
6056 +       return 0;
6057 +}
6058 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6059 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6060 +static int32_t chhltd_intr_rx_ssplit(ifxhcd_hcd_t      *_ifxhcd,
6061 +                                  ifxhcd_hc_t       *_ifxhc,
6062 +                                  ifxusb_hc_regs_t  *_hc_regs,
6063 +                                  ifxhcd_urbd_t     *_urbd)
6064 +{
6065 +       hcint_data_t  hcint;
6066 +       hcint_data_t  hcintmsk;
6067 +       hctsiz_data_t hctsiz;
6068 +
6069 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
6070 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
6071 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
6072 +
6073 +       disable_hc_int(_hc_regs,ack);
6074 +       disable_hc_int(_hc_regs,nak);
6075 +       disable_hc_int(_hc_regs,nyet);
6076 +
6077 +       _ifxhc->do_ping        =0;
6078 +
6079 +       if     (hcint.b.ack )
6080 +       {
6081 +               /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/
6082 +               _ifxhc->nyet_count=0;
6083 +
6084 +               _urbd->error_count=0;
6085 +               _ifxhc->split=2;
6086 +               _ifxhc->wait_for_sof   = 0;
6087 +               _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
6088 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6089 +               return 1;
6090 +       }
6091 +       else if(hcint.b.nak        )
6092 +       {
6093 +               _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6094 +               if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6095 +               _urbd->error_count=0;
6096 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6097 +               return 1;
6098 +       }
6099 +       else if(hcint.b.xacterr    )
6100 +       {
6101 +               hcchar_data_t   hcchar;
6102 +               hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar);
6103 +               _urbd->error_count=hcchar.b.multicnt;
6104 +               if(_urbd->error_count>=3)
6105 +               {
6106 +                       _urbd->error_count=0;
6107 +                       _ifxhc->wait_for_sof   = 0;
6108 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
6109 +               }
6110 +               else
6111 +               {
6112 +                       _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6113 +                       if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6114 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6115 +               }
6116 +               return 1;
6117 +       }
6118 +       else if(hcint.b.stall      )
6119 +       {
6120 +               _urbd->error_count   =0;
6121 +               _ifxhc->wait_for_sof =0;
6122 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
6123 +               return 1;
6124 +       }
6125 +       else if(hcint.b.bblerr     )
6126 +       {
6127 +               _urbd->error_count   =0;
6128 +               _ifxhc->wait_for_sof =0;
6129 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
6130 +               return 1;
6131 +       }
6132 +       else if(hcint.b.frmovrun   )
6133 +       {
6134 +               _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6135 +               if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6136 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6137 +               return 1;
6138 +       }
6139 +       else if(hcint.b.datatglerr )
6140 +       {
6141 +IFX_WARN( "%s() %d Warning INTR IN SPLIT1 DATATGLERR\n",__func__,__LINE__);
6142 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
6143 +               _urbd->error_count   =0;
6144 +               _ifxhc->wait_for_sof =0;
6145 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR);
6146 +               return 1;
6147 +       }
6148 +       else if(hcint.b.xfercomp   )
6149 +       {
6150 +IFX_WARN("%s() %d Warning INTR IN SPLIT1 COMPLETE\n",__func__,__LINE__);
6151 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
6152 +       }
6153 +       return 0;
6154 +}
6155 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6156 +static int32_t chhltd_intr_tx_ssplit(ifxhcd_hcd_t      *_ifxhcd,
6157 +                                  ifxhcd_hc_t       *_ifxhc,
6158 +                                  ifxusb_hc_regs_t  *_hc_regs,
6159 +                                  ifxhcd_urbd_t     *_urbd)
6160 +{
6161 +       hcint_data_t  hcint;
6162 +       hcint_data_t  hcintmsk;
6163 +       hctsiz_data_t hctsiz;
6164 +       int out_nak_enh = 0;
6165 +
6166 +       if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
6167 +               out_nak_enh = 1;
6168 +
6169 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
6170 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
6171 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
6172 +
6173 +       disable_hc_int(_hc_regs,ack);
6174 +       disable_hc_int(_hc_regs,nak);
6175 +       disable_hc_int(_hc_regs,nyet);
6176 +
6177 +       if     (hcint.b.ack )
6178 +       {
6179 +               /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/
6180 +               _ifxhc->nyet_count=0;
6181 +
6182 +               _urbd->error_count=0;
6183 +               _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len;
6184 +               _ifxhc->split=2;
6185 +               _ifxhc->wait_for_sof   = 0;
6186 +               _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
6187 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6188 +               return 1;
6189 +       }
6190 +       else if(hcint.b.nyet)
6191 +       {
6192 +IFX_WARN("%s() %d Warning INTR OUT SPLIT1 NYET\n",__func__,__LINE__);
6193 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
6194 +               _urbd->error_count=0;
6195 +               _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len;
6196 +               _ifxhc->split=2;
6197 +               _ifxhc->wait_for_sof   = 0;
6198 +               _ifxhc->data_pid_start = read_data_toggle(_hc_regs);
6199 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6200 +               return 1;
6201 +       }
6202 +       else if(hcint.b.nak        )
6203 +       {
6204 +               _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6205 +               if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6206 +               _urbd->error_count   =0;
6207 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6208 +               return 1;
6209 +       }
6210 +       else if(hcint.b.frmovrun   )
6211 +       {
6212 +               _urbd->error_count   =0;
6213 +               _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6214 +               if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6215 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6216 +               return 1;
6217 +       }
6218 +       else if(hcint.b.xacterr    )
6219 +       {
6220 +               hcchar_data_t   hcchar;
6221 +               hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar);
6222 +               _urbd->error_count=hcchar.b.multicnt;
6223 +               if(_urbd->error_count>=3)
6224 +               {
6225 +                       _urbd->error_count=0;
6226 +                       _ifxhc->wait_for_sof =0;
6227 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
6228 +               }
6229 +               else
6230 +               {
6231 +                       enable_hc_int(_hc_regs,ack);
6232 +                       enable_hc_int(_hc_regs,nak);
6233 +                       enable_hc_int(_hc_regs,nyet);
6234 +                       _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6235 +                       if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6236 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6237 +               }
6238 +               return 1;
6239 +       }
6240 +       else if(hcint.b.datatglerr )
6241 +       {
6242 +IFX_WARN("%s() %d Warning INTR IN SPLIT1 DATATGLERR\n",__func__,__LINE__);
6243 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
6244 +               _urbd->error_count   =0;
6245 +               _ifxhc->wait_for_sof =0;
6246 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR);
6247 +               return 1;
6248 +       }
6249 +       else if(hcint.b.bblerr     )
6250 +       {
6251 +IFX_WARN("%s() %d Warning INTR IN SPLIT1 BABBLEERR\n",__func__,__LINE__);
6252 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
6253 +               _urbd->error_count   =0;
6254 +               _ifxhc->wait_for_sof =0;
6255 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
6256 +               return 1;
6257 +       }
6258 +       else if(hcint.b.stall      )
6259 +       {
6260 +IFX_WARN("%s() %d Warning INTR IN SPLIT1 STALL\n",__func__,__LINE__);
6261 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
6262 +               _urbd->error_count   =0;
6263 +               _ifxhc->wait_for_sof =0;
6264 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
6265 +               return 1;
6266 +       }
6267 +       else if(hcint.b.xfercomp   )
6268 +       {
6269 +IFX_WARN("%s() %d Warning INTR IN SPLIT1 COMPLETE\n",__func__,__LINE__);
6270 +showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
6271 +       }
6272 +       return 0;
6273 +}
6274 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6275 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6276 +static int32_t chhltd_isoc_rx_ssplit(ifxhcd_hcd_t      *_ifxhcd,
6277 +                                   ifxhcd_hc_t       *_ifxhc,
6278 +                                   ifxusb_hc_regs_t  *_hc_regs,
6279 +                                   ifxhcd_urbd_t     *_urbd)
6280 +{
6281 +       #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__)
6282 +               hcint_data_t  hcint;
6283 +               hcint_data_t  hcintmsk;
6284 +               hctsiz_data_t hctsiz;
6285 +
6286 +               hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
6287 +               hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
6288 +               hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
6289 +               if     (hcint.b.ack )
6290 +               {
6291 +                       Do Complete Split
6292 +               }
6293 +               else if(hcint.b.frmovrun   )
6294 +               {
6295 +                       Rewind Buffer Pointers
6296 +                       Retry Start Split (in next b_interval ¡V 1 uF)
6297 +               }
6298 +               else if(hcint.b.datatglerr )
6299 +               {
6300 +                       warning
6301 +               }
6302 +               else if(hcint.b.bblerr     )
6303 +               {
6304 +                       warning
6305 +               }
6306 +               else if(hcint.b.xacterr    )
6307 +               {
6308 +                       warning
6309 +               }
6310 +               else if(hcint.b.stall      )
6311 +               {
6312 +                       warning
6313 +               }
6314 +               else if(hcint.b.nak        )
6315 +               {
6316 +                       warning
6317 +               }
6318 +               else if(hcint.b.xfercomp   )
6319 +               {
6320 +                       warning
6321 +               }
6322 +               else if(hcint.b.nyet)
6323 +               {
6324 +                       warning
6325 +               }
6326 +       #endif
6327 +       return 0;
6328 +}
6329 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6330 +static int32_t chhltd_isoc_tx_ssplit(ifxhcd_hcd_t      *_ifxhcd,
6331 +                                   ifxhcd_hc_t       *_ifxhc,
6332 +                                   ifxusb_hc_regs_t  *_hc_regs,
6333 +                                   ifxhcd_urbd_t     *_urbd)
6334 +{
6335 +       #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__)
6336 +               hcint_data_t  hcint;
6337 +               hcint_data_t  hcintmsk;
6338 +               hctsiz_data_t hctsiz;
6339 +               int out_nak_enh = 0;
6340 +
6341 +               if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
6342 +                       out_nak_enh = 1;
6343 +
6344 +               hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
6345 +               hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
6346 +               hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
6347 +               if     (hcint.b.ack )
6348 +               {
6349 +                       Do Next Start Split (in next b_interval ¡V 1 uF)
6350 +               }
6351 +               else if(hcint.b.frmovrun   )
6352 +               {
6353 +                       Do Next Transaction in next frame.
6354 +               }
6355 +               else if(hcint.b.datatglerr )
6356 +               {
6357 +                       warning
6358 +               }
6359 +               else if(hcint.b.bblerr     )
6360 +               {
6361 +                       warning
6362 +               }
6363 +               else if(hcint.b.xacterr    )
6364 +               {
6365 +                       warning
6366 +               }
6367 +               else if(hcint.b.stall      )
6368 +               {
6369 +                       warning
6370 +               }
6371 +               else if(hcint.b.nak        )
6372 +               {
6373 +                       warning
6374 +               }
6375 +               else if(hcint.b.xfercomp   )
6376 +               {
6377 +                       warning
6378 +               }
6379 +               else if(hcint.b.nyet)
6380 +               {
6381 +                       warning
6382 +               }
6383 +       #endif
6384 +       return 0;
6385 +}
6386 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6387 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6388 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6389 +static int32_t chhltd_ctrlbulk_rx_csplit(ifxhcd_hcd_t      *_ifxhcd,
6390 +                                      ifxhcd_hc_t       *_ifxhc,
6391 +                                      ifxusb_hc_regs_t  *_hc_regs,
6392 +                                      ifxhcd_urbd_t     *_urbd)
6393 +{
6394 +       hcint_data_t  hcint;
6395 +       hcint_data_t  hcintmsk;
6396 +       hctsiz_data_t hctsiz;
6397 +
6398 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
6399 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
6400 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
6401 +       disable_hc_int(_hc_regs,ack);
6402 +       disable_hc_int(_hc_regs,nak);
6403 +       disable_hc_int(_hc_regs,nyet);
6404 +
6405 +       _ifxhc->do_ping        = 0;
6406 +
6407 +       if (hcint.b.xfercomp)
6408 +       {
6409 +               _urbd->error_count   =0;
6410 +               _ifxhc->wait_for_sof = 0;
6411 +               _ifxhc->split=1;
6412 +               complete_channel(_ifxhcd, _ifxhc, _urbd);
6413 +               return 1;
6414 +       }
6415 +       else if (hcint.b.nak)
6416 +       {
6417 +               _urbd->error_count=0;
6418 +
6419 +               _ifxhc->split          = 1;
6420 +               _ifxhc->wait_for_sof   = 1;
6421 +               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6422 +               _ifxhc->xfer_count     = _urbd->urb->actual_length;
6423 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6424 +               return 1;
6425 +       }
6426 +       else if(hcint.b.nyet)
6427 +       {
6428 +               _urbd->error_count=0;
6429 +               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
6430 +               _ifxhc->wait_for_sof   = 1;
6431 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6432 +               return 1;
6433 +       }
6434 +       else if(hcint.b.stall || hcint.b.bblerr )
6435 +       {
6436 +               _urbd->error_count=0;
6437 +               _ifxhc->wait_for_sof   = 0;
6438 +               if     (hcint.b.stall)
6439 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
6440 +               else if(hcint.b.bblerr )
6441 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
6442 +               return 1;
6443 +       }
6444 +       else if(hcint.b.xacterr    )
6445 +       {
6446 +               _urbd->error_count++;
6447 +               if(_urbd->error_count>=3)
6448 +               {
6449 +                       _urbd->error_count=0;
6450 +                       _ifxhc->wait_for_sof   = 0;
6451 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
6452 +               }
6453 +               else
6454 +               {
6455 +                       _ifxhc->split=1;
6456 +                       _ifxhc->wait_for_sof   = 1;
6457 +                       _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6458 +                       _ifxhc->xfer_count     = _urbd->urb->actual_length;
6459 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6460 +               }
6461 +               return 1;
6462 +       }
6463 +       else if(hcint.b.datatglerr )
6464 +       {
6465 +               if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0)
6466 +                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1;
6467 +               else
6468 +                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0;
6469 +               _ifxhc->split=1;
6470 +               _ifxhc->wait_for_sof   = 1;
6471 +               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6472 +               _ifxhc->xfer_count     = _urbd->urb->actual_length;
6473 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6474 +               return 1;
6475 +       }
6476 +       else if(hcint.b.frmovrun   )
6477 +       {
6478 +               _urbd->error_count=0;
6479 +               _ifxhc->wait_for_sof   = 0;
6480 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN);
6481 +               return 1;
6482 +       }
6483 +       return 0;
6484 +}
6485 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6486 +static int32_t chhltd_ctrlbulk_tx_csplit(ifxhcd_hcd_t      *_ifxhcd,
6487 +                                      ifxhcd_hc_t       *_ifxhc,
6488 +                                      ifxusb_hc_regs_t  *_hc_regs,
6489 +                                      ifxhcd_urbd_t     *_urbd)
6490 +{
6491 +       hcint_data_t  hcint;
6492 +       hcint_data_t  hcintmsk;
6493 +       hctsiz_data_t hctsiz;
6494 +       int out_nak_enh = 0;
6495 +
6496 +#if 1
6497 +static int first=0;
6498 +#endif
6499 +
6500 +       if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
6501 +               out_nak_enh = 1;
6502 +
6503 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
6504 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
6505 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
6506 +       disable_hc_int(_hc_regs,ack);
6507 +       disable_hc_int(_hc_regs,nak);
6508 +       disable_hc_int(_hc_regs,nyet);
6509 +
6510 +#if 1
6511 +       if(!first&& _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK
6512 +          &&(hcint.b.stall || hcint.b.datatglerr || hcint.b.frmovrun || hcint.b.bblerr || hcint.b.xacterr) && !hcint.b.ack)
6513 +       {
6514 +               showint( hcint.d32,hcintmsk.d32,hctsiz.d32);
6515 +               first=1;
6516 +               printk(KERN_INFO "   [%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X] \n"
6517 +               ,*(_ifxhc->xfer_buff+ 0),*(_ifxhc->xfer_buff+ 1),*(_ifxhc->xfer_buff+ 2),*(_ifxhc->xfer_buff+ 3)
6518 +               ,*(_ifxhc->xfer_buff+ 4),*(_ifxhc->xfer_buff+ 5),*(_ifxhc->xfer_buff+ 6),*(_ifxhc->xfer_buff+ 7)
6519 +               ,*(_ifxhc->xfer_buff+ 8),*(_ifxhc->xfer_buff+ 9),*(_ifxhc->xfer_buff+10),*(_ifxhc->xfer_buff+11)
6520 +               ,*(_ifxhc->xfer_buff+12),*(_ifxhc->xfer_buff+13),*(_ifxhc->xfer_buff+14),*(_ifxhc->xfer_buff+15));
6521 +
6522 +               printk(KERN_INFO "   [_urbd->urb->actual_length:%08X _ifxhc->start_pkt_count:%08X hctsiz.b.pktcnt:%08X ,_urbd->xfer_len:%08x] \n"
6523 +               ,_urbd->urb->actual_length
6524 +               ,_ifxhc->start_pkt_count
6525 +               ,hctsiz.b.pktcnt
6526 +               ,_urbd->xfer_len);
6527 +       }
6528 +#endif
6529 +
6530 +       if(hcint.b.xfercomp   )
6531 +       {
6532 +               _urbd->error_count=0;
6533 +               _ifxhc->split=1;
6534 +               _ifxhc->do_ping= 0;
6535 +               #if 0
6536 +               if(_ifxhc->xfer_len==0 && !hcint.b.ack && (hcint.b.nak || hcint.b.nyet))
6537 +               {
6538 +                       // Walkaround: When sending ZLP and receive NYEY or NAK but also issue CMPT intr
6539 +                       // Solution:   NoSplit: Resend at next SOF
6540 +                       //             Split  : Resend at next SOF with SSPLIT
6541 +                       _ifxhc->xfer_len       = 0;
6542 +                       _ifxhc->xfer_count     = 0;
6543 +                       _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
6544 +                       _ifxhc->wait_for_sof   = 1;
6545 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6546 +               }
6547 +               else
6548 +               #endif
6549 +               {
6550 +                       _ifxhc->wait_for_sof   = 0;
6551 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
6552 +               }
6553 +               return 1;
6554 +       }
6555 +       else if(hcint.b.nak        )
6556 +       {
6557 +               _urbd->error_count=0;
6558 +
6559 +               _ifxhc->split          = 1;
6560 +               _ifxhc->wait_for_sof   = 1;
6561 +               if(!out_nak_enh  )
6562 +                       _ifxhc->do_ping        =1;
6563 +               else
6564 +                       _ifxhc->do_ping        =0;
6565 +               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6566 +               _ifxhc->xfer_count     = _urbd->urb->actual_length;
6567 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6568 +               return 1;
6569 +       }
6570 +       else if(hcint.b.nyet)
6571 +       {
6572 +               //Retry Complete Split
6573 +               // Issue Retry instantly on next SOF, without gothrough process_channels
6574 +               _urbd->error_count=0;
6575 +               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
6576 +               _ifxhc->wait_for_sof   = 1;
6577 +               _ifxhc->do_ping        = 0;
6578 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6579 +               return 1;
6580 +       }
6581 +       else if(hcint.b.stall      )
6582 +       {
6583 +               _urbd->error_count=0;
6584 +               _ifxhc->wait_for_sof   = 0;
6585 +               _ifxhc->do_ping        = 0;
6586 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
6587 +               return 1;
6588 +       }
6589 +       else if(hcint.b.xacterr    )
6590 +       {
6591 +               _urbd->error_count++;
6592 +               if(_urbd->error_count>=3)
6593 +               {
6594 +                       _urbd->error_count=0;
6595 +                       _ifxhc->wait_for_sof   = 0;
6596 +                       _ifxhc->do_ping        = 0;
6597 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
6598 +               }
6599 +               else
6600 +               {
6601 +                       _ifxhc->split=1;
6602 +                       _ifxhc->wait_for_sof   = 1;
6603 +                       if(!out_nak_enh  )
6604 +                               _ifxhc->do_ping        =1;
6605 +                       else
6606 +                               _ifxhc->do_ping        =0;
6607 +                       _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6608 +                       _ifxhc->xfer_count     = _urbd->urb->actual_length;
6609 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6610 +               }
6611 +               return 1;
6612 +       }
6613 +       else if(hcint.b.datatglerr )
6614 +       {
6615 +               if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0)
6616 +                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1;
6617 +               else
6618 +                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0;
6619 +               _ifxhc->split=1;
6620 +               _ifxhc->wait_for_sof   = 1;
6621 +               if(!out_nak_enh  )
6622 +                       _ifxhc->do_ping        =1;
6623 +               else
6624 +                       _ifxhc->do_ping        =0;
6625 +               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6626 +               _ifxhc->xfer_count     = _urbd->urb->actual_length;
6627 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6628 +               return 1;
6629 +       }
6630 +       else if(hcint.b.frmovrun   )
6631 +       {
6632 +               _urbd->error_count=0;
6633 +               _ifxhc->wait_for_sof   = 0;
6634 +               _ifxhc->do_ping        = 0;
6635 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN);
6636 +               return 1;
6637 +       }
6638 +       else if(hcint.b.bblerr     )
6639 +       {
6640 +               _urbd->error_count=0;
6641 +               _ifxhc->wait_for_sof   = 0;
6642 +               _ifxhc->do_ping        = 0;
6643 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
6644 +               return 1;
6645 +       }
6646 +       return 0;
6647 +}
6648 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6649 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6650 +static int32_t chhltd_intr_rx_csplit(ifxhcd_hcd_t      *_ifxhcd,
6651 +                                  ifxhcd_hc_t       *_ifxhc,
6652 +                                  ifxusb_hc_regs_t  *_hc_regs,
6653 +                                  ifxhcd_urbd_t     *_urbd)
6654 +{
6655 +       hcint_data_t  hcint;
6656 +       hcint_data_t  hcintmsk;
6657 +       hctsiz_data_t hctsiz;
6658 +
6659 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
6660 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
6661 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
6662 +       disable_hc_int(_hc_regs,ack);
6663 +       disable_hc_int(_hc_regs,nak);
6664 +       disable_hc_int(_hc_regs,nyet);
6665 +       _ifxhc->do_ping        = 0;
6666 +
6667 +       if (hcint.b.xfercomp   )
6668 +       {
6669 +               _urbd->error_count=0;
6670 +               _ifxhc->wait_for_sof   = 0;
6671 +               _ifxhc->split=1;
6672 +               complete_channel(_ifxhcd, _ifxhc, _urbd);
6673 +               return 1;
6674 +       }
6675 +       else if(hcint.b.nak        )
6676 +       {
6677 +               _urbd->error_count=0;
6678 +               _ifxhc->split          = 1;
6679 +               _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6680 +               if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6681 +               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6682 +               _ifxhc->xfer_count     = _urbd->urb->actual_length;
6683 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6684 +               return 1;
6685 +       }
6686 +       else if(hcint.b.nyet)
6687 +       {
6688 +               _urbd->error_count=0;
6689 +               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
6690 +               _ifxhc->wait_for_sof   = 0;
6691 +
6692 +               /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/
6693 +               _ifxhc->nyet_count++;
6694 +               if(_ifxhc->nyet_count > 2) {
6695 +                       _ifxhc->split = 1;
6696 +                       _ifxhc->nyet_count = 0;
6697 +                       _ifxhc->wait_for_sof   = 5;
6698 +               }
6699 +
6700 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6701 +               return 1;
6702 +       }
6703 +       else if(hcint.b.frmovrun || hcint.b.bblerr || hcint.b.stall )
6704 +       {
6705 +               _urbd->error_count=0;
6706 +               _ifxhc->wait_for_sof   = 0;
6707 +               if     (hcint.b.stall)
6708 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
6709 +               else if(hcint.b.bblerr )
6710 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
6711 +               else if(hcint.b.frmovrun )
6712 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN);
6713 +               return 1;
6714 +       }
6715 +       else if(hcint.b.xacterr    )
6716 +       {
6717 +               hcchar_data_t   hcchar;
6718 +               hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar);
6719 +               _urbd->error_count=hcchar.b.multicnt;
6720 +               if(_urbd->error_count>=3)
6721 +               {
6722 +                       _urbd->error_count=0;
6723 +                       _ifxhc->wait_for_sof   = 0;
6724 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
6725 +               }
6726 +               else
6727 +               {
6728 +                       _ifxhc->split=1;
6729 +                       _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6730 +                       if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6731 +                       _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6732 +                       _ifxhc->xfer_count     = _urbd->urb->actual_length;
6733 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6734 +               }
6735 +               return 1;
6736 +       }
6737 +       else if(hcint.b.datatglerr )
6738 +       {
6739 +               if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0)
6740 +                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1;
6741 +               else
6742 +                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0;
6743 +               _ifxhc->split=1;
6744 +               _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6745 +               if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6746 +               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6747 +               _ifxhc->xfer_count     = _urbd->urb->actual_length;
6748 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6749 +               return 1;
6750 +       }
6751 +       return 0;
6752 +}
6753 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6754 +static int32_t chhltd_intr_tx_csplit(ifxhcd_hcd_t      *_ifxhcd,
6755 +                                  ifxhcd_hc_t       *_ifxhc,
6756 +                                  ifxusb_hc_regs_t  *_hc_regs,
6757 +                                  ifxhcd_urbd_t     *_urbd)
6758 +{
6759 +       hcint_data_t  hcint;
6760 +       hcint_data_t  hcintmsk;
6761 +       hctsiz_data_t hctsiz;
6762 +       int out_nak_enh = 0;
6763 +
6764 +       if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
6765 +               out_nak_enh = 1;
6766 +
6767 +       hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
6768 +       hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
6769 +       hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
6770 +       disable_hc_int(_hc_regs,ack);
6771 +       disable_hc_int(_hc_regs,nak);
6772 +       disable_hc_int(_hc_regs,nyet);
6773 +
6774 +       if(hcint.b.xfercomp   )
6775 +       {
6776 +               _urbd->error_count=0;
6777 +               _ifxhc->wait_for_sof   = 0;
6778 +               _ifxhc->split=1;
6779 +               _ifxhc->do_ping        = 0;
6780 +               complete_channel(_ifxhcd, _ifxhc, _urbd);
6781 +               return 1;
6782 +       }
6783 +       else if(hcint.b.nak        )
6784 +       {
6785 +               _urbd->error_count=0;
6786 +               _ifxhc->split          = 1;
6787 +               _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6788 +               if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6789 +               if(!out_nak_enh  )
6790 +                       _ifxhc->do_ping        =1;
6791 +               else
6792 +                       _ifxhc->do_ping        =0;
6793 +               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6794 +               _ifxhc->xfer_count     = _urbd->urb->actual_length;
6795 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6796 +               return 1;
6797 +       }
6798 +       else if(hcint.b.nyet)
6799 +       {
6800 +               _urbd->error_count=0;
6801 +               _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
6802 +               _ifxhc->wait_for_sof   = 0;
6803 +               _ifxhc->do_ping        = 0;
6804 +
6805 +               /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/
6806 +               _ifxhc->nyet_count++;
6807 +               if(_ifxhc->nyet_count > 2) {
6808 +                       _ifxhc->split = 1;
6809 +                       _ifxhc->nyet_count = 0;
6810 +                       _ifxhc->wait_for_sof = 5;
6811 +               }
6812 +
6813 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6814 +               return 1;
6815 +       }
6816 +       else if(hcint.b.stall || hcint.b.frmovrun)
6817 +       {
6818 +               _urbd->error_count=0;
6819 +               _ifxhc->wait_for_sof   = 0;
6820 +               _ifxhc->do_ping        = 0;
6821 +               if     (hcint.b.stall)
6822 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
6823 +               else if(hcint.b.frmovrun )
6824 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN);
6825 +               return 1;
6826 +       }
6827 +       else if(hcint.b.xacterr    )
6828 +       {
6829 +               hcchar_data_t   hcchar;
6830 +               hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar);
6831 +               _urbd->error_count=hcchar.b.multicnt;
6832 +               if(_urbd->error_count>=3)
6833 +               {
6834 +                       _urbd->error_count=0;
6835 +                       _ifxhc->wait_for_sof   = 0;
6836 +                       _ifxhc->do_ping        = 0;
6837 +                       release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR);
6838 +               }
6839 +               else
6840 +               {
6841 +                       _ifxhc->split=1;
6842 +                       _ifxhc->wait_for_sof   = _ifxhc->epqh->interval-1;
6843 +                       if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1;
6844 +                       if(!out_nak_enh  )
6845 +                               _ifxhc->do_ping        =1;
6846 +                       else
6847 +                               _ifxhc->do_ping        =0;
6848 +                       _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6849 +                       _ifxhc->xfer_count     = _urbd->urb->actual_length;
6850 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6851 +               }
6852 +               return 1;
6853 +       }
6854 +       else if(hcint.b.datatglerr )
6855 +       {
6856 +               if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0)
6857 +                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1;
6858 +               else
6859 +                       _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0;
6860 +               _ifxhc->split=1;
6861 +               if(!out_nak_enh  )
6862 +                       _ifxhc->do_ping        =1;
6863 +               else
6864 +                       _ifxhc->do_ping        =0;
6865 +               _ifxhc->xfer_len       = _urbd->xfer_len - _urbd->urb->actual_length;
6866 +               _ifxhc->xfer_count     = _urbd->urb->actual_length;
6867 +               ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6868 +               return 1;
6869 +       }
6870 +       else if(hcint.b.bblerr     )
6871 +       {
6872 +               _urbd->error_count=0;
6873 +               _ifxhc->wait_for_sof   = 0;
6874 +               _ifxhc->do_ping        = 0;
6875 +               release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR);
6876 +               return 1;
6877 +       }
6878 +       return 0;
6879 +}
6880 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6881 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6882 +static int32_t chhltd_isoc_rx_csplit(ifxhcd_hcd_t      *_ifxhcd,
6883 +                                   ifxhcd_hc_t       *_ifxhc,
6884 +                                   ifxusb_hc_regs_t  *_hc_regs,
6885 +                                   ifxhcd_urbd_t     *_urbd)
6886 +{
6887 +       #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__)
6888 +               hcint_data_t  hcint;
6889 +               hcint_data_t  hcintmsk;
6890 +               hctsiz_data_t hctsiz;
6891 +
6892 +               hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
6893 +               hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
6894 +               hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
6895 +               if(hcint.b.xfercomp   )
6896 +               {
6897 +                       disable_hc_int(_hc_regs,ack);
6898 +                       disable_hc_int(_hc_regs,nak);
6899 +                       disable_hc_int(_hc_regs,nyet);
6900 +                       _urbd->error_count=0;
6901 +                       _ifxhc->wait_for_sof   = 0;
6902 +                       _ifxhc->split=1;
6903 +                       complete_channel(_ifxhcd, _ifxhc, _urbd);
6904 +                       return 1;
6905 +               }
6906 +               else if(hcint.b.nak        )
6907 +               {
6908 +                       Retry Start Split (in next b_interval ¡V 1 uF)
6909 +               }
6910 +               else if(hcint.b.nyet)
6911 +               {
6912 +                       //Do Next Complete Split
6913 +                       // Issue Retry instantly on next SOF, without gothrough process_channels
6914 +                       _urbd->error_count=0;
6915 +                       //disable_hc_int(_hc_regs,ack);
6916 +                       //disable_hc_int(_hc_regs,nak);
6917 +                       //disable_hc_int(_hc_regs,datatglerr);
6918 +                       _ifxhc->halt_status    = HC_XFER_NO_HALT_STATUS;
6919 +                       _ifxhc->wait_for_sof   = 1;
6920 +                       ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc);
6921 +                       return 1;
6922 +               }
6923 +               else if(hcint.b.frmovrun || hcint.b.stall || hcint.b.bblerr)
6924 +               {
6925 +                       _urbd->error_count=0;
6926 +                       disable_hc_int(_hc_regs,ack);
6927 +                       disable_hc_int(_hc_regs,nyet);
6928 +                       disable_hc_int(_hc_regs,nak);
6929 +                       _ifxhc->wait_for_sof   = 0;
6930 +
6931 +                       //if(hctsiz.b.pktcnt==0)
6932 +                       //{
6933 +                       //      complete_channel(_ifxhcd, _ifxhc, _urbd);
6934 +                       //      return 1;
6935 +                       //}
6936 +                       //else
6937 +                       //      _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
6938 +                       if     (hcint.b.stall)
6939 +                               release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL);
6940 +                       else if(hcint.b.frmovrun )
6941 +                       else if(hcint.b.bblerr )
6942 +                       return 1;
6943 +               }
6944 +               else if(hcint.b.xacterr    )
6945 +               {
6946 +                       Rewind Buffer Pointers
6947 +                       if (HCCHARn.EC = = 3) // ERR response received
6948 +                       {
6949 +                               Record ERR error
6950 +                               Do Next Start Split (in next frame)
6951 +                       }
6952 +                       else
6953 +                       {
6954 +                               De-allocate Channel
6955 +                       }
6956 +               }
6957 +               else if(hcint.b.datatglerr )
6958 +               {
6959 +                       warning
6960 +               }
6961 +               else if(hcint.b.ack )
6962 +               {
6963 +                       warning
6964 +               }
6965 +       #endif
6966 +       return 0;
6967 +}
6968 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6969 +static int32_t chhltd_isoc_tx_csplit(ifxhcd_hcd_t      *_ifxhcd,
6970 +                                   ifxhcd_hc_t       *_ifxhc,
6971 +                                   ifxusb_hc_regs_t  *_hc_regs,
6972 +                                   ifxhcd_urbd_t     *_urbd)
6973 +{
6974 +       #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__)
6975 +               hcint_data_t  hcint;
6976 +               hcint_data_t  hcintmsk;
6977 +               hctsiz_data_t hctsiz;
6978 +               int out_nak_enh = 0;
6979 +
6980 +               if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH)
6981 +                       out_nak_enh = 1;
6982 +
6983 +               hcint.d32    = ifxusb_rreg(&_hc_regs->hcint);
6984 +               hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk);
6985 +               hctsiz.d32   = ifxusb_rreg(&_hc_regs->hctsiz);
6986 +               warning
6987 +       #endif
6988 +       return 0;
6989 +}
6990 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6991 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6992 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6993 +
6994 +static int32_t handle_hc_chhltd_intr(ifxhcd_hcd_t      *_ifxhcd,
6995 +                                     ifxhcd_hc_t       *_ifxhc,
6996 +                                     ifxusb_hc_regs_t  *_hc_regs,
6997 +                                     ifxhcd_urbd_t      *_urbd)
6998 +{
6999 +       IFX_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: Channel Halted--\n", _ifxhc->hc_num);
7000 +
7001 +       _ifxhc->halting      = 0;
7002 +       _ifxhc->xfer_started = 0;
7003 +
7004 +       if (_ifxhc->halt_status == HC_XFER_URB_DEQUEUE ||
7005 +           _ifxhc->halt_status == HC_XFER_AHB_ERR) {
7006 +               /*
7007 +                * Just release the channel. A dequeue can happen on a
7008 +                * transfer timeout. In the case of an AHB Error, the channel
7009 +                * was forced to halt because there's no way to gracefully
7010 +                * recover.
7011 +                */
7012 +               release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status);
7013 +               return 1;
7014 +       }
7015 +
7016 +       if     (_ifxhc->ep_type == IFXUSB_EP_TYPE_CTRL || _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK)
7017 +       {
7018 +               if     (_ifxhc->split==0)
7019 +               {
7020 +                       if(_ifxhc->is_in)
7021 +                               return (chhltd_ctrlbulk_rx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7022 +                       else
7023 +                               return (chhltd_ctrlbulk_tx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7024 +               }
7025 +               else if(_ifxhc->split==1)
7026 +               {
7027 +                       if(_ifxhc->is_in)
7028 +                               return (chhltd_ctrlbulk_rx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7029 +                       else
7030 +                               return (chhltd_ctrlbulk_tx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7031 +               }
7032 +               else if(_ifxhc->split==2)
7033 +               {
7034 +                       if(_ifxhc->is_in)
7035 +                               return (chhltd_ctrlbulk_rx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7036 +                       else
7037 +                               return (chhltd_ctrlbulk_tx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7038 +               }
7039 +       }
7040 +       else if(_ifxhc->ep_type == IFXUSB_EP_TYPE_INTR)
7041 +       {
7042 +               if     (_ifxhc->split==0)
7043 +               {
7044 +                       if(_ifxhc->is_in)
7045 +                               return (chhltd_intr_rx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7046 +                       else
7047 +                               return (chhltd_intr_tx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7048 +               }
7049 +               else if(_ifxhc->split==1)
7050 +               {
7051 +                       if(_ifxhc->is_in)
7052 +                               return (chhltd_intr_rx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7053 +                       else
7054 +                               return (chhltd_intr_tx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7055 +               }
7056 +               else if(_ifxhc->split==2)
7057 +               {
7058 +                       if(_ifxhc->is_in)
7059 +                               return (chhltd_intr_rx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7060 +                       else
7061 +                               return (chhltd_intr_tx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7062 +               }
7063 +       }
7064 +       else if(_ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC)
7065 +       {
7066 +               if     (_ifxhc->split==0)
7067 +               {
7068 +                       if(_ifxhc->is_in)
7069 +                               return (chhltd_isoc_rx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7070 +                       else
7071 +                               return (chhltd_isoc_tx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7072 +               }
7073 +               else if(_ifxhc->split==1)
7074 +               {
7075 +                       if(_ifxhc->is_in)
7076 +                               return (chhltd_isoc_rx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7077 +                       else
7078 +                               return (chhltd_isoc_tx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7079 +               }
7080 +               else if(_ifxhc->split==2)
7081 +               {
7082 +                       if(_ifxhc->is_in)
7083 +                               return (chhltd_isoc_rx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7084 +                       else
7085 +                               return (chhltd_isoc_tx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd));
7086 +               }
7087 +       }
7088 +       return 0;
7089 +}
7090 +
7091 +/*
7092 + * Handles a host channel AHB error interrupt. This handler is only called in
7093 + * DMA mode.
7094 + */
7095 +static void hc_other_intr_dump(ifxhcd_hcd_t      *_ifxhcd,
7096 +                               ifxhcd_hc_t       *_ifxhc,
7097 +                               ifxusb_hc_regs_t  *_hc_regs,
7098 +                               ifxhcd_urbd_t      *_urbd)
7099 +{
7100 +       #ifdef __DEBUG__
7101 +               hcchar_data_t hcchar;
7102 +               hcsplt_data_t hcsplt;
7103 +               hctsiz_data_t hctsiz;
7104 +               uint32_t      hcdma;
7105 +               struct urb   *urb = _urbd->urb;
7106 +               hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar);
7107 +               hcsplt.d32 = ifxusb_rreg(&_hc_regs->hcsplt);
7108 +               hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz);
7109 +               hcdma = ifxusb_rreg(&_hc_regs->hcdma);
7110 +
7111 +               IFX_ERROR("Channel %d\n", _ifxhc->hc_num);
7112 +               IFX_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
7113 +               IFX_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
7114 +               IFX_ERROR("  Device address: %d\n", usb_pipedevice(urb->pipe));
7115 +               IFX_ERROR("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
7116 +                           (usb_pipein(urb->pipe) ? "IN" : "OUT"));
7117 +               IFX_ERROR("  Endpoint type: %s\n",
7118 +                           ({char *pipetype;
7119 +                           switch (usb_pipetype(urb->pipe)) {
7120 +                                   case PIPE_CONTROL: pipetype = "CTRL"; break;
7121 +                                   case PIPE_BULK: pipetype = "BULK"; break;
7122 +                                   case PIPE_INTERRUPT: pipetype = "INTR"; break;
7123 +                                   case PIPE_ISOCHRONOUS: pipetype = "ISOC"; break;
7124 +                                   default: pipetype = "????"; break;
7125 +                           }; pipetype;}));
7126 +               IFX_ERROR("  Speed: %s\n",
7127 +                           ({char *speed;
7128 +                           switch (urb->dev->speed) {
7129 +                                   case USB_SPEED_HIGH: speed = "HS"; break;
7130 +                                   case USB_SPEED_FULL: speed = "FS"; break;
7131 +                                   case USB_SPEED_LOW: speed = "LS"; break;
7132 +                               default: speed = "????"; break;
7133 +                           }; speed;}));
7134 +               IFX_ERROR("  Max packet size: %d\n",
7135 +                           usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
7136 +               IFX_ERROR("  Data buffer length: %d\n", urb->transfer_buffer_length);
7137 +               IFX_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
7138 +                           urb->transfer_buffer, (void *)urb->transfer_dma);
7139 +               IFX_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
7140 +                           urb->setup_packet, (void *)urb->setup_dma);
7141 +               IFX_ERROR("  Interval: %d\n", urb->interval);
7142 +       #endif //__DEBUG__
7143 +}
7144 +
7145 +/*
7146 + * Handles a host channel ACK interrupt. This interrupt is enabled when
7147 + *  errors occur, and during Start Split transactions.
7148 + */
7149 +static int32_t handle_hc_ack_intr(ifxhcd_hcd_t      *_ifxhcd,
7150 +                                  ifxhcd_hc_t      *_ifxhc,
7151 +                                  ifxusb_hc_regs_t *_hc_regs,
7152 +                                  ifxhcd_urbd_t     *_urbd)
7153 +{
7154 +       _urbd->error_count=0;
7155 +       if(_ifxhc->nak_countdown_r)
7156 +       {
7157 +               _ifxhc->nak_retry=_ifxhc->nak_retry_r;
7158 +               _ifxhc->nak_countdown=_ifxhc->nak_countdown_r;
7159 +       }
7160 +       else
7161 +               disable_hc_int(_hc_regs,nak);
7162 +       disable_hc_int(_hc_regs,ack);
7163 +       return 1;
7164 +}
7165 +
7166 +/*
7167 + * Handles a host channel ACK interrupt. This interrupt is enabled when
7168 + *  errors occur, and during Start Split transactions.
7169 + */
7170 +static int32_t handle_hc_nak_intr(ifxhcd_hcd_t      *_ifxhcd,
7171 +                                  ifxhcd_hc_t      *_ifxhc,
7172 +                                  ifxusb_hc_regs_t *_hc_regs,
7173 +                                  ifxhcd_urbd_t     *_urbd)
7174 +{
7175 +
7176 +       _urbd->error_count=0;
7177 +
7178 +       if(_ifxhc->nak_countdown_r)
7179 +       {
7180 +               _ifxhc->nak_countdown--;
7181 +               if(!_ifxhc->nak_countdown)
7182 +               {
7183 +                       _ifxhc->nak_countdown=_ifxhc->nak_countdown_r;
7184 +                       disable_hc_int(_hc_regs,ack);
7185 +                       disable_hc_int(_hc_regs,nak);
7186 +                       ifxhcd_hc_halt(&_ifxhcd->core_if, _ifxhc, HC_XFER_NAK);
7187 +               }
7188 +               else
7189 +                       enable_hc_int(_hc_regs,ack);
7190 +       }
7191 +       else
7192 +       {
7193 +               disable_hc_int(_hc_regs,ack);
7194 +               disable_hc_int(_hc_regs,nak);
7195 +       }
7196 +       return 1;
7197 +}
7198 +
7199 +/*
7200 + * Handles a host channel AHB error interrupt. This handler is only called in
7201 + * DMA mode.
7202 + */
7203 +static int32_t handle_hc_ahberr_intr(ifxhcd_hcd_t      *_ifxhcd,
7204 +                                     ifxhcd_hc_t       *_ifxhc,
7205 +                                     ifxusb_hc_regs_t  *_hc_regs,
7206 +                                     ifxhcd_urbd_t      *_urbd)
7207 +{
7208 +       IFX_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
7209 +                   "AHB Error--\n", _ifxhc->hc_num);
7210 +       hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd);
7211 +
7212 +       ifxhcd_hc_halt(&_ifxhcd->core_if, _ifxhc, HC_XFER_AHB_ERR);
7213 +       return 1;
7214 +}
7215 +
7216 +/*
7217 + * Datatoggle
7218 + */
7219 +static int32_t handle_hc_datatglerr_intr(ifxhcd_hcd_t      *_ifxhcd,
7220 +                                         ifxhcd_hc_t      *_ifxhc,
7221 +                                         ifxusb_hc_regs_t *_hc_regs,
7222 +                                         ifxhcd_urbd_t     *_urbd)
7223 +{
7224 +       IFX_ERROR( "--Host Channel %d Interrupt: "
7225 +                   "DATATOGGLE Error--\n", _ifxhc->hc_num);
7226 +       hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd);
7227 +       disable_hc_int(_hc_regs,datatglerr);
7228 +       return 1;
7229 +}
7230 +
7231 +
7232 +
7233 +/*
7234 + * Interrupts which should not been triggered
7235 + */
7236 +static int32_t handle_hc_frmovrun_intr(ifxhcd_hcd_t      *_ifxhcd,
7237 +                                       ifxhcd_hc_t      *_ifxhc,
7238 +                                       ifxusb_hc_regs_t *_hc_regs,
7239 +                                       ifxhcd_urbd_t     *_urbd)
7240 +{
7241 +       IFX_ERROR( "--Host Channel %d Interrupt: "
7242 +                   "FrameOverRun Error--\n", _ifxhc->hc_num);
7243 +       hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd);
7244 +       disable_hc_int(_hc_regs,frmovrun);
7245 +       return 1;
7246 +}
7247 +
7248 +static int32_t handle_hc_bblerr_intr(ifxhcd_hcd_t      *_ifxhcd,
7249 +                                     ifxhcd_hc_t      *_ifxhc,
7250 +                                     ifxusb_hc_regs_t *_hc_regs,
7251 +                                     ifxhcd_urbd_t     *_urbd)
7252 +{
7253 +       IFX_ERROR( "--Host Channel %d Interrupt: "
7254 +                   "BBL Error--\n", _ifxhc->hc_num);
7255 +       hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd);
7256 +       disable_hc_int(_hc_regs,bblerr);
7257 +       return 1;
7258 +}
7259 +
7260 +static int32_t handle_hc_xacterr_intr(ifxhcd_hcd_t      *_ifxhcd,
7261 +                                      ifxhcd_hc_t      *_ifxhc,
7262 +                                      ifxusb_hc_regs_t *_hc_regs,
7263 +                                      ifxhcd_urbd_t     *_urbd)
7264 +{
7265 +       IFX_ERROR( "--Host Channel %d Interrupt: "
7266 +                   "XACT Error--\n", _ifxhc->hc_num);
7267 +       hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd);
7268 +       disable_hc_int(_hc_regs,xacterr);
7269 +       return 1;
7270 +}
7271 +
7272 +static int32_t handle_hc_nyet_intr(ifxhcd_hcd_t      *_ifxhcd,
7273 +                                   ifxhcd_hc_t      *_ifxhc,
7274 +                                   ifxusb_hc_regs_t *_hc_regs,
7275 +                                   ifxhcd_urbd_t     *_urbd)
7276 +{
7277 +       IFX_ERROR( "--Host Channel %d Interrupt: "
7278 +                   "NYET--\n", _ifxhc->hc_num);
7279 +       hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd);
7280 +       _urbd->error_count=0;
7281 +       disable_hc_int(_hc_regs,nyet);
7282 +       return 1;
7283 +}
7284 +
7285 +static int32_t handle_hc_stall_intr(ifxhcd_hcd_t      *_ifxhcd,
7286 +                                    ifxhcd_hc_t      *_ifxhc,
7287 +                                    ifxusb_hc_regs_t *_hc_regs,
7288 +                                    ifxhcd_urbd_t     *_urbd)
7289 +{
7290 +       IFX_ERROR( "--Host Channel %d Interrupt: "
7291 +                   "STALL--\n", _ifxhc->hc_num);
7292 +       hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd);
7293 +       disable_hc_int(_hc_regs,stall);
7294 +       return 1;
7295 +}
7296 +
7297 +static int32_t handle_hc_xfercomp_intr(ifxhcd_hcd_t      *_ifxhcd,
7298 +                                       ifxhcd_hc_t      *_ifxhc,
7299 +                                       ifxusb_hc_regs_t *_hc_regs,
7300 +                                       ifxhcd_urbd_t     *_urbd)
7301 +{
7302 +       IFX_ERROR( "--Host Channel %d Interrupt: "
7303 +                   "XFERCOMP--\n", _ifxhc->hc_num);
7304 +       hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd);
7305 +       disable_hc_int(_hc_regs,xfercomp);
7306 +       return 1;
7307 +}
7308 +
7309 +
7310 +
7311 +/* This interrupt indicates that the specified host channels has a pending
7312 + * interrupt. There are multiple conditions that can cause each host channel
7313 + * interrupt. This function determines which conditions have occurred for this
7314 + * host channel interrupt and handles them appropriately. */
7315 +static int32_t handle_hc_n_intr (ifxhcd_hcd_t *_ifxhcd, uint32_t _num)
7316 +{
7317 +       uint32_t          hcintval,hcintmsk;
7318 +       hcint_data_t      hcint;
7319 +       ifxhcd_hc_t      *ifxhc;
7320 +       ifxusb_hc_regs_t *hc_regs;
7321 +       ifxhcd_urbd_t     *urbd;
7322 +       unsigned long     flags;
7323 +
7324 +       int retval = 0;
7325 +
7326 +       IFX_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", _num);
7327 +
7328 +       /*== AVM/BC 20101111 Lock needed ==*/
7329 +       SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
7330 +
7331 +       ifxhc = &_ifxhcd->ifxhc[_num];
7332 +       hc_regs = _ifxhcd->core_if.hc_regs[_num];
7333 +
7334 +       hcintval  = ifxusb_rreg(&hc_regs->hcint);
7335 +       hcintmsk  = ifxusb_rreg(&hc_regs->hcintmsk);
7336 +       hcint.d32 = hcintval & hcintmsk;
7337 +       IFX_DEBUGPL(DBG_HCDV, "  0x%08x & 0x%08x = 0x%08x\n",
7338 +                   hcintval, hcintmsk, hcint.d32);
7339 +
7340 +       urbd = list_entry(ifxhc->epqh->urbd_list.next, ifxhcd_urbd_t, urbd_list_entry);
7341 +
7342 +       if (hcint.b.datatglerr)
7343 +               retval |= handle_hc_datatglerr_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7344 +       if (hcint.b.frmovrun)
7345 +               retval |= handle_hc_frmovrun_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7346 +       if (hcint.b.bblerr)
7347 +               retval |= handle_hc_bblerr_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7348 +       if (hcint.b.xacterr)
7349 +               retval |= handle_hc_xacterr_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7350 +       if (hcint.b.nyet)
7351 +               retval |= handle_hc_nyet_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7352 +       if (hcint.b.ack)
7353 +               retval |= handle_hc_ack_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7354 +       if (hcint.b.nak)
7355 +               retval |= handle_hc_nak_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7356 +       if (hcint.b.stall)
7357 +               retval |= handle_hc_stall_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7358 +       if (hcint.b.ahberr) {
7359 +               clear_hc_int(hc_regs, ahberr);
7360 +               retval |= handle_hc_ahberr_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7361 +       }
7362 +       if (hcint.b.chhltd) {
7363 +               /* == 20110901 AVM/WK Fix: Flag must not be cleared after restart of channel ==*/
7364 +               clear_hc_int(hc_regs, chhltd);
7365 +               retval |= handle_hc_chhltd_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7366 +       }
7367 +       if (hcint.b.xfercomp)
7368 +               retval |= handle_hc_xfercomp_intr(_ifxhcd, ifxhc, hc_regs, urbd);
7369 +
7370 +       /* == 20110901 AVM/WK Fix: Never clear possibly new intvals ==*/
7371 +       //ifxusb_wreg(&hc_regs->hcint,hcintval);
7372 +
7373 +       SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
7374 +
7375 +       return retval;
7376 +}
7377 +
7378 +
7379 +
7380 +
7381 +
7382 +
7383 +static uint8_t update_interval_counter(ifxhcd_epqh_t *_epqh,uint32_t _diff)
7384 +{
7385 +       if(_diff>=_epqh->period_counter)
7386 +       {
7387 +               _epqh->period_do=1;
7388 +               if(_diff>_epqh->interval)
7389 +                       _epqh->period_counter=1;
7390 +               else
7391 +                       _epqh->period_counter=_epqh->period_counter+_epqh->interval-_diff;
7392 +               return 1;
7393 +       }
7394 +       _epqh->period_counter=_epqh->period_counter-_diff;
7395 +       return 0;
7396 +}
7397 +
7398 +
7399 +
7400 +
7401 +/*
7402 + * Handles the start-of-frame interrupt in host mode. Non-periodic
7403 + * transactions may be queued to the DWC_otg controller for the current
7404 + * (micro)frame. Periodic transactions may be queued to the controller for the
7405 + * next (micro)frame.
7406 + */
7407 +static int32_t handle_sof_intr (ifxhcd_hcd_t *_ifxhcd)
7408 +{
7409 +       #ifdef __DYN_SOF_INTR__
7410 +               uint8_t with_count_down=0;
7411 +       #endif
7412 +       uint8_t active_on=0;
7413 +       uint8_t ready_on=0;
7414 +       struct list_head  *epqh_entry;
7415 +       ifxhcd_epqh_t     *epqh;
7416 +       hfnum_data_t hfnum;
7417 +       uint32_t fndiff;
7418 +
7419 +       unsigned long flags;
7420 +#ifdef __USE_TIMER_4_SOF__
7421 +       uint32_t wait_for_sof = 0x10000;
7422 +#endif
7423 +
7424 +       SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
7425 +
7426 +       {
7427 +               int               num_channels;
7428 +               ifxusb_hc_regs_t *hc_regs;
7429 +               int                   i;
7430 +               num_channels = _ifxhcd->core_if.params.host_channels;
7431 +
7432 +// AVM/WK moved block here due to use of SOF timer
7433 +               hfnum.d32 = ifxusb_rreg(&_ifxhcd->core_if.host_global_regs->hfnum);
7434 +               fndiff = hfnum.b.frnum;
7435 +               fndiff+= 0x00004000;
7436 +               fndiff-= _ifxhcd->lastframe ;
7437 +               fndiff&= 0x00003FFF;
7438 +               if(!fndiff) fndiff =1;
7439 +
7440 +               for (i = 0; i < num_channels; i++)
7441 +               {
7442 +                       if(_ifxhcd->ifxhc[i].wait_for_sof && _ifxhcd->ifxhc[i].xfer_started)
7443 +                       {
7444 +#ifdef __USE_TIMER_4_SOF__
7445 +                               if (_ifxhcd->ifxhc[i].wait_for_sof > fndiff) {
7446 +                                       _ifxhcd->ifxhc[i].wait_for_sof -= fndiff;
7447 +                               } else {
7448 +                                       _ifxhcd->ifxhc[i].wait_for_sof = 0;
7449 +                               }
7450 +#else
7451 +                               _ifxhcd->ifxhc[i].wait_for_sof--;
7452 +#endif
7453 +                               if(_ifxhcd->ifxhc[i].wait_for_sof==0)
7454 +                               {
7455 +                                       hcint_data_t hcint= { .d32=0 };
7456 +                                       hc_regs = _ifxhcd->core_if.hc_regs[i];
7457 +
7458 +                                       hcint.d32 =0xFFFFFFFF;
7459 +                                       ifxusb_wreg(&hc_regs->hcint, hcint.d32);
7460 +
7461 +                                       hcint.d32=ifxusb_rreg(&hc_regs->hcintmsk);
7462 +                                       hcint.b.nak =0;
7463 +                                       hcint.b.ack =0;
7464 +                                       /* == 20110901 AVM/WK Fix: We don't need NOT YET IRQ ==*/
7465 +                                       hcint.b.nyet=0;
7466 +                                       _ifxhcd->ifxhc[i].nak_countdown=_ifxhcd->ifxhc[i].nak_countdown_r;
7467 +                                       if(_ifxhcd->ifxhc[i].nak_countdown_r)
7468 +                                               hcint.b.nak =1;
7469 +                                       ifxusb_wreg(&hc_regs->hcintmsk, hcint.d32);
7470 +
7471 +                                       /* AVM WK / BC 20100827
7472 +                                        * FIX: Packet was ignored because of wrong Oddframe bit
7473 +                                        */
7474 +                                       if (_ifxhcd->ifxhc[i].ep_type == IFXUSB_EP_TYPE_INTR || _ifxhcd->ifxhc[i].ep_type == IFXUSB_EP_TYPE_ISOC)
7475 +                                       {
7476 +                                               hcchar_data_t hcchar;
7477 +                                               hcchar.d32 = _ifxhcd->ifxhc[i].hcchar;
7478 +                                               hfnum.d32 = ifxusb_rreg(&_ifxhcd->core_if.host_global_regs->hfnum);
7479 +                                               /* 1 if _next_ frame is odd, 0 if it's even */
7480 +                                               hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
7481 +                                               _ifxhcd->ifxhc[i].hcchar = hcchar.d32;
7482 +                                       }
7483 +
7484 +                                       ifxusb_wreg(&hc_regs->hcchar, _ifxhcd->ifxhc[i].hcchar);
7485 +
7486 +                               }
7487 +                       }
7488 +                       else
7489 +                               _ifxhcd->ifxhc[i].wait_for_sof=0;
7490 +
7491 +#ifdef __USE_TIMER_4_SOF__
7492 +                       if (_ifxhcd->ifxhc[i].wait_for_sof && (wait_for_sof > _ifxhcd->ifxhc[i].wait_for_sof)) {
7493 +                               wait_for_sof = _ifxhcd->ifxhc[i].wait_for_sof;
7494 +                       }
7495 +#endif
7496 +               }
7497 +       }
7498 +
7499 +       // ISOC Active
7500 +       #ifdef __EN_ISOC__
7501 +               #error ISOC not supported: missing SOF code
7502 +               epqh_entry = _ifxhcd->epqh_isoc_active.next;
7503 +               while (epqh_entry != &_ifxhcd->epqh_isoc_active)
7504 +               {
7505 +                       epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry);
7506 +                       epqh_entry = epqh_entry->next;
7507 +                       #ifdef __DYN_SOF_INTR__
7508 +                               with_count_down=1;
7509 +                       #endif
7510 +                       active_on+=update_interval_counter(epqh,fndiff);
7511 +               }
7512 +
7513 +               // ISOC Ready
7514 +               epqh_entry = _ifxhcd->epqh_isoc_ready.next;
7515 +               while (epqh_entry != &_ifxhcd->epqh_isoc_ready)
7516 +               {
7517 +                       epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry);
7518 +                       epqh_entry = epqh_entry->next;
7519 +                       #ifdef __DYN_SOF_INTR__
7520 +                               with_count_down=1;
7521 +                       #endif
7522 +                       ready_on+=update_interval_counter(epqh,fndiff);
7523 +               }
7524 +       #endif
7525 +
7526 +       // INTR Active
7527 +       epqh_entry = _ifxhcd->epqh_intr_active.next;
7528 +       while (epqh_entry != &_ifxhcd->epqh_intr_active)
7529 +       {
7530 +               epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry);
7531 +               epqh_entry = epqh_entry->next;
7532 +               #ifdef __DYN_SOF_INTR__
7533 +                       with_count_down=1;
7534 +               #endif
7535 +#ifdef __USE_TIMER_4_SOF__
7536 +               if (update_interval_counter(epqh,fndiff)) {
7537 +                       active_on ++;
7538 +                       wait_for_sof = 1;
7539 +               } else {
7540 +                       if (epqh->period_counter && (wait_for_sof > epqh->period_counter)) {
7541 +                               wait_for_sof = epqh->period_counter;
7542 +                       }
7543 +               }
7544 +#else
7545 +               active_on+=update_interval_counter(epqh,fndiff);
7546 +#endif
7547 +       }
7548 +
7549 +       // INTR Ready
7550 +       epqh_entry = _ifxhcd->epqh_intr_ready.next;
7551 +       while (epqh_entry != &_ifxhcd->epqh_intr_ready)
7552 +       {
7553 +               epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry);
7554 +               epqh_entry = epqh_entry->next;
7555 +               #ifdef __DYN_SOF_INTR__
7556 +                       with_count_down=1;
7557 +               #endif
7558 +#ifdef __USE_TIMER_4_SOF__
7559 +               if (update_interval_counter(epqh,fndiff)) {
7560 +                       ready_on ++;
7561 +                       wait_for_sof = 1;
7562 +               } else {
7563 +                       if (epqh->period_counter && (wait_for_sof > epqh->period_counter)) {
7564 +                               wait_for_sof = epqh->period_counter;
7565 +                       }
7566 +               }
7567 +#else
7568 +               ready_on+=update_interval_counter(epqh,fndiff);
7569 +#endif
7570 +       }
7571 +
7572 +       // Stdby
7573 +       epqh_entry = _ifxhcd->epqh_stdby.next;
7574 +       while (epqh_entry != &_ifxhcd->epqh_stdby)
7575 +       {
7576 +               epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry);
7577 +               epqh_entry = epqh_entry->next;
7578 +               if(epqh->period_counter > 0 ) {
7579 +#ifdef __USE_TIMER_4_SOF__
7580 +                       if (epqh->period_counter > fndiff) {
7581 +                               epqh->period_counter -= fndiff;
7582 +                       } else {
7583 +                               epqh->period_counter = 0;
7584 +                       }
7585 +#else
7586 +                       epqh->period_counter --;
7587 +#endif
7588 +                       #ifdef __DYN_SOF_INTR__
7589 +                               with_count_down=1;
7590 +                       #endif
7591 +               }
7592 +               if(epqh->period_counter == 0) {
7593 +                       ifxhcd_epqh_idle_periodic(epqh);
7594 +               }
7595 +#ifdef __USE_TIMER_4_SOF__
7596 +               else {
7597 +                       if (wait_for_sof > epqh->period_counter) {
7598 +                               wait_for_sof = epqh->period_counter;
7599 +                       }
7600 +               }
7601 +#endif
7602 +       }
7603 +       SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
7604 +
7605 +       if(ready_on)
7606 +               select_eps(_ifxhcd);
7607 +       else if(active_on)
7608 +               process_channels(_ifxhcd);
7609 +
7610 +       /* Clear interrupt */
7611 +       {
7612 +               gint_data_t gintsts;
7613 +               gintsts.d32=0;
7614 +               gintsts.b.sofintr = 1;
7615 +               ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32);
7616 +
7617 +               #ifdef __DYN_SOF_INTR__
7618 +                       if(!with_count_down)
7619 +                               ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, gintsts.d32,0);
7620 +               #endif
7621 +#ifdef __USE_TIMER_4_SOF__
7622 +               wait_for_sof &= 0xFFFF; // reduce to 16 Bits.
7623 +
7624 +               if(wait_for_sof == 1) {
7625 +                       // enable SOF
7626 +                               gint_data_t gintsts;
7627 +                               gintsts.d32=0;
7628 +                               gintsts.b.sofintr = 1;
7629 +                               ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, 0,gintsts.d32);
7630 +               } else {
7631 +                       // disable SOF
7632 +                       ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, gintsts.d32,0);
7633 +                       if (wait_for_sof > 1) {
7634 +                               // use timer, not SOF IRQ
7635 +                               hprt0_data_t   hprt0;
7636 +                               ktime_t ktime;
7637 +                               hprt0.d32 = ifxusb_read_hprt0 (&_ifxhcd->core_if);
7638 +                               if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED) {
7639 +                                       ktime = ktime_set(0, wait_for_sof * 125 * 1000); /*--- wakeup in n*125usec ---*/
7640 +                               } else {
7641 +                                       ktime = ktime_set(0, wait_for_sof * (1000*1000)); /*--- wakeup in n*1000usec ---*/
7642 +                               }
7643 +                               hrtimer_start(&_ifxhcd->hr_timer, ktime, HRTIMER_MODE_REL);
7644 +                       }
7645 +               }
7646 +#endif
7647 +       }
7648 +       _ifxhcd->lastframe=hfnum.b.frnum;
7649 +       return 1;
7650 +}
7651 +
7652 +
7653 +
7654 +/* There are multiple conditions that can cause a port interrupt. This function
7655 + * determines which interrupt conditions have occurred and handles them
7656 + * appropriately. */
7657 +static int32_t handle_port_intr (ifxhcd_hcd_t *_ifxhcd)
7658 +{
7659 +       int retval = 0;
7660 +       hprt0_data_t hprt0;
7661 +       hprt0_data_t hprt0_modify;
7662 +
7663 +       hprt0.d32        =
7664 +       hprt0_modify.d32 = ifxusb_rreg(_ifxhcd->core_if.hprt0);
7665 +
7666 +       /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
7667 +        * GINTSTS */
7668 +
7669 +       hprt0_modify.b.prtena = 0;
7670 +       hprt0_modify.b.prtconndet = 0;
7671 +       hprt0_modify.b.prtenchng = 0;
7672 +       hprt0_modify.b.prtovrcurrchng = 0;
7673 +
7674 +       /* Port Connect Detected
7675 +        * Set flag and clear if detected */
7676 +       if (hprt0.b.prtconndet) {
7677 +               IFX_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
7678 +                           "Port Connect Detected--\n", hprt0.d32);
7679 +               _ifxhcd->flags.b.port_connect_status_change = 1;
7680 +               _ifxhcd->flags.b.port_connect_status = 1;
7681 +               hprt0_modify.b.prtconndet = 1;
7682 +
7683 +               /* The Hub driver asserts a reset when it sees port connect
7684 +                * status change flag */
7685 +               retval |= 1;
7686 +       }
7687 +
7688 +       /* Port Enable Changed
7689 +        * Clear if detected - Set internal flag if disabled */
7690 +       if (hprt0.b.prtenchng) {
7691 +
7692 +               IFX_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
7693 +                           "Port Enable Changed--\n", hprt0.d32);
7694 +               hprt0_modify.b.prtenchng = 1;
7695 +               if (hprt0.b.prtena == 1)
7696 +                       /* Port has been enabled set the reset change flag */
7697 +                       _ifxhcd->flags.b.port_reset_change = 1;
7698 +               else
7699 +                       _ifxhcd->flags.b.port_enable_change = 1;
7700 +               retval |= 1;
7701 +       }
7702 +
7703 +       /* Overcurrent Change Interrupt */
7704 +
7705 +       if (hprt0.b.prtovrcurrchng) {
7706 +               IFX_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
7707 +                           "Port Overcurrent Changed--\n", hprt0.d32);
7708 +               _ifxhcd->flags.b.port_over_current_change = 1;
7709 +               hprt0_modify.b.prtovrcurrchng = 1;
7710 +               retval |= 1;
7711 +       }
7712 +
7713 +       /* Clear Port Interrupts */
7714 +       ifxusb_wreg(_ifxhcd->core_if.hprt0, hprt0_modify.d32);
7715 +       return retval;
7716 +}
7717 +
7718 +/*
7719 + * This interrupt indicates that SUSPEND state has been detected on
7720 + * the USB.
7721 + * No Functioning in Host Mode
7722 + */
7723 +static int32_t handle_usb_suspend_intr(ifxhcd_hcd_t *_ifxhcd)
7724 +{
7725 +       gint_data_t gintsts;
7726 +       IFX_DEBUGP("USB SUSPEND RECEIVED!\n");
7727 +       /* Clear interrupt */
7728 +       gintsts.d32 = 0;
7729 +       gintsts.b.usbsuspend = 1;
7730 +       ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32);
7731 +       return 1;
7732 +}
7733 +
7734 +/*
7735 + * This interrupt indicates that the IFXUSB controller has detected a
7736 + * resume or remote wakeup sequence. If the IFXUSB controller is in
7737 + * low power mode, the handler must brings the controller out of low
7738 + * power mode. The controller automatically begins resume
7739 + * signaling. The handler schedules a time to stop resume signaling.
7740 + */
7741 +static int32_t handle_wakeup_detected_intr(ifxhcd_hcd_t *_ifxhcd)
7742 +{
7743 +       gint_data_t gintsts;
7744 +       hprt0_data_t hprt0 = {.d32=0};
7745 +       pcgcctl_data_t pcgcctl = {.d32=0};
7746 +       ifxusb_core_if_t *core_if = &_ifxhcd->core_if;
7747 +
7748 +       IFX_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
7749 +
7750 +       /*
7751 +        * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
7752 +        * so that OPT tests pass with all PHYs).
7753 +        */
7754 +       /* Restart the Phy Clock */
7755 +       pcgcctl.b.stoppclk = 1;
7756 +       ifxusb_mreg(core_if->pcgcctl, pcgcctl.d32, 0);
7757 +       UDELAY(10);
7758 +
7759 +       /* Now wait for 70 ms. */
7760 +       hprt0.d32 = ifxusb_read_hprt0( core_if );
7761 +       IFX_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
7762 +       MDELAY(70);
7763 +       hprt0.b.prtres = 0; /* Resume */
7764 +       ifxusb_wreg(core_if->hprt0, hprt0.d32);
7765 +       IFX_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", ifxusb_rreg(core_if->hprt0));
7766 +
7767 +       /* Clear interrupt */
7768 +       gintsts.d32 = 0;
7769 +       gintsts.b.wkupintr = 1;
7770 +       ifxusb_wreg(&core_if->core_global_regs->gintsts, gintsts.d32);
7771 +       return 1;
7772 +}
7773 +
7774 +/*
7775 + * This interrupt indicates that a device is initiating the Session
7776 + * Request Protocol to request the host to turn on bus power so a new
7777 + * session can begin. The handler responds by turning on bus power. If
7778 + * the DWC_otg controller is in low power mode, the handler brings the
7779 + * controller out of low power mode before turning on bus power.
7780 + */
7781 +static int32_t handle_session_req_intr(ifxhcd_hcd_t *_ifxhcd)
7782 +{
7783 +       /* Clear interrupt */
7784 +       gint_data_t gintsts = { .d32 = 0 };
7785 +       gintsts.b.sessreqintr = 1;
7786 +       ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32);
7787 +       return 1;
7788 +}
7789 +
7790 +/*
7791 + * This interrupt indicates that a device has been disconnected from
7792 + * the root port.
7793 + */
7794 +static int32_t handle_disconnect_intr(ifxhcd_hcd_t *_ifxhcd)
7795 +{
7796 +       gint_data_t gintsts;
7797 +
7798 +       ifxhcd_disconnect(_ifxhcd);
7799 +
7800 +       gintsts.d32 = 0;
7801 +       gintsts.b.disconnect = 1;
7802 +       ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32);
7803 +       return 1;
7804 +}
7805 +
7806 +/*
7807 + * This function handles the Connector ID Status Change Interrupt.  It
7808 + * reads the OTG Interrupt Register (GOTCTL) to determine whether this
7809 + * is a Device to Host Mode transition or a Host Mode to Device
7810 + * Transition.
7811 + * This only occurs when the cable is connected/removed from the PHY
7812 + * connector.
7813 + */
7814 +static int32_t handle_conn_id_status_change_intr(ifxhcd_hcd_t *_ifxhcd)
7815 +{
7816 +       gint_data_t gintsts;
7817 +
7818 +       IFX_WARN("ID Status Change Interrupt: currently in %s mode\n",
7819 +            ifxusb_mode(&_ifxhcd->core_if) ? "Host" : "Device");
7820 +
7821 +       gintsts.d32 = 0;
7822 +       gintsts.b.conidstschng = 1;
7823 +       ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32);
7824 +       return 1;
7825 +}
7826 +
7827 +static int32_t handle_otg_intr(ifxhcd_hcd_t *_ifxhcd)
7828 +{
7829 +       ifxusb_core_global_regs_t *global_regs = _ifxhcd->core_if.core_global_regs;
7830 +       gotgint_data_t gotgint;
7831 +       gotgint.d32 = ifxusb_rreg( &global_regs->gotgint);
7832 +       /* Clear GOTGINT */
7833 +       ifxusb_wreg (&global_regs->gotgint, gotgint.d32);
7834 +       return 1;
7835 +}
7836 +
7837 +/** This function will log a debug message */
7838 +static int32_t handle_mode_mismatch_intr(ifxhcd_hcd_t *_ifxhcd)
7839 +{
7840 +       gint_data_t gintsts;
7841 +
7842 +       IFX_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
7843 +            ifxusb_mode(&_ifxhcd->core_if) ? "Host" : "Device");
7844 +       gintsts.d32 = 0;
7845 +       gintsts.b.modemismatch = 1;
7846 +       ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32);
7847 +       return 1;
7848 +}
7849 +
7850 +/** This function handles interrupts for the HCD. */
7851 +int32_t ifxhcd_handle_intr (ifxhcd_hcd_t *_ifxhcd)
7852 +{
7853 +       int retval = 0;
7854 +
7855 +       ifxusb_core_if_t *core_if = &_ifxhcd->core_if;
7856 +       /* AVM/BC 20101111 Unnecesary variable removed*/
7857 +       //gint_data_t gintsts,gintsts2;
7858 +       gint_data_t gintsts;
7859 +
7860 +       /* Check if HOST Mode */
7861 +       if (ifxusb_is_device_mode(core_if))
7862 +       {
7863 +               IFX_ERROR("%s() CRITICAL!  IN DEVICE MODE\n", __func__);
7864 +               return 0;
7865 +       }
7866 +
7867 +       gintsts.d32 = ifxusb_read_core_intr(core_if);
7868 +
7869 +       if (!gintsts.d32)
7870 +               return 0;
7871 +
7872 +       //Common INT
7873 +       if (gintsts.b.modemismatch)
7874 +       {
7875 +               retval |= handle_mode_mismatch_intr(_ifxhcd);
7876 +               gintsts.b.modemismatch=0;
7877 +       }
7878 +       if (gintsts.b.otgintr)
7879 +       {
7880 +               retval |= handle_otg_intr(_ifxhcd);
7881 +               gintsts.b.otgintr=0;
7882 +       }
7883 +       if (gintsts.b.conidstschng)
7884 +       {
7885 +               retval |= handle_conn_id_status_change_intr(_ifxhcd);
7886 +               gintsts.b.conidstschng=0;
7887 +       }
7888 +       if (gintsts.b.disconnect)
7889 +       {
7890 +               retval |= handle_disconnect_intr(_ifxhcd);
7891 +               gintsts.b.disconnect=0;
7892 +       }
7893 +       if (gintsts.b.sessreqintr)
7894 +       {
7895 +               retval |= handle_session_req_intr(_ifxhcd);
7896 +               gintsts.b.sessreqintr=0;
7897 +       }
7898 +       if (gintsts.b.wkupintr)
7899 +       {
7900 +               retval |= handle_wakeup_detected_intr(_ifxhcd);
7901 +               gintsts.b.wkupintr=0;
7902 +       }
7903 +       if (gintsts.b.usbsuspend)
7904 +       {
7905 +               retval |= handle_usb_suspend_intr(_ifxhcd);
7906 +               gintsts.b.usbsuspend=0;
7907 +       }
7908 +
7909 +       //Host Int
7910 +       if (gintsts.b.sofintr)
7911 +       {
7912 +               retval |= handle_sof_intr (_ifxhcd);
7913 +               gintsts.b.sofintr=0;
7914 +       }
7915 +       if (gintsts.b.portintr)
7916 +       {
7917 +               retval |= handle_port_intr (_ifxhcd);
7918 +               gintsts.b.portintr=0;
7919 +       }
7920 +       if (gintsts.b.hcintr)
7921 +       {
7922 +               int i;
7923 +               haint_data_t haint;
7924 +               haint.d32 = ifxusb_read_host_all_channels_intr(core_if);
7925 +               for (i=0; i< core_if->params.host_channels; i++)
7926 +                       if (haint.b2.chint & (1 << i))
7927 +                               retval |= handle_hc_n_intr (_ifxhcd, i);
7928 +               gintsts.b.hcintr=0;
7929 +       }
7930 +       return retval;
7931 +}
7932 --- /dev/null
7933 +++ b/drivers/usb/ifxhcd/ifxhcd_queue.c
7934 @@ -0,0 +1,418 @@
7935 +/*****************************************************************************
7936 + **   FILE NAME       : ifxhcd_queue.c
7937 + **   PROJECT         : IFX USB sub-system V3
7938 + **   MODULES         : IFX USB sub-system Host and Device driver
7939 + **   SRC VERSION     : 1.0
7940 + **   DATE            : 1/Jan/2009
7941 + **   AUTHOR          : Chen, Howard
7942 + **   DESCRIPTION     : This file contains the functions to manage Queue Heads and Queue
7943 + **                     Transfer Descriptors.
7944 + *****************************************************************************/
7945 +
7946 +/*!
7947 + \file ifxhcd_queue.c
7948 + \ingroup IFXUSB_DRIVER_V3
7949 +  \brief This file contains the functions to manage Queue Heads and Queue
7950 +  Transfer Descriptors.
7951 +*/
7952 +#include <linux/version.h>
7953 +#include "ifxusb_version.h"
7954 +
7955 +#include <linux/kernel.h>
7956 +#include <linux/module.h>
7957 +#include <linux/moduleparam.h>
7958 +#include <linux/init.h>
7959 +#include <linux/device.h>
7960 +#include <linux/errno.h>
7961 +#include <linux/list.h>
7962 +#include <linux/interrupt.h>
7963 +#include <linux/string.h>
7964 +
7965 +#include "ifxusb_plat.h"
7966 +#include "ifxusb_regs.h"
7967 +#include "ifxusb_cif.h"
7968 +#include "ifxhcd.h"
7969 +
7970 +#ifdef __EPQD_DESTROY_TIMEOUT__
7971 +       #define epqh_self_destroy_timeout 5
7972 +       static void eqph_destroy_func(unsigned long _ptr)
7973 +       {
7974 +               ifxhcd_epqh_t *epqh=(ifxhcd_epqh_t *)_ptr;
7975 +               if(epqh)
7976 +               {
7977 +                       ifxhcd_epqh_free (epqh);
7978 +               }
7979 +       }
7980 +#endif
7981 +
7982 +#define SCHEDULE_SLOP 10
7983 +
7984 +/*!
7985 +  \brief This function allocates and initializes a EPQH.
7986 +
7987 +  \param _ifxhcd The HCD state structure for the USB Host controller.
7988 +  \param[in] _urb Holds the information about the device/endpoint that we need
7989 +  to initialize the EPQH.
7990 +
7991 +  \return Returns pointer to the newly allocated EPQH, or NULL on error.
7992 + */
7993 +ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb)
7994 +{
7995 +       ifxhcd_epqh_t *epqh;
7996 +
7997 +       hprt0_data_t   hprt0;
7998 +       struct usb_host_endpoint *sysep = ifxhcd_urb_to_endpoint(_urb);
7999 +
8000 +       /* Allocate memory */
8001 +//     epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_KERNEL);
8002 +       epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_ATOMIC);
8003 +
8004 +       if(epqh == NULL)
8005 +               return NULL;
8006 +
8007 +       memset (epqh, 0, sizeof (ifxhcd_epqh_t));
8008 +
8009 +       epqh->sysep=sysep;
8010 +
8011 +       /* Initialize EPQH */
8012 +       switch (usb_pipetype(_urb->pipe))
8013 +       {
8014 +               case PIPE_CONTROL    : epqh->ep_type = IFXUSB_EP_TYPE_CTRL; break;
8015 +               case PIPE_BULK       : epqh->ep_type = IFXUSB_EP_TYPE_BULK; break;
8016 +               case PIPE_ISOCHRONOUS: epqh->ep_type = IFXUSB_EP_TYPE_ISOC; break;
8017 +               case PIPE_INTERRUPT  : epqh->ep_type = IFXUSB_EP_TYPE_INTR; break;
8018 +       }
8019 +
8020 +       //epqh->data_toggle = IFXUSB_HC_PID_DATA0;
8021 +
8022 +       epqh->mps = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
8023 +
8024 +       hprt0.d32 = ifxusb_read_hprt0 (&_ifxhcd->core_if);
8025 +
8026 +       INIT_LIST_HEAD(&epqh->urbd_list);
8027 +       INIT_LIST_HEAD(&epqh->epqh_list_entry);
8028 +       epqh->hc = NULL;
8029 +
8030 +       epqh->dump_buf = ifxusb_alloc_buf(epqh->mps, 0);
8031 +
8032 +       /* FS/LS Enpoint on HS Hub
8033 +        * NOT virtual root hub */
8034 +       epqh->need_split = 0;
8035 +       epqh->pkt_count_limit=0;
8036 +       if(epqh->ep_type == IFXUSB_EP_TYPE_BULK && !(usb_pipein(_urb->pipe)) )
8037 +               epqh->pkt_count_limit=4;
8038 +       if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED &&
8039 +           ((_urb->dev->speed == USB_SPEED_LOW) ||
8040 +            (_urb->dev->speed == USB_SPEED_FULL)) &&
8041 +            (_urb->dev->tt) && (_urb->dev->tt->hub->devnum != 1))
8042 +       {
8043 +               IFX_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
8044 +                      usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
8045 +                      _urb->dev->ttport);
8046 +               epqh->need_split = 1;
8047 +               epqh->pkt_count_limit=1;
8048 +       }
8049 +
8050 +       if (epqh->ep_type == IFXUSB_EP_TYPE_INTR ||
8051 +           epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
8052 +       {
8053 +               /* Compute scheduling parameters once and save them. */
8054 +               epqh->interval    = _urb->interval;
8055 +               if(epqh->need_split)
8056 +                       epqh->interval *= 8;
8057 +       }
8058 +
8059 +       epqh->period_counter=0;
8060 +       epqh->is_active=0;
8061 +
8062 +       #ifdef __EPQD_DESTROY_TIMEOUT__
8063 +               /* Start a timer for this transfer. */
8064 +               init_timer(&epqh->destroy_timer);
8065 +               epqh->destroy_timer.function = eqph_destroy_func;
8066 +               epqh->destroy_timer.data = (unsigned long)(epqh);
8067 +       #endif
8068 +
8069 +       #ifdef __DEBUG__
8070 +               IFX_DEBUGPL(DBG_HCD , "IFXUSB HCD EPQH Initialized\n");
8071 +               IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH  - epqh = %p\n", epqh);
8072 +               IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH  - Device Address = %d EP %d, %s\n",
8073 +                           _urb->dev->devnum,
8074 +                           usb_pipeendpoint(_urb->pipe),
8075 +                           usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
8076 +               IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH  - Speed = %s\n",
8077 +                           ({ char *speed; switch (_urb->dev->speed) {
8078 +                           case USB_SPEED_LOW: speed  = "low" ; break;
8079 +                           case USB_SPEED_FULL: speed = "full"; break;
8080 +                           case USB_SPEED_HIGH: speed = "high"; break;
8081 +                           default: speed = "?";       break;
8082 +                           }; speed;}));
8083 +               IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH  - Type = %s\n",
8084 +                       ({
8085 +                               char *type; switch (epqh->ep_type)
8086 +                               {
8087 +                                   case IFXUSB_EP_TYPE_ISOC: type = "isochronous"; break;
8088 +                                   case IFXUSB_EP_TYPE_INTR: type = "interrupt"  ; break;
8089 +                                   case IFXUSB_EP_TYPE_CTRL: type = "control"    ; break;
8090 +                                   case IFXUSB_EP_TYPE_BULK: type = "bulk"       ; break;
8091 +                                   default: type = "?";        break;
8092 +                               };
8093 +                               type;
8094 +                       }));
8095 +               if (epqh->ep_type == IFXUSB_EP_TYPE_INTR)
8096 +                       IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - interval = %d\n", epqh->interval);
8097 +       #endif
8098 +
8099 +       return epqh;
8100 +}
8101 +
8102 +
8103 +
8104 +
8105 +
8106 +
8107 +/*!
8108 +  \brief Free the EPQH.  EPQH should already be removed from a list.
8109 +  URBD list should already be empty if called from URB Dequeue.
8110 +
8111 +  \param[in] _epqh The EPQH to free.
8112 + */
8113 +void ifxhcd_epqh_free (ifxhcd_epqh_t *_epqh)
8114 +{
8115 +       unsigned long     flags;
8116 +
8117 +       if(_epqh->sysep) _epqh->sysep->hcpriv=NULL;
8118 +       _epqh->sysep=NULL;
8119 +
8120 +       if(!_epqh)
8121 +               return;
8122 +
8123 +       /* Free each QTD in the QTD list */
8124 +       local_irq_save (flags);
8125 +       if (!list_empty(&_epqh->urbd_list))
8126 +               IFX_WARN("%s() invalid epqh state\n",__func__);
8127 +
8128 +       #if defined(__UNALIGNED_BUFFER_ADJ__)
8129 +               if(_epqh->aligned_buf)
8130 +                       ifxusb_free_buf(_epqh->aligned_buf);
8131 +               if(_epqh->aligned_setup)
8132 +                       ifxusb_free_buf(_epqh->aligned_setup);
8133 +       #endif
8134 +
8135 +       if (!list_empty(&_epqh->epqh_list_entry))
8136 +               list_del_init(&_epqh->epqh_list_entry);
8137 +
8138 +       #ifdef __EPQD_DESTROY_TIMEOUT__
8139 +               del_timer(&_epqh->destroy_timer);
8140 +       #endif
8141 +       if(_epqh->dump_buf)
8142 +               ifxusb_free_buf(_epqh->dump_buf);
8143 +       _epqh->dump_buf=0;
8144 +
8145 +
8146 +       kfree (_epqh);
8147 +       local_irq_restore (flags);
8148 +}
8149 +
8150 +/*!
8151 +  \brief This function adds a EPQH to
8152 +
8153 +  \return 0 if successful, negative error code otherwise.
8154 + */
8155 +void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
8156 +{
8157 +       unsigned long flags;
8158 +       local_irq_save(flags);
8159 +       if (list_empty(&_epqh->epqh_list_entry))
8160 +       {
8161 +               #ifdef __EN_ISOC__
8162 +               if     (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
8163 +                       list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
8164 +               else
8165 +               #endif
8166 +               if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
8167 +                       list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
8168 +               else
8169 +                       list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
8170 +               _epqh->is_active=0;
8171 +       }
8172 +       else if(!_epqh->is_active)
8173 +       {
8174 +               #ifdef __EN_ISOC__
8175 +               if     (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
8176 +                       list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
8177 +               else
8178 +               #endif
8179 +               if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
8180 +                       list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
8181 +               else
8182 +                       list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
8183 +       }
8184 +       #ifdef __EPQD_DESTROY_TIMEOUT__
8185 +               del_timer(&_epqh->destroy_timer);
8186 +       #endif
8187 +       local_irq_restore(flags);
8188 +}
8189 +
8190 +void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
8191 +{
8192 +       unsigned long flags;
8193 +       local_irq_save(flags);
8194 +       if (list_empty(&_epqh->epqh_list_entry))
8195 +               IFX_WARN("%s() invalid epqh state\n",__func__);
8196 +       #ifdef __EN_ISOC__
8197 +               if     (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
8198 +                       list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_active);
8199 +               else
8200 +       #endif
8201 +       if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
8202 +               list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_active);
8203 +       else
8204 +               list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_active);
8205 +       _epqh->is_active=1;
8206 +       #ifdef __EPQD_DESTROY_TIMEOUT__
8207 +               del_timer(&_epqh->destroy_timer);
8208 +       #endif
8209 +       local_irq_restore(flags);
8210 +}
8211 +
8212 +void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
8213 +{
8214 +       unsigned long flags;
8215 +       local_irq_save(flags);
8216 +
8217 +       if (list_empty(&_epqh->urbd_list))
8218 +       {
8219 +               if(_epqh->ep_type == IFXUSB_EP_TYPE_ISOC || _epqh->ep_type == IFXUSB_EP_TYPE_INTR)
8220 +               {
8221 +                       list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_stdby);
8222 +               }
8223 +               else
8224 +               {
8225 +                       list_del_init(&_epqh->epqh_list_entry);
8226 +                       #ifdef __EPQD_DESTROY_TIMEOUT__
8227 +                               del_timer(&_epqh->destroy_timer);
8228 +                               _epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout);
8229 +                               add_timer(&_epqh->destroy_timer );
8230 +                       #endif
8231 +               }
8232 +       }
8233 +       else
8234 +       {
8235 +               #ifdef __EN_ISOC__
8236 +               if     (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
8237 +                       list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
8238 +               else
8239 +               #endif
8240 +               if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
8241 +                       list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
8242 +               else
8243 +                       list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
8244 +       }
8245 +       _epqh->is_active=0;
8246 +       local_irq_restore(flags);
8247 +}
8248 +
8249 +
8250 +void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh)
8251 +{
8252 +       unsigned long flags;
8253 +       if(_epqh->ep_type != IFXUSB_EP_TYPE_ISOC && _epqh->ep_type != IFXUSB_EP_TYPE_INTR)
8254 +               return;
8255 +
8256 +       local_irq_save(flags);
8257 +
8258 +       if (list_empty(&_epqh->epqh_list_entry))
8259 +               IFX_WARN("%s() invalid epqh state\n",__func__);
8260 +       if (!list_empty(&_epqh->urbd_list))
8261 +               IFX_WARN("%s() invalid epqh state(not empty)\n",__func__);
8262 +
8263 +       _epqh->is_active=0;
8264 +       list_del_init(&_epqh->epqh_list_entry);
8265 +       #ifdef __EPQD_DESTROY_TIMEOUT__
8266 +               del_timer(&_epqh->destroy_timer);
8267 +               _epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout);
8268 +               add_timer(&_epqh->destroy_timer );
8269 +       #endif
8270 +
8271 +       local_irq_restore(flags);
8272 +}
8273 +
8274 +
8275 +int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb)
8276 +{
8277 +       ifxhcd_urbd_t            *urbd;
8278 +       struct usb_host_endpoint *sysep;
8279 +       ifxhcd_epqh_t            *epqh;
8280 +       unsigned long             flags;
8281 +       /* == AVM/WK 20100714 retval correctly initialized ==*/
8282 +       int                       retval = -ENOMEM;
8283 +
8284 +       /*== AVM/BC 20100630 - Spinlock ==*/
8285 +       //local_irq_save(flags);
8286 +       SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
8287 +
8288 +//             urbd =  (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_KERNEL);
8289 +       urbd =  (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_ATOMIC);
8290 +       if (urbd != NULL) /* Initializes a QTD structure.*/
8291 +       {
8292 +               retval = 0;
8293 +               memset (urbd, 0, sizeof (ifxhcd_urbd_t));
8294 +
8295 +               sysep = ifxhcd_urb_to_endpoint(_urb);
8296 +               epqh = (ifxhcd_epqh_t *)sysep->hcpriv;
8297 +               if (epqh == NULL)
8298 +               {
8299 +                       epqh = ifxhcd_epqh_create (_ifxhcd, _urb);
8300 +                       if (epqh == NULL)
8301 +                       {
8302 +                               retval = -ENOSPC;
8303 +                               kfree(urbd);
8304 +                               //local_irq_restore (flags);
8305 +                               SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
8306 +                               return retval;
8307 +                       }
8308 +                       sysep->hcpriv = epqh;
8309 +               }
8310 +
8311 +               INIT_LIST_HEAD(&urbd->urbd_list_entry);
8312 +
8313 +               /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/
8314 +               retval = usb_hcd_link_urb_to_ep(ifxhcd_to_syshcd(_ifxhcd), _urb);
8315 +
8316 +               if (unlikely(retval)){
8317 +                       kfree(urbd);
8318 +                       kfree(epqh);
8319 +                       SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
8320 +                       return retval;
8321 +               }
8322 +
8323 +               list_add_tail(&urbd->urbd_list_entry, &epqh->urbd_list);
8324 +               urbd->urb = _urb;
8325 +               _urb->hcpriv = urbd;
8326 +
8327 +               urbd->epqh=epqh;
8328 +               urbd->is_in=usb_pipein(_urb->pipe) ? 1 : 0;;
8329 +
8330 +               urbd->xfer_len=_urb->transfer_buffer_length;
8331 +#define URB_NO_SETUP_DMA_MAP 0
8332 +
8333 +               if(urbd->xfer_len>0)
8334 +               {
8335 +                       if(_urb->transfer_flags && URB_NO_TRANSFER_DMA_MAP)
8336 +                               urbd->xfer_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->transfer_dma));
8337 +                       else
8338 +                               urbd->xfer_buff = (uint8_t *) _urb->transfer_buffer;
8339 +               }
8340 +               if(epqh->ep_type == IFXUSB_EP_TYPE_CTRL)
8341 +               {
8342 +                       if(_urb->transfer_flags && URB_NO_SETUP_DMA_MAP)
8343 +                               urbd->setup_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->setup_dma));
8344 +                       else
8345 +                               urbd->setup_buff = (uint8_t *) _urb->setup_packet;
8346 +               }
8347 +       }
8348 +       //local_irq_restore (flags);
8349 +       SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
8350 +       return retval;
8351 +}
8352 +
8353 --- /dev/null
8354 +++ b/drivers/usb/ifxhcd/ifxusb_cif.c
8355 @@ -0,0 +1,1458 @@
8356 +/*****************************************************************************
8357 + **   FILE NAME       : ifxusb_cif.c
8358 + **   PROJECT         : IFX USB sub-system V3
8359 + **   MODULES         : IFX USB sub-system Host and Device driver
8360 + **   SRC VERSION     : 1.0
8361 + **   DATE            : 1/Jan/2009
8362 + **   AUTHOR          : Chen, Howard
8363 + **   DESCRIPTION     : The Core Interface provides basic services for accessing and
8364 + **                     managing the IFX USB hardware. These services are used by both the
8365 + **                     Host Controller Driver and the Peripheral Controller Driver.
8366 + *****************************************************************************/
8367 +
8368 +/*!
8369 + \file ifxusb_cif.c
8370 + \ingroup IFXUSB_DRIVER_V3
8371 + \brief This file contains the interface to the IFX USB Core.
8372 +*/
8373 +
8374 +#include <linux/clk.h>
8375 +#include <linux/version.h>
8376 +#include "ifxusb_version.h"
8377 +
8378 +#include <asm/byteorder.h>
8379 +#include <asm/unaligned.h>
8380 +
8381 +
8382 +#include <linux/jiffies.h>
8383 +#include <linux/platform_device.h>
8384 +#include <linux/kernel.h>
8385 +#include <linux/ioport.h>
8386 +
8387 +#if defined(__UEIP__)
8388 +//     #include <asm/ifx/ifx_pmu.h>
8389 +//     #include <ifx_pmu.h>
8390 +#endif
8391 +
8392 +
8393 +#include "ifxusb_plat.h"
8394 +#include "ifxusb_regs.h"
8395 +#include "ifxusb_cif.h"
8396 +
8397 +
8398 +#ifdef __IS_DEVICE__
8399 +       #include "ifxpcd.h"
8400 +#endif
8401 +
8402 +#ifdef __IS_HOST__
8403 +       #include "ifxhcd.h"
8404 +#endif
8405 +
8406 +#include <linux/mm.h>
8407 +
8408 +#include <linux/gfp.h>
8409 +
8410 +#if defined(__UEIP__)
8411 +//     #include <asm/ifx/ifx_board.h>
8412 +       //#include <ifx_board.h>
8413 +#endif
8414 +
8415 +//#include <asm/ifx/ifx_gpio.h>
8416 +//#include <ifx_gpio.h>
8417 +#if defined(__UEIP__)
8418 +//     #include <asm/ifx/ifx_led.h>
8419 +       //#include <ifx_led.h>
8420 +#endif
8421 +
8422 +
8423 +
8424 +#if defined(__UEIP__)
8425 +       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
8426 +               #ifndef USB_CTRL_PMU_SETUP
8427 +                       #define USB_CTRL_PMU_SETUP(__x) USB0_CTRL_PMU_SETUP(__x)
8428 +               #endif
8429 +               #ifndef USB_PHY_PMU_SETUP
8430 +                       #define USB_PHY_PMU_SETUP(__x) USB0_PHY_PMU_SETUP(__x)
8431 +               #endif
8432 +       #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
8433 +#endif // defined(__UEIP__)
8434 +
8435 +/*!
8436 + \brief This function is called to allocate buffer of specified size.
8437 +        The allocated buffer is mapped into DMA accessable address.
8438 + \param size Size in BYTE to be allocated
8439 + \param clear 0: don't do clear after buffer allocated, other: do clear to zero
8440 + \return 0/NULL: Fail; uncached pointer of allocated buffer
8441 + */
8442 +void *ifxusb_alloc_buf(size_t size, int clear)
8443 +{
8444 +       uint32_t *cached,*uncached;
8445 +       uint32_t totalsize,page;
8446 +
8447 +       if(!size)
8448 +               return 0;
8449 +
8450 +       size=(size+3)&0xFFFFFFFC;
8451 +       totalsize=size + 12;
8452 +       page=get_order(totalsize);
8453 +
8454 +       cached = (void *) __get_free_pages(( GFP_ATOMIC | GFP_DMA), page);
8455 +
8456 +       if(!cached)
8457 +       {
8458 +               IFX_PRINT("%s Allocation Failed size:%d\n",__func__,size);
8459 +               return NULL;
8460 +       }
8461 +
8462 +       uncached = (uint32_t *)(KSEG1ADDR(cached));
8463 +       if(clear)
8464 +               memset(uncached, 0, totalsize);
8465 +
8466 +       *(uncached+0)=totalsize;
8467 +       *(uncached+1)=page;
8468 +       *(uncached+2)=(uint32_t)cached;
8469 +       return (void *)(uncached+3);
8470 +}
8471 +
8472 +
8473 +/*!
8474 + \brief This function is called to free allocated buffer.
8475 + \param vaddr the uncached pointer of the buffer
8476 + */
8477 +void ifxusb_free_buf(void *vaddr)
8478 +{
8479 +       uint32_t totalsize,page;
8480 +       uint32_t *cached,*uncached;
8481 +
8482 +       if(vaddr != NULL)
8483 +       {
8484 +               uncached=vaddr;
8485 +               uncached-=3;
8486 +               totalsize=*(uncached+0);
8487 +               page=*(uncached+1);
8488 +               cached=(uint32_t *)(*(uncached+2));
8489 +               if(totalsize && page==get_order(totalsize) && cached==(uint32_t *)(KSEG0ADDR(uncached)))
8490 +               {
8491 +                       free_pages((unsigned long)cached, page);
8492 +                       return;
8493 +               }
8494 +               // the memory is not allocated by ifxusb_alloc_buf. Allowed but must be careful.
8495 +               return;
8496 +       }
8497 +}
8498 +
8499 +
8500 +
8501 +/*!
8502 +   \brief This function is called to initialize the IFXUSB CSR data
8503 +        structures.  The register addresses in the device and host
8504 +        structures are initialized from the base address supplied by the
8505 +        caller.  The calling function must make the OS calls to get the
8506 +        base address of the IFXUSB controller registers.
8507 +
8508 +   \param _core_if        Pointer of core_if structure
8509 +   \param _irq            irq number
8510 +   \param _reg_base_addr  Base address of IFXUSB core registers
8511 +   \param _fifo_base_addr Fifo base address
8512 +   \param _fifo_dbg_addr  Fifo debug address
8513 +   \return     0: success;
8514 + */
8515 +int ifxusb_core_if_init(ifxusb_core_if_t *_core_if,
8516 +                        int               _irq,
8517 +                        uint32_t          _reg_base_addr,
8518 +                        uint32_t          _fifo_base_addr,
8519 +                        uint32_t          _fifo_dbg_addr)
8520 +{
8521 +       int retval = 0;
8522 +       uint32_t *reg_base  =NULL;
8523 +    uint32_t *fifo_base =NULL;
8524 +    uint32_t *fifo_dbg  =NULL;
8525 +
8526 +    int i;
8527 +
8528 +       IFX_DEBUGPL(DBG_CILV, "%s(%p,%d,0x%08X,0x%08X,0x%08X)\n", __func__,
8529 +                                                    _core_if,
8530 +                                                    _irq,
8531 +                                                    _reg_base_addr,
8532 +                                                    _fifo_base_addr,
8533 +                                                    _fifo_dbg_addr);
8534 +
8535 +       if( _core_if == NULL)
8536 +       {
8537 +               IFX_ERROR("%s() invalid _core_if\n", __func__);
8538 +               retval = -ENOMEM;
8539 +               goto fail;
8540 +       }
8541 +
8542 +       //memset(_core_if, 0, sizeof(ifxusb_core_if_t));
8543 +
8544 +       _core_if->irq=_irq;
8545 +
8546 +       reg_base  =ioremap_nocache(_reg_base_addr , IFXUSB_IOMEM_SIZE  );
8547 +       fifo_base =ioremap_nocache(_fifo_base_addr, IFXUSB_FIFOMEM_SIZE);
8548 +    fifo_dbg  =ioremap_nocache(_fifo_dbg_addr , IFXUSB_FIFODBG_SIZE);
8549 +       if( reg_base == NULL || fifo_base == NULL || fifo_dbg == NULL)
8550 +       {
8551 +               IFX_ERROR("%s() usb ioremap() failed\n", __func__);
8552 +               retval = -ENOMEM;
8553 +               goto fail;
8554 +       }
8555 +
8556 +       _core_if->core_global_regs = (ifxusb_core_global_regs_t *)reg_base;
8557 +
8558 +       /*
8559 +        * Attempt to ensure this device is really a IFXUSB Controller.
8560 +        * Read and verify the SNPSID register contents. The value should be
8561 +        * 0x45F42XXX
8562 +        */
8563 +       {
8564 +               int32_t snpsid;
8565 +               snpsid = ifxusb_rreg(&_core_if->core_global_regs->gsnpsid);
8566 +               if ((snpsid & 0xFFFFF000) != 0x4F542000)
8567 +               {
8568 +                       IFX_ERROR("%s() snpsid error(0x%08x) failed\n", __func__,snpsid);
8569 +                       retval = -EINVAL;
8570 +                       goto fail;
8571 +               }
8572 +               _core_if->snpsid=snpsid;
8573 +       }
8574 +
8575 +       #ifdef __IS_HOST__
8576 +               _core_if->host_global_regs = (ifxusb_host_global_regs_t *)
8577 +                   ((uint32_t)reg_base + IFXUSB_HOST_GLOBAL_REG_OFFSET);
8578 +               _core_if->hprt0 = (uint32_t*)((uint32_t)reg_base + IFXUSB_HOST_PORT_REGS_OFFSET);
8579 +
8580 +               for (i=0; i<MAX_EPS_CHANNELS; i++)
8581 +               {
8582 +                       _core_if->hc_regs[i] = (ifxusb_hc_regs_t *)
8583 +                           ((uint32_t)reg_base + IFXUSB_HOST_CHAN_REGS_OFFSET +
8584 +                           (i * IFXUSB_CHAN_REGS_OFFSET));
8585 +                       IFX_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
8586 +                           i, &_core_if->hc_regs[i]->hcchar);
8587 +               }
8588 +       #endif //__IS_HOST__
8589 +
8590 +       #ifdef __IS_DEVICE__
8591 +               _core_if->dev_global_regs =
8592 +                   (ifxusb_device_global_regs_t *)((uint32_t)reg_base + IFXUSB_DEV_GLOBAL_REG_OFFSET);
8593 +
8594 +               for (i=0; i<MAX_EPS_CHANNELS; i++)
8595 +               {
8596 +                       _core_if->in_ep_regs[i] = (ifxusb_dev_in_ep_regs_t *)
8597 +                           ((uint32_t)reg_base + IFXUSB_DEV_IN_EP_REG_OFFSET +
8598 +                           (i * IFXUSB_EP_REG_OFFSET));
8599 +                       _core_if->out_ep_regs[i] = (ifxusb_dev_out_ep_regs_t *)
8600 +                           ((uint32_t)reg_base + IFXUSB_DEV_OUT_EP_REG_OFFSET +
8601 +                           (i * IFXUSB_EP_REG_OFFSET));
8602 +                       IFX_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p/%p %p/0x%08X/0x%08X\n",
8603 +                           i, &_core_if->in_ep_regs[i]->diepctl, _core_if->in_ep_regs[i],
8604 +                           reg_base,IFXUSB_DEV_IN_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET)
8605 +                           );
8606 +                       IFX_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p/%p %p/0x%08X/0x%08X\n",
8607 +                           i, &_core_if->out_ep_regs[i]->doepctl, _core_if->out_ep_regs[i],
8608 +                           reg_base,IFXUSB_DEV_OUT_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET)
8609 +                           );
8610 +               }
8611 +       #endif //__IS_DEVICE__
8612 +
8613 +       /* Setting the FIFO and other Address. */
8614 +       for (i=0; i<MAX_EPS_CHANNELS; i++)
8615 +       {
8616 +               _core_if->data_fifo[i] = fifo_base + (i * IFXUSB_DATA_FIFO_SIZE);
8617 +               IFX_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
8618 +                   i, (unsigned)_core_if->data_fifo[i]);
8619 +       }
8620 +
8621 +       _core_if->data_fifo_dbg = fifo_dbg;
8622 +       _core_if->pcgcctl = (uint32_t*)(((uint32_t)reg_base) + IFXUSB_PCGCCTL_OFFSET);
8623 +
8624 +       /*
8625 +        * Store the contents of the hardware configuration registers here for
8626 +        * easy access later.
8627 +        */
8628 +       _core_if->hwcfg1.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg1);
8629 +       _core_if->hwcfg2.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg2);
8630 +       _core_if->hwcfg3.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg3);
8631 +       _core_if->hwcfg4.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg4);
8632 +
8633 +       IFX_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",_core_if->hwcfg1.d32);
8634 +       IFX_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",_core_if->hwcfg2.d32);
8635 +       IFX_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",_core_if->hwcfg3.d32);
8636 +       IFX_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",_core_if->hwcfg4.d32);
8637 +
8638 +
8639 +       #ifdef __DED_FIFO__
8640 +               IFX_PRINT("Waiting for PHY Clock Lock!\n");
8641 +               while(!( ifxusb_rreg(&_core_if->core_global_regs->grxfsiz) & (1<<9)))
8642 +               {
8643 +               }
8644 +               IFX_PRINT("PHY Clock Locked!\n");
8645 +               //ifxusb_clean_spram(_core_if,128*1024/4);
8646 +       #endif
8647 +
8648 +       /* Create new workqueue and init works */
8649 +#if 0
8650 +       _core_if->wq_usb = create_singlethread_workqueue(_core_if->core_name);
8651 +
8652 +       if(_core_if->wq_usb == 0)
8653 +       {
8654 +               IFX_DEBUGPL(DBG_CIL, "Creation of wq_usb failed\n");
8655 +               retval = -EINVAL;
8656 +               goto fail;
8657 +       }
8658 +
8659 +       #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
8660 +               INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if);
8661 +               INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if);
8662 +       #else
8663 +               INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change);
8664 +               INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected);
8665 +       #endif
8666 +#endif
8667 +       return 0;
8668 +
8669 +fail:
8670 +       if( reg_base  != NULL) iounmap(reg_base );
8671 +       if( fifo_base != NULL) iounmap(fifo_base);
8672 +       if( fifo_dbg  != NULL) iounmap(fifo_dbg );
8673 +       return retval;
8674 +}
8675 +
8676 +/*!
8677 + \brief This function free the mapped address in the IFXUSB CSR data structures.
8678 + \param _core_if Pointer of core_if structure
8679 + */
8680 +void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if)
8681 +{
8682 +       /* Disable all interrupts */
8683 +       if( _core_if->core_global_regs  != NULL)
8684 +       {
8685 +               ifxusb_mreg( &_core_if->core_global_regs->gahbcfg, 1, 0);
8686 +               ifxusb_wreg( &_core_if->core_global_regs->gintmsk, 0);
8687 +       }
8688 +
8689 +       if( _core_if->core_global_regs  != NULL) iounmap(_core_if->core_global_regs );
8690 +       if( _core_if->data_fifo[0]      != NULL) iounmap(_core_if->data_fifo[0]     );
8691 +       if( _core_if->data_fifo_dbg     != NULL) iounmap(_core_if->data_fifo_dbg    );
8692 +
8693 +#if 0
8694 +       if (_core_if->wq_usb)
8695 +               destroy_workqueue(_core_if->wq_usb);
8696 +#endif
8697 +       memset(_core_if, 0, sizeof(ifxusb_core_if_t));
8698 +}
8699 +
8700 +
8701 +
8702 +
8703 +/*!
8704 + \brief This function enbles the controller's Global Interrupt in the AHB Config register.
8705 + \param _core_if Pointer of core_if structure
8706 + */
8707 +void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if )
8708 +{
8709 +       gahbcfg_data_t ahbcfg ={ .d32 = 0};
8710 +       ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
8711 +       ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
8712 +}
8713 +
8714 +/*!
8715 + \brief This function disables the controller's Global Interrupt in the AHB Config register.
8716 + \param _core_if Pointer of core_if structure
8717 + */
8718 +void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if )
8719 +{
8720 +       gahbcfg_data_t ahbcfg ={ .d32 = 0};
8721 +       ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
8722 +       ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
8723 +}
8724 +
8725 +
8726 +
8727 +
8728 +/*!
8729 + \brief Flush Tx and Rx FIFO.
8730 + \param _core_if Pointer of core_if structure
8731 + */
8732 +void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if )
8733 +{
8734 +       ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
8735 +       volatile grstctl_t greset ={ .d32 = 0};
8736 +       int count = 0;
8737 +
8738 +       IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
8739 +       greset.b.rxfflsh = 1;
8740 +       greset.b.txfflsh = 1;
8741 +       greset.b.txfnum = 0x10;
8742 +       greset.b.intknqflsh=1;
8743 +       greset.b.hstfrm=1;
8744 +       ifxusb_wreg( &global_regs->grstctl, greset.d32 );
8745 +
8746 +       do
8747 +       {
8748 +               greset.d32 = ifxusb_rreg( &global_regs->grstctl);
8749 +               if (++count > 10000)
8750 +               {
8751 +                       IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32);
8752 +                       break;
8753 +               }
8754 +       } while (greset.b.rxfflsh == 1 || greset.b.txfflsh == 1);
8755 +       /* Wait for 3 PHY Clocks*/
8756 +       UDELAY(1);
8757 +}
8758 +
8759 +/*!
8760 + \brief Flush a Tx FIFO.
8761 + \param _core_if Pointer of core_if structure
8762 + \param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO )
8763 + */
8764 +void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num )
8765 +{
8766 +       ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
8767 +       volatile grstctl_t greset ={ .d32 = 0};
8768 +       int count = 0;
8769 +
8770 +       IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num);
8771 +
8772 +       greset.b.intknqflsh=1;
8773 +       greset.b.txfflsh = 1;
8774 +       greset.b.txfnum = _num;
8775 +       ifxusb_wreg( &global_regs->grstctl, greset.d32 );
8776 +
8777 +       do
8778 +       {
8779 +               greset.d32 = ifxusb_rreg( &global_regs->grstctl);
8780 +               if (++count > 10000&&(_num==0 ||_num==0x10))
8781 +               {
8782 +                       IFX_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
8783 +                           __func__, greset.d32,
8784 +                       ifxusb_rreg( &global_regs->gnptxsts));
8785 +                       break;
8786 +               }
8787 +       } while (greset.b.txfflsh == 1);
8788 +       /* Wait for 3 PHY Clocks*/
8789 +       UDELAY(1);
8790 +}
8791 +
8792 +
8793 +/*!
8794 + \brief Flush Rx FIFO.
8795 + \param _core_if Pointer of core_if structure
8796 + */
8797 +void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if )
8798 +{
8799 +       ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
8800 +       volatile grstctl_t greset ={ .d32 = 0};
8801 +       int count = 0;
8802 +
8803 +       IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
8804 +       greset.b.rxfflsh = 1;
8805 +       ifxusb_wreg( &global_regs->grstctl, greset.d32 );
8806 +
8807 +       do
8808 +       {
8809 +               greset.d32 = ifxusb_rreg( &global_regs->grstctl);
8810 +               if (++count > 10000)
8811 +               {
8812 +                       IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32);
8813 +                       break;
8814 +               }
8815 +       } while (greset.b.rxfflsh == 1);
8816 +       /* Wait for 3 PHY Clocks*/
8817 +       UDELAY(1);
8818 +}
8819 +
8820 +
8821 +#define SOFT_RESET_DELAY 100
8822 +
8823 +/*!
8824 + \brief Do a soft reset of the core.  Be careful with this because it
8825 +        resets all the internal state machines of the core.
8826 + \param _core_if Pointer of core_if structure
8827 + */
8828 +int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if)
8829 +{
8830 +       ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
8831 +       volatile grstctl_t greset ={ .d32 = 0};
8832 +       int count = 0;
8833 +
8834 +       IFX_DEBUGPL(DBG_CILV, "%s\n", __func__);
8835 +       /* Wait for AHB master IDLE state. */
8836 +       do
8837 +       {
8838 +               UDELAY(10);
8839 +               greset.d32 = ifxusb_rreg( &global_regs->grstctl);
8840 +               if (++count > 100000)
8841 +               {
8842 +                       IFX_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__,
8843 +                       greset.d32, greset.b.ahbidle);
8844 +                       break;
8845 +               }
8846 +       } while (greset.b.ahbidle == 0);
8847 +
8848 +       UDELAY(1);
8849 +
8850 +       /* Core Soft Reset */
8851 +       count = 0;
8852 +       greset.b.csftrst = 1;
8853 +       ifxusb_wreg( &global_regs->grstctl, greset.d32 );
8854 +
8855 +       #ifdef SOFT_RESET_DELAY
8856 +               MDELAY(SOFT_RESET_DELAY);
8857 +       #endif
8858 +
8859 +       do
8860 +       {
8861 +               UDELAY(10);
8862 +               greset.d32 = ifxusb_rreg( &global_regs->grstctl);
8863 +               if (++count > 100000)
8864 +               {
8865 +                       IFX_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, greset.d32);
8866 +                       return -1;
8867 +               }
8868 +       } while (greset.b.csftrst == 1);
8869 +
8870 +       #ifdef SOFT_RESET_DELAY
8871 +               MDELAY(SOFT_RESET_DELAY);
8872 +       #endif
8873 +
8874 +
8875 +       #if defined(__IS_VR9__)
8876 +               if(_core_if->core_no==0)
8877 +               {
8878 +                       set_bit (4, VR9_RCU_USBRESET2);
8879 +                       MDELAY(50);
8880 +                       clear_bit (4, VR9_RCU_USBRESET2);
8881 +               }
8882 +               else
8883 +               {
8884 +                       set_bit (5, VR9_RCU_USBRESET2);
8885 +                       MDELAY(50);
8886 +                       clear_bit (5, VR9_RCU_USBRESET2);
8887 +               }
8888 +               MDELAY(50);
8889 +       #endif //defined(__IS_VR9__)
8890 +
8891 +       IFX_PRINT("USB core #%d soft-reset\n",_core_if->core_no);
8892 +
8893 +       return 0;
8894 +}
8895 +
8896 +/*!
8897 + \brief Turn on the USB Core Power
8898 + \param _core_if Pointer of core_if structure
8899 +*/
8900 +void ifxusb_power_on (ifxusb_core_if_t *_core_if)
8901 +{
8902 +       struct clk *clk0 = clk_get_sys("usb0", NULL);
8903 +       struct clk *clk1 = clk_get_sys("usb1", NULL);
8904 +       // set clock gating
8905 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
8906 +       #if defined(__UEIP__)
8907 +
8908 +               #if defined(__IS_TWINPASS) || defined(__IS_DANUBE__)
8909 +                       set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR);
8910 +                       set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR);
8911 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
8912 +               #if defined(__IS_AMAZON_SE__)
8913 +               //      clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
8914 +                       clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
8915 +               #endif //defined(__IS_AMAZON_SE__)
8916 +               #if defined(__IS_AR9__)
8917 +                       set_bit (0, (volatile unsigned long *)AR9_CGU_IFCCR);
8918 +                       set_bit (1, (volatile unsigned long *)AR9_CGU_IFCCR);
8919 +               #endif //defined(__IS_AR9__)
8920 +               #if defined(__IS_VR9__)
8921 +//                     set_bit (0, (volatile unsigned long *)VR9_CGU_IFCCR);
8922 +//                     set_bit (1, (volatile unsigned long *)VR9_CGU_IFCCR);
8923 +               #endif //defined(__IS_VR9__)
8924 +
8925 +               MDELAY(50);
8926 +
8927 +               // set power
8928 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
8929 +                       USB_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
8930 +                       //#if defined(__IS_TWINPASS__)
8931 +                       //      ifxusb_enable_afe_oc();
8932 +                       //#endif
8933 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
8934 +               #if defined(__IS_AR9__) || defined(__IS_VR9__)
8935 +                       if(_core_if->core_no==0)
8936 +                               clk_enable(clk0);
8937 +//                             USB0_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
8938 +                       else
8939 +                               clk_enable(clk1);
8940 +//                             USB1_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
8941 +               #endif //defined(__IS_AR9__) || defined(__IS_VR9__)
8942 +
8943 +               if(_core_if->core_global_regs)
8944 +               {
8945 +                       // PHY configurations.
8946 +                       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
8947 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
8948 +                       #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
8949 +                       #if defined(__IS_AMAZON_SE__)
8950 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
8951 +                       #endif //defined(__IS_AMAZON_SE__)
8952 +                       #if defined(__IS_AR9__)
8953 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
8954 +                       #endif //defined(__IS_AR9__)
8955 +                       #if defined(__IS_VR9__)
8956 +                               //ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
8957 +                       #endif //defined(__IS_VR9__)
8958 +               }
8959 +       #else //defined(__UEIP__)
8960 +               #if defined(__IS_TWINPASS) || defined(__IS_DANUBE__)
8961 +                       set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR);
8962 +                       set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR);
8963 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
8964 +               #if defined(__IS_AMAZON_SE__)
8965 +               //      clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
8966 +                       clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
8967 +               #endif //defined(__IS_AMAZON_SE__)
8968 +               #if defined(__IS_AR9__)
8969 +                       set_bit (0, (volatile unsigned long *)AMAZON_S_CGU_IFCCR);
8970 +                       set_bit (1, (volatile unsigned long *)AMAZON_S_CGU_IFCCR);
8971 +               #endif //defined(__IS_AR9__)
8972 +
8973 +               MDELAY(50);
8974 +
8975 +               // set power
8976 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
8977 +                       clear_bit (6,  (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB
8978 +                       clear_bit (9,  (volatile unsigned long *)DANUBE_PMU_PWDCR);//DSL
8979 +                       clear_bit (15, (volatile unsigned long *)DANUBE_PMU_PWDCR);//AHB
8980 +                       #if defined(__IS_TWINPASS__)
8981 +                               ifxusb_enable_afe_oc();
8982 +                       #endif
8983 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
8984 +               #if defined(__IS_AMAZON_SE__)
8985 +                       clear_bit (6,  (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
8986 +                       clear_bit (9,  (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
8987 +                       clear_bit (15, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
8988 +               #endif //defined(__IS_AMAZON_SE__)
8989 +               #if defined(__IS_AR9__)
8990 +                       if(_core_if->core_no==0)
8991 +                               clear_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
8992 +                       else
8993 +                               clear_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
8994 +                       clear_bit (9, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//DSL
8995 +                       clear_bit (15, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//AHB
8996 +               #endif //defined(__IS_AR9__)
8997 +
8998 +               if(_core_if->core_global_regs)
8999 +               {
9000 +                       // PHY configurations.
9001 +                       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9002 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9003 +                       #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9004 +                       #if defined(__IS_AMAZON_SE__)
9005 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9006 +                       #endif //defined(__IS_AMAZON_SE__)
9007 +                       #if defined(__IS_AR9__)
9008 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9009 +                       #endif //defined(__IS_AR9__)
9010 +               }
9011 +
9012 +       #endif //defined(__UEIP__)
9013 +}
9014 +
9015 +/*!
9016 + \brief Turn off the USB Core Power
9017 + \param _core_if Pointer of core_if structure
9018 +*/
9019 +void ifxusb_power_off (ifxusb_core_if_t *_core_if)
9020 +{
9021 +       struct clk *clk0 = clk_get_sys("usb0", NULL);
9022 +       struct clk *clk1 = clk_get_sys("usb1", NULL);
9023 +       ifxusb_phy_power_off (_core_if);
9024 +
9025 +       // set power
9026 +       #if defined(__UEIP__)
9027 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
9028 +                       USB_CTRL_PMU_SETUP(IFX_PMU_DISABLE);
9029 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
9030 +               #if defined(__IS_AR9__) || defined(__IS_VR9__)
9031 +                       if(_core_if->core_no==0)
9032 +                               clk_disable(clk0);
9033 +                               //USB0_CTRL_PMU_SETUP(IFX_PMU_DISABLE);
9034 +                       else
9035 +                               clk_disable(clk1);
9036 +                               //USB1_CTRL_PMU_SETUP(IFX_PMU_DISABLE);
9037 +               #endif //defined(__IS_AR9__) || defined(__IS_VR9__)
9038 +       #else //defined(__UEIP__)
9039 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9040 +                       set_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB
9041 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9042 +               #if defined(__IS_AMAZON_SE__)
9043 +                       set_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//USB
9044 +               #endif //defined(__IS_AMAZON_SE__)
9045 +               #if defined(__IS_AR9__)
9046 +                       if(_core_if->core_no==0)
9047 +                               set_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
9048 +                       else
9049 +                               set_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
9050 +               #endif //defined(__IS_AR9__)
9051 +       #endif //defined(__UEIP__)
9052 +}
9053 +
9054 +/*!
9055 + \brief Turn on the USB PHY Power
9056 + \param _core_if Pointer of core_if structure
9057 +*/
9058 +void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if)
9059 +{
9060 +       struct clk *clk0 = clk_get_sys("usb0", NULL);
9061 +       struct clk *clk1 = clk_get_sys("usb1", NULL);
9062 +       #if defined(__UEIP__)
9063 +               if(_core_if->core_global_regs)
9064 +               {
9065 +                       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9066 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9067 +                       #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9068 +                       #if defined(__IS_AMAZON_SE__)
9069 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9070 +                       #endif //defined(__IS_AMAZON_SE__)
9071 +                       #if defined(__IS_AR9__)
9072 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9073 +                       #endif //defined(__IS_AR9__)
9074 +                       #if defined(__IS_VR9_S__)
9075 +                               if(_core_if->core_no==0)
9076 +                                       set_bit (0, VR9_RCU_USB_ANA_CFG1A);
9077 +                               else
9078 +                                       set_bit (0, VR9_RCU_USB_ANA_CFG1B);
9079 +                       #endif //defined(__IS_VR9__)
9080 +               }
9081 +
9082 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
9083 +                       USB_PHY_PMU_SETUP(IFX_PMU_ENABLE);
9084 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
9085 +               #if defined(__IS_AR9__) || defined(__IS_VR9__)
9086 +                       if(_core_if->core_no==0)
9087 +                               clk_enable(clk0);
9088 +                               //USB0_PHY_PMU_SETUP(IFX_PMU_ENABLE);
9089 +                       else
9090 +                               clk_enable(clk1);
9091 +                               //USB1_PHY_PMU_SETUP(IFX_PMU_ENABLE);
9092 +               #endif //defined(__IS_AR9__) || defined(__IS_VR9__)
9093 +
9094 +               // PHY configurations.
9095 +               if(_core_if->core_global_regs)
9096 +               {
9097 +                       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9098 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9099 +                       #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9100 +                       #if defined(__IS_AMAZON_SE__)
9101 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9102 +                       #endif //defined(__IS_AMAZON_SE__)
9103 +                       #if defined(__IS_AR9__)
9104 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9105 +                       #endif //defined(__IS_AR9__)
9106 +                       #if defined(__IS_VR9_S__)
9107 +                               if(_core_if->core_no==0)
9108 +                                       set_bit (0, VR9_RCU_USB_ANA_CFG1A);
9109 +                               else
9110 +                                       set_bit (0, VR9_RCU_USB_ANA_CFG1B);
9111 +                       #endif //defined(__IS_VR9__)
9112 +               }
9113 +       #else //defined(__UEIP__)
9114 +               // PHY configurations.
9115 +               if(_core_if->core_global_regs)
9116 +               {
9117 +                       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9118 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9119 +                       #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9120 +                       #if defined(__IS_AMAZON_SE__)
9121 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9122 +                       #endif //defined(__IS_AMAZON_SE__)
9123 +                       #if defined(__IS_AR9__)
9124 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9125 +                       #endif //defined(__IS_AR9__)
9126 +               }
9127 +
9128 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9129 +                       clear_bit (0,  (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY
9130 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9131 +               #if defined(__IS_AMAZON_SE__)
9132 +                       clear_bit (0,  (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
9133 +               #endif //defined(__IS_AMAZON_SE__)
9134 +               #if defined(__IS_AR9__)
9135 +                       if(_core_if->core_no==0)
9136 +                               clear_bit (0,  (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
9137 +                       else
9138 +                               clear_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
9139 +               #endif //defined(__IS_AR9__)
9140 +
9141 +               // PHY configurations.
9142 +               if(_core_if->core_global_regs)
9143 +               {
9144 +                       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9145 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9146 +                       #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9147 +                       #if defined(__IS_AMAZON_SE__)
9148 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9149 +                       #endif //defined(__IS_AMAZON_SE__)
9150 +                       #if defined(__IS_AR9__)
9151 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9152 +                       #endif //defined(__IS_AR9__)
9153 +               }
9154 +       #endif //defined(__UEIP__)
9155 +}
9156 +
9157 +
9158 +/*!
9159 + \brief Turn off the USB PHY Power
9160 + \param _core_if Pointer of core_if structure
9161 +*/
9162 +void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if)
9163 +{
9164 +       struct clk *clk0 = clk_get_sys("usb0", NULL);
9165 +       struct clk *clk1 = clk_get_sys("usb1", NULL);
9166 +       #if defined(__UEIP__)
9167 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
9168 +                       USB_PHY_PMU_SETUP(IFX_PMU_DISABLE);
9169 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
9170 +               #if defined(__IS_AR9__) || defined(__IS_VR9__)
9171 +                       if(_core_if->core_no==0)
9172 +                               clk_disable(clk0);
9173 +                               //USB0_PHY_PMU_SETUP(IFX_PMU_DISABLE);
9174 +                       else
9175 +                               clk_disable(clk1);
9176 +                               //USB1_PHY_PMU_SETUP(IFX_PMU_DISABLE);
9177 +               #endif // defined(__IS_AR9__) || defined(__IS_VR9__)
9178 +       #else //defined(__UEIP__)
9179 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9180 +                       set_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY
9181 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9182 +               #if defined(__IS_AMAZON_SE__)
9183 +                       set_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//PHY
9184 +               #endif //defined(__IS_AMAZON_SE__)
9185 +               #if defined(__IS_AR9__)
9186 +                       if(_core_if->core_no==0)
9187 +                               set_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
9188 +                       else
9189 +                               set_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
9190 +               #endif //defined(__IS_AR9__)
9191 +       #endif //defined(__UEIP__)
9192 +}
9193 +
9194 +
9195 +/*!
9196 + \brief Reset on the USB Core RCU
9197 + \param _core_if Pointer of core_if structure
9198 + */
9199 +#if defined(__IS_VR9__)
9200 +       int already_hard_reset=0;
9201 +#endif
9202 +void ifxusb_hard_reset(ifxusb_core_if_t *_core_if)
9203 +{
9204 +       #if defined(__UEIP__)
9205 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9206 +                       #if defined (__IS_HOST__)
9207 +                               clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
9208 +                       #elif defined (__IS_DEVICE__)
9209 +                               set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
9210 +                       #endif
9211 +               #endif //defined(__IS_AMAZON_SE__)
9212 +
9213 +               #if defined(__IS_AMAZON_SE__)
9214 +                       #if defined (__IS_HOST__)
9215 +                               clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
9216 +                       #elif defined (__IS_DEVICE__)
9217 +                               set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
9218 +                       #endif
9219 +               #endif //defined(__IS_AMAZON_SE__)
9220 +
9221 +               #if defined(__IS_AR9__)
9222 +                       if(_core_if->core_no==0)
9223 +                       {
9224 +                               #if defined (__IS_HOST__)
9225 +                                       clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
9226 +                               #elif defined (__IS_DEVICE__)
9227 +                                       set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
9228 +                               #endif
9229 +                       }
9230 +                       else
9231 +                       {
9232 +                               #if defined (__IS_HOST__)
9233 +                                       clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
9234 +                               #elif defined (__IS_DEVICE__)
9235 +                                       set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
9236 +                               #endif
9237 +                       }
9238 +               #endif //defined(__IS_AR9__)
9239 +
9240 +               #if defined(__IS_VR9__)
9241 +                       if(_core_if->core_no==0)
9242 +                       {
9243 +                               #if defined (__IS_HOST__)
9244 +                                       clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
9245 +                               #elif defined (__IS_DEVICE__)
9246 +                                       set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
9247 +                               #endif
9248 +                       }
9249 +                       else
9250 +                       {
9251 +                               #if defined (__IS_HOST__)
9252 +                                       clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
9253 +                               #elif defined (__IS_DEVICE__)
9254 +                                       set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
9255 +                               #endif
9256 +                       }
9257 +               #endif //defined(__IS_VR9__)
9258 +
9259 +
9260 +               // set the HC's byte-order to big-endian
9261 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9262 +                       set_bit   (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
9263 +                       clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
9264 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9265 +               #if defined(__IS_AMAZON_SE__)
9266 +                       set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
9267 +                       clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
9268 +               #endif //defined(__IS_AMAZON_SE__)
9269 +               #if defined(__IS_AR9__)
9270 +                       if(_core_if->core_no==0)
9271 +                       {
9272 +                               set_bit   (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
9273 +                               clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
9274 +                       }
9275 +                       else
9276 +                       {
9277 +                               set_bit   (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
9278 +                               clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
9279 +                       }
9280 +               #endif //defined(__IS_AR9__)
9281 +               #if defined(__IS_VR9__)
9282 +                       if(_core_if->core_no==0)
9283 +                       {
9284 +                               set_bit   (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
9285 +                               clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
9286 +                       }
9287 +                       else
9288 +                       {
9289 +                               set_bit   (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
9290 +                               clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
9291 +                       }
9292 +               #endif //defined(__IS_VR9__)
9293 +
9294 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9295 +                   set_bit (4, DANUBE_RCU_RESET);
9296 +                       MDELAY(500);
9297 +                   clear_bit (4, DANUBE_RCU_RESET);
9298 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9299 +
9300 +               #if defined(__IS_AMAZON_SE__)
9301 +                   set_bit (4, AMAZON_SE_RCU_RESET);
9302 +                       MDELAY(500);
9303 +                   clear_bit (4, AMAZON_SE_RCU_RESET);
9304 +                       MDELAY(500);
9305 +               #endif //defined(__IS_AMAZON_SE__)
9306 +
9307 +               #if defined(__IS_AR9__)
9308 +                       if(_core_if->core_no==0)
9309 +                       {
9310 +                               set_bit (4, AR9_RCU_USBRESET);
9311 +                               MDELAY(500);
9312 +                               clear_bit (4, AR9_RCU_USBRESET);
9313 +                       }
9314 +                       else
9315 +                       {
9316 +                               set_bit (28, AR9_RCU_USBRESET);
9317 +                               MDELAY(500);
9318 +                               clear_bit (28, AR9_RCU_USBRESET);
9319 +                       }
9320 +                       MDELAY(500);
9321 +               #endif //defined(__IS_AR9__)
9322 +               #if defined(__IS_VR9__)
9323 +                       if(!already_hard_reset)
9324 +                       {
9325 +                               set_bit (4, VR9_RCU_USBRESET);
9326 +                               MDELAY(500);
9327 +                               clear_bit (4, VR9_RCU_USBRESET);
9328 +                               MDELAY(500);
9329 +                               already_hard_reset=1;
9330 +                       }
9331 +               #endif //defined(__IS_VR9__)
9332 +
9333 +               #if defined(__IS_TWINPASS__)
9334 +                       ifxusb_enable_afe_oc();
9335 +               #endif
9336 +
9337 +               if(_core_if->core_global_regs)
9338 +               {
9339 +                       // PHY configurations.
9340 +                       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9341 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9342 +                       #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9343 +                       #if defined(__IS_AMAZON_SE__)
9344 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9345 +                       #endif //defined(__IS_AMAZON_SE__)
9346 +                       #if defined(__IS_AR9__)
9347 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9348 +                       #endif //defined(__IS_AR9__)
9349 +                       #if defined(__IS_VR9__)
9350 +                       //      ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9351 +                       #endif //defined(__IS_VR9__)
9352 +               }
9353 +       #else //defined(__UEIP__)
9354 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9355 +                       #if defined (__IS_HOST__)
9356 +                               clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
9357 +                       #elif defined (__IS_DEVICE__)
9358 +                               set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
9359 +                       #endif
9360 +               #endif //defined(__IS_AMAZON_SE__)
9361 +
9362 +               #if defined(__IS_AMAZON_SE__)
9363 +                       #if defined (__IS_HOST__)
9364 +                               clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
9365 +                       #elif defined (__IS_DEVICE__)
9366 +                               set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
9367 +                       #endif
9368 +               #endif //defined(__IS_AMAZON_SE__)
9369 +
9370 +               #if defined(__IS_AR9__)
9371 +                       if(_core_if->core_no==0)
9372 +                       {
9373 +                               #if defined (__IS_HOST__)
9374 +                                       clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
9375 +                               #elif defined (__IS_DEVICE__)
9376 +                                       set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
9377 +                               #endif
9378 +                       }
9379 +                       else
9380 +                       {
9381 +                               #if defined (__IS_HOST__)
9382 +                                       clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
9383 +                               #elif defined (__IS_DEVICE__)
9384 +                                       set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
9385 +                               #endif
9386 +                       }
9387 +               #endif //defined(__IS_AR9__)
9388 +
9389 +               // set the HC's byte-order to big-endian
9390 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9391 +                       set_bit   (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
9392 +                       clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
9393 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9394 +               #if defined(__IS_AMAZON_SE__)
9395 +                       set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
9396 +                       clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
9397 +               #endif //defined(__IS_AMAZON_SE__)
9398 +               #if defined(__IS_AR9__)
9399 +                       if(_core_if->core_no==0)
9400 +                       {
9401 +                               set_bit   (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
9402 +                               clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
9403 +                       }
9404 +                       else
9405 +                       {
9406 +                               set_bit   (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
9407 +                               clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
9408 +                       }
9409 +               #endif //defined(__IS_AR9__)
9410 +
9411 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9412 +                   set_bit (4, DANUBE_RCU_RESET);
9413 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9414 +               #if defined(__IS_AMAZON_SE__)
9415 +                   set_bit (4, AMAZON_SE_RCU_RESET);
9416 +               #endif //defined(__IS_AMAZON_SE__)
9417 +               #if defined(__IS_AR9__)
9418 +                       if(_core_if->core_no==0)
9419 +                       {
9420 +                               set_bit (4, AMAZON_S_RCU_USBRESET);
9421 +                       }
9422 +                       else
9423 +                       {
9424 +                               set_bit (28, AMAZON_S_RCU_USBRESET);
9425 +                       }
9426 +               #endif //defined(__IS_AR9__)
9427 +
9428 +               MDELAY(500);
9429 +
9430 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9431 +                   clear_bit (4, DANUBE_RCU_RESET);
9432 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9433 +               #if defined(__IS_AMAZON_SE__)
9434 +                   clear_bit (4, AMAZON_SE_RCU_RESET);
9435 +               #endif //defined(__IS_AMAZON_SE__)
9436 +               #if defined(__IS_AR9__)
9437 +                       if(_core_if->core_no==0)
9438 +                       {
9439 +                               clear_bit (4, AMAZON_S_RCU_USBRESET);
9440 +                       }
9441 +                       else
9442 +                       {
9443 +                               clear_bit (28, AMAZON_S_RCU_USBRESET);
9444 +                       }
9445 +               #endif //defined(__IS_AR9__)
9446 +
9447 +               MDELAY(500);
9448 +
9449 +               #if defined(__IS_TWINPASS__)
9450 +                       ifxusb_enable_afe_oc();
9451 +               #endif
9452 +
9453 +               if(_core_if->core_global_regs)
9454 +               {
9455 +                       // PHY configurations.
9456 +                       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9457 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9458 +                       #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
9459 +                       #if defined(__IS_AMAZON_SE__)
9460 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9461 +                       #endif //defined(__IS_AMAZON_SE__)
9462 +                       #if defined(__IS_AR9__)
9463 +                               ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
9464 +                       #endif //defined(__IS_AR9__)
9465 +               }
9466 +       #endif //defined(__UEIP__)
9467 +}
9468 +
9469 +#if defined(__GADGET_LED__) || defined(__HOST_LED__)
9470 +       #if defined(__UEIP__)
9471 +               static void *g_usb_led_trigger  = NULL;
9472 +       #endif
9473 +
9474 +       void ifxusb_led_init(ifxusb_core_if_t *_core_if)
9475 +       {
9476 +               #if defined(__UEIP__)
9477 +                       if ( !g_usb_led_trigger )
9478 +                       {
9479 +                               ifx_led_trigger_register("usb_link", &g_usb_led_trigger);
9480 +                               if ( g_usb_led_trigger != NULL )
9481 +                               {
9482 +                                       struct ifx_led_trigger_attrib attrib = {0};
9483 +                                       attrib.delay_on     = 250;
9484 +                                       attrib.delay_off    = 250;
9485 +                                       attrib.timeout      = 2000;
9486 +                                       attrib.def_value    = 1;
9487 +                                       attrib.flags        = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
9488 +                                       IFX_DEBUGP("Reg USB LED!!\n");
9489 +                                       ifx_led_trigger_set_attrib(g_usb_led_trigger, &attrib);
9490 +                               }
9491 +                       }
9492 +               #endif //defined(__UEIP__)
9493 +       }
9494 +
9495 +       void ifxusb_led_free(ifxusb_core_if_t *_core_if)
9496 +       {
9497 +               #if defined(__UEIP__)
9498 +                       if ( g_usb_led_trigger )
9499 +                       {
9500 +                           ifx_led_trigger_deregister(g_usb_led_trigger);
9501 +                           g_usb_led_trigger = NULL;
9502 +                       }
9503 +               #endif //defined(__UEIP__)
9504 +       }
9505 +
9506 +       /*!
9507 +          \brief Turn off the USB 5V VBus Power
9508 +          \param _core_if        Pointer of core_if structure
9509 +        */
9510 +       void ifxusb_led(ifxusb_core_if_t *_core_if)
9511 +       {
9512 +               #if defined(__UEIP__)
9513 +                       if(g_usb_led_trigger)
9514 +                               ifx_led_trigger_activate(g_usb_led_trigger);
9515 +               #else
9516 +               #endif //defined(__UEIP__)
9517 +       }
9518 +#endif // defined(__GADGET_LED__) || defined(__HOST_LED__)
9519 +
9520 +
9521 +
9522 +#if defined(__IS_HOST__) && defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
9523 +/*!
9524 + \brief Turn on the OC Int
9525 + */
9526 +       void ifxusb_oc_int_on()
9527 +       {
9528 +               #if defined(__UEIP__)
9529 +               #else
9530 +                       #if defined(__IS_TWINPASS__)
9531 +                               irq_enable(DANUBE_USB_OC_INT);
9532 +                       #endif
9533 +               #endif //defined(__UEIP__)
9534 +       }
9535 +/*!
9536 + \brief Turn off the OC Int
9537 + */
9538 +       void ifxusb_oc_int_off()
9539 +       {
9540 +               #if defined(__UEIP__)
9541 +               #else
9542 +                       #if defined(__IS_TWINPASS__)
9543 +                               irq_disable(DANUBE_USB_OC_INT);
9544 +                       #endif
9545 +               #endif //defined(__UEIP__)
9546 +       }
9547 +#endif //defined(__IS_HOST__) && defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
9548 +
9549 +/* internal routines for debugging */
9550 +void ifxusb_dump_msg(const u8 *buf, unsigned int length)
9551 +{
9552 +#ifdef __DEBUG__
9553 +       unsigned int    start, num, i;
9554 +       char            line[52], *p;
9555 +
9556 +       if (length >= 512)
9557 +               return;
9558 +       start = 0;
9559 +       while (length > 0)
9560 +       {
9561 +               num = min(length, 16u);
9562 +               p = line;
9563 +               for (i = 0; i < num; ++i)
9564 +               {
9565 +                       if (i == 8)
9566 +                               *p++ = ' ';
9567 +                       sprintf(p, " %02x", buf[i]);
9568 +                       p += 3;
9569 +               }
9570 +               *p = 0;
9571 +               IFX_PRINT( "%6x: %s\n", start, line);
9572 +               buf += num;
9573 +               start += num;
9574 +               length -= num;
9575 +       }
9576 +#endif
9577 +}
9578 +
9579 +/* This functions reads the SPRAM and prints its content */
9580 +void ifxusb_dump_spram(ifxusb_core_if_t *_core_if)
9581 +{
9582 +#ifdef __ENABLE_DUMP__
9583 +       volatile uint8_t *addr, *start_addr, *end_addr;
9584 +       uint32_t size;
9585 +       IFX_PRINT("SPRAM Data:\n");
9586 +       start_addr = (void*)_core_if->core_global_regs;
9587 +       IFX_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr);
9588 +
9589 +       start_addr = (void*)_core_if->data_fifo_dbg;
9590 +       IFX_PRINT("Starting Address: 0x%8X\n", (uint32_t)start_addr);
9591 +
9592 +       size=_core_if->hwcfg3.b.dfifo_depth;
9593 +       size<<=2;
9594 +       size+=0x200;
9595 +       size&=0x0003FFFC;
9596 +
9597 +       end_addr = (void*)_core_if->data_fifo_dbg;
9598 +       end_addr += size;
9599 +
9600 +       for(addr = start_addr; addr < end_addr; addr+=16)
9601 +       {
9602 +               IFX_PRINT("0x%8X:\t%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", (uint32_t)addr,
9603 +                       addr[ 0], addr[ 1], addr[ 2], addr[ 3],
9604 +                       addr[ 4], addr[ 5], addr[ 6], addr[ 7],
9605 +                       addr[ 8], addr[ 9], addr[10], addr[11],
9606 +                       addr[12], addr[13], addr[14], addr[15]
9607 +                       );
9608 +       }
9609 +       return;
9610 +#endif //__ENABLE_DUMP__
9611 +}
9612 +
9613 +
9614 +
9615 +
9616 +/* This function reads the core global registers and prints them */
9617 +void ifxusb_dump_registers(ifxusb_core_if_t *_core_if)
9618 +{
9619 +#ifdef __ENABLE_DUMP__
9620 +       int i;
9621 +       volatile uint32_t *addr;
9622 +       #ifdef __IS_DEVICE__
9623 +               volatile uint32_t *addri,*addro;
9624 +       #endif
9625 +
9626 +       IFX_PRINT("Core Global Registers\n");
9627 +       addr=&_core_if->core_global_regs->gotgctl;
9628 +       IFX_PRINT("GOTGCTL   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9629 +       addr=&_core_if->core_global_regs->gotgint;
9630 +       IFX_PRINT("GOTGINT   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9631 +       addr=&_core_if->core_global_regs->gahbcfg;
9632 +       IFX_PRINT("GAHBCFG   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9633 +       addr=&_core_if->core_global_regs->gusbcfg;
9634 +       IFX_PRINT("GUSBCFG   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9635 +       addr=&_core_if->core_global_regs->grstctl;
9636 +       IFX_PRINT("GRSTCTL   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9637 +       addr=&_core_if->core_global_regs->gintsts;
9638 +       IFX_PRINT("GINTSTS   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9639 +       addr=&_core_if->core_global_regs->gintmsk;
9640 +       IFX_PRINT("GINTMSK   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9641 +       addr=&_core_if->core_global_regs->gi2cctl;
9642 +       IFX_PRINT("GI2CCTL   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9643 +       addr=&_core_if->core_global_regs->gpvndctl;
9644 +       IFX_PRINT("GPVNDCTL  @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9645 +       addr=&_core_if->core_global_regs->ggpio;
9646 +       IFX_PRINT("GGPIO     @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9647 +       addr=&_core_if->core_global_regs->guid;
9648 +       IFX_PRINT("GUID      @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9649 +       addr=&_core_if->core_global_regs->gsnpsid;
9650 +       IFX_PRINT("GSNPSID   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9651 +       addr=&_core_if->core_global_regs->ghwcfg1;
9652 +       IFX_PRINT("GHWCFG1   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9653 +       addr=&_core_if->core_global_regs->ghwcfg2;
9654 +       IFX_PRINT("GHWCFG2   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9655 +       addr=&_core_if->core_global_regs->ghwcfg3;
9656 +       IFX_PRINT("GHWCFG3   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9657 +       addr=&_core_if->core_global_regs->ghwcfg4;
9658 +       IFX_PRINT("GHWCFG4   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9659 +
9660 +       addr=_core_if->pcgcctl;
9661 +       IFX_PRINT("PCGCCTL   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9662 +
9663 +       addr=&_core_if->core_global_regs->grxfsiz;
9664 +       IFX_PRINT("GRXFSIZ   @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9665 +
9666 +       #ifdef __IS_HOST__
9667 +               addr=&_core_if->core_global_regs->gnptxfsiz;
9668 +               IFX_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9669 +               addr=&_core_if->core_global_regs->hptxfsiz;
9670 +               IFX_PRINT("HPTXFSIZ  @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9671 +       #endif //__IS_HOST__
9672 +
9673 +       #ifdef __IS_DEVICE__
9674 +               #ifdef __DED_FIFO__
9675 +                       addr=&_core_if->core_global_regs->gnptxfsiz;
9676 +                       IFX_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9677 +                       for (i=0; i<= _core_if->hwcfg4.b.num_in_eps; i++)
9678 +                       {
9679 +                               addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i];
9680 +                               IFX_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,ifxusb_rreg(addr));
9681 +                       }
9682 +               #else
9683 +                       addr=&_core_if->core_global_regs->gnptxfsiz;
9684 +                       IFX_PRINT("TXFSIZ[00] @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9685 +                       for (i=0; i< _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
9686 +                       {
9687 +                               addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i];
9688 +                               IFX_PRINT("TXFSIZ[%02d] @0x%08X : 0x%08X\n",i+1,(uint32_t)addr,ifxusb_rreg(addr));
9689 +                       }
9690 +               #endif
9691 +       #endif //__IS_DEVICE__
9692 +
9693 +       #ifdef __IS_HOST__
9694 +               IFX_PRINT("Host Global Registers\n");
9695 +               addr=&_core_if->host_global_regs->hcfg;
9696 +               IFX_PRINT("HCFG          @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9697 +               addr=&_core_if->host_global_regs->hfir;
9698 +               IFX_PRINT("HFIR          @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9699 +               addr=&_core_if->host_global_regs->hfnum;
9700 +               IFX_PRINT("HFNUM         @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9701 +               addr=&_core_if->host_global_regs->hptxsts;
9702 +               IFX_PRINT("HPTXSTS       @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9703 +               addr=&_core_if->host_global_regs->haint;
9704 +               IFX_PRINT("HAINT         @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9705 +               addr=&_core_if->host_global_regs->haintmsk;
9706 +               IFX_PRINT("HAINTMSK      @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9707 +               addr= _core_if->hprt0;
9708 +               IFX_PRINT("HPRT0         @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9709 +
9710 +               for (i=0; i<MAX_EPS_CHANNELS; i++)
9711 +               {
9712 +                       IFX_PRINT("Host Channel %d Specific Registers\n", i);
9713 +                       addr=&_core_if->hc_regs[i]->hcchar;
9714 +                       IFX_PRINT("HCCHAR        @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9715 +                       addr=&_core_if->hc_regs[i]->hcsplt;
9716 +                       IFX_PRINT("HCSPLT        @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9717 +                       addr=&_core_if->hc_regs[i]->hcint;
9718 +                       IFX_PRINT("HCINT         @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9719 +                       addr=&_core_if->hc_regs[i]->hcintmsk;
9720 +                       IFX_PRINT("HCINTMSK      @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9721 +                       addr=&_core_if->hc_regs[i]->hctsiz;
9722 +                       IFX_PRINT("HCTSIZ        @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9723 +                       addr=&_core_if->hc_regs[i]->hcdma;
9724 +                       IFX_PRINT("HCDMA         @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9725 +               }
9726 +       #endif //__IS_HOST__
9727 +
9728 +       #ifdef __IS_DEVICE__
9729 +               IFX_PRINT("Device Global Registers\n");
9730 +               addr=&_core_if->dev_global_regs->dcfg;
9731 +               IFX_PRINT("DCFG          @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9732 +               addr=&_core_if->dev_global_regs->dctl;
9733 +               IFX_PRINT("DCTL          @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9734 +               addr=&_core_if->dev_global_regs->dsts;
9735 +               IFX_PRINT("DSTS          @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9736 +               addr=&_core_if->dev_global_regs->diepmsk;
9737 +               IFX_PRINT("DIEPMSK       @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9738 +               addr=&_core_if->dev_global_regs->doepmsk;
9739 +               IFX_PRINT("DOEPMSK       @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9740 +               addr=&_core_if->dev_global_regs->daintmsk;
9741 +               IFX_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9742 +               addr=&_core_if->dev_global_regs->daint;
9743 +               IFX_PRINT("DAINT         @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9744 +               addr=&_core_if->dev_global_regs->dvbusdis;
9745 +               IFX_PRINT("DVBUSID       @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9746 +               addr=&_core_if->dev_global_regs->dvbuspulse;
9747 +               IFX_PRINT("DVBUSPULSE   @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr));
9748 +
9749 +               addr=&_core_if->dev_global_regs->dtknqr1;
9750 +               IFX_PRINT("DTKNQR1       @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
9751 +               if (_core_if->hwcfg2.b.dev_token_q_depth > 6) {
9752 +                       addr=&_core_if->dev_global_regs->dtknqr2;
9753 +                       IFX_PRINT("DTKNQR2       @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr));
9754 +               }
9755 +
9756 +               if (_core_if->hwcfg2.b.dev_token_q_depth > 14)
9757 +               {
9758 +                       addr=&_core_if->dev_global_regs->dtknqr3_dthrctl;
9759 +                       IFX_PRINT("DTKNQR3_DTHRCTL       @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr));
9760 +               }
9761 +
9762 +               if (_core_if->hwcfg2.b.dev_token_q_depth > 22)
9763 +               {
9764 +                       addr=&_core_if->dev_global_regs->dtknqr4_fifoemptymsk;
9765 +                       IFX_PRINT("DTKNQR4       @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr));
9766 +               }
9767 +
9768 +               //for (i=0; i<= MAX_EPS_CHANNELS; i++)
9769 +               //for (i=0; i<= 10; i++)
9770 +               for (i=0; i<= 3; i++)
9771 +               {
9772 +                       IFX_PRINT("Device EP %d Registers\n", i);
9773 +                       addri=&_core_if->in_ep_regs[i]->diepctl;addro=&_core_if->out_ep_regs[i]->doepctl;
9774 +                       IFX_PRINT("DEPCTL        I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
9775 +                                                               addro=&_core_if->out_ep_regs[i]->doepfn;
9776 +                       IFX_PRINT("DEPFN         I:            O: 0x%08X\n",ifxusb_rreg(addro));
9777 +                       addri=&_core_if->in_ep_regs[i]->diepint;addro=&_core_if->out_ep_regs[i]->doepint;
9778 +                       IFX_PRINT("DEPINT        I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
9779 +                       addri=&_core_if->in_ep_regs[i]->dieptsiz;addro=&_core_if->out_ep_regs[i]->doeptsiz;
9780 +                       IFX_PRINT("DETSIZ        I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
9781 +                       addri=&_core_if->in_ep_regs[i]->diepdma;addro=&_core_if->out_ep_regs[i]->doepdma;
9782 +                       IFX_PRINT("DEPDMA        I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
9783 +                       addri=&_core_if->in_ep_regs[i]->dtxfsts;
9784 +                       IFX_PRINT("DTXFSTS       I: 0x%08X\n",ifxusb_rreg(addri)                   );
9785 +                       addri=&_core_if->in_ep_regs[i]->diepdmab;addro=&_core_if->out_ep_regs[i]->doepdmab;
9786 +                       IFX_PRINT("DEPDMAB       I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
9787 +               }
9788 +       #endif //__IS_DEVICE__
9789 +#endif //__ENABLE_DUMP__
9790 +}
9791 +
9792 +void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords)
9793 +{
9794 +       volatile uint32_t *addr1,*addr2, *start_addr, *end_addr;
9795 +
9796 +       if(!dwords)
9797 +               return;
9798 +
9799 +       start_addr = (uint32_t *)_core_if->data_fifo_dbg;
9800 +
9801 +       end_addr = (uint32_t *)_core_if->data_fifo_dbg;
9802 +       end_addr += dwords;
9803 +
9804 +       IFX_PRINT("Clearning SPRAM: 0x%8X-0x%8X\n", (uint32_t)start_addr,(uint32_t)end_addr);
9805 +       for(addr1 = start_addr; addr1 < end_addr; addr1+=4)
9806 +       {
9807 +               for(addr2 = addr1; addr2 < addr1+4; addr2++)
9808 +                       *addr2=0x00000000;
9809 +       }
9810 +       IFX_PRINT("Clearning SPRAM: 0x%8X-0x%8X Done\n", (uint32_t)start_addr,(uint32_t)end_addr);
9811 +       return;
9812 +}
9813 +
9814 --- /dev/null
9815 +++ b/drivers/usb/ifxhcd/ifxusb_cif.h
9816 @@ -0,0 +1,665 @@
9817 +/*****************************************************************************
9818 + **   FILE NAME       : ifxusb_cif.h
9819 + **   PROJECT         : IFX USB sub-system V3
9820 + **   MODULES         : IFX USB sub-system Host and Device driver
9821 + **   SRC VERSION     : 1.0
9822 + **   DATE            : 1/Jan/2009
9823 + **   AUTHOR          : Chen, Howard
9824 + **   DESCRIPTION     : The Core Interface provides basic services for accessing and
9825 + **                     managing the IFX USB hardware. These services are used by both the
9826 + **                     Host Controller Driver and the Peripheral Controller Driver.
9827 + **   FUNCTIONS       :
9828 + **   COMPILER        : gcc
9829 + **   REFERENCE       : IFX hardware ref handbook for each plateforms
9830 + **   COPYRIGHT       :
9831 + **  Version Control Section  **
9832 + **   $Author$
9833 + **   $Date$
9834 + **   $Revisions$
9835 + **   $Log$       Revision history
9836 +*****************************************************************************/
9837 +
9838 +/*!
9839 + \defgroup IFXUSB_DRIVER_V3 IFX USB SS Project
9840 + \brief IFX USB subsystem V3.x
9841 + */
9842 +
9843 +/*!
9844 + \defgroup IFXUSB_CIF Core Interface APIs
9845 + \ingroup IFXUSB_DRIVER_V3
9846 + \brief The Core Interface provides basic services for accessing and
9847 +        managing the IFXUSB hardware. These services are used by both the
9848 +        Host Controller Driver and the Peripheral Controller Driver.
9849 + */
9850 +
9851 +
9852 +/*!
9853 + \file ifxusb_cif.h
9854 + \ingroup IFXUSB_DRIVER_V3
9855 + \brief This file contains the interface to the IFX USB Core.
9856 + */
9857 +
9858 +#if !defined(__IFXUSB_CIF_H__)
9859 +#define __IFXUSB_CIF_H__
9860 +
9861 +#include <linux/workqueue.h>
9862 +
9863 +#include <linux/version.h>
9864 +#include <asm/param.h>
9865 +
9866 +#include "ifxusb_plat.h"
9867 +#include "ifxusb_regs.h"
9868 +
9869 +#ifdef __DEBUG__
9870 +       #include "linux/timer.h"
9871 +#endif
9872 +
9873 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
9874 +
9875 +#define IFXUSB_PARAM_SPEED_HIGH 0
9876 +#define IFXUSB_PARAM_SPEED_FULL 1
9877 +
9878 +#define IFXUSB_EP_SPEED_LOW     0
9879 +#define IFXUSB_EP_SPEED_FULL    1
9880 +#define IFXUSB_EP_SPEED_HIGH    2
9881 +
9882 +#define IFXUSB_EP_TYPE_CTRL     0
9883 +#define IFXUSB_EP_TYPE_ISOC     1
9884 +#define IFXUSB_EP_TYPE_BULK     2
9885 +#define IFXUSB_EP_TYPE_INTR     3
9886 +
9887 +#define IFXUSB_HC_PID_DATA0 0
9888 +#define IFXUSB_HC_PID_DATA2 1
9889 +#define IFXUSB_HC_PID_DATA1 2
9890 +#define IFXUSB_HC_PID_MDATA 3
9891 +#define IFXUSB_HC_PID_SETUP 3
9892 +
9893 +
9894 +/*!
9895 + \addtogroup IFXUSB_CIF
9896 + */
9897 +/*@{*/
9898 +
9899 +/*!
9900 + \struct ifxusb_params
9901 + \brief IFXUSB Parameters structure.
9902 +       This structure is used for both importing from insmod stage and run-time storage.
9903 +       These parameters define how the IFXUSB controller should be configured.
9904 + */
9905 +typedef struct ifxusb_params
9906 +{
9907 +       int32_t dma_burst_size;  /*!< The DMA Burst size (applicable only for Internal DMA
9908 +                                     Mode). 0(for single), 1(incr), 4(incr4), 8(incr8) 16(incr16)
9909 +                                 */
9910 +                                /* Translate this to GAHBCFG values */
9911 +       int32_t speed;           /*!< Specifies the maximum speed of operation in host and device mode.
9912 +                                     The actual speed depends on the speed of the attached device and
9913 +                                     the value of phy_type. The actual speed depends on the speed of the
9914 +                                     attached device.
9915 +                                     0 - High Speed (default)
9916 +                                     1 - Full Speed
9917 +                              */
9918 +
9919 +       int32_t data_fifo_size;   /*!< Total number of dwords in the data FIFO memory. This
9920 +                                      memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
9921 +                                      Tx FIFOs.
9922 +                                      32 to 32768
9923 +                                  */
9924 +       #ifdef __IS_DEVICE__
9925 +               int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in device mode.
9926 +                                          16 to 32768
9927 +                                      */
9928 +
9929 +
9930 +               int32_t tx_fifo_size[MAX_EPS_CHANNELS]; /*!< Number of dwords in each of the Tx FIFOs in device mode.
9931 +                                                            4 to 768
9932 +                                                        */
9933 +               #ifdef __DED_FIFO__
9934 +                       int32_t thr_ctl;        /*!< Threshold control on/off */
9935 +                       int32_t tx_thr_length;  /*!< Threshold length for Tx */
9936 +                       int32_t rx_thr_length;  /*!< Threshold length for Rx*/
9937 +               #endif
9938 +       #else //__IS_HOST__
9939 +               int32_t host_channels;      /*!< The number of host channel registers to use.
9940 +                                                1 to 16
9941 +                                            */
9942 +
9943 +               int32_t rx_fifo_size;       /*!< Number of dwords in the Rx FIFO in host mode.
9944 +                                               16 to 32768
9945 +                                            */
9946 +
9947 +               int32_t nperio_tx_fifo_size;/*!< Number of dwords in the non-periodic Tx FIFO in host mode.
9948 +                                                16 to 32768
9949 +                                            */
9950 +
9951 +               int32_t perio_tx_fifo_size; /*!< Number of dwords in the host periodic Tx FIFO.
9952 +                                                16 to 32768
9953 +                                            */
9954 +       #endif //__IS_HOST__
9955 +
9956 +       int32_t max_transfer_size;      /*!< The maximum transfer size supported in bytes.
9957 +                                            2047 to 65,535
9958 +                                        */
9959 +
9960 +       int32_t max_packet_count;       /*!< The maximum number of packets in a transfer.
9961 +                                            15 to 511  (default 511)
9962 +                                        */
9963 +       int32_t phy_utmi_width;         /*!< Specifies the UTMI+ Data Width.
9964 +                                            8 or 16 bits (default 16)
9965 +                                        */
9966 +
9967 +       int32_t turn_around_time_hs;    /*!< Specifies the Turn-Around time at HS*/
9968 +       int32_t turn_around_time_fs;    /*!< Specifies the Turn-Around time at FS*/
9969 +
9970 +       int32_t timeout_cal_hs;         /*!< Specifies the Timeout_Calibration at HS*/
9971 +       int32_t timeout_cal_fs;         /*!< Specifies the Timeout_Calibration at FS*/
9972 +} ifxusb_params_t;
9973 +
9974 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
9975 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
9976 +
9977 +/*!
9978 + \struct ifxusb_core_if
9979 + \brief The ifx_core_if structure contains information needed to manage
9980 +       the IFX USB controller acting in either host or device mode. It
9981 +       represents the programming view of the controller as a whole.
9982 + */
9983 +typedef struct ifxusb_core_if
9984 +{
9985 +       ifxusb_params_t      params;  /*!< Run-time Parameters */
9986 +
9987 +       uint8_t  core_no;             /*!< core number (used as id when multi-core case */
9988 +       char    *core_name;           /*!< core name used for registration and informative purpose*/
9989 +       int      irq;                 /*!< irq number this core is hooked */
9990 +
9991 +       /*****************************************************************
9992 +        * Structures and pointers to physical register interface.
9993 +        *****************************************************************/
9994 +       /** Core Global registers starting at offset 000h. */
9995 +       ifxusb_core_global_regs_t *core_global_regs;  /*!< pointer to Core Global Registers, offset at 000h */
9996 +
9997 +       /** Host-specific registers */
9998 +       #ifdef __IS_HOST__
9999 +               /** Host Global Registers starting at offset 400h.*/
10000 +               ifxusb_host_global_regs_t *host_global_regs; /*!< pointer to Host Global Registers, offset at 400h */
10001 +                       #define IFXUSB_HOST_GLOBAL_REG_OFFSET 0x400
10002 +               /** Host Port 0 Control and Status Register */
10003 +               volatile uint32_t *hprt0;                    /*!< pointer to HPRT0 Registers, offset at 440h */
10004 +                       #define IFXUSB_HOST_PORT_REGS_OFFSET 0x440
10005 +               /** Host Channel Specific Registers at offsets 500h-5FCh. */
10006 +               ifxusb_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; /*!< pointer to Host-Channel n Registers, offset at 500h */
10007 +                       #define IFXUSB_HOST_CHAN_REGS_OFFSET 0x500
10008 +                       #define IFXUSB_CHAN_REGS_OFFSET 0x20
10009 +       #endif
10010 +
10011 +       /** Device-specific registers */
10012 +       #ifdef __IS_DEVICE__
10013 +               /** Device Global Registers starting at offset 800h */
10014 +               ifxusb_device_global_regs_t *dev_global_regs; /*!< pointer to Device Global Registers, offset at 800h */
10015 +                       #define IFXUSB_DEV_GLOBAL_REG_OFFSET 0x800
10016 +
10017 +               /** Device Logical IN Endpoint-Specific Registers 900h-AFCh */
10018 +               ifxusb_dev_in_ep_regs_t     *in_ep_regs[MAX_EPS_CHANNELS]; /*!< pointer to Device IN-EP Registers, offset at 900h */
10019 +                       #define IFXUSB_DEV_IN_EP_REG_OFFSET 0x900
10020 +                       #define IFXUSB_EP_REG_OFFSET 0x20
10021 +               /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
10022 +               ifxusb_dev_out_ep_regs_t    *out_ep_regs[MAX_EPS_CHANNELS];/*!< pointer to Device OUT-EP Registers, offset at 900h */
10023 +                       #define IFXUSB_DEV_OUT_EP_REG_OFFSET 0xB00
10024 +       #endif
10025 +
10026 +       /** Power and Clock Gating Control Register */
10027 +       volatile uint32_t *pcgcctl;                                    /*!< pointer to Power and Clock Gating Control Registers, offset at E00h */
10028 +               #define IFXUSB_PCGCCTL_OFFSET 0xE00
10029 +
10030 +       /** Push/pop addresses for endpoints or host channels.*/
10031 +       uint32_t *data_fifo[MAX_EPS_CHANNELS];    /*!< pointer to FIFO access windows, offset at 1000h */
10032 +               #define IFXUSB_DATA_FIFO_OFFSET 0x1000
10033 +               #define IFXUSB_DATA_FIFO_SIZE   0x1000
10034 +
10035 +       uint32_t *data_fifo_dbg;                 /*!< pointer to FIFO debug windows, offset at 1000h */
10036 +
10037 +       /** Hardware Configuration -- stored here for convenience.*/
10038 +       hwcfg1_data_t hwcfg1;  /*!< preserved Hardware Configuration 1 */
10039 +       hwcfg2_data_t hwcfg2;  /*!< preserved Hardware Configuration 2 */
10040 +       hwcfg3_data_t hwcfg3;  /*!< preserved Hardware Configuration 3 */
10041 +       hwcfg4_data_t hwcfg4;  /*!< preserved Hardware Configuration 3 */
10042 +       uint32_t      snpsid;  /*!< preserved SNPSID */
10043 +
10044 +       /*****************************************************************
10045 +        * Run-time informations.
10046 +        *****************************************************************/
10047 +       /* Set to 1 if the core PHY interface bits in USBCFG have been  initialized. */
10048 +       uint8_t phy_init_done;  /*!< indicated PHY is initialized. */
10049 +
10050 +       #ifdef __IS_HOST__
10051 +               uint8_t queuing_high_bandwidth; /*!< Host mode, Queueing High Bandwidth. */
10052 +       #endif
10053 +} ifxusb_core_if_t;
10054 +
10055 +/*@}*//*IFXUSB_CIF*/
10056 +
10057 +
10058 +/*!
10059 + \fn    void *ifxusb_alloc_buf(size_t size, int clear)
10060 + \brief This function is called to allocate buffer of specified size.
10061 +        The allocated buffer is mapped into DMA accessable address.
10062 + \param    size Size in BYTE to be allocated
10063 + \param    clear 0: don't do clear after buffer allocated, other: do clear to zero
10064 + \return   0/NULL: Fail; uncached pointer of allocated buffer
10065 + \ingroup  IFXUSB_CIF
10066 + */
10067 +extern void *ifxusb_alloc_buf(size_t size, int clear);
10068 +
10069 +/*!
10070 + \fn    void ifxusb_free_buf(void *vaddr)
10071 + \brief This function is called to free allocated buffer.
10072 + \param vaddr the uncached pointer of the buffer
10073 + \ingroup  IFXUSB_CIF
10074 + */
10075 +extern void ifxusb_free_buf(void *vaddr);
10076 +
10077 +/*!
10078 + \fn    int ifxusb_core_if_init(ifxusb_core_if_t *_core_if,
10079 +                        int               _irq,
10080 +                        uint32_t          _reg_base_addr,
10081 +                        uint32_t          _fifo_base_addr,
10082 +                        uint32_t          _fifo_dbg_addr)
10083 + \brief This function is called to initialize the IFXUSB CSR data
10084 +        structures.  The register addresses in the device and host
10085 +        structures are initialized from the base address supplied by the
10086 +        caller.  The calling function must make the OS calls to get the
10087 +        base address of the IFXUSB controller registers.
10088 + \param _core_if        Pointer of core_if structure
10089 + \param _irq            irq number
10090 + \param _reg_base_addr  Base address of IFXUSB core registers
10091 + \param _fifo_base_addr Fifo base address
10092 + \param _fifo_dbg_addr  Fifo debug address
10093 + \return 0: success;
10094 + \ingroup  IFXUSB_CIF
10095 + */
10096 +extern int ifxusb_core_if_init(ifxusb_core_if_t *_core_if,
10097 +                        int               _irq,
10098 +                        uint32_t          _reg_base_addr,
10099 +                        uint32_t          _fifo_base_addr,
10100 +                        uint32_t          _fifo_dbg_addr);
10101 +
10102 +
10103 +/*!
10104 + \fn    void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if)
10105 + \brief This function free the mapped address in the IFXUSB CSR data structures.
10106 + \param _core_if Pointer of core_if structure
10107 + \ingroup  IFXUSB_CIF
10108 + */
10109 +extern void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if);
10110 +
10111 +/*!
10112 + \fn    void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if )
10113 + \brief This function enbles the controller's Global Interrupt in the AHB Config register.
10114 + \param _core_if Pointer of core_if structure
10115 + */
10116 +extern void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if );
10117 +
10118 +/*!
10119 + \fn    void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if )
10120 + \brief This function disables the controller's Global Interrupt in the AHB Config register.
10121 + \param _core_if Pointer of core_if structure
10122 + \ingroup  IFXUSB_CIF
10123 + */
10124 +extern void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if );
10125 +
10126 +/*!
10127 + \fn    void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num )
10128 + \brief Flush a Tx FIFO.
10129 + \param _core_if Pointer of core_if structure
10130 + \param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO )
10131 + \ingroup  IFXUSB_CIF
10132 + */
10133 +extern void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num );
10134 +
10135 +/*!
10136 + \fn    void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if )
10137 + \brief Flush Rx FIFO.
10138 + \param _core_if Pointer of core_if structure
10139 + \ingroup  IFXUSB_CIF
10140 + */
10141 +extern void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if );
10142 +
10143 +/*!
10144 + \fn    void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if )
10145 + \brief Flush ALL Rx and Tx FIFO.
10146 + \param _core_if Pointer of core_if structure
10147 + \ingroup  IFXUSB_CIF
10148 + */
10149 +extern void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if );
10150 +
10151 +
10152 +/*!
10153 + \fn    int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if)
10154 + \brief Do core a soft reset of the core.  Be careful with this because it
10155 +        resets all the internal state machines of the core.
10156 + \param    _core_if Pointer of core_if structure
10157 + \ingroup  IFXUSB_CIF
10158 + */
10159 +extern int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if);
10160 +
10161 +
10162 +/*!
10163 + \brief Turn on the USB Core Power
10164 + \param _core_if Pointer of core_if structure
10165 + \ingroup  IFXUSB_CIF
10166 +*/
10167 +extern void ifxusb_power_on (ifxusb_core_if_t *_core_if);
10168 +
10169 +/*!
10170 + \fn    void ifxusb_power_off (ifxusb_core_if_t *_core_if)
10171 + \brief Turn off the USB Core Power
10172 + \param _core_if Pointer of core_if structure
10173 + \ingroup  IFXUSB_CIF
10174 +*/
10175 +extern void ifxusb_power_off (ifxusb_core_if_t *_core_if);
10176 +
10177 +/*!
10178 + \fn    void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if)
10179 + \brief Turn on the USB PHY Power
10180 + \param _core_if Pointer of core_if structure
10181 + \ingroup  IFXUSB_CIF
10182 +*/
10183 +extern void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if);
10184 +
10185 +/*!
10186 + \fn    void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if)
10187 + \brief Turn off the USB PHY Power
10188 + \param _core_if Pointer of core_if structure
10189 + \ingroup  IFXUSB_CIF
10190 +*/
10191 +extern void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if);
10192 +
10193 +/*!
10194 + \fn    void ifxusb_hard_reset(ifxusb_core_if_t *_core_if)
10195 + \brief Reset on the USB Core RCU
10196 + \param _core_if Pointer of core_if structure
10197 + \ingroup  IFXUSB_CIF
10198 + */
10199 +extern void ifxusb_hard_reset(ifxusb_core_if_t *_core_if);
10200 +
10201 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
10202 +
10203 +
10204 +#ifdef __IS_HOST__
10205 +       /*!
10206 +        \fn    void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t  *_params)
10207 +        \brief This function initializes the IFXUSB controller registers for  Host mode.
10208 +               This function flushes the Tx and Rx FIFOs and it flushes any entries in the
10209 +               request queues.
10210 +        \param _core_if        Pointer of core_if structure
10211 +        \param _params         parameters to be set
10212 +        \ingroup  IFXUSB_CIF
10213 +        */
10214 +       extern void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t  *_params);
10215 +
10216 +       /*!
10217 +        \fn    void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if)
10218 +        \brief This function enables the Host mode interrupts.
10219 +        \param _core_if        Pointer of core_if structure
10220 +        \ingroup  IFXUSB_CIF
10221 +        */
10222 +       extern void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if);
10223 +
10224 +       /*!
10225 +        \fn    void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if)
10226 +        \brief This function disables the Host mode interrupts.
10227 +        \param _core_if        Pointer of core_if structure
10228 +        \ingroup  IFXUSB_CIF
10229 +        */
10230 +       extern void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if);
10231 +
10232 +       #if defined(__IS_TWINPASS__)
10233 +               extern void ifxusb_enable_afe_oc(void);
10234 +       #endif
10235 +
10236 +       /*!
10237 +        \fn    void ifxusb_vbus_init(ifxusb_core_if_t *_core_if)
10238 +        \brief This function init the VBUS control.
10239 +        \param _core_if        Pointer of core_if structure
10240 +        \ingroup  IFXUSB_CIF
10241 +        */
10242 +       extern void ifxusb_vbus_init(ifxusb_core_if_t *_core_if);
10243 +
10244 +       /*!
10245 +        \fn    void ifxusb_vbus_free(ifxusb_core_if_t *_core_if)
10246 +        \brief This function free the VBUS control.
10247 +        \param _core_if        Pointer of core_if structure
10248 +        \ingroup  IFXUSB_CIF
10249 +        */
10250 +       extern void ifxusb_vbus_free(ifxusb_core_if_t *_core_if);
10251 +
10252 +       /*!
10253 +        \fn    void ifxusb_vbus_on(ifxusb_core_if_t *_core_if)
10254 +        \brief Turn on the USB 5V VBus Power
10255 +        \param _core_if        Pointer of core_if structure
10256 +        \ingroup  IFXUSB_CIF
10257 +        */
10258 +       extern void ifxusb_vbus_on(ifxusb_core_if_t *_core_if);
10259 +
10260 +       /*!
10261 +        \fn    void ifxusb_vbus_off(ifxusb_core_if_t *_core_if)
10262 +        \brief Turn off the USB 5V VBus Power
10263 +        \param _core_if        Pointer of core_if structure
10264 +        \ingroup  IFXUSB_CIF
10265 +        */
10266 +       extern void ifxusb_vbus_off(ifxusb_core_if_t *_core_if);
10267 +
10268 +       /*!
10269 +        \fn    int ifxusb_vbus(ifxusb_core_if_t *_core_if)
10270 +        \brief Read Current VBus status
10271 +        \param _core_if        Pointer of core_if structure
10272 +        \ingroup  IFXUSB_CIF
10273 +        */
10274 +       extern int ifxusb_vbus(ifxusb_core_if_t *_core_if);
10275 +
10276 +       #if defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
10277 +               /*!
10278 +                \fn    void ifxusb_oc_int_on(void)
10279 +                \brief Turn on the OC interrupt
10280 +                \ingroup  IFXUSB_CIF
10281 +                */
10282 +               extern void ifxusb_oc_int_on(void);
10283 +
10284 +               /*!
10285 +                \fn    void ifxusb_oc_int_off(void)
10286 +                \brief Turn off the OC interrupt
10287 +                \ingroup  IFXUSB_CIF
10288 +                */
10289 +               extern void ifxusb_oc_int_off(void);
10290 +       #endif //defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
10291 +#endif
10292 +
10293 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
10294 +
10295 +
10296 +#ifdef __IS_DEVICE__
10297 +       /*!
10298 +        \fn    void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if)
10299 +        \brief This function enables the Device mode interrupts.
10300 +        \param _core_if        Pointer of core_if structure
10301 +        \ingroup  IFXUSB_CIF
10302 +        */
10303 +       extern void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if);
10304 +
10305 +       /*!
10306 +        \fn    uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if)
10307 +        \brief Gets the current USB frame number. This is the frame number from the last SOF packet.
10308 +        \param _core_if        Pointer of core_if structure
10309 +        \ingroup  IFXUSB_CIF
10310 +        */
10311 +       extern uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if);
10312 +
10313 +       /*!
10314 +        \fn    void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in)
10315 +        \brief Set the EP STALL.
10316 +        \param _core_if        Pointer of core_if structure
10317 +        \param _epno           EP number
10318 +        \param _is_in          1: is IN transfer
10319 +        \ingroup  IFXUSB_CIF
10320 +        */
10321 +       extern void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in);
10322 +
10323 +       /*!
10324 +        \fn    void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in)
10325 +        \brief Set the EP STALL.
10326 +        \param _core_if        Pointer of core_if structure
10327 +        \param _epno           EP number
10328 +        \param _ep_type        EP Type
10329 +        \ingroup  IFXUSB_CIF
10330 +        */
10331 +       extern void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in);
10332 +
10333 +       /*!
10334 +        \fn    void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t  *_params)
10335 +        \brief  This function initializes the IFXUSB controller registers for Device mode.
10336 +                This function flushes the Tx and Rx FIFOs and it flushes any entries in the
10337 +                request queues.
10338 +                This function validate the imported parameters and store the result in the CIF structure.
10339 +                    After
10340 +        \param _core_if  Pointer of core_if structure
10341 +        \param _params   structure of inported parameters
10342 +        \ingroup  IFXUSB_CIF
10343 +        */
10344 +       extern void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t  *_params);
10345 +#endif
10346 +
10347 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
10348 +
10349 +#if defined(__GADGET_LED__) || defined(__HOST_LED__)
10350 +       /*!
10351 +        \fn    void ifxusb_led_init(ifxusb_core_if_t *_core_if)
10352 +        \brief This function init the LED control.
10353 +        \param _core_if        Pointer of core_if structure
10354 +        \ingroup  IFXUSB_CIF
10355 +        */
10356 +       extern void ifxusb_led_init(ifxusb_core_if_t *_core_if);
10357 +
10358 +       /*!
10359 +        \fn    void ifxusb_led_free(ifxusb_core_if_t *_core_if)
10360 +        \brief This function free the LED control.
10361 +        \param _core_if        Pointer of core_if structure
10362 +        \ingroup  IFXUSB_CIF
10363 +        */
10364 +       extern void ifxusb_led_free(ifxusb_core_if_t *_core_if);
10365 +
10366 +       /*!
10367 +        \fn    void ifxusb_led(ifxusb_core_if_t *_core_if)
10368 +        \brief This function trigger the LED access.
10369 +        \param _core_if        Pointer of core_if structure
10370 +        \ingroup  IFXUSB_CIF
10371 +        */
10372 +       extern void ifxusb_led(ifxusb_core_if_t *_core_if);
10373 +#endif
10374 +
10375 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
10376 +
10377 +/* internal routines for debugging */
10378 +extern void ifxusb_dump_msg(const u8 *buf, unsigned int length);
10379 +extern void ifxusb_dump_spram(ifxusb_core_if_t *_core_if);
10380 +extern void ifxusb_dump_registers(ifxusb_core_if_t *_core_if);
10381 +extern void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords);
10382 +
10383 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
10384 +
10385 +static inline uint32_t ifxusb_read_core_intr(ifxusb_core_if_t *_core_if)
10386 +{
10387 +       return (ifxusb_rreg(&_core_if->core_global_regs->gintsts) &
10388 +               (ifxusb_rreg(&_core_if->core_global_regs->gintmsk)
10389 +#ifdef __USE_TIMER_4_SOF__
10390 +                        | IFXUSB_SOF_INTR_MASK
10391 +#endif
10392 +                       ));
10393 +}
10394 +
10395 +static inline uint32_t ifxusb_read_otg_intr (ifxusb_core_if_t *_core_if)
10396 +{
10397 +       return (ifxusb_rreg (&_core_if->core_global_regs->gotgint));
10398 +}
10399 +
10400 +static inline uint32_t ifxusb_mode(ifxusb_core_if_t *_core_if)
10401 +{
10402 +       return (ifxusb_rreg( &_core_if->core_global_regs->gintsts ) & 0x1);
10403 +}
10404 +static inline uint8_t ifxusb_is_device_mode(ifxusb_core_if_t *_core_if)
10405 +{
10406 +       return (ifxusb_mode(_core_if) != 1);
10407 +}
10408 +static inline uint8_t ifxusb_is_host_mode(ifxusb_core_if_t *_core_if)
10409 +{
10410 +       return (ifxusb_mode(_core_if) == 1);
10411 +}
10412 +
10413 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
10414 +
10415 +#ifdef __IS_HOST__
10416 +       static inline uint32_t ifxusb_read_hprt0(ifxusb_core_if_t *_core_if)
10417 +       {
10418 +               hprt0_data_t hprt0;
10419 +               hprt0.d32 = ifxusb_rreg(_core_if->hprt0);
10420 +               hprt0.b.prtena = 0;
10421 +               hprt0.b.prtconndet = 0;
10422 +               hprt0.b.prtenchng = 0;
10423 +               hprt0.b.prtovrcurrchng = 0;
10424 +               return hprt0.d32;
10425 +       }
10426 +
10427 +       static inline uint32_t ifxusb_read_host_all_channels_intr (ifxusb_core_if_t *_core_if)
10428 +       {
10429 +               return (ifxusb_rreg (&_core_if->host_global_regs->haint));
10430 +       }
10431 +
10432 +       static inline uint32_t ifxusb_read_host_channel_intr (ifxusb_core_if_t *_core_if, int hc_num)
10433 +       {
10434 +               return (ifxusb_rreg (&_core_if->hc_regs[hc_num]->hcint));
10435 +       }
10436 +#endif
10437 +
10438 +#ifdef __IS_DEVICE__
10439 +       static inline uint32_t ifxusb_read_dev_all_in_ep_intr(ifxusb_core_if_t *_core_if)
10440 +       {
10441 +               uint32_t v;
10442 +               v = ifxusb_rreg(&_core_if->dev_global_regs->daint) &
10443 +                   ifxusb_rreg(&_core_if->dev_global_regs->daintmsk);
10444 +               return (v & 0xffff);
10445 +       }
10446 +
10447 +       static inline uint32_t ifxusb_read_dev_all_out_ep_intr(ifxusb_core_if_t *_core_if)
10448 +       {
10449 +               uint32_t v;
10450 +               v = ifxusb_rreg(&_core_if->dev_global_regs->daint) &
10451 +                   ifxusb_rreg(&_core_if->dev_global_regs->daintmsk);
10452 +               return ((v & 0xffff0000) >> 16);
10453 +       }
10454 +
10455 +       static inline uint32_t ifxusb_read_dev_in_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num)
10456 +       {
10457 +               uint32_t v;
10458 +               v = ifxusb_rreg(&_core_if->in_ep_regs[_ep_num]->diepint) &
10459 +                   ifxusb_rreg(&_core_if->dev_global_regs->diepmsk);
10460 +               return v;
10461 +       }
10462 +
10463 +       static inline uint32_t ifxusb_read_dev_out_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num)
10464 +       {
10465 +               uint32_t v;
10466 +               v = ifxusb_rreg(&_core_if->out_ep_regs[_ep_num]->doepint) &
10467 +                   ifxusb_rreg(&_core_if->dev_global_regs->doepmsk);
10468 +               return v;
10469 +       }
10470 +
10471 +#endif
10472 +
10473 +extern void ifxusb_attr_create (void *_dev);
10474 +
10475 +extern void ifxusb_attr_remove (void *_dev);
10476 +
10477 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
10478 +
10479 +#endif // !defined(__IFXUSB_CIF_H__)
10480 +
10481 +
10482 --- /dev/null
10483 +++ b/drivers/usb/ifxhcd/ifxusb_cif_d.c
10484 @@ -0,0 +1,458 @@
10485 +/*****************************************************************************
10486 + **   FILE NAME       : ifxusb_cif_d.c
10487 + **   PROJECT         : IFX USB sub-system V3
10488 + **   MODULES         : IFX USB sub-system Host and Device driver
10489 + **   SRC VERSION     : 1.0
10490 + **   DATE            : 1/Jan/2009
10491 + **   AUTHOR          : Chen, Howard
10492 + **   DESCRIPTION     : The Core Interface provides basic services for accessing and
10493 + **                     managing the IFX USB hardware. These services are used by the
10494 + **                     Peripheral Controller Driver only.
10495 + *****************************************************************************/
10496 +
10497 +/*!
10498 + \file ifxusb_cif_d.c
10499 + \ingroup IFXUSB_DRIVER_V3
10500 + \brief This file contains the interface to the IFX USB Core.
10501 +*/
10502 +
10503 +#include <linux/version.h>
10504 +#include "ifxusb_version.h"
10505 +
10506 +
10507 +#include <asm/byteorder.h>
10508 +#include <asm/unaligned.h>
10509 +
10510 +#ifdef __DEBUG__
10511 +       #include <linux/jiffies.h>
10512 +#endif
10513 +
10514 +#include "ifxusb_plat.h"
10515 +#include "ifxusb_regs.h"
10516 +#include "ifxusb_cif.h"
10517 +
10518 +#include "ifxpcd.h"
10519 +
10520 +
10521 +
10522 +/*!
10523 + \brief Initializes the DevSpd field of the DCFG register depending on the PHY type
10524 + and the enumeration speed of the device.
10525 + \param _core_if        Pointer of core_if structure
10526 + */
10527 +void ifxusb_dev_init_spd(ifxusb_core_if_t *_core_if)
10528 +{
10529 +       uint32_t    val;
10530 +       dcfg_data_t dcfg;
10531 +
10532 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
10533 +       if (_core_if->params.speed == IFXUSB_PARAM_SPEED_FULL)
10534 +               /* High speed PHY running at full speed */
10535 +               val = 0x1;
10536 +       else
10537 +               /* High speed PHY running at high speed and full speed*/
10538 +               val = 0x0;
10539 +
10540 +       IFX_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
10541 +       dcfg.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dcfg);
10542 +       dcfg.b.devspd = val;
10543 +       ifxusb_wreg(&_core_if->dev_global_regs->dcfg, dcfg.d32);
10544 +}
10545 +
10546 +
10547 +/*!
10548 + \brief This function enables the Device mode interrupts.
10549 + \param _core_if        Pointer of core_if structure
10550 + */
10551 +void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if)
10552 +{
10553 +       gint_data_t intr_mask ={ .d32 = 0};
10554 +       ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
10555 +
10556 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
10557 +       IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__);
10558 +
10559 +       /* Clear any pending OTG Interrupts */
10560 +       ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF);
10561 +
10562 +       /* Clear any pending interrupts */
10563 +       ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF);
10564 +
10565 +       /* Enable the interrupts in the GINTMSK.*/
10566 +       intr_mask.b.modemismatch = 1;
10567 +       intr_mask.b.conidstschng = 1;
10568 +       intr_mask.b.wkupintr = 1;
10569 +       intr_mask.b.disconnect = 1;
10570 +       intr_mask.b.usbsuspend = 1;
10571 +
10572 +       intr_mask.b.usbreset = 1;
10573 +       intr_mask.b.enumdone = 1;
10574 +       intr_mask.b.inepintr = 1;
10575 +       intr_mask.b.outepintr = 1;
10576 +       intr_mask.b.erlysuspend = 1;
10577 +       #ifndef __DED_FIFO__
10578 +//             intr_mask.b.epmismatch = 1;
10579 +       #endif
10580 +
10581 +       ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
10582 +       IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk));
10583 +}
10584 +
10585 +/*!
10586 + \brief Gets the current USB frame number. This is the frame number from the last SOF packet.
10587 + \param _core_if        Pointer of core_if structure
10588 + */
10589 +uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if)
10590 +{
10591 +       dsts_data_t dsts;
10592 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
10593 +       dsts.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dsts);
10594 +       /* read current frame/microfreme number from DSTS register */
10595 +       return dsts.b.soffn;
10596 +}
10597 +
10598 +
10599 +/*!
10600 + \brief  Set the EP STALL.
10601 + */
10602 +void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in)
10603 +{
10604 +       depctl_data_t depctl;
10605 +       volatile uint32_t *depctl_addr;
10606 +
10607 +       IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT"));
10608 +
10609 +       depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)):
10610 +                               (&(_core_if->out_ep_regs[_epno]->doepctl));
10611 +       depctl.d32 = ifxusb_rreg(depctl_addr);
10612 +       depctl.b.stall = 1;
10613 +
10614 +       if (_is_in && depctl.b.epena)
10615 +               depctl.b.epdis = 1;
10616 +
10617 +       ifxusb_wreg(depctl_addr, depctl.d32);
10618 +       IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr));
10619 +       return;
10620 +}
10621 +
10622 +/*!
10623 +\brief  Clear the EP STALL.
10624 + */
10625 +void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in)
10626 +{
10627 +       depctl_data_t depctl;
10628 +       volatile uint32_t *depctl_addr;
10629 +
10630 +       IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT"));
10631 +
10632 +       depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)):
10633 +                               (&(_core_if->out_ep_regs[_epno]->doepctl));
10634 +
10635 +       depctl.d32 = ifxusb_rreg(depctl_addr);
10636 +       /* clear the stall bits */
10637 +       depctl.b.stall = 0;
10638 +
10639 +       /*
10640 +        * USB Spec 9.4.5: For endpoints using data toggle, regardless
10641 +        * of whether an endpoint has the Halt feature set, a
10642 +        * ClearFeature(ENDPOINT_HALT) request always results in the
10643 +        * data toggle being reinitialized to DATA0.
10644 +        */
10645 +       if (_ep_type == IFXUSB_EP_TYPE_INTR || _ep_type == IFXUSB_EP_TYPE_BULK)
10646 +               depctl.b.setd0pid = 1; /* DATA0 */
10647 +
10648 +       ifxusb_wreg(depctl_addr, depctl.d32);
10649 +       IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr));
10650 +       return;
10651 +}
10652 +
10653 +/*!
10654 +   \brief This function initializes the IFXUSB controller registers for Device mode.
10655 + This function flushes the Tx and Rx FIFOs and it flushes any entries in the
10656 + request queues.
10657 +   \param _core_if        Pointer of core_if structure
10658 +   \param _params         parameters to be set
10659 + */
10660 +void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t  *_params)
10661 +{
10662 +       ifxusb_core_global_regs_t *global_regs =  _core_if->core_global_regs;
10663 +
10664 +       gusbcfg_data_t usbcfg   ={.d32 = 0};
10665 +       gahbcfg_data_t ahbcfg   ={.d32 = 0};
10666 +       dcfg_data_t    dcfg     ={.d32 = 0};
10667 +       grstctl_t      resetctl ={.d32 = 0};
10668 +       gotgctl_data_t gotgctl  ={.d32 = 0};
10669 +
10670 +       uint32_t dir;
10671 +       int i;
10672 +
10673 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
10674 +       IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if);
10675 +
10676 +       /* Copy Params */
10677 +       _core_if->params.dma_burst_size      =  _params->dma_burst_size;
10678 +       _core_if->params.speed               =  _params->speed;
10679 +       if(_params->max_transfer_size < 2048 || _params->max_transfer_size > ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1) )
10680 +               _core_if->params.max_transfer_size = ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1);
10681 +       else
10682 +               _core_if->params.max_transfer_size = _params->max_transfer_size;
10683 +
10684 +       if(_params->max_packet_count < 16 || _params->max_packet_count > ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1) )
10685 +               _core_if->params.max_packet_count= ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
10686 +       else
10687 +               _core_if->params.max_packet_count=  _params->max_packet_count;
10688 +       _core_if->params.phy_utmi_width      =  _params->phy_utmi_width;
10689 +       _core_if->params.turn_around_time_hs =  _params->turn_around_time_hs;
10690 +       _core_if->params.turn_around_time_fs =  _params->turn_around_time_fs;
10691 +       _core_if->params.timeout_cal_hs      =  _params->timeout_cal_hs;
10692 +       _core_if->params.timeout_cal_fs      =  _params->timeout_cal_fs;
10693 +
10694 +       #ifdef __DED_FIFO__
10695 +               _core_if->params.thr_ctl         =  _params->thr_ctl;
10696 +               _core_if->params.tx_thr_length   =  _params->tx_thr_length;
10697 +               _core_if->params.rx_thr_length   =  _params->rx_thr_length;
10698 +       #endif
10699 +
10700 +       /* Reset the Controller */
10701 +       do
10702 +       {
10703 +               while(ifxusb_core_soft_reset( _core_if ))
10704 +                       ifxusb_hard_reset(_core_if);
10705 +       } while (ifxusb_is_host_mode(_core_if));
10706 +
10707 +       usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg);
10708 +       #if 0
10709 +       #if defined(__DED_FIFO__)
10710 +               usbcfg.b.ForceDevMode = 1;
10711 +               usbcfg.b.ForceHstMode = 0;
10712 +       #endif
10713 +       #endif
10714 +       usbcfg.b.term_sel_dl_pulse = 0;
10715 +       ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32);
10716 +
10717 +       /* This programming sequence needs to happen in FS mode before any other
10718 +        * programming occurs */
10719 +       /* High speed PHY. */
10720 +       if (!_core_if->phy_init_done)
10721 +       {
10722 +               _core_if->phy_init_done = 1;
10723 +               /* HS PHY parameters.  These parameters are preserved
10724 +                * during soft reset so only program the first time.  Do
10725 +                * a soft reset immediately after setting phyif.  */
10726 +               usbcfg.b.ulpi_utmi_sel = 0; //UTMI+
10727 +               usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0;
10728 +               ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
10729 +               /* Reset after setting the PHY parameters */
10730 +               ifxusb_core_soft_reset( _core_if );
10731 +       }
10732 +
10733 +       /* Program the GAHBCFG Register.*/
10734 +       switch (_core_if->params.dma_burst_size)
10735 +       {
10736 +               case 0 :
10737 +                       ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE;
10738 +                       break;
10739 +               case 1 :
10740 +                       ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR;
10741 +                       break;
10742 +               case 4 :
10743 +                       ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4;
10744 +                       break;
10745 +               case 8 :
10746 +                       ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8;
10747 +                       break;
10748 +               case 16:
10749 +                       ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16;
10750 +                       break;
10751 +       }
10752 +       ahbcfg.b.dmaenable = 1;
10753 +       ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32);
10754 +
10755 +       /* Program the GUSBCFG register. */
10756 +       usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg );
10757 +       usbcfg.b.hnpcap = 0;
10758 +       usbcfg.b.srpcap = 0;
10759 +       ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
10760 +
10761 +       /* Restart the Phy Clock */
10762 +       ifxusb_wreg(_core_if->pcgcctl, 0);
10763 +
10764 +       /* Device configuration register */
10765 +       ifxusb_dev_init_spd(_core_if);
10766 +       dcfg.d32 = ifxusb_rreg( &_core_if->dev_global_regs->dcfg);
10767 +       dcfg.b.perfrint = IFXUSB_DCFG_FRAME_INTERVAL_80;
10768 +       #if defined(__DED_FIFO__)
10769 +               #if defined(__DESC_DMA__)
10770 +                       dcfg.b.descdma = 1;
10771 +               #else
10772 +                       dcfg.b.descdma = 0;
10773 +               #endif
10774 +       #endif
10775 +
10776 +       ifxusb_wreg( &_core_if->dev_global_regs->dcfg, dcfg.d32 );
10777 +
10778 +       /* Configure data FIFO sizes */
10779 +       _core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth;
10780 +       _core_if->params.rx_fifo_size   = ifxusb_rreg(&global_regs->grxfsiz);
10781 +       IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n"   , _core_if->params.data_fifo_size);
10782 +       IFX_DEBUGPL(DBG_CIL, "         Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size);
10783 +
10784 +       _core_if->params.tx_fifo_size[0]= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16;
10785 +
10786 +       #ifdef __DED_FIFO__
10787 +               for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
10788 +                       _core_if->params.tx_fifo_size[i] =
10789 +                               ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]) >> 16;
10790 +       #else
10791 +               for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
10792 +                       _core_if->params.tx_fifo_size[i+1] =
10793 +                               ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
10794 +       #endif
10795 +
10796 +       #ifdef __DEBUG__
10797 +               #ifdef __DED_FIFO__
10798 +                       for (i=0; i <= _core_if->hwcfg4.b.num_in_eps; i++)
10799 +                               IFX_DEBUGPL(DBG_CIL, "         Tx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i]);
10800 +               #else
10801 +                       IFX_DEBUGPL(DBG_CIL, "         NPTx FIFO Size=0x%06X\n", _core_if->params.tx_fifo_size[0]);
10802 +                       for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
10803 +                               IFX_DEBUGPL(DBG_CIL, "         PTx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i+1]);
10804 +               #endif
10805 +       #endif
10806 +
10807 +       {
10808 +               fifosize_data_t txfifosize;
10809 +               if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size)
10810 +                       _core_if->params.data_fifo_size = _params->data_fifo_size;
10811 +
10812 +
10813 +               if(_params->rx_fifo_size >=0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size)
10814 +                       _core_if->params.rx_fifo_size = _params->rx_fifo_size;
10815 +               if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size)
10816 +                       _core_if->params.rx_fifo_size = _core_if->params.data_fifo_size;
10817 +               ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size);
10818 +
10819 +               for (i=0; i < MAX_EPS_CHANNELS; i++)
10820 +                       if(_params->tx_fifo_size[i] >=0 && _params->tx_fifo_size[i] < _core_if->params.tx_fifo_size[i])
10821 +                               _core_if->params.tx_fifo_size[i] = _params->tx_fifo_size[i];
10822 +
10823 +               txfifosize.b.startaddr = _core_if->params.rx_fifo_size;
10824 +               #ifdef __DED_FIFO__
10825 +                       if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size)
10826 +                               _core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
10827 +                       txfifosize.b.depth=_core_if->params.tx_fifo_size[0];
10828 +                       ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
10829 +                       txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0];
10830 +                       for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
10831 +                       {
10832 +                               if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i] > _core_if->params.data_fifo_size)
10833 +                                       _core_if->params.tx_fifo_size[i]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
10834 +                               txfifosize.b.depth=_core_if->params.tx_fifo_size[i];
10835 +                               ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i-1], txfifosize.d32);
10836 +                               txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i];
10837 +                       }
10838 +               #else
10839 +                       if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size)
10840 +                               _core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
10841 +                       txfifosize.b.depth=_core_if->params.tx_fifo_size[0];
10842 +                       ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
10843 +                       txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0];
10844 +                       for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
10845 +                       {
10846 +                               if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i+1] > _core_if->params.data_fifo_size)
10847 +                                       _core_if->params.tx_fifo_size[i+1]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
10848 +                               //txfifosize.b.depth=_core_if->params.tx_fifo_size[i+1];
10849 +                               ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i], txfifosize.d32);
10850 +                               txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i+1];
10851 +                       }
10852 +               #endif
10853 +       }
10854 +
10855 +       #ifdef __DEBUG__
10856 +       {
10857 +               fifosize_data_t fifosize;
10858 +               IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n"   , _core_if->params.data_fifo_size);
10859 +
10860 +               IFX_DEBUGPL(DBG_CIL, "         Rx FIFO =0x%06X Sz=0x%06X\n", 0,ifxusb_rreg(&global_regs->grxfsiz));
10861 +               #ifdef __DED_FIFO__
10862 +                       fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
10863 +                       IFX_DEBUGPL(DBG_CIL, "         Tx[00] FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
10864 +                       for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
10865 +                       {
10866 +                               fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]);
10867 +                               IFX_DEBUGPL(DBG_CIL, "         Tx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth);
10868 +                       }
10869 +               #else
10870 +                       fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
10871 +                       IFX_DEBUGPL(DBG_CIL, "         NPTx FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
10872 +                       for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
10873 +                       {
10874 +                               fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]);
10875 +                               IFX_DEBUGPL(DBG_CIL, "         PTx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth);
10876 +                       }
10877 +               #endif
10878 +       }
10879 +       #endif
10880 +
10881 +       /* Clear Host Set HNP Enable in the OTG Control Register */
10882 +       gotgctl.b.hstsethnpen = 1;
10883 +       ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0);
10884 +
10885 +       /* Flush the FIFOs */
10886 +       ifxusb_flush_tx_fifo(_core_if, 0x10);  /* all Tx FIFOs */
10887 +       ifxusb_flush_rx_fifo(_core_if);
10888 +
10889 +       /* Flush the Learning Queue. */
10890 +       resetctl.b.intknqflsh = 1;
10891 +       ifxusb_wreg( &global_regs->grstctl, resetctl.d32);
10892 +
10893 +       /* Clear all pending Device Interrupts */
10894 +       ifxusb_wreg( &_core_if->dev_global_regs->diepmsk , 0 );
10895 +       ifxusb_wreg( &_core_if->dev_global_regs->doepmsk , 0 );
10896 +       ifxusb_wreg( &_core_if->dev_global_regs->daint   , 0xFFFFFFFF );
10897 +       ifxusb_wreg( &_core_if->dev_global_regs->daintmsk, 0 );
10898 +
10899 +       dir=_core_if->hwcfg1.d32;
10900 +       for (i=0; i <= _core_if->hwcfg2.b.num_dev_ep ; i++,dir>>=2)
10901 +       {
10902 +               depctl_data_t depctl;
10903 +               if((dir&0x03)==0 || (dir&0x03) ==1)
10904 +               {
10905 +                       depctl.d32 = ifxusb_rreg(&_core_if->in_ep_regs[i]->diepctl);
10906 +                       if (depctl.b.epena)
10907 +                       {
10908 +                               depctl.d32 = 0;
10909 +                               depctl.b.epdis = 1;
10910 +                               depctl.b.snak = 1;
10911 +                       }
10912 +                       else
10913 +                               depctl.d32 = 0;
10914 +                       ifxusb_wreg( &_core_if->in_ep_regs[i]->diepctl, depctl.d32);
10915 +                       #ifndef __DESC_DMA__
10916 +                               ifxusb_wreg( &_core_if->in_ep_regs[i]->dieptsiz, 0);
10917 +                       #endif
10918 +                       ifxusb_wreg( &_core_if->in_ep_regs[i]->diepdma, 0);
10919 +                       ifxusb_wreg( &_core_if->in_ep_regs[i]->diepint, 0xFF);
10920 +               }
10921 +
10922 +               if((dir&0x03)==0 || (dir&0x03) ==2)
10923 +               {
10924 +                       depctl.d32 = ifxusb_rreg(&_core_if->out_ep_regs[i]->doepctl);
10925 +                       if (depctl.b.epena)
10926 +                       {
10927 +                               depctl.d32 = 0;
10928 +                               depctl.b.epdis = 1;
10929 +                               depctl.b.snak = 1;
10930 +                       }
10931 +                       else
10932 +                               depctl.d32 = 0;
10933 +                       ifxusb_wreg( &_core_if->out_ep_regs[i]->doepctl, depctl.d32);
10934 +                       #ifndef __DESC_DMA__
10935 +                               ifxusb_wreg( &_core_if->out_ep_regs[i]->doeptsiz, 0);
10936 +                       #endif
10937 +                       ifxusb_wreg( &_core_if->out_ep_regs[i]->doepdma, 0);
10938 +                       ifxusb_wreg( &_core_if->out_ep_regs[i]->doepint, 0xFF);
10939 +               }
10940 +       }
10941 +}
10942 +
10943 --- /dev/null
10944 +++ b/drivers/usb/ifxhcd/ifxusb_cif_h.c
10945 @@ -0,0 +1,846 @@
10946 +/*****************************************************************************
10947 + **   FILE NAME       : ifxusb_cif_h.c
10948 + **   PROJECT         : IFX USB sub-system V3
10949 + **   MODULES         : IFX USB sub-system Host and Device driver
10950 + **   SRC VERSION     : 1.0
10951 + **   DATE            : 1/Jan/2009
10952 + **   AUTHOR          : Chen, Howard
10953 + **   DESCRIPTION     : The Core Interface provides basic services for accessing and
10954 + **                     managing the IFX USB hardware. These services are used by the
10955 + **                     Host Controller Driver only.
10956 + *****************************************************************************/
10957 +
10958 +/*!
10959 + \file ifxusb_cif_h.c
10960 + \ingroup IFXUSB_DRIVER_V3
10961 + \brief This file contains the interface to the IFX USB Core.
10962 +*/
10963 +#include <linux/version.h>
10964 +#include "ifxusb_version.h"
10965 +
10966 +#include <asm/byteorder.h>
10967 +#include <asm/unaligned.h>
10968 +
10969 +#ifdef __DEBUG__
10970 +       #include <linux/jiffies.h>
10971 +#endif
10972 +#include <linux/platform_device.h>
10973 +#include <linux/kernel.h>
10974 +#include <linux/ioport.h>
10975 +#if defined(__UEIP__)
10976 +//     #include <asm/ifx/ifx_board.h>
10977 +#endif
10978 +
10979 +//#include <asm/ifx/ifx_gpio.h>
10980 +#if defined(__UEIP__)
10981 +//     #include <asm/ifx/ifx_led.h>
10982 +#endif
10983 +
10984 +#include "ifxusb_plat.h"
10985 +#include "ifxusb_regs.h"
10986 +#include "ifxusb_cif.h"
10987 +
10988 +#include "ifxhcd.h"
10989 +
10990 +#if !defined(__UEIP__)
10991 +       #undef __USING_LED_AS_GPIO__
10992 +#endif
10993 +
10994 +
10995 +/*!
10996 + \brief This function enables the Host mode interrupts.
10997 + \param _core_if        Pointer of core_if structure
10998 + */
10999 +void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if)
11000 +{
11001 +       gint_data_t intr_mask ={ .d32 = 0};
11002 +       ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
11003 +
11004 +       IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__);
11005 +
11006 +       /* Clear any pending OTG Interrupts */
11007 +       ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF);
11008 +
11009 +       /* Clear any pending interrupts */
11010 +       ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF);
11011 +
11012 +       /* Enable the interrupts in the GINTMSK.*/
11013 +
11014 +       /* Common interrupts */
11015 +       intr_mask.b.modemismatch = 1;
11016 +       intr_mask.b.conidstschng = 1;
11017 +       intr_mask.b.wkupintr = 1;
11018 +       intr_mask.b.disconnect = 1;
11019 +       intr_mask.b.usbsuspend = 1;
11020 +
11021 +       /* Host interrupts */
11022 +       intr_mask.b.sofintr = 1;
11023 +       intr_mask.b.portintr = 1;
11024 +       intr_mask.b.hcintr = 1;
11025 +
11026 +       ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
11027 +       IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk));
11028 +}
11029 +
11030 +/*!
11031 + \brief This function disables the Host mode interrupts.
11032 + \param _core_if        Pointer of core_if structure
11033 + */
11034 +void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if)
11035 +{
11036 +       ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
11037 +
11038 +       IFX_DEBUGPL(DBG_CILV, "%s()\n", __func__);
11039 +
11040 +       #if 1
11041 +               ifxusb_wreg( &global_regs->gintmsk, 0);
11042 +       #else
11043 +               /* Common interrupts */
11044 +               {
11045 +                       gint_data_t intr_mask ={.d32 = 0};
11046 +                       intr_mask.b.modemismatch = 1;
11047 +                       intr_mask.b.rxstsqlvl = 1;
11048 +                       intr_mask.b.conidstschng = 1;
11049 +                       intr_mask.b.wkupintr = 1;
11050 +                       intr_mask.b.disconnect = 1;
11051 +                       intr_mask.b.usbsuspend = 1;
11052 +
11053 +                       /* Host interrupts */
11054 +                       intr_mask.b.sofintr = 1;
11055 +                       intr_mask.b.portintr = 1;
11056 +                       intr_mask.b.hcintr = 1;
11057 +                       intr_mask.b.ptxfempty = 1;
11058 +                       intr_mask.b.nptxfempty = 1;
11059 +                       ifxusb_mreg(&global_regs->gintmsk, intr_mask.d32, 0);
11060 +               }
11061 +       #endif
11062 +}
11063 +
11064 +/*!
11065 + \brief This function initializes the IFXUSB controller registers for  Host mode.
11066 +        This function flushes the Tx and Rx FIFOs and it flushes any entries in the
11067 +        request queues.
11068 + \param _core_if        Pointer of core_if structure
11069 + \param _params         parameters to be set
11070 + */
11071 +void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t  *_params)
11072 +{
11073 +       ifxusb_core_global_regs_t *global_regs =  _core_if->core_global_regs;
11074 +
11075 +       gusbcfg_data_t usbcfg   ={.d32 = 0};
11076 +       gahbcfg_data_t ahbcfg   ={.d32 = 0};
11077 +       gotgctl_data_t gotgctl  ={.d32 = 0};
11078 +
11079 +       int i;
11080 +
11081 +       IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if);
11082 +
11083 +       /* Copy Params */
11084 +
11085 +       _core_if->params.dma_burst_size      =  _params->dma_burst_size;
11086 +       _core_if->params.speed               =  _params->speed;
11087 +       _core_if->params.max_transfer_size   =  _params->max_transfer_size;
11088 +       _core_if->params.max_packet_count    =  _params->max_packet_count;
11089 +       _core_if->params.phy_utmi_width      =  _params->phy_utmi_width;
11090 +       _core_if->params.turn_around_time_hs =  _params->turn_around_time_hs;
11091 +       _core_if->params.turn_around_time_fs =  _params->turn_around_time_fs;
11092 +       _core_if->params.timeout_cal_hs      =  _params->timeout_cal_hs;
11093 +       _core_if->params.timeout_cal_fs      =  _params->timeout_cal_fs;
11094 +
11095 +       /* Reset the Controller */
11096 +       do
11097 +       {
11098 +               while(ifxusb_core_soft_reset( _core_if ))
11099 +                       ifxusb_hard_reset(_core_if);
11100 +       } while (ifxusb_is_device_mode(_core_if));
11101 +
11102 +       usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg);
11103 +//     usbcfg.b.ulpi_ext_vbus_drv = 1;
11104 +       usbcfg.b.term_sel_dl_pulse = 0;
11105 +       ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32);
11106 +
11107 +       /* This programming sequence needs to happen in FS mode before any other
11108 +        * programming occurs */
11109 +       /* High speed PHY. */
11110 +       if (!_core_if->phy_init_done)
11111 +       {
11112 +               _core_if->phy_init_done = 1;
11113 +               /* HS PHY parameters.  These parameters are preserved
11114 +                * during soft reset so only program the first time.  Do
11115 +                * a soft reset immediately after setting phyif.  */
11116 +               usbcfg.b.ulpi_utmi_sel = 0; //UTMI+
11117 +               usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0;
11118 +               ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
11119 +               /* Reset after setting the PHY parameters */
11120 +               ifxusb_core_soft_reset( _core_if );
11121 +       }
11122 +
11123 +       usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg);
11124 +//     usbcfg.b.ulpi_fsls = 0;
11125 +//     usbcfg.b.ulpi_clk_sus_m = 0;
11126 +       ifxusb_wreg(&global_regs->gusbcfg, usbcfg.d32);
11127 +
11128 +       /* Program the GAHBCFG Register.*/
11129 +       switch (_core_if->params.dma_burst_size)
11130 +       {
11131 +               case 0 :
11132 +                       ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE;
11133 +                       break;
11134 +               case 1 :
11135 +                       ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR;
11136 +                       break;
11137 +               case 4 :
11138 +                       ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4;
11139 +                       break;
11140 +               case 8 :
11141 +                       ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8;
11142 +                       break;
11143 +               case 16:
11144 +                       ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16;
11145 +                       break;
11146 +       }
11147 +       ahbcfg.b.dmaenable = 1;
11148 +       ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32);
11149 +
11150 +       /* Program the GUSBCFG register. */
11151 +       usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg );
11152 +       usbcfg.b.hnpcap = 0;
11153 +       usbcfg.b.srpcap = 0;
11154 +       ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
11155 +
11156 +       /* Restart the Phy Clock */
11157 +       ifxusb_wreg(_core_if->pcgcctl, 0);
11158 +
11159 +       /* Initialize Host Configuration Register */
11160 +       {
11161 +               hcfg_data_t     hcfg;
11162 +               hcfg.d32 = ifxusb_rreg(&_core_if->host_global_regs->hcfg);
11163 +               hcfg.b.fslspclksel = IFXUSB_HCFG_30_60_MHZ;
11164 +               if (_params->speed == IFXUSB_PARAM_SPEED_FULL)
11165 +                       hcfg.b.fslssupp = 1;
11166 +               ifxusb_wreg(&_core_if->host_global_regs->hcfg, hcfg.d32);
11167 +       }
11168 +
11169 +       _core_if->params.host_channels=(_core_if->hwcfg2.b.num_host_chan + 1);
11170 +
11171 +       if(_params->host_channels>0 && _params->host_channels < _core_if->params.host_channels)
11172 +               _core_if->params.host_channels = _params->host_channels;
11173 +
11174 +       /* Configure data FIFO sizes */
11175 +       _core_if->params.data_fifo_size     = _core_if->hwcfg3.b.dfifo_depth;
11176 +       _core_if->params.rx_fifo_size       = ifxusb_rreg(&global_regs->grxfsiz);
11177 +       _core_if->params.nperio_tx_fifo_size= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16;
11178 +       _core_if->params.perio_tx_fifo_size = ifxusb_rreg(&global_regs->hptxfsiz) >> 16;
11179 +       IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n"   , _core_if->params.data_fifo_size);
11180 +       IFX_DEBUGPL(DBG_CIL, "           Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size);
11181 +       IFX_DEBUGPL(DBG_CIL, "         NPTx FIFO Size=0x%06X\n", _core_if->params.nperio_tx_fifo_size);
11182 +       IFX_DEBUGPL(DBG_CIL, "          PTx FIFO Size=0x%06X\n", _core_if->params.perio_tx_fifo_size);
11183 +
11184 +       {
11185 +               fifosize_data_t txfifosize;
11186 +               if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size)
11187 +                       _core_if->params.data_fifo_size = _params->data_fifo_size;
11188 +
11189 +               if( _params->rx_fifo_size >= 0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size)
11190 +                       _core_if->params.rx_fifo_size = _params->rx_fifo_size;
11191 +               if( _params->nperio_tx_fifo_size >=0 && _params->nperio_tx_fifo_size < _core_if->params.nperio_tx_fifo_size)
11192 +                       _core_if->params.nperio_tx_fifo_size = _params->nperio_tx_fifo_size;
11193 +               if( _params->perio_tx_fifo_size >=0 && _params->perio_tx_fifo_size < _core_if->params.perio_tx_fifo_size)
11194 +                       _core_if->params.perio_tx_fifo_size = _params->perio_tx_fifo_size;
11195 +
11196 +               if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size)
11197 +                       _core_if->params.rx_fifo_size = _core_if->params.data_fifo_size;
11198 +               ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size);
11199 +               txfifosize.b.startaddr = _core_if->params.rx_fifo_size;
11200 +
11201 +               if(txfifosize.b.startaddr + _core_if->params.nperio_tx_fifo_size > _core_if->params.data_fifo_size)
11202 +                       _core_if->params.nperio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr;
11203 +               txfifosize.b.depth=_core_if->params.nperio_tx_fifo_size;
11204 +               ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
11205 +               txfifosize.b.startaddr += _core_if->params.nperio_tx_fifo_size;
11206 +
11207 +               if(txfifosize.b.startaddr + _core_if->params.perio_tx_fifo_size > _core_if->params.data_fifo_size)
11208 +                       _core_if->params.perio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr;
11209 +               txfifosize.b.depth=_core_if->params.perio_tx_fifo_size;
11210 +               ifxusb_wreg( &global_regs->hptxfsiz, txfifosize.d32);
11211 +               txfifosize.b.startaddr += _core_if->params.perio_tx_fifo_size;
11212 +       }
11213 +
11214 +       #ifdef __DEBUG__
11215 +       {
11216 +               fifosize_data_t fifosize;
11217 +               IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n"   , _core_if->params.data_fifo_size);
11218 +
11219 +               fifosize.d32=ifxusb_rreg(&global_regs->grxfsiz);
11220 +               IFX_DEBUGPL(DBG_CIL, "         Rx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
11221 +               fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
11222 +               IFX_DEBUGPL(DBG_CIL, "         NPTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
11223 +               fifosize.d32=ifxusb_rreg(&global_regs->hptxfsiz);
11224 +               IFX_DEBUGPL(DBG_CIL, "          PTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
11225 +       }
11226 +       #endif
11227 +
11228 +       /* Clear Host Set HNP Enable in the OTG Control Register */
11229 +       gotgctl.b.hstsethnpen = 1;
11230 +       ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0);
11231 +
11232 +       /* Flush the FIFOs */
11233 +       ifxusb_flush_tx_fifo(_core_if, 0x10);  /* all Tx FIFOs */
11234 +       ifxusb_flush_rx_fifo(_core_if);
11235 +
11236 +       for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++)
11237 +       {
11238 +               hcchar_data_t    hcchar;
11239 +               hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar);
11240 +               hcchar.b.chen  = 0;
11241 +               hcchar.b.chdis = 1;
11242 +               hcchar.b.epdir = 0;
11243 +               ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32);
11244 +       }
11245 +       /* Halt all channels to put them into a known state. */
11246 +       for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++)
11247 +       {
11248 +               hcchar_data_t    hcchar;
11249 +               int count = 0;
11250 +
11251 +               hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar);
11252 +               hcchar.b.chen  = 1;
11253 +               hcchar.b.chdis = 1;
11254 +               hcchar.b.epdir = 0;
11255 +               ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32);
11256 +
11257 +               IFX_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
11258 +               do{
11259 +                       hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar);
11260 +                       if (++count > 1000)
11261 +                       {
11262 +                               IFX_ERROR("%s: Unable to clear halt on channel %d\n", __func__, i);
11263 +                               break;
11264 +                       }
11265 +               } while (hcchar.b.chen);
11266 +       }
11267 +}
11268 +
11269 +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
11270 +
11271 +#if defined(__UEIP__)
11272 +       #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
11273 +               int ifxusb_vbus_status =-1;
11274 +       #endif
11275 +
11276 +       #if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
11277 +               int ifxusb_vbus1_status =-1;
11278 +       #endif
11279 +
11280 +       #if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
11281 +               int ifxusb_vbus2_status =-1;
11282 +       #endif
11283 +
11284 +       #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
11285 +               static void *g_usb_vbus_trigger  = NULL;
11286 +       #endif
11287 +       #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
11288 +               static void *g_usb_vbus1_trigger = NULL;
11289 +       #endif
11290 +       #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
11291 +               static void *g_usb_vbus2_trigger = NULL;
11292 +       #endif
11293 +
11294 +       #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
11295 +               int ifxusb_vbus_gpio_inited=0;
11296 +       #endif
11297 +
11298 +#else //defined(__UEIP__)
11299 +       int ifxusb_vbus_gpio_inited=0;
11300 +#endif
11301 +
11302 +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
11303 +
11304 +void ifxusb_vbus_init(ifxusb_core_if_t *_core_if)
11305 +{
11306 +       #if defined(__UEIP__)
11307 +               #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
11308 +                       if ( !g_usb_vbus_trigger )
11309 +                       {
11310 +                               ifx_led_trigger_register("USB_VBUS", &g_usb_vbus_trigger);
11311 +                               if ( g_usb_vbus_trigger != NULL )
11312 +                               {
11313 +                                       struct ifx_led_trigger_attrib attrib = {0};
11314 +                                       attrib.delay_on     = 0;
11315 +                                       attrib.delay_off    = 0;
11316 +                                       attrib.timeout      = 0;
11317 +                                       attrib.def_value    = 0;
11318 +                                       attrib.flags        = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
11319 +                                       IFX_DEBUGP("Reg USB power!!\n");
11320 +                                       ifx_led_trigger_set_attrib(g_usb_vbus_trigger, &attrib);
11321 +                                       ifxusb_vbus_status =0;
11322 +                               }
11323 +                       }
11324 +               #endif
11325 +               #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
11326 +                       if(_core_if->core_no==0 && !g_usb_vbus1_trigger )
11327 +                       {
11328 +                               ifx_led_trigger_register("USB_VBUS1", &g_usb_vbus1_trigger);
11329 +                               if ( g_usb_vbus1_trigger != NULL )
11330 +                               {
11331 +                                       struct ifx_led_trigger_attrib attrib = {0};
11332 +                                       attrib.delay_on     = 0;
11333 +                                       attrib.delay_off    = 0;
11334 +                                       attrib.timeout      = 0;
11335 +                                       attrib.def_value    = 0;
11336 +                                       attrib.flags        = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
11337 +                                       IFX_DEBUGP("Reg USB1 power!!\n");
11338 +                                       ifx_led_trigger_set_attrib(g_usb_vbus1_trigger, &attrib);
11339 +                                       ifxusb_vbus1_status =0;
11340 +                               }
11341 +                       }
11342 +               #endif
11343 +               #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
11344 +                       if(_core_if->core_no==1 && !g_usb_vbus2_trigger )
11345 +                       {
11346 +                               ifx_led_trigger_register("USB_VBUS2", &g_usb_vbus2_trigger);
11347 +                               if ( g_usb_vbus2_trigger != NULL )
11348 +                               {
11349 +                                       struct ifx_led_trigger_attrib attrib = {0};
11350 +                                       attrib.delay_on     = 0;
11351 +                                       attrib.delay_off    = 0;
11352 +                                       attrib.timeout      = 0;
11353 +                                       attrib.def_value    = 0;
11354 +                                       attrib.flags        = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
11355 +                                       IFX_DEBUGP("Reg USB2 power!!\n");
11356 +                                       ifx_led_trigger_set_attrib(g_usb_vbus2_trigger, &attrib);
11357 +                                       ifxusb_vbus2_status =0;
11358 +                               }
11359 +                       }
11360 +               #endif
11361 +
11362 +               #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
11363 +                       /* == 20100712 AVM/WK use gpio_inited as bitmask == */
11364 +                       if(ifxusb_vbus_gpio_inited == 0)
11365 +                       {
11366 +                               if(!ifx_gpio_register(IFX_GPIO_MODULE_USB))
11367 +                               {
11368 +                                       IFX_DEBUGP("Register USB VBus through GPIO OK!!\n");
11369 +                                       #ifdef IFX_GPIO_USB_VBUS
11370 +                                               ifxusb_vbus_status =0;
11371 +                                       #endif //IFX_GPIO_USB_VBUS
11372 +                                       #ifdef IFX_GPIO_USB_VBUS1
11373 +                                               ifxusb_vbus1_status=0;
11374 +                                       #endif //IFX_GPIO_USB_VBUS1
11375 +                                       #ifdef IFX_GPIO_USB_VBUS2
11376 +                                               ifxusb_vbus2_status=0;
11377 +                                       #endif //IFX_GPIO_USB_VBUS2
11378 +                                       ifxusb_vbus_gpio_inited|= (1<<_core_if->core_no);
11379 +                               }
11380 +                               else
11381 +                                       IFX_PRINT("Register USB VBus Failed!!\n");
11382 +                       } else {
11383 +                               ifxusb_vbus_gpio_inited|= (1<<_core_if->core_no);
11384 +                       }
11385 +               #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
11386 +       #endif //defined(__UEIP__)
11387 +}
11388 +
11389 +void ifxusb_vbus_free(ifxusb_core_if_t *_core_if)
11390 +{
11391 +       #if defined(__UEIP__)
11392 +               #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
11393 +                       if ( g_usb_vbus_trigger )
11394 +                       {
11395 +                           ifx_led_trigger_deregister(g_usb_vbus_trigger);
11396 +                           g_usb_vbus_trigger = NULL;
11397 +                           ifxusb_vbus_status =-1;
11398 +                       }
11399 +               #endif
11400 +               #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
11401 +                       if(_core_if->core_no==0 && g_usb_vbus1_trigger )
11402 +                       {
11403 +                           ifx_led_trigger_deregister(g_usb_vbus1_trigger);
11404 +                           g_usb_vbus1_trigger = NULL;
11405 +                           ifxusb_vbus1_status =-1;
11406 +                       }
11407 +               #endif
11408 +               #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
11409 +                       if(_core_if->core_no==1 && g_usb_vbus2_trigger )
11410 +                       {
11411 +                           ifx_led_trigger_deregister(g_usb_vbus2_trigger);
11412 +                           g_usb_vbus2_trigger = NULL;
11413 +                           ifxusb_vbus2_status =-1;
11414 +                       }
11415 +               #endif
11416 +
11417 +               #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
11418 +                       /* == 20100712 AVM/WK use gpio_inited as bitmask == */
11419 +                       if((ifxusb_vbus_gpio_inited & (1<<_core_if->core_no)) == ifxusb_vbus_gpio_inited)
11420 +                       {
11421 +                               ifx_gpio_deregister(IFX_GPIO_MODULE_USB);
11422 +                               #ifdef IFX_GPIO_USB_VBUS
11423 +                                       ifxusb_vbus_status =-1;
11424 +                               #endif //IFX_GPIO_USB_VBUS
11425 +                               #ifdef IFX_GPIO_USB_VBUS1
11426 +                                       ifxusb_vbus1_status=-1;
11427 +                               #endif //IFX_GPIO_USB_VBUS1
11428 +                               #ifdef IFX_GPIO_USB_VBUS2
11429 +                                       ifxusb_vbus2_status=-1;
11430 +                               #endif //IFX_GPIO_USB_VBUS2
11431 +                       }
11432 +                       ifxusb_vbus_gpio_inited &= ~(1<<_core_if->core_no);
11433 +               #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
11434 +       #endif //defined(__UEIP__)
11435 +}
11436 +
11437 +
11438 +/*!
11439 +   \brief Turn on the USB 5V VBus Power
11440 +   \param _core_if        Pointer of core_if structure
11441 + */
11442 +void ifxusb_vbus_on(ifxusb_core_if_t *_core_if)
11443 +{
11444 +       IFX_DEBUGP("SENDING VBus POWER UP\n");
11445 +       #if defined(__UEIP__)
11446 +               #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
11447 +                       if ( g_usb_vbus_trigger && ifxusb_vbus_status==0)
11448 +                       {
11449 +                               ifx_led_trigger_activate(g_usb_vbus_trigger);
11450 +                               IFX_DEBUGP("Enable USB power!!\n");
11451 +                               ifxusb_vbus_status=1;
11452 +                       }
11453 +               #endif
11454 +               #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
11455 +                       if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==0)
11456 +                       {
11457 +                               ifx_led_trigger_activate(g_usb_vbus1_trigger);
11458 +                               IFX_DEBUGP("Enable USB1 power!!\n");
11459 +                               ifxusb_vbus1_status=1;
11460 +                       }
11461 +               #endif
11462 +               #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
11463 +                       if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==0)
11464 +                       {
11465 +                               ifx_led_trigger_activate(g_usb_vbus2_trigger);
11466 +                               IFX_DEBUGP("Enable USB2 power!!\n");
11467 +                               ifxusb_vbus2_status=1;
11468 +                       }
11469 +               #endif
11470 +
11471 +               #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
11472 +                       if(ifxusb_vbus_gpio_inited)
11473 +                       {
11474 +                               #if defined(IFX_GPIO_USB_VBUS)
11475 +                                       if(ifxusb_vbus_status==0)
11476 +                                       {
11477 +                                               ifx_gpio_output_set(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB);
11478 +                                               ifxusb_vbus_status=1;
11479 +                                       }
11480 +                               #endif
11481 +                               #if defined(IFX_GPIO_USB_VBUS1)
11482 +                                       if(_core_if->core_no==0 && ifxusb_vbus1_status==0)
11483 +                                       {
11484 +                                               ifx_gpio_output_set(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB);
11485 +                                               ifxusb_vbus1_status=1;
11486 +                                       }
11487 +                               #endif
11488 +                               #if defined(IFX_GPIO_USB_VBUS2)
11489 +                                       if(_core_if->core_no==1 && ifxusb_vbus2_status==0)
11490 +                                       {
11491 +                                               ifx_gpio_output_set(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB);
11492 +                                               ifxusb_vbus2_status=1;
11493 +                                       }
11494 +                               #endif
11495 +                       }
11496 +               #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
11497 +       #else
11498 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
11499 +                       ifxusb_vbus_status=1;
11500 +                       //usb_set_vbus_on();
11501 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
11502 +               #if defined(__IS_AMAZON_SE__)
11503 +                       set_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT);
11504 +                       ifxusb_vbus_status=1;
11505 +               #endif //defined(__IS_AMAZON_SE__)
11506 +               #if defined(__IS_AR9__)
11507 +                       if(_core_if->core_no==0)
11508 +                       {
11509 +                               if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0)
11510 +                               {
11511 +                                       IFX_PRINT("Can't enable USB1 5.5V power!!\n");
11512 +                                       return;
11513 +                               }
11514 +                               bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB);
11515 +                               bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB);
11516 +                               bsp_port_set_dir_out(1, 13, PORT_MODULE_USB);
11517 +                               bsp_port_set_pudsel(1, 13, PORT_MODULE_USB);
11518 +                               bsp_port_set_puden(1, 13, PORT_MODULE_USB);
11519 +                               bsp_port_set_output(1, 13, PORT_MODULE_USB);
11520 +                               IFX_DEBUGP("Enable USB1 power!!\n");
11521 +                               ifxusb_vbus1_status=1;
11522 +                       }
11523 +                       else
11524 +                       {
11525 +                               if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0)
11526 +                               {
11527 +                                       IFX_PRINT("Can't enable USB2 5.5V power!!\n");
11528 +                                       return;
11529 +                               }
11530 +                               bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB);
11531 +                               bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB);
11532 +                               bsp_port_set_dir_out(3, 4, PORT_MODULE_USB);
11533 +                               bsp_port_set_pudsel(3, 4, PORT_MODULE_USB);
11534 +                               bsp_port_set_puden(3, 4, PORT_MODULE_USB);
11535 +                               bsp_port_set_output(3, 4, PORT_MODULE_USB);
11536 +                               IFX_DEBUGP("Enable USB2 power!!\n");
11537 +                               ifxusb_vbus2_status=1;
11538 +                       }
11539 +               #endif //defined(__IS_AR9__)
11540 +               #if defined(__IS_VR9__)
11541 +                       if(_core_if->core_no==0)
11542 +                       {
11543 +                               ifxusb_vbus1_status=1;
11544 +                       }
11545 +                       else
11546 +                       {
11547 +                               ifxusb_vbus2_status=1;
11548 +                       }
11549 +               #endif //defined(__IS_VR9__)
11550 +       #endif //defined(__UEIP__)
11551 +}
11552 +
11553 +
11554 +/*!
11555 +   \brief Turn off the USB 5V VBus Power
11556 +   \param _core_if        Pointer of core_if structure
11557 + */
11558 +void ifxusb_vbus_off(ifxusb_core_if_t *_core_if)
11559 +{
11560 +       IFX_DEBUGP("SENDING VBus POWER OFF\n");
11561 +
11562 +       #if defined(__UEIP__)
11563 +               #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
11564 +                       if ( g_usb_vbus_trigger && ifxusb_vbus_status==1)
11565 +                       {
11566 +                               ifx_led_trigger_deactivate(g_usb_vbus_trigger);
11567 +                               IFX_DEBUGP("Disable USB power!!\n");
11568 +                               ifxusb_vbus_status=0;
11569 +                       }
11570 +               #endif
11571 +               #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
11572 +                       if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==1)
11573 +                       {
11574 +                               ifx_led_trigger_deactivate(g_usb_vbus1_trigger);
11575 +                               IFX_DEBUGP("Disable USB1 power!!\n");
11576 +                               ifxusb_vbus1_status=0;
11577 +                       }
11578 +               #endif
11579 +               #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
11580 +                       if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==1)
11581 +                       {
11582 +                               ifx_led_trigger_deactivate(g_usb_vbus2_trigger);
11583 +                               IFX_DEBUGP("Disable USB2 power!!\n");
11584 +                               ifxusb_vbus2_status=0;
11585 +                       }
11586 +               #endif
11587 +
11588 +               #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
11589 +                       if(ifxusb_vbus_gpio_inited)
11590 +                       {
11591 +                               #if defined(IFX_GPIO_USB_VBUS)
11592 +                                       if(ifxusb_vbus_status==1)
11593 +                                       {
11594 +                                               ifx_gpio_output_clear(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB);
11595 +                                               ifxusb_vbus_status=0;
11596 +                                       }
11597 +                               #endif
11598 +                               #if defined(IFX_GPIO_USB_VBUS1)
11599 +                                       if(_core_if->core_no==0 && ifxusb_vbus1_status==1)
11600 +                                       {
11601 +                                               ifx_gpio_output_clear(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB);
11602 +                                               ifxusb_vbus1_status=0;
11603 +                                       }
11604 +                               #endif
11605 +                               #if defined(IFX_GPIO_USB_VBUS2)
11606 +                                       if(_core_if->core_no==1 && ifxusb_vbus2_status==1)
11607 +                                       {
11608 +                                               ifx_gpio_output_clear(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB);
11609 +                                               ifxusb_vbus2_status=0;
11610 +                                       }
11611 +                               #endif
11612 +                       }
11613 +               #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
11614 +       #else
11615 +               #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
11616 +                       ifxusb_vbus_status=0;
11617 +                       //usb_set_vbus_on();
11618 +               #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
11619 +               #if defined(__IS_AMAZON_SE__)
11620 +                       clear_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT);
11621 +                       ifxusb_vbus_status=0;
11622 +               #endif //defined(__IS_AMAZON_SE__)
11623 +               #if defined(__IS_AR9__)
11624 +                       if(_core_if->core_no==0)
11625 +                       {
11626 +                               if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0) {
11627 +                                       IFX_PRINT("Can't Disable USB1 5.5V power!!\n");
11628 +                                       return;
11629 +                               }
11630 +                               bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB);
11631 +                               bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB);
11632 +                               bsp_port_set_dir_out(1, 13, PORT_MODULE_USB);
11633 +                               bsp_port_set_pudsel(1, 13, PORT_MODULE_USB);
11634 +                               bsp_port_set_puden(1, 13, PORT_MODULE_USB);
11635 +                               bsp_port_clear_output(1, 13, PORT_MODULE_USB);
11636 +                               IFX_DEBUGP("Disable USB1 power!!\n");
11637 +                               ifxusb_vbus1_status=0;
11638 +                       }
11639 +                       else
11640 +                       {
11641 +                               if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0) {
11642 +                                       IFX_PRINT("Can't Disable USB2 5.5V power!!\n");
11643 +                                       return;
11644 +                               }
11645 +                               bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB);
11646 +                               bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB);
11647 +                               bsp_port_set_dir_out(3, 4, PORT_MODULE_USB);
11648 +                               bsp_port_set_pudsel(3, 4, PORT_MODULE_USB);
11649 +                               bsp_port_set_puden(3, 4, PORT_MODULE_USB);
11650 +                               bsp_port_clear_output(3, 4, PORT_MODULE_USB);
11651 +                               IFX_DEBUGP("Disable USB2 power!!\n");
11652 +
11653 +                               ifxusb_vbus2_status=0;
11654 +                       }
11655 +               #endif //defined(__IS_AR9__)
11656 +               #if defined(__IS_VR9__)
11657 +                       if(_core_if->core_no==0)
11658 +                       {
11659 +                               ifxusb_vbus1_status=0;
11660 +                       }
11661 +                       else
11662 +                       {
11663 +                               ifxusb_vbus2_status=0;
11664 +                       }
11665 +               #endif //defined(__IS_VR9__)
11666 +       #endif //defined(__UEIP__)
11667 +}
11668 +
11669 +
11670 +
11671 +/*!
11672 +   \brief Read Current VBus status
11673 +   \param _core_if        Pointer of core_if structure
11674 + */
11675 +int ifxusb_vbus(ifxusb_core_if_t *_core_if)
11676 +{
11677 +#if defined(__UEIP__)
11678 +       #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
11679 +               return (ifxusb_vbus_status);
11680 +       #endif
11681 +
11682 +       #if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
11683 +               if(_core_if->core_no==0)
11684 +                       return (ifxusb_vbus1_status);
11685 +       #endif
11686 +
11687 +       #if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
11688 +               if(_core_if->core_no==1)
11689 +                       return (ifxusb_vbus2_status);
11690 +       #endif
11691 +#else //defined(__UEIP__)
11692 +#endif
11693 +       return -1;
11694 +}
11695 +
11696 +#if defined(__UEIP__)
11697 +#else
11698 +       #if defined(__IS_TWINPASS__)
11699 +               #define ADSL_BASE 0x20000
11700 +               #define CRI_BASE          0x31F00
11701 +               #define CRI_CCR0          CRI_BASE + 0x00
11702 +               #define CRI_CCR1          CRI_BASE + 0x01*4
11703 +               #define CRI_CDC0          CRI_BASE + 0x02*4
11704 +               #define CRI_CDC1          CRI_BASE + 0x03*4
11705 +               #define CRI_RST           CRI_BASE + 0x04*4
11706 +               #define CRI_MASK0         CRI_BASE + 0x05*4
11707 +               #define CRI_MASK1         CRI_BASE + 0x06*4
11708 +               #define CRI_MASK2         CRI_BASE + 0x07*4
11709 +               #define CRI_STATUS0       CRI_BASE + 0x08*4
11710 +               #define CRI_STATUS1       CRI_BASE + 0x09*4
11711 +               #define CRI_STATUS2       CRI_BASE + 0x0A*4
11712 +               #define CRI_AMASK0        CRI_BASE + 0x0B*4
11713 +               #define CRI_AMASK1        CRI_BASE + 0x0C*4
11714 +               #define CRI_UPDCTL        CRI_BASE + 0x0D*4
11715 +               #define CRI_MADST         CRI_BASE + 0x0E*4
11716 +               // 0x0f is missing
11717 +               #define CRI_EVENT0        CRI_BASE + 0x10*4
11718 +               #define CRI_EVENT1        CRI_BASE + 0x11*4
11719 +               #define CRI_EVENT2        CRI_BASE + 0x12*4
11720 +
11721 +               #define IRI_I_ENABLE    0x32000
11722 +               #define STY_SMODE       0x3c004
11723 +               #define AFE_TCR_0       0x3c0dc
11724 +               #define AFE_ADDR_ADDR   0x3c0e8
11725 +               #define AFE_RDATA_ADDR  0x3c0ec
11726 +               #define AFE_WDATA_ADDR  0x3c0f0
11727 +               #define AFE_CONFIG      0x3c0f4
11728 +               #define AFE_SERIAL_CFG  0x3c0fc
11729 +
11730 +               #define DFE_BASE_ADDR         0xBE116000
11731 +               //#define DFE_BASE_ADDR         0x9E116000
11732 +
11733 +               #define MEI_FR_ARCINT_C       (DFE_BASE_ADDR + 0x0000001C)
11734 +               #define MEI_DBG_WADDR_C       (DFE_BASE_ADDR + 0x00000024)
11735 +               #define MEI_DBG_RADDR_C       (DFE_BASE_ADDR + 0x00000028)
11736 +               #define MEI_DBG_DATA_C        (DFE_BASE_ADDR + 0x0000002C)
11737 +               #define MEI_DBG_DECO_C        (DFE_BASE_ADDR + 0x00000030)
11738 +               #define MEI_DBG_MASTER_C      (DFE_BASE_ADDR + 0x0000003C)
11739 +
11740 +               static void WriteARCmem(uint32_t addr, uint32_t data)
11741 +               {
11742 +                       writel(1    ,(volatile uint32_t *)MEI_DBG_MASTER_C);
11743 +                       writel(1    ,(volatile uint32_t *)MEI_DBG_DECO_C  );
11744 +                       writel(addr ,(volatile uint32_t *)MEI_DBG_WADDR_C  );
11745 +                       writel(data ,(volatile uint32_t *)MEI_DBG_DATA_C  );
11746 +                       while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){};
11747 +                       writel(0    ,(volatile uint32_t *)MEI_DBG_MASTER_C);
11748 +                       IFX_DEBUGP("WriteARCmem %08x %08x\n",addr,data);
11749 +               };
11750 +
11751 +               static uint32_t ReadARCmem(uint32_t addr)
11752 +               {
11753 +                       u32 data;
11754 +                       writel(1    ,(volatile uint32_t *)MEI_DBG_MASTER_C);
11755 +                       writel(1    ,(volatile uint32_t *)MEI_DBG_DECO_C  );
11756 +                       writel(addr ,(volatile uint32_t *)MEI_DBG_RADDR_C  );
11757 +                       while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){};
11758 +                       data = ifxusb_rreg((volatile uint32_t *)MEI_DBG_DATA_C  );
11759 +                       writel(0    ,(volatile uint32_t *)MEI_DBG_MASTER_C);
11760 +                       IFX_DEBUGP("ReadARCmem %08x %08x\n",addr,data);
11761 +                 return data;
11762 +               };
11763 +
11764 +               void ifxusb_enable_afe_oc(void)
11765 +               {
11766 +                       /* Start the clock */
11767 +                       WriteARCmem(CRI_UPDCTL    ,0x00000008);
11768 +                       WriteARCmem(CRI_CCR0      ,0x00000014);
11769 +                       WriteARCmem(CRI_CCR1      ,0x00000500);
11770 +                       WriteARCmem(AFE_CONFIG    ,0x000001c8);
11771 +                       WriteARCmem(AFE_SERIAL_CFG,0x00000016); // (DANUBE_PCI_CFG_BASE+(1<<addrline))AFE serial interface clock & data latch edge
11772 +                       WriteARCmem(AFE_TCR_0     ,0x00000002);
11773 +                       //Take afe out of reset
11774 +                       WriteARCmem(AFE_CONFIG    ,0x000000c0);
11775 +                       WriteARCmem(IRI_I_ENABLE  ,0x00000101);
11776 +                       WriteARCmem(STY_SMODE     ,0x00001980);
11777 +
11778 +                       ReadARCmem(CRI_UPDCTL    );
11779 +                       ReadARCmem(CRI_CCR0      );
11780 +                       ReadARCmem(CRI_CCR1      );
11781 +                       ReadARCmem(AFE_CONFIG    );
11782 +                       ReadARCmem(AFE_SERIAL_CFG); // (DANUBE_PCI_CFG_BASE+(1<<addrline))AFE serial interface clock & data latch edge
11783 +                       ReadARCmem(AFE_TCR_0     );
11784 +                       ReadARCmem(AFE_CONFIG    );
11785 +                       ReadARCmem(IRI_I_ENABLE  );
11786 +                       ReadARCmem(STY_SMODE     );
11787 +               }
11788 +       #endif  //defined(__IS_TWINPASS__)
11789 +#endif //defined(__UEIP__)
11790 +
11791 +
11792 --- /dev/null
11793 +++ b/drivers/usb/ifxhcd/ifxusb_ctl.c
11794 @@ -0,0 +1,1385 @@
11795 +/*****************************************************************************
11796 + **   FILE NAME       : ifxusb_ctl.c
11797 + **   PROJECT         : IFX USB sub-system V3
11798 + **   MODULES         : IFX USB sub-system Host and Device driver
11799 + **   SRC VERSION     : 1.0
11800 + **   DATE            : 1/Jan/2009
11801 + **   AUTHOR          : Chen, Howard
11802 + **   DESCRIPTION     : Implementing the procfs and sysfs for IFX USB driver
11803 + *****************************************************************************/
11804 +
11805 +/*! \file ifxusb_ctl.c
11806 +  \ingroup IFXUSB_DRIVER_V3
11807 +    \brief Implementing the procfs and sysfs for IFX USB driver
11808 +*/
11809 +
11810 +#include <linux/version.h>
11811 +#include "ifxusb_version.h"
11812 +
11813 +
11814 +#include <linux/proc_fs.h>
11815 +#include <asm/byteorder.h>
11816 +#include <asm/unaligned.h>
11817 +#include <asm/uaccess.h>
11818 +
11819 +#include "ifxusb_plat.h"
11820 +#include "ifxusb_regs.h"
11821 +#include "ifxusb_cif.h"
11822 +
11823 +#ifdef __IS_DEVICE__
11824 +       #include "ifxpcd.h"
11825 +#endif
11826 +
11827 +#ifdef __IS_HOST__
11828 +       #include "ifxhcd.h"
11829 +#endif
11830 +
11831 +#include <linux/device.h>
11832 +#include <linux/platform_device.h>
11833 +#include <linux/gfp.h>
11834 +
11835 +
11836 +#ifdef __IS_HOST__
11837 +       extern char ifxusb_driver_name[];
11838 +
11839 +       #ifdef __IS_DUAL__
11840 +               extern ifxhcd_hcd_t ifxusb_hcd_1;
11841 +               extern ifxhcd_hcd_t ifxusb_hcd_2;
11842 +               extern char ifxusb_hcd_name_1[];
11843 +               extern char ifxusb_hcd_name_2[];
11844 +       #else
11845 +               extern ifxhcd_hcd_t ifxusb_hcd;
11846 +               extern char ifxusb_hcd_name[];
11847 +       #endif
11848 +
11849 +#endif
11850 +
11851 +#ifdef __IS_DEVICE__
11852 +       extern char ifxusb_driver_name[];
11853 +
11854 +       extern ifxpcd_pcd_t ifxusb_pcd;
11855 +       extern char ifxusb_pcd_name[];
11856 +#endif
11857 +
11858 +
11859 +//Attributes for sysfs (for 2.6 only)
11860 +
11861 +extern struct device_attribute dev_attr_dbglevel;
11862 +
11863 +#ifdef __IS_DUAL__
11864 +       extern struct device_attribute dev_attr_dump_params_1;
11865 +       extern struct device_attribute dev_attr_dump_params_2;
11866 +#else
11867 +       extern struct device_attribute dev_attr_dump_params;
11868 +#endif
11869 +
11870 +#ifdef __IS_DUAL__
11871 +       extern struct device_attribute dev_attr_mode_1;
11872 +       extern struct device_attribute dev_attr_mode_2;
11873 +#else
11874 +       extern struct device_attribute dev_attr_mode;
11875 +#endif
11876 +
11877 +#ifdef __IS_HOST__
11878 +       #ifdef __IS_DUAL__
11879 +               extern struct device_attribute dev_attr_buspower_1;
11880 +               extern struct device_attribute dev_attr_buspower_2;
11881 +               extern struct device_attribute dev_attr_bussuspend_1;
11882 +               extern struct device_attribute dev_attr_bussuspend_2;
11883 +               extern struct device_attribute dev_attr_busconnected_1;
11884 +               extern struct device_attribute dev_attr_busconnected_2;
11885 +               extern struct device_attribute dev_attr_connectspeed_1;
11886 +               extern struct device_attribute dev_attr_connectspeed_1;
11887 +       #else
11888 +               extern struct device_attribute dev_attr_buspower;
11889 +               extern struct device_attribute dev_attr_bussuspend;
11890 +               extern struct device_attribute dev_attr_busconnected;
11891 +               extern struct device_attribute dev_attr_connectspeed;
11892 +       #endif
11893 +#endif //__IS_HOST__
11894 +
11895 +#ifdef __IS_DEVICE__
11896 +       extern struct device_attribute dev_attr_devspeed;
11897 +       extern struct device_attribute dev_attr_enumspeed;
11898 +#endif //__IS_DEVICE__
11899 +
11900 +#ifdef __ENABLE_DUMP__
11901 +       #ifdef __IS_DUAL__
11902 +               extern struct device_attribute dev_attr_dump_reg_1;
11903 +               extern struct device_attribute dev_attr_dump_reg_2;
11904 +               extern struct device_attribute dev_attr_dump_spram_1;
11905 +               extern struct device_attribute dev_attr_dump_spram_2;
11906 +               #ifdef __IS_HOST__
11907 +                       extern struct device_attribute dev_attr_dump_host_state_1;
11908 +                       extern struct device_attribute dev_attr_dump_host_state_2;
11909 +               #else
11910 +               #endif
11911 +       #else
11912 +               extern struct device_attribute dev_attr_dump_reg;
11913 +               extern struct device_attribute dev_attr_dump_spram;
11914 +               #ifdef __IS_HOST__
11915 +                       extern struct device_attribute dev_attr_dump_host_state;
11916 +               #else
11917 +               #endif
11918 +       #endif
11919 +#endif //__ENABLE_DUMP__
11920 +
11921 +
11922 +/////////////////////////////////////////////////////////////////////////////////////////////////////
11923 +/////////////////////////////////////////////////////////////////////////////////////////////////////
11924 +/////////////////////////////////////////////////////////////////////////////////////////////////////
11925 +
11926 +static ssize_t procfs_dbglevel_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
11927 +{
11928 +       #ifdef __IS_HOST__
11929 +               return sprintf( buf, "%08X\n",h_dbg_lvl );
11930 +       #else
11931 +               return sprintf( buf, "%08X\n",d_dbg_lvl );
11932 +       #endif
11933 +}
11934 +
11935 +static ssize_t procfs_dbglevel_store(struct file *file, const char *buffer, unsigned long count, void *data)
11936 +{
11937 +       char buf[10];
11938 +       int i = 0;
11939 +       uint32_t value;
11940 +       if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1))
11941 +               return -EFAULT;
11942 +       value = simple_strtoul(buf, NULL, 16);
11943 +       #ifdef __IS_HOST__
11944 +               h_dbg_lvl =value;
11945 +       #else
11946 +               d_dbg_lvl =value;
11947 +       #endif
11948 +               //turn on and off power
11949 +       return count;
11950 +}
11951 +
11952 +#if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
11953 +       static ssize_t sysfs_dbglevel_show( struct device *_dev, struct device_attribute *attr,char *buf)
11954 +#else
11955 +       static ssize_t sysfs_dbglevel_show( struct device *_dev,                               char *buf)
11956 +#endif
11957 +{
11958 +       #ifdef __IS_HOST__
11959 +               return sprintf( buf, "%08X\n",h_dbg_lvl );
11960 +       #else
11961 +               return sprintf( buf, "%08X\n",d_dbg_lvl );
11962 +       #endif
11963 +}
11964 +
11965 +#if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
11966 +       static ssize_t sysfs_dbglevel_store( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count )
11967 +#else
11968 +    static ssize_t sysfs_dbglevel_store( struct device *_dev,                               const char *buffer, size_t count )
11969 +#endif
11970 +{
11971 +       char buf[10];
11972 +       int i = 0;
11973 +       uint32_t value;
11974 +       if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1))
11975 +               return -EFAULT;
11976 +       value = simple_strtoul(buf, NULL, 16);
11977 +       #ifdef __IS_HOST__
11978 +               h_dbg_lvl =value;
11979 +       #else
11980 +               d_dbg_lvl =value;
11981 +       #endif
11982 +               //turn on and off power
11983 +       return count;
11984 +}
11985 +
11986 +DEVICE_ATTR(dbglevel, S_IRUGO|S_IWUSR, sysfs_dbglevel_show, sysfs_dbglevel_store);
11987 +
11988 +
11989 +/////////////////////////////////////////////////////////////////////////////////////////////////////
11990 +/////////////////////////////////////////////////////////////////////////////////////////////////////
11991 +/////////////////////////////////////////////////////////////////////////////////////////////////////
11992 +
11993 +static void ifxusb_dump_params(ifxusb_core_if_t *_core_if);
11994 +
11995 +#ifdef __IS_DUAL__
11996 +       static void dump_params_1(void)
11997 +       {
11998 +               ifxusb_dump_params(&ifxusb_hcd_1.core_if);
11999 +       }
12000 +       static void dump_params_2(void)
12001 +       {
12002 +               ifxusb_dump_params(&ifxusb_hcd_2.core_if);
12003 +       }
12004 +
12005 +       static ssize_t procfs_dump_params_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12006 +       {
12007 +               dump_params_1();
12008 +               return 0;
12009 +       }
12010 +       static ssize_t procfs_dump_params_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12011 +       {
12012 +               dump_params_2();
12013 +               return 0;
12014 +       }
12015 +
12016 +       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12017 +               static ssize_t sysfs_dump_params_show_1( struct device *_dev, struct device_attribute *attr,char *buf)
12018 +       #else
12019 +               static ssize_t sysfs_dump_params_show_1( struct device *_dev,char *buf)
12020 +       #endif
12021 +       {
12022 +               dump_params_1();
12023 +               return 0;
12024 +       }
12025 +       DEVICE_ATTR(dump_params_1, S_IRUGO|S_IWUSR, sysfs_dump_params_show_1, NULL);
12026 +
12027 +       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12028 +               static ssize_t sysfs_dump_params_show_2( struct device *_dev, struct device_attribute *attr,char *buf)
12029 +       #else
12030 +               static ssize_t sysfs_dump_params_show_2( struct device *_dev,char *buf)
12031 +       #endif
12032 +       {
12033 +               dump_params_2();
12034 +               return 0;
12035 +       }
12036 +
12037 +       DEVICE_ATTR(dump_params_2, S_IRUGO|S_IWUSR, sysfs_dump_params_show_2, NULL);
12038 +#else
12039 +       static void dump_params(void)
12040 +       {
12041 +               #ifdef __IS_HOST__
12042 +                       ifxusb_dump_params(&ifxusb_hcd.core_if);
12043 +               #else
12044 +                       ifxusb_dump_params(&ifxusb_pcd.core_if);
12045 +               #endif
12046 +       }
12047 +
12048 +       static ssize_t procfs_dump_params_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12049 +       {
12050 +               dump_params();
12051 +               return 0;
12052 +       }
12053 +
12054 +       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12055 +               static ssize_t sysfs_dump_params_show( struct device *_dev, struct device_attribute *attr,char *buf)
12056 +       #else
12057 +               static ssize_t sysfs_dump_params_show( struct device *_dev,char *buf)
12058 +       #endif
12059 +       {
12060 +               dump_params();
12061 +               return 0;
12062 +       }
12063 +       DEVICE_ATTR(dump_params, S_IRUGO|S_IWUSR, sysfs_dump_params_show, NULL);
12064 +#endif
12065 +
12066 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12067 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12068 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12069 +
12070 +#ifdef __IS_DUAL__
12071 +       static ssize_t mode_show_1(char *buf)
12072 +       {
12073 +               if((ifxusb_rreg(&ifxusb_hcd_1.core_if.core_global_regs->gintsts ) & 0x1) == 1)
12074 +                       return sprintf( buf, "HOST\n" );
12075 +               else
12076 +                       return sprintf( buf, "DEVICE(INCORRECT!)\n" );
12077 +       }
12078 +
12079 +       static ssize_t mode_show_2(char *buf)
12080 +       {
12081 +               if((ifxusb_rreg(&ifxusb_hcd_2.core_if.core_global_regs->gintsts ) & 0x1) == 1)
12082 +                       return sprintf( buf, "HOST\n" );
12083 +               else
12084 +                       return sprintf( buf, "DEVICE(INCORRECT!)\n" );
12085 +       }
12086 +
12087 +       static ssize_t procfs_mode_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12088 +       {
12089 +               return mode_show_1(buf);
12090 +       }
12091 +       static ssize_t procfs_mode_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12092 +       {
12093 +               return mode_show_2(buf);
12094 +       }
12095 +
12096 +       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12097 +               static ssize_t sysfs_mode_show_1( struct device *_dev, struct device_attribute *attr,char *buf)
12098 +       #else
12099 +               static ssize_t sysfs_mode_show_1( struct device *_dev,char *buf)
12100 +       #endif
12101 +       {
12102 +               return mode_show_1(buf);
12103 +       }
12104 +
12105 +       DEVICE_ATTR(mode_1, S_IRUGO|S_IWUSR, sysfs_mode_show_1, 0);
12106 +
12107 +       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12108 +               static ssize_t sysfs_mode_show_2( struct device *_dev, struct device_attribute *attr,char *buf)
12109 +       #else
12110 +               static ssize_t sysfs_mode_show_2( struct device *_dev,char *buf)
12111 +       #endif
12112 +       {
12113 +               return mode_show_2(buf);
12114 +       }
12115 +       DEVICE_ATTR(mode_2, S_IRUGO|S_IWUSR, sysfs_mode_show_2, NULL);
12116 +#else
12117 +       static ssize_t mode_show(char *buf)
12118 +       {
12119 +               #ifdef __IS_HOST__
12120 +                       if((ifxusb_rreg(&ifxusb_hcd.core_if.core_global_regs->gintsts ) & 0x1) == 1)
12121 +                               return sprintf( buf, "HOST\n" );
12122 +                       else
12123 +                               return sprintf( buf, "DEVICE(INCORRECT!)\n" );
12124 +               #else
12125 +                       if((ifxusb_rreg(&ifxusb_pcd.core_if.core_global_regs->gintsts ) & 0x1) != 1)
12126 +                               return sprintf( buf, "DEVICE\n" );
12127 +                       else
12128 +                               return sprintf( buf, "HOST(INCORRECT!)\n" );
12129 +               #endif
12130 +       }
12131 +       static ssize_t procfs_mode_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12132 +       {
12133 +               return mode_show(buf);
12134 +       }
12135 +       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12136 +               static ssize_t sysfs_mode_show( struct device *_dev, struct device_attribute *attr,char *buf)
12137 +       #else
12138 +               static ssize_t sysfs_mode_show( struct device *_dev,                               char *buf)
12139 +       #endif
12140 +       {
12141 +               return mode_show(buf);
12142 +       }
12143 +       DEVICE_ATTR(mode, S_IRUGO|S_IWUSR, sysfs_mode_show, NULL);
12144 +#endif
12145 +
12146 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12147 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12148 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12149 +
12150 +#ifdef __IS_HOST__
12151 +       #ifdef __IS_DUAL__
12152 +               static ssize_t buspower_show_1(char *buf)
12153 +               {
12154 +                       if(ifxusb_vbus (&ifxusb_hcd_1.core_if)==1) return sprintf( buf, "1\n" );
12155 +                       if(ifxusb_vbus (&ifxusb_hcd_1.core_if)==0) return sprintf( buf, "0\n" );
12156 +                       return sprintf( buf, "UNKNOWN\n" );
12157 +               }
12158 +               static void buspower_store_1(uint32_t value)
12159 +               {
12160 +                       if     (value==1)  ifxusb_vbus_on (&ifxusb_hcd_1.core_if);
12161 +                       else if(value==0)  ifxusb_vbus_off(&ifxusb_hcd_1.core_if);
12162 +               }
12163 +               static ssize_t buspower_show_2(char *buf)
12164 +               {
12165 +                       if(ifxusb_vbus (&ifxusb_hcd_2.core_if)==1) return sprintf( buf, "1\n" );
12166 +                       if(ifxusb_vbus (&ifxusb_hcd_2.core_if)==0) return sprintf( buf, "0\n" );
12167 +                       return sprintf( buf, "UNKNOWN\n" );
12168 +               }
12169 +               static void buspower_store_2(uint32_t value)
12170 +               {
12171 +                       if     (value==1)  ifxusb_vbus_on (&ifxusb_hcd_2.core_if);
12172 +                       else if(value==0)  ifxusb_vbus_off(&ifxusb_hcd_2.core_if);
12173 +               }
12174 +               static ssize_t procfs_buspower_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12175 +               {
12176 +                       return buspower_show_1(buf);
12177 +               }
12178 +               static ssize_t procfs_buspower_store_1(struct file *file, const char *buffer, unsigned long count, void *data)
12179 +               {
12180 +                       char buf[10];
12181 +                       int i = 0;
12182 +                       uint32_t value;
12183 +                       if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1))
12184 +                               return -EFAULT;
12185 +                       value = simple_strtoul(buf, NULL, 16);
12186 +                       buspower_store_1(value);
12187 +                       return count;
12188 +               }
12189 +               static ssize_t procfs_buspower_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12190 +               {
12191 +                       return buspower_show_2(buf);
12192 +               }
12193 +               static ssize_t procfs_buspower_store_2(struct file *file, const char *buffer, unsigned long count, void *data)
12194 +               {
12195 +                       char buf[10];
12196 +                       int i = 0;
12197 +                       uint32_t value;
12198 +                       if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1))
12199 +                               return -EFAULT;
12200 +                       value = simple_strtoul(buf, NULL, 16);
12201 +                       buspower_store_2(value);
12202 +                       return count;
12203 +               }
12204 +
12205 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12206 +                       static ssize_t sysfs_buspower_show_1( struct device *_dev, struct device_attribute *attr,char *buf)
12207 +               #else
12208 +                       static ssize_t sysfs_buspower_show_1( struct device *_dev,char *buf)
12209 +               #endif
12210 +               {
12211 +                       return buspower_show_1(buf);
12212 +               }
12213 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12214 +                       static ssize_t sysfs_buspower_store_1( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count )
12215 +               #else
12216 +                   static ssize_t sysfs_buspower_store_1( struct device *_dev,                               const char *buffer, size_t count )
12217 +               #endif
12218 +               {
12219 +                       char buf[10];
12220 +                       int i = 0;
12221 +                       uint32_t value;
12222 +                       if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1))
12223 +                               return -EFAULT;
12224 +                       value = simple_strtoul(buf, NULL, 16);
12225 +                       buspower_store_1(value);
12226 +                       return count;
12227 +               }
12228 +               DEVICE_ATTR(buspower_1, S_IRUGO|S_IWUSR, sysfs_buspower_show_1, sysfs_buspower_store_1);
12229 +
12230 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12231 +                       static ssize_t sysfs_buspower_show_2( struct device *_dev, struct device_attribute *attr,char *buf)
12232 +               #else
12233 +                       static ssize_t sysfs_buspower_show_2( struct device *_dev,char *buf)
12234 +               #endif
12235 +               {
12236 +                       return buspower_show_2(buf);
12237 +               }
12238 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12239 +                       static ssize_t sysfs_buspower_store_2( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count )
12240 +               #else
12241 +                   static ssize_t sysfs_buspower_store_2( struct device *_dev,                               const char *buffer, size_t count )
12242 +               #endif
12243 +               {
12244 +                       char buf[10];
12245 +                       int i = 0;
12246 +                       uint32_t value;
12247 +                       if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1))
12248 +                               return -EFAULT;
12249 +                       value = simple_strtoul(buf, NULL, 16);
12250 +                       buspower_store_2(value);
12251 +                       return count;
12252 +               }
12253 +               DEVICE_ATTR(buspower_2, S_IRUGO|S_IWUSR, sysfs_buspower_show_2, sysfs_buspower_store_2);
12254 +       #else
12255 +               static ssize_t buspower_show(char *buf)
12256 +               {
12257 +                       if(ifxusb_vbus (&ifxusb_hcd.core_if)==1) return sprintf( buf, "1\n" );
12258 +                       if(ifxusb_vbus (&ifxusb_hcd.core_if)==0) return sprintf( buf, "0\n" );
12259 +                       return sprintf( buf, "UNKNOWN\n" );
12260 +               }
12261 +               static void buspower_store(uint32_t value)
12262 +               {
12263 +                       if     (value==1)  ifxusb_vbus_on (&ifxusb_hcd.core_if);
12264 +                       else if(value==0)  ifxusb_vbus_off(&ifxusb_hcd.core_if);
12265 +               }
12266 +               static ssize_t procfs_buspower_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12267 +               {
12268 +                       return buspower_show(buf);
12269 +               }
12270 +               static ssize_t procfs_buspower_store(struct file *file, const char *buffer, unsigned long count, void *data)
12271 +               {
12272 +                       char buf[10];
12273 +                       int i = 0;
12274 +                       uint32_t value;
12275 +                       if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1))
12276 +                               return -EFAULT;
12277 +                       value = simple_strtoul(buf, NULL, 16);
12278 +                       buspower_store(value);
12279 +                       return count;
12280 +               }
12281 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12282 +                       static ssize_t sysfs_buspower_show( struct device *_dev, struct device_attribute *attr,char *buf)
12283 +               #else
12284 +                       static ssize_t sysfs_buspower_show( struct device *_dev,                               char *buf)
12285 +               #endif
12286 +               {
12287 +                       return buspower_show(buf);
12288 +               }
12289 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12290 +                       static ssize_t sysfs_buspower_store( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count )
12291 +               #else
12292 +                   static ssize_t sysfs_buspower_store( struct device *_dev,                               const char *buffer, size_t count )
12293 +               #endif
12294 +               {
12295 +                       char buf[10];
12296 +                       int i = 0;
12297 +                       uint32_t value;
12298 +                       if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1))
12299 +                               return -EFAULT;
12300 +                       value = simple_strtoul(buf, NULL, 16);
12301 +                       buspower_store(value);
12302 +                       return count;
12303 +               }
12304 +               DEVICE_ATTR(buspower, S_IRUGO|S_IWUSR, sysfs_buspower_show, sysfs_buspower_store);
12305 +       #endif
12306 +
12307 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12308 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12309 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12310 +
12311 +
12312 +       #ifdef __IS_DUAL__
12313 +               static ssize_t bussuspend_show_1(char *buf)
12314 +               {
12315 +                       hprt0_data_t val;
12316 +                       val.d32 = ifxusb_rreg(ifxusb_hcd_1.core_if.hprt0);
12317 +                       return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
12318 +               }
12319 +               static ssize_t bussuspend_show_2(char *buf)
12320 +               {
12321 +                       hprt0_data_t val;
12322 +                       val.d32 = ifxusb_rreg(ifxusb_hcd_2.core_if.hprt0);
12323 +                       return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
12324 +               }
12325 +
12326 +               static ssize_t procfs_bussuspend_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12327 +               {
12328 +                       return bussuspend_show_1(buf);
12329 +               }
12330 +               static ssize_t procfs_bussuspend_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12331 +               {
12332 +                       return bussuspend_show_2(buf);
12333 +               }
12334 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12335 +                       static ssize_t sysfs_bussuspend_show_1( struct device *_dev, struct device_attribute *attr,char *buf)
12336 +               #else
12337 +                       static ssize_t sysfs_bussuspend_show_1( struct device *_dev,char *buf)
12338 +               #endif
12339 +               {
12340 +                       return bussuspend_show_1(buf);
12341 +               }
12342 +               DEVICE_ATTR(bussuspend_1, S_IRUGO|S_IWUSR, sysfs_bussuspend_show_1, 0);
12343 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12344 +                       static ssize_t sysfs_bussuspend_show_2( struct device *_dev, struct device_attribute *attr,char *buf)
12345 +               #else
12346 +                       static ssize_t sysfs_bussuspend_show_2( struct device *_dev,char *buf)
12347 +               #endif
12348 +               {
12349 +                       return bussuspend_show_2(buf);
12350 +               }
12351 +               DEVICE_ATTR(bussuspend_2, S_IRUGO|S_IWUSR, sysfs_bussuspend_show_2, 0);
12352 +       #else
12353 +               static ssize_t bussuspend_show(char *buf)
12354 +               {
12355 +                       hprt0_data_t val;
12356 +                       val.d32 = ifxusb_rreg(ifxusb_hcd.core_if.hprt0);
12357 +                       return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
12358 +               }
12359 +               static ssize_t procfs_bussuspend_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12360 +               {
12361 +                       return bussuspend_show(buf);
12362 +               }
12363 +
12364 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12365 +                       static ssize_t sysfs_bussuspend_show( struct device *_dev, struct device_attribute *attr,char *buf)
12366 +               #else
12367 +                       static ssize_t sysfs_bussuspend_show( struct device *_dev,                               char *buf)
12368 +               #endif
12369 +               {
12370 +                       return bussuspend_show(buf);
12371 +               }
12372 +               DEVICE_ATTR(bussuspend, S_IRUGO|S_IWUSR, sysfs_bussuspend_show, 0);
12373 +       #endif
12374 +
12375 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12376 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12377 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12378 +
12379 +       #ifdef __IS_DUAL__
12380 +               static ssize_t busconnected_show_1(char *buf)
12381 +               {
12382 +                       hprt0_data_t val;
12383 +                       val.d32 = ifxusb_rreg(ifxusb_hcd_1.core_if.hprt0);
12384 +                       return sprintf (buf, "Bus Connected = 0x%x\n", val.b.prtconnsts);
12385 +               }
12386 +               static ssize_t busconnected_show_2(char *buf)
12387 +               {
12388 +                       hprt0_data_t val;
12389 +                       val.d32 = ifxusb_rreg(ifxusb_hcd_2.core_if.hprt0);
12390 +                       return sprintf (buf, "Bus Connected = 0x%x\n", val.b.prtconnsts);
12391 +               }
12392 +
12393 +               static ssize_t procfs_busconnected_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12394 +               {
12395 +                       return busconnected_show_1(buf);
12396 +               }
12397 +               static ssize_t procfs_busconnected_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12398 +               {
12399 +                       return busconnected_show_2(buf);
12400 +               }
12401 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12402 +                       static ssize_t sysfs_busconnected_show_1( struct device *_dev, struct device_attribute *attr,char *buf)
12403 +               #else
12404 +                       static ssize_t sysfs_busconnected_show_1( struct device *_dev,char *buf)
12405 +               #endif
12406 +               {
12407 +                       return busconnected_show_1(buf);
12408 +               }
12409 +               DEVICE_ATTR(busconnected_1, S_IRUGO|S_IWUSR, sysfs_busconnected_show_1, 0);
12410 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12411 +                       static ssize_t sysfs_busconnected_show_2( struct device *_dev, struct device_attribute *attr,char *buf)
12412 +               #else
12413 +                       static ssize_t sysfs_busconnected_show_2( struct device *_dev,char *buf)
12414 +               #endif
12415 +               {
12416 +                       return busconnected_show_2(buf);
12417 +               }
12418 +               DEVICE_ATTR(busconnected_2, S_IRUGO|S_IWUSR, sysfs_busconnected_show_2, 0);
12419 +       #else
12420 +               static ssize_t busconnected_show(char *buf)
12421 +               {
12422 +                       hprt0_data_t val;
12423 +                       val.d32 = ifxusb_rreg(ifxusb_hcd.core_if.hprt0);
12424 +                       return sprintf (buf, "Bus Connected = 0x%x\n", val.b.prtconnsts);
12425 +               }
12426 +               static ssize_t procfs_busconnected_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12427 +               {
12428 +                       return busconnected_show(buf);
12429 +               }
12430 +
12431 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12432 +                       static ssize_t sysfs_busconnected_show( struct device *_dev, struct device_attribute *attr,char *buf)
12433 +               #else
12434 +                       static ssize_t sysfs_busconnected_show( struct device *_dev,                               char *buf)
12435 +               #endif
12436 +               {
12437 +                       return busconnected_show(buf);
12438 +               }
12439 +               DEVICE_ATTR(busconnected, S_IRUGO|S_IWUSR, sysfs_busconnected_show, 0);
12440 +       #endif
12441 +
12442 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12443 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12444 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12445 +
12446 +       #ifdef __IS_DUAL__
12447 +               static ssize_t connectspeed_show_1(char *buf)
12448 +               {
12449 +                       hprt0_data_t val;
12450 +                       val.d32 = ifxusb_rreg(ifxusb_hcd_1.core_if.hprt0);
12451 +                       if( val.b.prtspd ==0) return sprintf (buf, "Bus Speed = High (%d)\n", val.b.prtspd);
12452 +                       if( val.b.prtspd ==1) return sprintf (buf, "Bus Speed = Full (%d)\n", val.b.prtspd);
12453 +                       if( val.b.prtspd ==2) return sprintf (buf, "Bus Speed = Low  (%d)\n", val.b.prtspd);
12454 +                                             return sprintf (buf, "Bus Speed = Unknown (%d)\n", val.b.prtspd);
12455 +               }
12456 +               static ssize_t connectspeed_show_2(char *buf)
12457 +               {
12458 +                       hprt0_data_t val;
12459 +                       val.d32 = ifxusb_rreg(ifxusb_hcd_2.core_if.hprt0);
12460 +                       if( val.b.prtspd ==0) return sprintf (buf, "Bus Speed = High (%d)\n", val.b.prtspd);
12461 +                       if( val.b.prtspd ==1) return sprintf (buf, "Bus Speed = Full (%d)\n", val.b.prtspd);
12462 +                       if( val.b.prtspd ==2) return sprintf (buf, "Bus Speed = Low  (%d)\n", val.b.prtspd);
12463 +                                             return sprintf (buf, "Bus Speed = Unknown (%d)\n", val.b.prtspd);
12464 +               }
12465 +
12466 +               static ssize_t procfs_connectspeed_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12467 +               {
12468 +                       return connectspeed_show_1(buf);
12469 +               }
12470 +               static ssize_t procfs_connectspeed_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12471 +               {
12472 +                       return connectspeed_show_2(buf);
12473 +               }
12474 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12475 +                       static ssize_t sysfs_connectspeed_show_1( struct device *_dev, struct device_attribute *attr,char *buf)
12476 +               #else
12477 +                       static ssize_t sysfs_connectspeed_show_1( struct device *_dev,char *buf)
12478 +               #endif
12479 +               {
12480 +                       return connectspeed_show_1(buf);
12481 +               }
12482 +               DEVICE_ATTR(connectspeed_1, S_IRUGO|S_IWUSR, sysfs_connectspeed_show_1, 0);
12483 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12484 +                       static ssize_t sysfs_connectspeed_show_2( struct device *_dev, struct device_attribute *attr,char *buf)
12485 +               #else
12486 +                       static ssize_t sysfs_connectspeed_show_2( struct device *_dev,char *buf)
12487 +               #endif
12488 +               {
12489 +                       return connectspeed_show_2(buf);
12490 +               }
12491 +               DEVICE_ATTR(connectspeed_2, S_IRUGO|S_IWUSR, sysfs_connectspeed_show_2, 0);
12492 +       #else
12493 +               static ssize_t connectspeed_show(char *buf)
12494 +               {
12495 +                       hprt0_data_t val;
12496 +                       val.d32 = ifxusb_rreg(ifxusb_hcd.core_if.hprt0);
12497 +                       if( val.b.prtspd ==0) return sprintf (buf, "Bus Speed = High (%d)\n", val.b.prtspd);
12498 +                       if( val.b.prtspd ==1) return sprintf (buf, "Bus Speed = Full (%d)\n", val.b.prtspd);
12499 +                       if( val.b.prtspd ==2) return sprintf (buf, "Bus Speed = Low  (%d)\n", val.b.prtspd);
12500 +                                             return sprintf (buf, "Bus Speed = Unknown (%d)\n", val.b.prtspd);
12501 +               }
12502 +
12503 +               static ssize_t procfs_connectspeed_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12504 +               {
12505 +                       return connectspeed_show(buf);
12506 +               }
12507 +
12508 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12509 +                       static ssize_t sysfs_connectspeed_show( struct device *_dev, struct device_attribute *attr,char *buf)
12510 +               #else
12511 +                       static ssize_t sysfs_connectspeed_show( struct device *_dev,                               char *buf)
12512 +               #endif
12513 +               {
12514 +                       return connectspeed_show(buf);
12515 +               }
12516 +               DEVICE_ATTR(connectspeed, S_IRUGO|S_IWUSR, sysfs_connectspeed_show, 0);
12517 +       #endif
12518 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12519 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12520 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12521 +#endif
12522 +
12523 +
12524 +#ifdef __IS_DEVICE__
12525 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12526 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12527 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12528 +       static ssize_t devspeed_show(char *buf)
12529 +       {
12530 +               dcfg_data_t val;
12531 +               val.d32 = ifxusb_rreg(&ifxusb_pcd.core_if.dev_global_regs->dcfg);
12532 +               if( val.b.devspd ==0) return sprintf (buf, "Dev Speed = High (%d)\n", val.b.devspd);
12533 +               if( val.b.devspd ==1) return sprintf (buf, "Dev Speed = Full (%d)\n", val.b.devspd);
12534 +               if( val.b.devspd ==3) return sprintf (buf, "Dev Speed = Full (%d)\n", val.b.devspd);
12535 +                                     return sprintf (buf, "Dev Speed = Unknown (%d)\n", val.b.devspd);
12536 +       }
12537 +
12538 +       static ssize_t procfs_devspeed_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12539 +       {
12540 +               return devspeed_show(buf);
12541 +       }
12542 +
12543 +       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12544 +               static ssize_t sysfs_devspeed_show( struct device *_dev, struct device_attribute *attr,char *buf)
12545 +       #else
12546 +               static ssize_t sysfs_devspeed_show( struct device *_dev,                               char *buf)
12547 +       #endif
12548 +       {
12549 +               return devspeed_show(buf);
12550 +       }
12551 +       DEVICE_ATTR(devspeed, S_IRUGO|S_IWUSR, sysfs_devspeed_show, 0);
12552 +
12553 +       static ssize_t enumspeed_show(char *buf)
12554 +       {
12555 +               dsts_data_t val;
12556 +               val.d32 = ifxusb_rreg(&ifxusb_pcd.core_if.dev_global_regs->dsts);
12557 +               if( val.b.enumspd ==0) return sprintf (buf, "Enum Speed = High (%d)\n", val.b.enumspd);
12558 +               if( val.b.enumspd ==1) return sprintf (buf, "Enum Speed = Full (%d)\n", val.b.enumspd);
12559 +               if( val.b.enumspd ==2) return sprintf (buf, "Enum Speed = Low  (%d)\n", val.b.enumspd);
12560 +               return sprintf (buf, "Enum Speed = invalid(%d)\n", val.b.enumspd);
12561 +       }
12562 +
12563 +       static ssize_t procfs_enumspeed_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12564 +       {
12565 +               return enumspeed_show(buf);
12566 +       }
12567 +
12568 +       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12569 +               static ssize_t sysfs_enumspeed_show( struct device *_dev, struct device_attribute *attr,char *buf)
12570 +       #else
12571 +               static ssize_t sysfs_enumspeed_show( struct device *_dev,                               char *buf)
12572 +       #endif
12573 +       {
12574 +               return enumspeed_show(buf);
12575 +       }
12576 +       DEVICE_ATTR(enumspeed, S_IRUGO|S_IWUSR, sysfs_enumspeed_show, 0);
12577 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12578 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12579 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12580 +#endif
12581 +
12582 +
12583 +//////////////////////////////////////////////////////////////////////////////////
12584 +#ifdef __ENABLE_DUMP__
12585 +
12586 +       #ifdef __IS_DUAL__
12587 +               static void dump_reg_1(void)
12588 +               {
12589 +                       ifxusb_dump_registers(&ifxusb_hcd_1.core_if);
12590 +               }
12591 +               static void dump_reg_2(void)
12592 +               {
12593 +                       ifxusb_dump_registers(&ifxusb_hcd_2.core_if);
12594 +               }
12595 +
12596 +               static ssize_t procfs_dump_reg_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12597 +               {
12598 +                       dump_reg_1();
12599 +                       return 0;
12600 +               }
12601 +               static ssize_t procfs_dump_reg_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12602 +               {
12603 +                       dump_reg_2();
12604 +                       return 0;
12605 +               }
12606 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12607 +                       static ssize_t sysfs_dump_reg_show_1( struct device *_dev, struct device_attribute *attr,char *buf)
12608 +               #else
12609 +                       static ssize_t sysfs_dump_reg_show_1( struct device *_dev,char *buf)
12610 +               #endif
12611 +               {
12612 +                       dump_reg_1();
12613 +                       return 0;
12614 +               }
12615 +               DEVICE_ATTR(dump_reg_1, S_IRUGO|S_IWUSR, sysfs_dump_reg_show_1, 0);
12616 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12617 +                       static ssize_t sysfs_dump_reg_show_2( struct device *_dev, struct device_attribute *attr,char *buf)
12618 +               #else
12619 +                       static ssize_t sysfs_dump_reg_show_2( struct device *_dev,char *buf)
12620 +               #endif
12621 +               {
12622 +                       dump_reg_2();
12623 +                       return 0;
12624 +               }
12625 +               DEVICE_ATTR(dump_reg_2, S_IRUGO|S_IWUSR, sysfs_dump_reg_show_2, 0);
12626 +       #else
12627 +               static void dump_reg(void)
12628 +               {
12629 +                       #ifdef __IS_HOST__
12630 +                               ifxusb_dump_registers(&ifxusb_hcd.core_if);
12631 +                       #endif
12632 +                       #ifdef __IS_DEVICE__
12633 +                               ifxusb_dump_registers(&ifxusb_pcd.core_if);
12634 +                       #endif
12635 +               }
12636 +               static ssize_t procfs_dump_reg_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12637 +               {
12638 +                       dump_reg();
12639 +                       return 0;
12640 +               }
12641 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12642 +                       static ssize_t sysfs_dump_reg_show( struct device *_dev, struct device_attribute *attr,char *buf)
12643 +               #else
12644 +                       static ssize_t sysfs_dump_reg_show( struct device *_dev,char *buf)
12645 +               #endif
12646 +               {
12647 +                       dump_reg();
12648 +                       return 0;
12649 +               }
12650 +               DEVICE_ATTR(dump_reg, S_IRUGO|S_IWUSR, sysfs_dump_reg_show, 0);
12651 +       #endif
12652 +
12653 +
12654 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12655 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12656 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12657 +
12658 +       #ifdef __IS_DUAL__
12659 +               static void dump_spram_1(void)
12660 +               {
12661 +                       ifxusb_dump_spram(&ifxusb_hcd_1.core_if);
12662 +               }
12663 +               static void dump_spram_2(void)
12664 +               {
12665 +                       ifxusb_dump_spram(&ifxusb_hcd_2.core_if);
12666 +               }
12667 +
12668 +               static ssize_t procfs_dump_spram_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12669 +               {
12670 +                       dump_spram_1();
12671 +                       return 0;
12672 +               }
12673 +               static ssize_t procfs_dump_spram_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12674 +               {
12675 +                       dump_spram_2();
12676 +                       return 0;
12677 +               }
12678 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12679 +                       static ssize_t sysfs_dump_spram_show_1( struct device *_dev, struct device_attribute *attr,char *buf)
12680 +               #else
12681 +                       static ssize_t sysfs_dump_spram_show_1( struct device *_dev,char *buf)
12682 +               #endif
12683 +               {
12684 +                       dump_spram_1();
12685 +                       return 0;
12686 +               }
12687 +               DEVICE_ATTR(dump_spram_1, S_IRUGO|S_IWUSR, sysfs_dump_spram_show_1, 0);
12688 +
12689 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12690 +                       static ssize_t sysfs_dump_spram_show_2( struct device *_dev, struct device_attribute *attr,char *buf)
12691 +               #else
12692 +                       static ssize_t sysfs_dump_spram_show_2( struct device *_dev,char *buf)
12693 +               #endif
12694 +               {
12695 +                       dump_spram_2();
12696 +                       return 0;
12697 +               }
12698 +               DEVICE_ATTR(dump_spram_2, S_IRUGO|S_IWUSR, sysfs_dump_spram_show_2, 0);
12699 +       #else
12700 +               static void dump_spram(void)
12701 +               {
12702 +                       #ifdef __IS_HOST__
12703 +                               ifxusb_dump_spram(&ifxusb_hcd.core_if);
12704 +                       #endif
12705 +                       #ifdef __IS_DEVICE__
12706 +                               ifxusb_dump_spram(&ifxusb_pcd.core_if);
12707 +                       #endif
12708 +               }
12709 +               static ssize_t procfs_dump_spram_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12710 +               {
12711 +                       dump_spram();
12712 +                       return 0;
12713 +               }
12714 +               #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12715 +                       static ssize_t sysfs_dump_spram_show( struct device *_dev, struct device_attribute *attr,char *buf)
12716 +               #else
12717 +                       static ssize_t sysfs_dump_spram_show( struct device *_dev,char *buf)
12718 +               #endif
12719 +               {
12720 +                       dump_spram();
12721 +                       return 0;
12722 +               }
12723 +               DEVICE_ATTR(dump_spram, S_IRUGO|S_IWUSR, sysfs_dump_spram_show, 0);
12724 +       #endif
12725 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12726 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12727 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12728 +
12729 +       #ifdef __IS_HOST__
12730 +               #ifdef __IS_DUAL__
12731 +                       static ssize_t procfs_dump_host_state_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12732 +                       {
12733 +                               ifxhcd_dump_state(&ifxusb_hcd_1);
12734 +                               return 0;
12735 +                       }
12736 +                       static ssize_t procfs_dump_host_state_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12737 +                       {
12738 +                               ifxhcd_dump_state(&ifxusb_hcd_2);
12739 +                               return 0;
12740 +                       }
12741 +                       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12742 +                               static ssize_t sysfs_dump_host_state_show_1( struct device *_dev, struct device_attribute *attr,char *buf)
12743 +                       #else
12744 +                               static ssize_t sysfs_dump_host_state_show_1( struct device *_dev,char *buf)
12745 +                       #endif
12746 +                       {
12747 +                               ifxhcd_dump_state(&ifxusb_hcd_1);
12748 +                               return 0;
12749 +                       }
12750 +                       DEVICE_ATTR(dump_host_state_1, S_IRUGO|S_IWUSR, sysfs_dump_host_state_show_1, 0);
12751 +                       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12752 +                               static ssize_t sysfs_dump_host_state_show_2( struct device *_dev, struct device_attribute *attr,char *buf)
12753 +                       #else
12754 +                               static ssize_t sysfs_dump_host_state_show_2( struct device *_dev,char *buf)
12755 +                       #endif
12756 +                       {
12757 +                               ifxhcd_dump_state(&ifxusb_hcd_2);
12758 +                               return 0;
12759 +                       }
12760 +                       DEVICE_ATTR(dump_host_state_2, S_IRUGO|S_IWUSR, sysfs_dump_host_state_show_2, 0);
12761 +               #else
12762 +                       static ssize_t procfs_dump_host_state_show(char *buf, char **start, off_t offset, int count, int *eof, void *data)
12763 +                       {
12764 +                               ifxhcd_dump_state(&ifxusb_hcd);
12765 +                               return 0;
12766 +                       }
12767 +                       #if   LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12768 +                               static ssize_t sysfs_dump_host_state_show( struct device *_dev, struct device_attribute *attr,char *buf)
12769 +                       #else
12770 +                               static ssize_t sysfs_dump_host_state_show( struct device *_dev,char *buf)
12771 +                       #endif
12772 +                       {
12773 +                               ifxhcd_dump_state(&ifxusb_hcd);
12774 +                               return 0;
12775 +                       }
12776 +                       DEVICE_ATTR(dump_host_state, S_IRUGO|S_IWUSR, sysfs_dump_host_state_show, 0);
12777 +               #endif
12778 +
12779 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12780 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12781 +/////////////////////////////////////////////////////////////////////////////////////////////////////
12782 +
12783 +       #endif //IS_HOST_
12784 +
12785 +#endif //__ENABLE_DUMP__
12786 +
12787 +//////////////////////////////////////////////////////////////////////////////////
12788 +
12789 +static int  ifx_proc_addproc(char *funcname, read_proc_t *hookfuncr, write_proc_t *hookfuncw);
12790 +static void ifx_proc_delproc(char *funcname);
12791 +
12792 +//////////////////////////////////////////////////////////////////////////////////
12793 +
12794 +/*!
12795 +  \brief This function create the sysfs and procfs entries
12796 +  \param[in] _dev Pointer of device structure, if applied
12797 + */
12798 +void ifxusb_attr_create (void *_dev)
12799 +{
12800 +       int error;
12801 +
12802 +       struct device *dev = (struct device *) _dev;
12803 +
12804 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
12805 +       error = ifx_proc_addproc("dbglevel", procfs_dbglevel_show, procfs_dbglevel_store);
12806 +       error = device_create_file(dev, &dev_attr_dbglevel);
12807 +
12808 +       #ifdef __IS_DUAL__
12809 +               error = ifx_proc_addproc("dump_params_1", procfs_dump_params_show_1, NULL);
12810 +               error = ifx_proc_addproc("dump_params_2", procfs_dump_params_show_2, NULL);
12811 +               error = device_create_file(dev, &dev_attr_dump_params_1);
12812 +               error = device_create_file(dev, &dev_attr_dump_params_2);
12813 +       #else
12814 +               error = ifx_proc_addproc("dump_params", procfs_dump_params_show, NULL);
12815 +               error = device_create_file(dev, &dev_attr_dump_params);
12816 +       #endif
12817 +
12818 +       #ifdef __IS_DUAL__
12819 +               error = ifx_proc_addproc("mode_1", procfs_mode_show_1, NULL);
12820 +               error = ifx_proc_addproc("mode_2", procfs_mode_show_2, NULL);
12821 +               error = device_create_file(dev, &dev_attr_mode_1);
12822 +               error = device_create_file(dev, &dev_attr_mode_2);
12823 +       #else
12824 +               error = ifx_proc_addproc("mode", procfs_mode_show, NULL);
12825 +               error = device_create_file(dev, &dev_attr_mode);
12826 +       #endif
12827 +
12828 +       #ifdef __IS_HOST__
12829 +               #ifdef __IS_DUAL__
12830 +                       error = ifx_proc_addproc("buspower_1", procfs_buspower_show_1, procfs_buspower_store_1);
12831 +                       error = ifx_proc_addproc("buspower_2", procfs_buspower_show_2, procfs_buspower_store_2);
12832 +                       error = device_create_file(dev, &dev_attr_buspower_1);
12833 +                       error = device_create_file(dev, &dev_attr_buspower_2);
12834 +               #else
12835 +                       error = ifx_proc_addproc("buspower", procfs_buspower_show, procfs_buspower_store);
12836 +                       error = device_create_file(dev, &dev_attr_buspower);
12837 +               #endif
12838 +
12839 +               #ifdef __IS_DUAL__
12840 +                       error = ifx_proc_addproc("bussuspend_1", procfs_bussuspend_show_1, NULL);
12841 +                       error = ifx_proc_addproc("bussuspend_2", procfs_bussuspend_show_2, NULL);
12842 +                       error = device_create_file(dev, &dev_attr_bussuspend_1);
12843 +                       error = device_create_file(dev, &dev_attr_bussuspend_2);
12844 +               #else
12845 +                       error = ifx_proc_addproc("bussuspend", procfs_bussuspend_show, NULL);
12846 +                       error = device_create_file(dev, &dev_attr_bussuspend);
12847 +               #endif
12848 +
12849 +               #ifdef __IS_DUAL__
12850 +                       error = ifx_proc_addproc("busconnected_1", procfs_busconnected_show_1, NULL);
12851 +                       error = ifx_proc_addproc("busconnected_2", procfs_busconnected_show_2, NULL);
12852 +                       error = device_create_file(dev, &dev_attr_busconnected_1);
12853 +                       error = device_create_file(dev, &dev_attr_busconnected_2);
12854 +               #else
12855 +                       error = ifx_proc_addproc("busconnected", procfs_busconnected_show, NULL);
12856 +                       error = device_create_file(dev, &dev_attr_busconnected);
12857 +               #endif
12858 +
12859 +               #ifdef __IS_DUAL__
12860 +                       error = ifx_proc_addproc("connectspeed_1", procfs_connectspeed_show_1, NULL);
12861 +                       error = ifx_proc_addproc("connectspeed_2", procfs_connectspeed_show_2, NULL);
12862 +                       error = device_create_file(dev, &dev_attr_connectspeed_1);
12863 +                       error = device_create_file(dev, &dev_attr_connectspeed_2);
12864 +               #else
12865 +                       error = ifx_proc_addproc("connectspeed", procfs_connectspeed_show, NULL);
12866 +                       error = device_create_file(dev, &dev_attr_connectspeed);
12867 +               #endif
12868 +       #endif
12869 +
12870 +       #ifdef __IS_DEVICE__
12871 +               error = ifx_proc_addproc("devspeed", procfs_devspeed_show, NULL);
12872 +               error = device_create_file(dev, &dev_attr_devspeed);
12873 +               error = ifx_proc_addproc("enumspeed", procfs_enumspeed_show, NULL);
12874 +               error = device_create_file(dev, &dev_attr_enumspeed);
12875 +       #endif
12876 +
12877 +       //////////////////////////////////////////////////////
12878 +       #ifdef __ENABLE_DUMP__
12879 +               #ifdef __IS_DUAL__
12880 +                       error = ifx_proc_addproc("dump_reg_1", procfs_dump_reg_show_1, NULL);
12881 +                       error = ifx_proc_addproc("dump_reg_2", procfs_dump_reg_show_2, NULL);
12882 +                       error = device_create_file(dev, &dev_attr_dump_reg_1);
12883 +                       error = device_create_file(dev, &dev_attr_dump_reg_2);
12884 +               #else
12885 +                       error = ifx_proc_addproc("dump_reg", procfs_dump_reg_show, NULL);
12886 +                       error = device_create_file(dev, &dev_attr_dump_reg);
12887 +               #endif
12888 +
12889 +               #ifdef __IS_DUAL__
12890 +                       error = ifx_proc_addproc("dump_spram_1", procfs_dump_spram_show_1, NULL);
12891 +                       error = ifx_proc_addproc("dump_spram_2", procfs_dump_spram_show_2, NULL);
12892 +                       error = device_create_file(dev, &dev_attr_dump_spram_1);
12893 +                       error = device_create_file(dev, &dev_attr_dump_spram_2);
12894 +               #else
12895 +                       error = ifx_proc_addproc("dump_spram", procfs_dump_spram_show, NULL);
12896 +                       error = device_create_file(dev, &dev_attr_dump_spram);
12897 +               #endif
12898 +
12899 +               #ifdef __IS_HOST__
12900 +                       #ifdef __IS_DUAL__
12901 +                               error = ifx_proc_addproc("dump_host_state_1", procfs_dump_host_state_show_1, NULL);
12902 +                               error = ifx_proc_addproc("dump_host_state_2", procfs_dump_host_state_show_2, NULL);
12903 +                               error = device_create_file(dev, &dev_attr_dump_host_state_1);
12904 +                               error = device_create_file(dev, &dev_attr_dump_host_state_2);
12905 +                       #else
12906 +                               error = ifx_proc_addproc("dump_host_state", procfs_dump_host_state_show, NULL);
12907 +                               error = device_create_file(dev, &dev_attr_dump_host_state);
12908 +                       #endif
12909 +               #endif
12910 +       #endif //__ENABLE_DUMP__
12911 +       //////////////////////////////////////////////////////
12912 +}
12913 +
12914 +
12915 +/*!
12916 +  \brief This function remove the sysfs and procfs entries
12917 +  \param[in] _dev Pointer of device structure, if applied
12918 + */
12919 +void ifxusb_attr_remove (void *_dev)
12920 +{
12921 +       struct device *dev = (struct device *) _dev;
12922 +
12923 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
12924 +       ifx_proc_delproc("dbglevel");
12925 +       device_remove_file(dev, &dev_attr_dbglevel);
12926 +
12927 +       #ifdef __IS_DUAL__
12928 +               ifx_proc_delproc("dump_params_1");
12929 +               ifx_proc_delproc("dump_params_2");
12930 +               device_remove_file(dev, &dev_attr_dump_params_1);
12931 +               device_remove_file(dev, &dev_attr_dump_params_2);
12932 +       #else
12933 +               ifx_proc_delproc("dump_params");
12934 +               device_remove_file(dev, &dev_attr_dump_params);
12935 +       #endif
12936 +
12937 +       #ifdef __IS_DUAL__
12938 +               ifx_proc_delproc("mode_1");
12939 +               ifx_proc_delproc("mode_2");
12940 +               device_remove_file(dev, &dev_attr_mode_1);
12941 +               device_remove_file(dev, &dev_attr_mode_2);
12942 +       #else
12943 +               ifx_proc_delproc("mode");
12944 +               device_remove_file(dev, &dev_attr_mode);
12945 +       #endif
12946 +
12947 +       #ifdef __IS_HOST__
12948 +               #ifdef __IS_DUAL__
12949 +                       ifx_proc_delproc("buspower_1");
12950 +                       ifx_proc_delproc("buspower_2");
12951 +                       device_remove_file(dev, &dev_attr_buspower_1);
12952 +                       device_remove_file(dev, &dev_attr_buspower_2);
12953 +               #else
12954 +                       ifx_proc_delproc("buspower");
12955 +                       device_remove_file(dev, &dev_attr_buspower);
12956 +               #endif
12957 +
12958 +               #ifdef __IS_DUAL__
12959 +                       ifx_proc_delproc("bussuspend_1");
12960 +                       ifx_proc_delproc("bussuspend_2");
12961 +                       device_remove_file(dev, &dev_attr_bussuspend_1);
12962 +                       device_remove_file(dev, &dev_attr_bussuspend_2);
12963 +               #else
12964 +                       ifx_proc_delproc("bussuspend");
12965 +                       device_remove_file(dev, &dev_attr_bussuspend);
12966 +               #endif
12967 +
12968 +               #ifdef __IS_DUAL__
12969 +                       ifx_proc_delproc("busconnected_1");
12970 +                       ifx_proc_delproc("busconnected_2");
12971 +                       device_remove_file(dev, &dev_attr_busconnected_1);
12972 +                       device_remove_file(dev, &dev_attr_busconnected_2);
12973 +               #else
12974 +                       ifx_proc_delproc("busconnected");
12975 +                       device_remove_file(dev, &dev_attr_busconnected);
12976 +               #endif
12977 +
12978 +               #ifdef __IS_DUAL__
12979 +                       ifx_proc_delproc("connectspeed_1");
12980 +                       ifx_proc_delproc("connectspeed_2");
12981 +                       device_remove_file(dev, &dev_attr_connectspeed_1);
12982 +                       device_remove_file(dev, &dev_attr_connectspeed_2);
12983 +               #else
12984 +                       ifx_proc_delproc("connectspeed");
12985 +                       device_remove_file(dev, &dev_attr_connectspeed);
12986 +               #endif
12987 +       #endif
12988 +
12989 +       #ifdef __IS_DEVICE__
12990 +               ifx_proc_delproc("devspeed");
12991 +               device_remove_file(dev, &dev_attr_devspeed);
12992 +               ifx_proc_delproc("enumspeed");
12993 +               device_remove_file(dev, &dev_attr_enumspeed);
12994 +       #endif
12995 +
12996 +       #ifdef __ENABLE_DUMP__
12997 +               #ifdef __IS_DUAL__
12998 +                       ifx_proc_delproc("dump_reg_1");
12999 +                       ifx_proc_delproc("dump_reg_2");
13000 +                       device_remove_file(dev, &dev_attr_dump_reg_1);
13001 +                       device_remove_file(dev, &dev_attr_dump_reg_2);
13002 +               #else
13003 +                       ifx_proc_delproc("dump_reg");
13004 +                       device_remove_file(dev, &dev_attr_dump_reg);
13005 +               #endif
13006 +
13007 +               #ifdef __IS_DUAL__
13008 +                       ifx_proc_delproc("dump_spram_1");
13009 +                       ifx_proc_delproc("dump_spram_2");
13010 +                       device_remove_file(dev, &dev_attr_dump_spram_1);
13011 +                       device_remove_file(dev, &dev_attr_dump_spram_2);
13012 +               #else
13013 +                       ifx_proc_delproc("dump_spram");
13014 +                       device_remove_file(dev, &dev_attr_dump_spram);
13015 +               #endif
13016 +
13017 +               #ifdef __IS_HOST__
13018 +                       #ifdef __IS_DUAL__
13019 +                               ifx_proc_delproc("dump_host_state_1");
13020 +                               ifx_proc_delproc("dump_host_state_2");
13021 +                               device_remove_file(dev, &dev_attr_dump_host_state_1);
13022 +                               device_remove_file(dev, &dev_attr_dump_host_state_2);
13023 +                       #else
13024 +                               ifx_proc_delproc("dump_host_state");
13025 +                               device_remove_file(dev, &dev_attr_dump_host_state);
13026 +                       #endif
13027 +               #endif
13028 +       #endif //__ENABLE_DUMP__
13029 +       /* AVM/WK fix: del IFXUSB root dir*/
13030 +       ifx_proc_delproc(NULL);
13031 +}
13032 +
13033 +static struct proc_dir_entry * proc_ifx_root = NULL;
13034 +
13035 +/* initialize the proc file system and make a dir named /proc/[name] */
13036 +static void ifx_proc_init(void)
13037 +{
13038 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13039 +       proc_ifx_root = proc_mkdir(ifxusb_driver_name, (void *)0);
13040 +       if (!proc_ifx_root){
13041 +               IFX_PRINT("%s proc initialization failed! \n", ifxusb_driver_name);
13042 +               return;
13043 +       }
13044 +}
13045 +
13046 +/* proc file system add function for debugging. */
13047 +static int ifx_proc_addproc(char *funcname, read_proc_t *hookfuncr, write_proc_t *hookfuncw)
13048 +{
13049 +       struct proc_dir_entry *pe;
13050 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13051 +       if (!proc_ifx_root)
13052 +               ifx_proc_init();
13053 +
13054 +       if (hookfuncw == NULL)
13055 +       {
13056 +               pe = create_proc_read_entry(funcname, S_IRUGO, proc_ifx_root, hookfuncr, NULL);
13057 +               if (!pe)
13058 +               {
13059 +                       IFX_PRINT("ERROR in creating read proc entry (%s)! \n", funcname);
13060 +                       return -1;
13061 +               }
13062 +       }
13063 +       else
13064 +       {
13065 +               pe = create_proc_entry(funcname, S_IRUGO | S_IWUGO, proc_ifx_root);
13066 +               if (pe)
13067 +               {
13068 +                       pe->read_proc = hookfuncr;
13069 +                       pe->write_proc = hookfuncw;
13070 +               }
13071 +               else
13072 +               {
13073 +                       IFX_PRINT("ERROR in creating proc entry (%s)! \n", funcname);
13074 +                       return -1;
13075 +               }
13076 +       }
13077 +       return 0;
13078 +}
13079 +
13080 +
13081 +/* proc file system del function for removing module. */
13082 +static void ifx_proc_delproc(char *funcname)
13083 +{
13084 +/* AVM/WK Fix*/
13085 +       if (funcname != NULL) {
13086 +               remove_proc_entry(funcname, proc_ifx_root);
13087 +       } else {
13088 +               remove_proc_entry(ifxusb_driver_name, NULL);
13089 +               proc_ifx_root = NULL;
13090 +       }
13091 +}
13092 +
13093 +static void ifxusb_dump_params(ifxusb_core_if_t *_core_if)
13094 +{
13095 +       ifxusb_params_t *params=&_core_if->params;
13096 +
13097 +       #ifdef __IS_HOST__
13098 +               IFX_PRINT("IFXUSB Dump Parameters ( Host Mode) \n");
13099 +       #endif //__IS_HOST__
13100 +       #ifdef __IS_DEVICE__
13101 +               IFX_PRINT("IFXUSB Dump Parameters ( Device Mode) \n");
13102 +       #endif //__IS_DEVICE__
13103 +
13104 +       #ifdef __DESC_DMA__
13105 +               IFX_PRINT("DMA: Hermes DMA\n");
13106 +       #else
13107 +               IFX_PRINT("DMA: Non-Desc DMA\n");
13108 +       #endif
13109 +       IFX_PRINT("     Burst size: %d\n",params->dma_burst_size);
13110 +
13111 +       if     (params->speed==1)
13112 +               IFX_PRINT("Full Speed only\n");
13113 +       else if(params->speed==0)
13114 +               IFX_PRINT("Full/Hign Speed\n");
13115 +       else
13116 +               IFX_PRINT("Unkonwn setting (%d) for Speed\n",params->speed);
13117 +
13118 +       IFX_PRINT("Total Data FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n",
13119 +               params->data_fifo_size,params->data_fifo_size,
13120 +               params->data_fifo_size*4, params->data_fifo_size*4
13121 +       );
13122 +
13123 +       #ifdef __IS_DEVICE__
13124 +               IFX_PRINT("Rx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n",
13125 +                       params->rx_fifo_size,params->rx_fifo_size,
13126 +                       params->rx_fifo_size*4, params->rx_fifo_size*4
13127 +               );
13128 +               {
13129 +                       int i;
13130 +                       for(i=0;i<MAX_EPS_CHANNELS;i++)
13131 +                       {
13132 +                               IFX_PRINT("Tx FIFO #%d size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n",i,
13133 +                                       params->tx_fifo_size[i],params->tx_fifo_size[i],
13134 +                                       params->tx_fifo_size[i]*4, params->tx_fifo_size[i]*4
13135 +                               );
13136 +                       }
13137 +               }
13138 +               #ifdef __DED_FIFO__
13139 +                       IFX_PRINT("Treshold : %s Rx:%d Tx:%d \n",
13140 +                               (params->thr_ctl)?"On":"Off",params->tx_thr_length,params->rx_thr_length);
13141 +               #endif
13142 +       #else //__IS_HOST__
13143 +               IFX_PRINT("Host Channels: %d\n",params->host_channels);
13144 +
13145 +               IFX_PRINT("Rx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n",
13146 +                       params->data_fifo_size,params->data_fifo_size,
13147 +                       params->data_fifo_size*4, params->data_fifo_size*4
13148 +               );
13149 +
13150 +               IFX_PRINT("NP Tx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n",
13151 +                       params->nperio_tx_fifo_size,params->nperio_tx_fifo_size,
13152 +                       params->nperio_tx_fifo_size*4, params->nperio_tx_fifo_size*4
13153 +               );
13154 +
13155 +               IFX_PRINT(" P Tx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n",
13156 +                       params->perio_tx_fifo_size,params->perio_tx_fifo_size,
13157 +                       params->perio_tx_fifo_size*4, params->perio_tx_fifo_size*4
13158 +               );
13159 +       #endif //__IS_HOST__
13160 +
13161 +       IFX_PRINT("Max Transfer size: %d(0x%06X) Bytes\n",
13162 +               params->max_transfer_size,params->max_transfer_size
13163 +       );
13164 +       IFX_PRINT("Max Packet Count: %d(0x%06X)\n",
13165 +               params->max_packet_count,params->max_packet_count
13166 +       );
13167 +
13168 +       IFX_PRINT("PHY UTMI Width: %d\n",params->phy_utmi_width);
13169 +
13170 +       IFX_PRINT("Turn Around Time: HS:%d FS:%d\n",params->turn_around_time_hs,params->turn_around_time_fs);
13171 +       IFX_PRINT("Timeout Calibration: HS:%d FS:%d\n",params->timeout_cal_hs,params->timeout_cal_fs);
13172 +
13173 +
13174 +       IFX_PRINT("==================================================\n");
13175 +       IFX_PRINT("End of Parameters Dump\n");
13176 +       IFX_PRINT("==================================================\n");
13177 +}
13178 +
13179 +
13180 --- /dev/null
13181 +++ b/drivers/usb/ifxhcd/ifxusb_driver.c
13182 @@ -0,0 +1,970 @@
13183 +/*****************************************************************************
13184 + **   FILE NAME       : ifxusb_driver.c
13185 + **   PROJECT         : IFX USB sub-system V3
13186 + **   MODULES         : IFX USB sub-system Host and Device driver
13187 + **   SRC VERSION     : 1.0
13188 + **   DATE            : 1/Jan/2009
13189 + **   AUTHOR          : Chen, Howard
13190 + **   DESCRIPTION     : The provides the initialization and cleanup entry
13191 + **                     points for the IFX USB driver. This module can be
13192 + **                     dynamically loaded with insmod command or built-in
13193 + **                     with kernel. When loaded or executed the ifxusb_driver_init
13194 + **                     function is called. When the module is removed (using rmmod),
13195 + **                     the ifxusb_driver_cleanup function is called.
13196 + *****************************************************************************/
13197 +
13198 +/*!
13199 + \file ifxusb_driver.c
13200 + \brief This file contains the loading/unloading interface to the Linux driver.
13201 +*/
13202 +
13203 +#include <linux/version.h>
13204 +#include "ifxusb_version.h"
13205 +
13206 +#include <linux/kernel.h>
13207 +#include <linux/module.h>
13208 +#include <linux/moduleparam.h>
13209 +#include <linux/init.h>
13210 +
13211 +#include <linux/device.h>
13212 +#include <linux/platform_device.h>
13213 +
13214 +#include <linux/errno.h>
13215 +#include <linux/types.h>
13216 +#include <linux/stat.h>  /* permission constants */
13217 +#include <linux/gpio.h>
13218 +#include <lantiq_soc.h>
13219 +
13220 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
13221 +       #include <linux/irq.h>
13222 +#endif
13223 +
13224 +#include <asm/io.h>
13225 +
13226 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
13227 +       #include <asm/irq.h>
13228 +#endif
13229 +
13230 +#include "ifxusb_plat.h"
13231 +
13232 +#include "ifxusb_cif.h"
13233 +
13234 +#ifdef __IS_HOST__
13235 +       #include "ifxhcd.h"
13236 +
13237 +       #define    USB_DRIVER_DESC              "IFX USB HCD driver"
13238 +       const char ifxusb_driver_name[]    = "ifxusb_hcd";
13239 +
13240 +       #ifdef __IS_DUAL__
13241 +               ifxhcd_hcd_t ifxusb_hcd_1;
13242 +               ifxhcd_hcd_t ifxusb_hcd_2;
13243 +               const char ifxusb_hcd_name_1[] = "ifxusb_hcd_1";
13244 +               const char ifxusb_hcd_name_2[] = "ifxusb_hcd_2";
13245 +       #else
13246 +               ifxhcd_hcd_t ifxusb_hcd;
13247 +               const char ifxusb_hcd_name[]   = "ifxusb_hcd";
13248 +       #endif
13249 +
13250 +       #if defined(__DO_OC_INT__)
13251 +               static unsigned int  oc_int_installed=0;
13252 +               static ifxhcd_hcd_t *oc_int_id=NULL;
13253 +       #endif
13254 +#endif
13255 +
13256 +#ifdef __IS_DEVICE__
13257 +       #include "ifxpcd.h"
13258 +
13259 +       #define    USB_DRIVER_DESC              "IFX USB PCD driver"
13260 +       const char ifxusb_driver_name[] = "ifxusb_pcd";
13261 +
13262 +       ifxpcd_pcd_t ifxusb_pcd;
13263 +       const char ifxusb_pcd_name[]    = "ifxusb_pcd";
13264 +#endif
13265 +
13266 +/* Global Debug Level Mask. */
13267 +#ifdef __IS_HOST__
13268 +       uint32_t h_dbg_lvl = 0x00;
13269 +#endif
13270 +
13271 +#ifdef __IS_DEVICE__
13272 +       uint32_t d_dbg_lvl = 0x00;
13273 +#endif
13274 +
13275 +ifxusb_params_t ifxusb_module_params;
13276 +
13277 +static void parse_parms(void);
13278 +
13279 +
13280 +#include <lantiq_irq.h>
13281 +#define IFX_USB0_IR                     (INT_NUM_IM1_IRL0 + 22)
13282 +#define IFX_USB1_IR                     (INT_NUM_IM2_IRL0 + 19)
13283 +
13284 +/*!
13285 +   \brief This function is called when a driver is unregistered. This happens when
13286 +  the rmmod command is executed. The device may or may not be electrically
13287 +  present. If it is present, the driver stops device processing. Any resources
13288 +  used on behalf of this device are freed.
13289 +*/
13290 +static int ifxusb_driver_remove(struct platform_device *_dev)
13291 +{
13292 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13293 +       #ifdef __IS_HOST__
13294 +               #if defined(__DO_OC_INT__)
13295 +                       #if defined(__DO_OC_INT_ENABLE__)
13296 +                               ifxusb_oc_int_off();
13297 +                       #endif
13298 +
13299 +                       if(oc_int_installed && oc_int_id)
13300 +                               free_irq((unsigned int)IFXUSB_OC_IRQ, oc_int_id );
13301 +                       oc_int_installed=0;
13302 +                       oc_int_id=NULL;
13303 +               #endif
13304 +
13305 +               #if defined(__IS_DUAL__)
13306 +                       ifxhcd_remove(&ifxusb_hcd_1);
13307 +                       ifxusb_core_if_remove(&ifxusb_hcd_1.core_if );
13308 +                       ifxhcd_remove(&ifxusb_hcd_2);
13309 +                       ifxusb_core_if_remove(&ifxusb_hcd_2.core_if );
13310 +               #else
13311 +                       ifxhcd_remove(&ifxusb_hcd);
13312 +                       ifxusb_core_if_remove(&ifxusb_hcd.core_if );
13313 +               #endif
13314 +       #endif
13315 +
13316 +       #ifdef __IS_DEVICE__
13317 +               ifxpcd_remove();
13318 +               ifxusb_core_if_remove(&ifxusb_pcd.core_if );
13319 +       #endif
13320 +
13321 +       /* Remove the device attributes */
13322 +
13323 +       ifxusb_attr_remove(&_dev->dev);
13324 +
13325 +       return 0;
13326 +}
13327 +
13328 +
13329 +/* Function to setup the structures to control one usb core running as host*/
13330 +#ifdef __IS_HOST__
13331 +/*!
13332 +   \brief inlined by ifxusb_driver_probe(), handling host mode probing. Run at each host core.
13333 +*/
13334 +       static inline int ifxusb_driver_probe_h(ifxhcd_hcd_t *_hcd,
13335 +                                               int           _irq,
13336 +                                               uint32_t      _iobase,
13337 +                                               uint32_t      _fifomem,
13338 +                                               uint32_t      _fifodbg
13339 +                                               )
13340 +       {
13341 +               int retval = 0;
13342 +
13343 +               IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13344 +
13345 +#ifdef __DEV_NEW__
13346 +               ifxusb_power_off  (&_hcd->core_if);
13347 +               ifxusb_phy_power_off  (&_hcd->core_if); // Test
13348 +               mdelay(500);
13349 +#endif //__DEV_NEW__
13350 +               ifxusb_power_on  (&_hcd->core_if);
13351 +               mdelay(50);
13352 +               ifxusb_phy_power_on  (&_hcd->core_if); // Test
13353 +               mdelay(50);
13354 +               ifxusb_hard_reset(&_hcd->core_if);
13355 +               retval =ifxusb_core_if_init(&_hcd->core_if,
13356 +                                            _irq,
13357 +                                            _iobase,
13358 +                                            _fifomem,
13359 +                                            _fifodbg);
13360 +               if(retval)
13361 +                       return retval;
13362 +
13363 +               ifxusb_host_core_init(&_hcd->core_if,&ifxusb_module_params);
13364 +
13365 +               ifxusb_disable_global_interrupts( &_hcd->core_if);
13366 +
13367 +               /* The driver is now initialized and need to be registered into Linux USB sub-system */
13368 +
13369 +               retval = ifxhcd_init(_hcd); // hook the hcd into usb ss
13370 +
13371 +               if (retval != 0)
13372 +               {
13373 +                       IFX_ERROR("_hcd_init failed\n");
13374 +                       return retval;
13375 +               }
13376 +
13377 +               //ifxusb_enable_global_interrupts( _hcd->core_if ); // this should be done at hcd_start , including hcd_interrupt
13378 +               return 0;
13379 +       }
13380 +#endif //__IS_HOST__
13381 +
13382 +#ifdef __IS_DEVICE__
13383 +/*!
13384 +  \brief inlined by ifxusb_driver_probe(), handling device mode probing.
13385 +*/
13386 +       static inline int ifxusb_driver_probe_d(ifxpcd_pcd_t *_pcd,
13387 +                                               int           _irq,
13388 +                                               uint32_t      _iobase,
13389 +                                               uint32_t      _fifomem,
13390 +                                               uint32_t      _fifodbg
13391 +                                               )
13392 +       {
13393 +               int retval = 0;
13394 +
13395 +               IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13396 +#ifdef __DEV_NEW__
13397 +               ifxusb_power_off  (&_pcd->core_if);
13398 +               ifxusb_phy_power_off (&_pcd->core_if); // Test
13399 +               mdelay(500);
13400 +#endif // __DEV_NEW__
13401 +               ifxusb_power_on  (&_pcd->core_if);
13402 +               mdelay(50);
13403 +               ifxusb_phy_power_on  (&_pcd->core_if); // Test
13404 +               mdelay(50);
13405 +               ifxusb_hard_reset(&_pcd->core_if);
13406 +               retval =ifxusb_core_if_init(&_pcd->core_if,
13407 +                                            _irq,
13408 +                                            _iobase,
13409 +                                            _fifomem,
13410 +                                            _fifodbg);
13411 +               if(retval)
13412 +                       return retval;
13413 +
13414 +               IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13415 +               ifxusb_dev_core_init(&_pcd->core_if,&ifxusb_module_params);
13416 +
13417 +               IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13418 +               ifxusb_disable_global_interrupts( &_pcd->core_if);
13419 +
13420 +               /* The driver is now initialized and need to be registered into
13421 +                  Linux USB Gadget sub-system
13422 +                */
13423 +               retval = ifxpcd_init();
13424 +               IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13425 +
13426 +               if (retval != 0)
13427 +               {
13428 +                       IFX_ERROR("_pcd_init failed\n");
13429 +                       return retval;
13430 +               }
13431 +               //ifxusb_enable_global_interrupts( _pcd->core_if );  // this should be done at gadget bind or start
13432 +               return 0;
13433 +       }
13434 +#endif //__IS_DEVICE__
13435 +
13436 +
13437 +
13438 +/*!
13439 +   \brief This function is called by module management in 2.6 kernel or by ifxusb_driver_init with 2.4 kernel
13440 +  It is to probe and setup IFXUSB core(s).
13441 +*/
13442 +static int ifxusb_driver_probe(struct platform_device *_dev)
13443 +{
13444 +       int retval = 0;
13445 +       int *pins = _dev->dev.platform_data;
13446 +       if (ltq_is_vr9()) {
13447 +               gpio_request(6, "id1");
13448 +               gpio_request(9, "id2");
13449 +               gpio_direction_input(6);
13450 +               gpio_direction_input(9);
13451 +       }
13452 +       if (pins) {
13453 +               if (pins[0]) {
13454 +                       gpio_request(pins[0], "vbus1");
13455 +                       gpio_direction_output(pins[0], 1);
13456 +               }
13457 +               if (pins[1] && ltq_is_vr9()) {
13458 +                       gpio_request(pins[1], "vbus2");
13459 +                       gpio_direction_output(pins[1], 1);
13460 +               }
13461 +       }
13462 +       // Parsing and store the parameters
13463 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13464 +       parse_parms();
13465 +
13466 +       #ifdef __IS_HOST__
13467 +               #if   defined(__IS_DUAL__)
13468 +                       memset(&ifxusb_hcd_1, 0, sizeof(ifxhcd_hcd_t));
13469 +                       memset(&ifxusb_hcd_2, 0, sizeof(ifxhcd_hcd_t));
13470 +
13471 +                       ifxusb_hcd_1.core_if.core_no=0;
13472 +                       ifxusb_hcd_2.core_if.core_no=1;
13473 +                       ifxusb_hcd_1.core_if.core_name=(char *)ifxusb_hcd_name_1;
13474 +                       ifxusb_hcd_2.core_if.core_name=(char *)ifxusb_hcd_name_2;
13475 +
13476 +                       ifxusb_hcd_1.dev=&_dev->dev;
13477 +                       ifxusb_hcd_2.dev=&_dev->dev;
13478 +
13479 +                       retval = ifxusb_driver_probe_h(&ifxusb_hcd_1,
13480 +                                                      IFX_USB0_IR,
13481 +                                                      IFXUSB1_IOMEM_BASE,
13482 +                                                      IFXUSB1_FIFOMEM_BASE,
13483 +                                                      IFXUSB1_FIFODBG_BASE
13484 +                                                      );
13485 +                       if(retval)
13486 +                               goto ifxusb_driver_probe_fail;
13487 +
13488 +                       retval = ifxusb_driver_probe_h(&ifxusb_hcd_2,
13489 +                                                      IFX_USB1_IR,
13490 +                                                      IFXUSB2_IOMEM_BASE,
13491 +                                                      IFXUSB2_FIFOMEM_BASE,
13492 +                                                      IFXUSB2_FIFODBG_BASE
13493 +                                                     );
13494 +                       if(retval)
13495 +                               goto ifxusb_driver_probe_fail;
13496 +
13497 +               #elif defined(__IS_FIRST__)
13498 +                       memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
13499 +
13500 +                       ifxusb_hcd.core_if.core_no=0;
13501 +                       ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
13502 +
13503 +                       ifxusb_hcd.dev=&_dev->dev;
13504 +
13505 +                       retval = ifxusb_driver_probe_h(&ifxusb_hcd,
13506 +                                                      IFX_USB0_IR,
13507 +                                                      IFXUSB1_IOMEM_BASE,
13508 +                                                      IFXUSB1_FIFOMEM_BASE,
13509 +                                                      IFXUSB1_FIFODBG_BASE
13510 +                                                     );
13511 +                       if(retval)
13512 +                               goto ifxusb_driver_probe_fail;
13513 +
13514 +               #elif defined(__IS_SECOND__)
13515 +                       memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
13516 +
13517 +                       ifxusb_hcd.core_if.core_no=1;
13518 +                       ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
13519 +
13520 +                       ifxusb_hcd.dev=&_dev->dev;
13521 +
13522 +                       retval = ifxusb_driver_probe_h(&ifxusb_hcd,
13523 +                                                      IFX_USB1_IR,
13524 +                                                      IFXUSB2_IOMEM_BASE,
13525 +                                                      IFXUSB2_FIFOMEM_BASE,
13526 +                                                      IFXUSB2_FIFODBG_BASE
13527 +                                                     );
13528 +                       if(retval)
13529 +                               goto ifxusb_driver_probe_fail;
13530 +
13531 +               #else
13532 +                       memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
13533 +
13534 +                       ifxusb_hcd.core_if.core_no=0;
13535 +                       ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
13536 +
13537 +                       ifxusb_hcd.dev=&_dev->dev;
13538 +
13539 +                       retval = ifxusb_driver_probe_h(&ifxusb_hcd,
13540 +                                                      IFXUSB_IRQ,
13541 +                                                      IFXUSB_IOMEM_BASE,
13542 +                                                      IFXUSB_FIFOMEM_BASE,
13543 +                                                      IFXUSB_FIFODBG_BASE
13544 +                                                     );
13545 +                       if(retval)
13546 +                               goto ifxusb_driver_probe_fail;
13547 +               #endif
13548 +
13549 +               #if defined(__DO_OC_INT__)
13550 +                       IFXUSB_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for irq%d\n", IFXUSB_OC_IRQ);
13551 +                       #if   defined(__IS_DUAL__)
13552 +                               request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq,
13553 +//                               SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd_1);
13554 +                                 IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd_1);
13555 +                               oc_int_id=&ifxusb_hcd_1;
13556 +                       #else
13557 +                               request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq,
13558 +//                               SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd);
13559 +                                 IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd);
13560 +                               oc_int_id=&ifxusb_hcd;
13561 +                       #endif
13562 +                       oc_int_installed=1;
13563 +
13564 +                       #if defined(__DO_OC_INT_ENABLE__)
13565 +                               ifxusb_oc_int_on();
13566 +                       #endif
13567 +               #endif
13568 +
13569 +       #endif
13570 +
13571 +       #ifdef __IS_DEVICE__
13572 +               memset(&ifxusb_pcd, 0, sizeof(ifxpcd_pcd_t));
13573 +               ifxusb_pcd.core_if.core_name=(char *)&ifxusb_pcd_name[0];
13574 +
13575 +               ifxusb_pcd.dev=&_dev->dev;
13576 +
13577 +               #if   defined(__IS_FIRST__)
13578 +                       ifxusb_pcd.core_if.core_no=0;
13579 +                       retval = ifxusb_driver_probe_d(&ifxusb_pcd,
13580 +                                                      IFXUSB1_IRQ,
13581 +                                                      IFXUSB1_IOMEM_BASE,
13582 +                                                      IFXUSB1_FIFOMEM_BASE,
13583 +                                                      IFXUSB1_FIFODBG_BASE
13584 +                                                     );
13585 +               #elif defined(__IS_SECOND__)
13586 +                       ifxusb_pcd.core_if.core_no=1;
13587 +                       retval = ifxusb_driver_probe_d(&ifxusb_pcd,
13588 +                                                      IFXUSB2_IRQ,
13589 +                                                      IFXUSB2_IOMEM_BASE,
13590 +                                                      IFXUSB2_FIFOMEM_BASE,
13591 +                                                      IFXUSB2_FIFODBG_BASE
13592 +                                                     );
13593 +               #else
13594 +                       ifxusb_pcd.core_if.core_no=0;
13595 +                       retval = ifxusb_driver_probe_d(&ifxusb_pcd,
13596 +                                                      IFXUSB_IRQ,
13597 +                                                      IFXUSB_IOMEM_BASE,
13598 +                                                      IFXUSB_FIFOMEM_BASE,
13599 +                                                      IFXUSB_FIFODBG_BASE
13600 +                                                     );
13601 +               #endif
13602 +               if(retval)
13603 +                       goto ifxusb_driver_probe_fail;
13604 +       #endif
13605 +
13606 +       ifxusb_attr_create(&_dev->dev);
13607 +
13608 +       return 0;
13609 +
13610 +ifxusb_driver_probe_fail:
13611 +       ifxusb_driver_remove(_dev);
13612 +       return retval;
13613 +}
13614 +
13615 +
13616 +
13617 +/*!
13618 +   \brief This function is called when the ifxusb_driver is installed with the insmod command.
13619 +*/
13620 +
13621 +
13622 +static struct platform_driver ifxusb_driver = {
13623 +       .driver = {
13624 +               .name           = ifxusb_driver_name,
13625 +               .owner = THIS_MODULE,
13626 +       },
13627 +       .probe          = ifxusb_driver_probe,
13628 +       .remove         = ifxusb_driver_remove,
13629 +};
13630 +
13631 +int __init ifxusb_driver_init(void)
13632 +{
13633 +       int retval = 0;
13634 +
13635 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13636 +       IFX_PRINT("%s: version %s\n", ifxusb_driver_name, IFXUSB_VERSION);
13637 +
13638 +       retval = platform_driver_register(&ifxusb_driver);
13639 +
13640 +       if (retval < 0) {
13641 +               IFX_ERROR("%s retval=%d\n", __func__, retval);
13642 +               return retval;
13643 +       }
13644 +       return retval;
13645 +}
13646 +
13647 +#if 0 // 2.4
13648 +       int __init ifxusb_driver_init(void)
13649 +       {
13650 +               int retval = 0;
13651 +               IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13652 +               IFX_PRINT("%s: version %s\n", ifxusb_driver_name, IFXUSB_VERSION);
13653 +               retval = ifxusb_driver_probe();
13654 +
13655 +               if (retval < 0) {
13656 +                       IFX_ERROR("%s retval=%d\n", __func__, retval);
13657 +                       return retval;
13658 +               }
13659 +
13660 +               return retval;
13661 +       }
13662 +#endif
13663 +
13664 +module_init(ifxusb_driver_init);
13665 +
13666 +
13667 +/*!
13668 +   \brief This function is called when the driver is removed from the kernel
13669 +  with the rmmod command. The driver unregisters itself with its bus
13670 +  driver.
13671 +*/
13672 +
13673 +void __exit ifxusb_driver_cleanup(void)
13674 +{
13675 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13676 +
13677 +       platform_driver_unregister(&ifxusb_driver);
13678 +
13679 +       IFX_PRINT("%s module removed\n", ifxusb_driver_name);
13680 +}
13681 +#if 0
13682 +       void __exit ifxusb_driver_cleanup(void)
13683 +       {
13684 +               IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13685 +               ifxusb_driver_remove();
13686 +               IFX_PRINT("%s module removed\n", ifxusb_driver_name);
13687 +       }
13688 +#endif
13689 +module_exit(ifxusb_driver_cleanup);
13690 +
13691 +
13692 +
13693 +MODULE_DESCRIPTION(USB_DRIVER_DESC);
13694 +MODULE_AUTHOR("Infineon");
13695 +MODULE_LICENSE("GPL");
13696 +
13697 +
13698 +
13699 +// Parameters set when loaded
13700 +//static long  dbg_lvl =0xFFFFFFFF;
13701 +static long  dbg_lvl =0;
13702 +static short dma_burst_size =-1;
13703 +static short speed =-1;
13704 +static long  data_fifo_size =-1;
13705 +#ifdef __IS_DEVICE__
13706 +       static long   rx_fifo_size =-1;
13707 +       #ifdef __DED_FIFO__
13708 +               static long  tx_fifo_size_00 =-1;
13709 +               static long  tx_fifo_size_01 =-1;
13710 +               static long  tx_fifo_size_02 =-1;
13711 +               static long  tx_fifo_size_03 =-1;
13712 +               static long  tx_fifo_size_04 =-1;
13713 +               static long  tx_fifo_size_05 =-1;
13714 +               static long  tx_fifo_size_06 =-1;
13715 +               static long  tx_fifo_size_07 =-1;
13716 +               static long  tx_fifo_size_08 =-1;
13717 +               static long  tx_fifo_size_09 =-1;
13718 +               static long  tx_fifo_size_10 =-1;
13719 +               static long  tx_fifo_size_11 =-1;
13720 +               static long  tx_fifo_size_12 =-1;
13721 +               static long  tx_fifo_size_13 =-1;
13722 +               static long  tx_fifo_size_14 =-1;
13723 +               static long  tx_fifo_size_15 =-1;
13724 +               static short thr_ctl=-1;
13725 +               static long  tx_thr_length =-1;
13726 +               static long  rx_thr_length =-1;
13727 +       #else
13728 +               static long   nperio_tx_fifo_size =-1;
13729 +               static long   perio_tx_fifo_size_01 =-1;
13730 +               static long   perio_tx_fifo_size_02 =-1;
13731 +               static long   perio_tx_fifo_size_03 =-1;
13732 +               static long   perio_tx_fifo_size_04 =-1;
13733 +               static long   perio_tx_fifo_size_05 =-1;
13734 +               static long   perio_tx_fifo_size_06 =-1;
13735 +               static long   perio_tx_fifo_size_07 =-1;
13736 +               static long   perio_tx_fifo_size_08 =-1;
13737 +               static long   perio_tx_fifo_size_09 =-1;
13738 +               static long   perio_tx_fifo_size_10 =-1;
13739 +               static long   perio_tx_fifo_size_11 =-1;
13740 +               static long   perio_tx_fifo_size_12 =-1;
13741 +               static long   perio_tx_fifo_size_13 =-1;
13742 +               static long   perio_tx_fifo_size_14 =-1;
13743 +               static long   perio_tx_fifo_size_15 =-1;
13744 +       #endif
13745 +       static short   dev_endpoints =-1;
13746 +#endif
13747 +
13748 +#ifdef __IS_HOST__
13749 +       static long   rx_fifo_size =-1;
13750 +       static long   nperio_tx_fifo_size =-1;
13751 +       static long   perio_tx_fifo_size =-1;
13752 +       static short  host_channels =-1;
13753 +#endif
13754 +
13755 +static long   max_transfer_size =-1;
13756 +static long   max_packet_count =-1;
13757 +static long   phy_utmi_width =-1;
13758 +static long   turn_around_time_hs =-1;
13759 +static long   turn_around_time_fs =-1;
13760 +static long   timeout_cal_hs =-1;
13761 +static long   timeout_cal_fs =-1;
13762 +
13763 +/*!
13764 +   \brief Parsing the parameters taken when module load
13765 +*/
13766 +static void parse_parms(void)
13767 +{
13768 +
13769 +       IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
13770 +       #ifdef __IS_HOST__
13771 +               h_dbg_lvl=dbg_lvl;
13772 +       #endif
13773 +       #ifdef __IS_DEVICE__
13774 +               d_dbg_lvl=dbg_lvl;
13775 +       #endif
13776 +
13777 +       switch(dma_burst_size)
13778 +       {
13779 +               case 0:
13780 +               case 1:
13781 +               case 4:
13782 +               case 8:
13783 +               case 16:
13784 +                       ifxusb_module_params.dma_burst_size=dma_burst_size;
13785 +                       break;
13786 +               default:
13787 +                       ifxusb_module_params.dma_burst_size=default_param_dma_burst_size;
13788 +       }
13789 +
13790 +       if(speed==0 || speed==1)
13791 +               ifxusb_module_params.speed=speed;
13792 +       else
13793 +               ifxusb_module_params.speed=default_param_speed;
13794 +
13795 +       if(max_transfer_size>=2048 && max_transfer_size<=65535)
13796 +               ifxusb_module_params.max_transfer_size=max_transfer_size;
13797 +       else
13798 +               ifxusb_module_params.max_transfer_size=default_param_max_transfer_size;
13799 +
13800 +       if(max_packet_count>=15 && max_packet_count<=511)
13801 +               ifxusb_module_params.max_packet_count=max_packet_count;
13802 +       else
13803 +               ifxusb_module_params.max_packet_count=default_param_max_packet_count;
13804 +
13805 +       switch(phy_utmi_width)
13806 +       {
13807 +               case 8:
13808 +               case 16:
13809 +                       ifxusb_module_params.phy_utmi_width=phy_utmi_width;
13810 +                       break;
13811 +               default:
13812 +                       ifxusb_module_params.phy_utmi_width=default_param_phy_utmi_width;
13813 +       }
13814 +
13815 +       if(turn_around_time_hs>=0 && turn_around_time_hs<=7)
13816 +               ifxusb_module_params.turn_around_time_hs=turn_around_time_hs;
13817 +       else
13818 +               ifxusb_module_params.turn_around_time_hs=default_param_turn_around_time_hs;
13819 +
13820 +       if(turn_around_time_fs>=0 && turn_around_time_fs<=7)
13821 +               ifxusb_module_params.turn_around_time_fs=turn_around_time_fs;
13822 +       else
13823 +               ifxusb_module_params.turn_around_time_fs=default_param_turn_around_time_fs;
13824 +
13825 +       if(timeout_cal_hs>=0 && timeout_cal_hs<=7)
13826 +               ifxusb_module_params.timeout_cal_hs=timeout_cal_hs;
13827 +       else
13828 +               ifxusb_module_params.timeout_cal_hs=default_param_timeout_cal_hs;
13829 +
13830 +       if(timeout_cal_fs>=0 && timeout_cal_fs<=7)
13831 +               ifxusb_module_params.timeout_cal_fs=timeout_cal_fs;
13832 +       else
13833 +               ifxusb_module_params.timeout_cal_fs=default_param_timeout_cal_fs;
13834 +
13835 +       if(data_fifo_size>=32 && data_fifo_size<=32768)
13836 +               ifxusb_module_params.data_fifo_size=data_fifo_size;
13837 +       else
13838 +               ifxusb_module_params.data_fifo_size=default_param_data_fifo_size;
13839 +
13840 +       #ifdef __IS_HOST__
13841 +               if(host_channels>=1 && host_channels<=16)
13842 +                       ifxusb_module_params.host_channels=host_channels;
13843 +               else
13844 +                       ifxusb_module_params.host_channels=default_param_host_channels;
13845 +
13846 +               if(rx_fifo_size>=16 && rx_fifo_size<=32768)
13847 +                       ifxusb_module_params.rx_fifo_size=rx_fifo_size;
13848 +               else
13849 +                       ifxusb_module_params.rx_fifo_size=default_param_rx_fifo_size;
13850 +
13851 +               if(nperio_tx_fifo_size>=16 && nperio_tx_fifo_size<=32768)
13852 +                       ifxusb_module_params.nperio_tx_fifo_size=nperio_tx_fifo_size;
13853 +               else
13854 +                       ifxusb_module_params.nperio_tx_fifo_size=default_param_nperio_tx_fifo_size;
13855 +
13856 +               if(perio_tx_fifo_size>=16 && perio_tx_fifo_size<=32768)
13857 +                       ifxusb_module_params.perio_tx_fifo_size=perio_tx_fifo_size;
13858 +               else
13859 +                       ifxusb_module_params.perio_tx_fifo_size=default_param_perio_tx_fifo_size;
13860 +       #endif //__IS_HOST__
13861 +
13862 +       #ifdef __IS_DEVICE__
13863 +               if(rx_fifo_size>=16 && rx_fifo_size<=32768)
13864 +                       ifxusb_module_params.rx_fifo_size=rx_fifo_size;
13865 +               else
13866 +                       ifxusb_module_params.rx_fifo_size=default_param_rx_fifo_size;
13867 +               #ifdef __DED_FIFO__
13868 +                       if(tx_fifo_size_00>=16 && tx_fifo_size_00<=32768)
13869 +                               ifxusb_module_params.tx_fifo_size[ 0]=tx_fifo_size_00;
13870 +                       else
13871 +                               ifxusb_module_params.tx_fifo_size[ 0]=default_param_tx_fifo_size_00;
13872 +                       if(tx_fifo_size_01>=0 && tx_fifo_size_01<=32768)
13873 +                               ifxusb_module_params.tx_fifo_size[ 1]=tx_fifo_size_01;
13874 +                       else
13875 +                               ifxusb_module_params.tx_fifo_size[ 1]=default_param_tx_fifo_size_01;
13876 +                       if(tx_fifo_size_02>=0 && tx_fifo_size_02<=32768)
13877 +                               ifxusb_module_params.tx_fifo_size[ 2]=tx_fifo_size_02;
13878 +                       else
13879 +                               ifxusb_module_params.tx_fifo_size[ 2]=default_param_tx_fifo_size_02;
13880 +                       if(tx_fifo_size_03>=0 && tx_fifo_size_03<=32768)
13881 +                               ifxusb_module_params.tx_fifo_size[ 3]=tx_fifo_size_03;
13882 +                       else
13883 +                               ifxusb_module_params.tx_fifo_size[ 3]=default_param_tx_fifo_size_03;
13884 +                       if(tx_fifo_size_04>=0 && tx_fifo_size_04<=32768)
13885 +                               ifxusb_module_params.tx_fifo_size[ 4]=tx_fifo_size_04;
13886 +                       else
13887 +                               ifxusb_module_params.tx_fifo_size[ 4]=default_param_tx_fifo_size_04;
13888 +                       if(tx_fifo_size_05>=0 && tx_fifo_size_05<=32768)
13889 +                               ifxusb_module_params.tx_fifo_size[ 5]=tx_fifo_size_05;
13890 +                       else
13891 +                               ifxusb_module_params.tx_fifo_size[ 5]=default_param_tx_fifo_size_05;
13892 +                       if(tx_fifo_size_06>=0 && tx_fifo_size_06<=32768)
13893 +                               ifxusb_module_params.tx_fifo_size[ 6]=tx_fifo_size_06;
13894 +                       else
13895 +                               ifxusb_module_params.tx_fifo_size[ 6]=default_param_tx_fifo_size_06;
13896 +                       if(tx_fifo_size_07>=0 && tx_fifo_size_07<=32768)
13897 +                               ifxusb_module_params.tx_fifo_size[ 7]=tx_fifo_size_07;
13898 +                       else
13899 +                               ifxusb_module_params.tx_fifo_size[ 7]=default_param_tx_fifo_size_07;
13900 +                       if(tx_fifo_size_08>=0 && tx_fifo_size_08<=32768)
13901 +                               ifxusb_module_params.tx_fifo_size[ 8]=tx_fifo_size_08;
13902 +                       else
13903 +                               ifxusb_module_params.tx_fifo_size[ 8]=default_param_tx_fifo_size_08;
13904 +                       if(tx_fifo_size_09>=0 && tx_fifo_size_09<=32768)
13905 +                               ifxusb_module_params.tx_fifo_size[ 9]=tx_fifo_size_09;
13906 +                       else
13907 +                               ifxusb_module_params.tx_fifo_size[ 9]=default_param_tx_fifo_size_09;
13908 +                       if(tx_fifo_size_10>=0 && tx_fifo_size_10<=32768)
13909 +                               ifxusb_module_params.tx_fifo_size[10]=tx_fifo_size_10;
13910 +                       else
13911 +                               ifxusb_module_params.tx_fifo_size[10]=default_param_tx_fifo_size_10;
13912 +                       if(tx_fifo_size_11>=0 && tx_fifo_size_11<=32768)
13913 +                               ifxusb_module_params.tx_fifo_size[11]=tx_fifo_size_11;
13914 +                       else
13915 +                               ifxusb_module_params.tx_fifo_size[11]=default_param_tx_fifo_size_11;
13916 +                       if(tx_fifo_size_12>=0 && tx_fifo_size_12<=32768)
13917 +                               ifxusb_module_params.tx_fifo_size[12]=tx_fifo_size_12;
13918 +                       else
13919 +                               ifxusb_module_params.tx_fifo_size[12]=default_param_tx_fifo_size_12;
13920 +                       if(tx_fifo_size_13>=0 && tx_fifo_size_13<=32768)
13921 +                               ifxusb_module_params.tx_fifo_size[13]=tx_fifo_size_13;
13922 +                       else
13923 +                               ifxusb_module_params.tx_fifo_size[13]=default_param_tx_fifo_size_13;
13924 +                       if(tx_fifo_size_14>=0 && tx_fifo_size_14<=32768)
13925 +                               ifxusb_module_params.tx_fifo_size[14]=tx_fifo_size_14;
13926 +                       else
13927 +                               ifxusb_module_params.tx_fifo_size[14]=default_param_tx_fifo_size_14;
13928 +                       if(tx_fifo_size_15>=0 && tx_fifo_size_15<=32768)
13929 +                               ifxusb_module_params.tx_fifo_size[15]=tx_fifo_size_15;
13930 +                       else
13931 +                               ifxusb_module_params.tx_fifo_size[15]=default_param_tx_fifo_size_15;
13932 +                       if(thr_ctl==0 || thr_ctl==1)
13933 +                               ifxusb_module_params.thr_ctl=thr_ctl;
13934 +                       else
13935 +                               ifxusb_module_params.thr_ctl=default_param_thr_ctl;
13936 +                       if(tx_thr_length>=16 && tx_thr_length<=511)
13937 +                               ifxusb_module_params.tx_thr_length=tx_thr_length;
13938 +                       else
13939 +                               ifxusb_module_params.tx_thr_length=default_param_tx_thr_length;
13940 +                       if(rx_thr_length>=16 && rx_thr_length<=511)
13941 +                               ifxusb_module_params.rx_thr_length=rx_thr_length;
13942 +                       else
13943 +                               ifxusb_module_params.rx_thr_length=default_param_rx_thr_length;
13944 +               #else  //__DED_FIFO__
13945 +                       if(nperio_tx_fifo_size>=16 && nperio_tx_fifo_size<=32768)
13946 +                               ifxusb_module_params.tx_fifo_size[ 0]=nperio_tx_fifo_size;
13947 +                       else
13948 +                               ifxusb_module_params.tx_fifo_size[ 0]=default_param_nperio_tx_fifo_size;
13949 +                       if(perio_tx_fifo_size_01>=0 && perio_tx_fifo_size_01<=32768)
13950 +                               ifxusb_module_params.tx_fifo_size[ 1]=perio_tx_fifo_size_01;
13951 +                       else
13952 +                               ifxusb_module_params.tx_fifo_size[ 1]=default_param_perio_tx_fifo_size_01;
13953 +                       if(perio_tx_fifo_size_02>=0 && perio_tx_fifo_size_02<=32768)
13954 +                               ifxusb_module_params.tx_fifo_size[ 2]=perio_tx_fifo_size_02;
13955 +                       else
13956 +                               ifxusb_module_params.tx_fifo_size[ 2]=default_param_perio_tx_fifo_size_02;
13957 +                       if(perio_tx_fifo_size_03>=0 && perio_tx_fifo_size_03<=32768)
13958 +                               ifxusb_module_params.tx_fifo_size[ 3]=perio_tx_fifo_size_03;
13959 +                       else
13960 +                               ifxusb_module_params.tx_fifo_size[ 3]=default_param_perio_tx_fifo_size_03;
13961 +                       if(perio_tx_fifo_size_04>=0 && perio_tx_fifo_size_04<=32768)
13962 +                               ifxusb_module_params.tx_fifo_size[ 4]=perio_tx_fifo_size_04;
13963 +                       else
13964 +                               ifxusb_module_params.tx_fifo_size[ 4]=default_param_perio_tx_fifo_size_04;
13965 +                       if(perio_tx_fifo_size_05>=0 && perio_tx_fifo_size_05<=32768)
13966 +                               ifxusb_module_params.tx_fifo_size[ 5]=perio_tx_fifo_size_05;
13967 +                       else
13968 +                               ifxusb_module_params.tx_fifo_size[ 5]=default_param_perio_tx_fifo_size_05;
13969 +                       if(perio_tx_fifo_size_06>=0 && perio_tx_fifo_size_06<=32768)
13970 +                               ifxusb_module_params.tx_fifo_size[ 6]=perio_tx_fifo_size_06;
13971 +                       else
13972 +                               ifxusb_module_params.tx_fifo_size[ 6]=default_param_perio_tx_fifo_size_06;
13973 +                       if(perio_tx_fifo_size_07>=0 && perio_tx_fifo_size_07<=32768)
13974 +                               ifxusb_module_params.tx_fifo_size[ 7]=perio_tx_fifo_size_07;
13975 +                       else
13976 +                               ifxusb_module_params.tx_fifo_size[ 7]=default_param_perio_tx_fifo_size_07;
13977 +                       if(perio_tx_fifo_size_08>=0 && perio_tx_fifo_size_08<=32768)
13978 +                               ifxusb_module_params.tx_fifo_size[ 8]=perio_tx_fifo_size_08;
13979 +                       else
13980 +                               ifxusb_module_params.tx_fifo_size[ 8]=default_param_perio_tx_fifo_size_08;
13981 +                       if(perio_tx_fifo_size_09>=0 && perio_tx_fifo_size_09<=32768)
13982 +                               ifxusb_module_params.tx_fifo_size[ 9]=perio_tx_fifo_size_09;
13983 +                       else
13984 +                               ifxusb_module_params.tx_fifo_size[ 9]=default_param_perio_tx_fifo_size_09;
13985 +                       if(perio_tx_fifo_size_10>=0 && perio_tx_fifo_size_10<=32768)
13986 +                               ifxusb_module_params.tx_fifo_size[10]=perio_tx_fifo_size_10;
13987 +                       else
13988 +                               ifxusb_module_params.tx_fifo_size[10]=default_param_perio_tx_fifo_size_10;
13989 +                       if(perio_tx_fifo_size_11>=0 && perio_tx_fifo_size_11<=32768)
13990 +                               ifxusb_module_params.tx_fifo_size[11]=perio_tx_fifo_size_11;
13991 +                       else
13992 +                               ifxusb_module_params.tx_fifo_size[11]=default_param_perio_tx_fifo_size_11;
13993 +                       if(perio_tx_fifo_size_12>=0 && perio_tx_fifo_size_12<=32768)
13994 +                               ifxusb_module_params.tx_fifo_size[12]=perio_tx_fifo_size_12;
13995 +                       else
13996 +                               ifxusb_module_params.tx_fifo_size[12]=default_param_perio_tx_fifo_size_12;
13997 +                       if(perio_tx_fifo_size_13>=0 && perio_tx_fifo_size_13<=32768)
13998 +                               ifxusb_module_params.tx_fifo_size[13]=perio_tx_fifo_size_13;
13999 +                       else
14000 +                               ifxusb_module_params.tx_fifo_size[13]=default_param_perio_tx_fifo_size_13;
14001 +                       if(perio_tx_fifo_size_14>=0 && perio_tx_fifo_size_14<=32768)
14002 +                               ifxusb_module_params.tx_fifo_size[14]=perio_tx_fifo_size_14;
14003 +                       else
14004 +                               ifxusb_module_params.tx_fifo_size[14]=default_param_perio_tx_fifo_size_14;
14005 +                       if(perio_tx_fifo_size_15>=0 && perio_tx_fifo_size_15<=32768)
14006 +                               ifxusb_module_params.tx_fifo_size[15]=perio_tx_fifo_size_15;
14007 +                       else
14008 +                               ifxusb_module_params.tx_fifo_size[15]=default_param_perio_tx_fifo_size_15;
14009 +               #endif //__DED_FIFO__
14010 +       #endif //__IS_DEVICE__
14011 +}
14012 +
14013 +
14014 +
14015 +
14016 +
14017 +
14018 +
14019 +module_param(dbg_lvl, long, 0444);
14020 +MODULE_PARM_DESC(dbg_lvl, "Debug level.");
14021 +
14022 +module_param(dma_burst_size, short, 0444);
14023 +MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 0, 1, 4, 8, 16");
14024 +
14025 +module_param(speed, short, 0444);
14026 +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
14027 +
14028 +module_param(data_fifo_size, long, 0444);
14029 +MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
14030 +
14031 +#ifdef __IS_DEVICE__
14032 +       module_param(rx_fifo_size, long, 0444);
14033 +       MODULE_PARM_DESC(rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
14034 +
14035 +       #ifdef __DED_FIFO__
14036 +               module_param(tx_fifo_size_00, long, 0444);
14037 +               MODULE_PARM_DESC(tx_fifo_size_00, "Number of words in the Tx FIFO #00 16-32768");
14038 +               module_param(tx_fifo_size_01, long, 0444);
14039 +               MODULE_PARM_DESC(tx_fifo_size_01, "Number of words in the Tx FIFO #01  0-32768");
14040 +               module_param(tx_fifo_size_02, long, 0444);
14041 +               MODULE_PARM_DESC(tx_fifo_size_02, "Number of words in the Tx FIFO #02  0-32768");
14042 +               module_param(tx_fifo_size_03, long, 0444);
14043 +               MODULE_PARM_DESC(tx_fifo_size_03, "Number of words in the Tx FIFO #03  0-32768");
14044 +               module_param(tx_fifo_size_04, long, 0444);
14045 +               MODULE_PARM_DESC(tx_fifo_size_04, "Number of words in the Tx FIFO #04  0-32768");
14046 +               module_param(tx_fifo_size_05, long, 0444);
14047 +               MODULE_PARM_DESC(tx_fifo_size_05, "Number of words in the Tx FIFO #05  0-32768");
14048 +               module_param(tx_fifo_size_06, long, 0444);
14049 +               MODULE_PARM_DESC(tx_fifo_size_06, "Number of words in the Tx FIFO #06  0-32768");
14050 +               module_param(tx_fifo_size_07, long, 0444);
14051 +               MODULE_PARM_DESC(tx_fifo_size_07, "Number of words in the Tx FIFO #07  0-32768");
14052 +               module_param(tx_fifo_size_08, long, 0444);
14053 +               MODULE_PARM_DESC(tx_fifo_size_08, "Number of words in the Tx FIFO #08  0-32768");
14054 +               module_param(tx_fifo_size_09, long, 0444);
14055 +               MODULE_PARM_DESC(tx_fifo_size_09, "Number of words in the Tx FIFO #09  0-32768");
14056 +               module_param(tx_fifo_size_10, long, 0444);
14057 +               MODULE_PARM_DESC(tx_fifo_size_10, "Number of words in the Tx FIFO #10  0-32768");
14058 +               module_param(tx_fifo_size_11, long, 0444);
14059 +               MODULE_PARM_DESC(tx_fifo_size_11, "Number of words in the Tx FIFO #11  0-32768");
14060 +               module_param(tx_fifo_size_12, long, 0444);
14061 +               MODULE_PARM_DESC(tx_fifo_size_12, "Number of words in the Tx FIFO #12  0-32768");
14062 +               module_param(tx_fifo_size_13, long, 0444);
14063 +               MODULE_PARM_DESC(tx_fifo_size_13, "Number of words in the Tx FIFO #13  0-32768");
14064 +               module_param(tx_fifo_size_14, long, 0444);
14065 +               MODULE_PARM_DESC(tx_fifo_size_14, "Number of words in the Tx FIFO #14  0-32768");
14066 +               module_param(tx_fifo_size_15, long, 0444);
14067 +               MODULE_PARM_DESC(tx_fifo_size_15, "Number of words in the Tx FIFO #15  0-32768");
14068 +
14069 +               module_param(thr_ctl, short, 0444);
14070 +               MODULE_PARM_DESC(thr_ctl, "0=Without 1=With Theshold Ctrl");
14071 +
14072 +               module_param(tx_thr_length, long, 0444);
14073 +               MODULE_PARM_DESC(tx_thr_length, "TX Threshold length");
14074 +
14075 +               module_param(rx_thr_length, long, 0444);
14076 +               MODULE_PARM_DESC(rx_thr_length, "RX Threshold length");
14077 +
14078 +       #else
14079 +               module_param(nperio_tx_fifo_size, long, 0444);
14080 +               MODULE_PARM_DESC(nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
14081 +
14082 +               module_param(perio_tx_fifo_size_01, long, 0444);
14083 +               MODULE_PARM_DESC(perio_tx_fifo_size_01, "Number of words in the periodic Tx FIFO #01  0-32768");
14084 +               module_param(perio_tx_fifo_size_02, long, 0444);
14085 +               MODULE_PARM_DESC(perio_tx_fifo_size_02, "Number of words in the periodic Tx FIFO #02  0-32768");
14086 +               module_param(perio_tx_fifo_size_03, long, 0444);
14087 +               MODULE_PARM_DESC(perio_tx_fifo_size_03, "Number of words in the periodic Tx FIFO #03  0-32768");
14088 +               module_param(perio_tx_fifo_size_04, long, 0444);
14089 +               MODULE_PARM_DESC(perio_tx_fifo_size_04, "Number of words in the periodic Tx FIFO #04  0-32768");
14090 +               module_param(perio_tx_fifo_size_05, long, 0444);
14091 +               MODULE_PARM_DESC(perio_tx_fifo_size_05, "Number of words in the periodic Tx FIFO #05  0-32768");
14092 +               module_param(perio_tx_fifo_size_06, long, 0444);
14093 +               MODULE_PARM_DESC(perio_tx_fifo_size_06, "Number of words in the periodic Tx FIFO #06  0-32768");
14094 +               module_param(perio_tx_fifo_size_07, long, 0444);
14095 +               MODULE_PARM_DESC(perio_tx_fifo_size_07, "Number of words in the periodic Tx FIFO #07  0-32768");
14096 +               module_param(perio_tx_fifo_size_08, long, 0444);
14097 +               MODULE_PARM_DESC(perio_tx_fifo_size_08, "Number of words in the periodic Tx FIFO #08  0-32768");
14098 +               module_param(perio_tx_fifo_size_09, long, 0444);
14099 +               MODULE_PARM_DESC(perio_tx_fifo_size_09, "Number of words in the periodic Tx FIFO #09  0-32768");
14100 +               module_param(perio_tx_fifo_size_10, long, 0444);
14101 +               MODULE_PARM_DESC(perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO #10  0-32768");
14102 +               module_param(perio_tx_fifo_size_11, long, 0444);
14103 +               MODULE_PARM_DESC(perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO #11  0-32768");
14104 +               module_param(perio_tx_fifo_size_12, long, 0444);
14105 +               MODULE_PARM_DESC(perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO #12  0-32768");
14106 +               module_param(perio_tx_fifo_size_13, long, 0444);
14107 +               MODULE_PARM_DESC(perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO #13  0-32768");
14108 +               module_param(perio_tx_fifo_size_14, long, 0444);
14109 +               MODULE_PARM_DESC(perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO #14  0-32768");
14110 +               module_param(perio_tx_fifo_size_15, long, 0444);
14111 +               MODULE_PARM_DESC(perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO #15  0-32768");
14112 +       #endif//__DED_FIFO__
14113 +       module_param(dev_endpoints, short, 0444);
14114 +       MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
14115 +#endif
14116 +
14117 +#ifdef __IS_HOST__
14118 +       module_param(rx_fifo_size, long, 0444);
14119 +       MODULE_PARM_DESC(rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
14120 +
14121 +       module_param(nperio_tx_fifo_size, long, 0444);
14122 +       MODULE_PARM_DESC(nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
14123 +
14124 +       module_param(perio_tx_fifo_size, long, 0444);
14125 +       MODULE_PARM_DESC(perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
14126 +
14127 +       module_param(host_channels, short, 0444);
14128 +       MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
14129 +#endif
14130 +
14131 +module_param(max_transfer_size, long, 0444);
14132 +MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
14133 +
14134 +module_param(max_packet_count, long, 0444);
14135 +MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
14136 +
14137 +module_param(phy_utmi_width, long, 0444);
14138 +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
14139 +
14140 +module_param(turn_around_time_hs, long, 0444);
14141 +MODULE_PARM_DESC(turn_around_time_hs, "Turn-Around time for HS");
14142 +
14143 +module_param(turn_around_time_fs, long, 0444);
14144 +MODULE_PARM_DESC(turn_around_time_fs, "Turn-Around time for FS");
14145 +
14146 +module_param(timeout_cal_hs, long, 0444);
14147 +MODULE_PARM_DESC(timeout_cal_hs, "Timeout Cal for HS");
14148 +
14149 +module_param(timeout_cal_fs, long, 0444);
14150 +MODULE_PARM_DESC(timeout_cal_fs, "Timeout Cal for FS");
14151 +
14152 +
14153 --- /dev/null
14154 +++ b/drivers/usb/ifxhcd/ifxusb_plat.h
14155 @@ -0,0 +1,1018 @@
14156 +/*****************************************************************************
14157 + **   FILE NAME       : ifxusb_plat.h
14158 + **   PROJECT         : IFX USB sub-system V3
14159 + **   MODULES         : IFX USB sub-system Host and Device driver
14160 + **   SRC VERSION     : 1.0
14161 + **   DATE            : 1/Jan/2009
14162 + **   AUTHOR          : Chen, Howard
14163 + **   DESCRIPTION     : This file contains the Platform Specific constants, interfaces
14164 + **                     (functions and macros).
14165 + **   FUNCTIONS       :
14166 + **   COMPILER        : gcc
14167 + **   REFERENCE       : IFX hardware ref handbook for each plateforms
14168 + **   COPYRIGHT       :
14169 + **  Version Control Section  **
14170 + **   $Author$
14171 + **   $Date$
14172 + **   $Revisions$
14173 + **   $Log$       Revision history
14174 + *****************************************************************************/
14175 +
14176 +
14177 +/*!
14178 +  \defgroup IFXUSB_PLATEFORM_DEFINITION Platform Specific constants, interfaces (functions and macros).
14179 +  \ingroup IFXUSB_DRIVER_V3
14180 +  \brief Maintain plateform specific definitions and macros in this file.
14181 +         Each plateform has its own definition zone.
14182 + */
14183 +
14184 +/*!
14185 +  \defgroup IFXUSB_PLATEFORM_MEM_ADDR Definition of memory address and size and default parameters
14186 +  \ingroup IFXUSB_PLATEFORM_DEFINITION
14187 + */
14188 +
14189 +/*!
14190 +  \defgroup IFXUSB_DBG_ROUTINE Routines for debug message
14191 +  \ingroup IFXUSB_PLATEFORM_DEFINITION
14192 + */
14193 +
14194 +
14195 +/*! \file ifxusb_plat.h
14196 +    \ingroup IFXUSB_DRIVER_V3
14197 +    \brief This file contains the Platform Specific constants, interfaces (functions and macros).
14198 +*/
14199 +
14200 +#if !defined(__IFXUSB_PLAT_H__)
14201 +#define __IFXUSB_PLAT_H__
14202 +
14203 +
14204 +#include <linux/types.h>
14205 +#include <linux/slab.h>
14206 +#include <linux/list.h>
14207 +#include <linux/delay.h>
14208 +#include <asm/io.h>
14209 +
14210 +
14211 +#define IFXUSB_IOMEM_SIZE   0x00001000
14212 +#define IFXUSB_FIFOMEM_SIZE 0x00010000
14213 +#define IFXUSB_FIFODBG_SIZE 0x00020000
14214 +
14215 +
14216 +
14217 +/*!
14218 +  \addtogroup IFXUSB_PLATEFORM_MEM_ADDR
14219 + */
14220 +/*@{*/
14221 +#if defined(__UEIP__)
14222 +       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
14223 +//             #define IFXUSB_IRQ          54
14224 +               #define IFXUSB_IOMEM_BASE   0x1e101000
14225 +               #define IFXUSB_FIFOMEM_BASE 0x1e120000
14226 +               #define IFXUSB_FIFODBG_BASE 0x1e140000
14227 +//             #define IFXUSB_OC_IRQ       151
14228 +
14229 +               #ifndef DANUBE_RCU_BASE_ADDR
14230 +                       #define DANUBE_RCU_BASE_ADDR            (0xBF203000)
14231 +               #endif
14232 +
14233 +               #ifndef DANUBE_CGU
14234 +                       #define DANUBE_CGU                      (0xBF103000)
14235 +               #endif
14236 +               #ifndef DANUBE_CGU_IFCCR
14237 +                       #define DANUBE_CGU_IFCCR                ((volatile unsigned long *)(DANUBE_CGU+ 0x0018))
14238 +               #endif
14239 +               #ifndef DANUBE_PMU
14240 +                       #define DANUBE_PMU                      (KSEG1+0x1F102000)
14241 +               #endif
14242 +               #ifndef DANUBE_PMU_PWDCR
14243 +                       #define DANUBE_PMU_PWDCR                ((volatile unsigned long *)(DANUBE_PMU+0x001C))
14244 +               #endif
14245 +
14246 +               #ifndef DANUBE_GPIO_P0_OUT
14247 +                       #define DANUBE_GPIO_P0_OUT                      (0xBF103000+0x10)
14248 +                       #define DANUBE_GPIO_P0_DIR                      (0xBF103000+0x18)
14249 +                       #define DANUBE_GPIO_P0_ALTSEL0                  (0xBF103000+0x1C)
14250 +                       #define DANUBE_GPIO_P0_ALTSEL1                  (0xBF103000+0x20)
14251 +                       #define DANUBE_GPIO_P0_OD                       (0xBF103000+0x24)
14252 +                       #define DANUBE_GPIO_P0_PUDSEL                   (0xBF103000+0x2C)
14253 +                       #define DANUBE_GPIO_P0_PUDEN                    (0xBF103000+0x30)
14254 +                       #define DANUBE_GPIO_P1_OUT                      (0xBF103000+0x40)
14255 +                       #define DANUBE_GPIO_P1_DIR                      (0xBF103000+0x48)
14256 +                       #define DANUBE_GPIO_P1_ALTSEL0                  (0xBF103000+0x4C)
14257 +                       #define DANUBE_GPIO_P1_ALTSEL1                  (0xBF103000+0x50)
14258 +                       #define DANUBE_GPIO_P1_OD                       (0xBF103000+0x54)
14259 +                       #define DANUBE_GPIO_P1_PUDSEL                   (0xBF103000+0x5C)
14260 +                       #define DANUBE_GPIO_P1_PUDEN                    (0xBF103000+0x60)
14261 +               #endif
14262 +
14263 +               #define DANUBE_RCU_USBCFG  ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x18))
14264 +               #define DANUBE_RCU_RESET   ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x10))
14265 +               #define DANUBE_USBCFG_HDSEL_BIT    11   // 0:host, 1:device
14266 +               #define DANUBE_USBCFG_HOST_END_BIT 10   // 0:little_end, 1:big_end
14267 +               #define DANUBE_USBCFG_SLV_END_BIT  9    // 0:little_end, 1:big_end
14268 +
14269 +               #define default_param_dma_burst_size      4
14270 +
14271 +               #define default_param_speed               IFXUSB_PARAM_SPEED_HIGH
14272 +
14273 +               #define default_param_max_transfer_size   -1  //(Max, hwcfg)
14274 +               #define default_param_max_packet_count    -1  //(Max, hwcfg)
14275 +               #define default_param_phy_utmi_width      16
14276 +
14277 +               #define default_param_turn_around_time_hs 4
14278 +               #define default_param_turn_around_time_fs 4
14279 +               #define default_param_timeout_cal_hs      -1 //(NoChange)
14280 +               #define default_param_timeout_cal_fs      -1 //(NoChange)
14281 +
14282 +               #define default_param_data_fifo_size      -1 //(Max, hwcfg)
14283 +
14284 +               #ifdef __IS_HOST__
14285 +                       #define default_param_host_channels       -1 //(Max, hwcfg)
14286 +                       #define default_param_rx_fifo_size        640
14287 +                       #define default_param_nperio_tx_fifo_size 640
14288 +                       #define default_param_perio_tx_fifo_size  768
14289 +               #endif //__IS_HOST__
14290 +
14291 +               #ifdef __IS_DEVICE__
14292 +                       #ifdef __DED_INTR__
14293 +                               #define default_param_rx_fifo_size          1024
14294 +                               #define default_param_nperio_tx_fifo_size   1016
14295 +                               #define default_param_perio_tx_fifo_size_01 8
14296 +                       #else
14297 +                               #define default_param_rx_fifo_size          1024
14298 +                               #define default_param_nperio_tx_fifo_size   1024
14299 +                               #define default_param_perio_tx_fifo_size_01 0
14300 +                       #endif
14301 +                       #define default_param_perio_tx_fifo_size_02 0
14302 +                       #define default_param_perio_tx_fifo_size_03 0
14303 +                       #define default_param_perio_tx_fifo_size_04 0
14304 +                       #define default_param_perio_tx_fifo_size_05 0
14305 +                       #define default_param_perio_tx_fifo_size_06 0
14306 +                       #define default_param_perio_tx_fifo_size_07 0
14307 +                       #define default_param_perio_tx_fifo_size_08 0
14308 +                       #define default_param_perio_tx_fifo_size_09 0
14309 +                       #define default_param_perio_tx_fifo_size_10 0
14310 +                       #define default_param_perio_tx_fifo_size_11 0
14311 +                       #define default_param_perio_tx_fifo_size_12 0
14312 +                       #define default_param_perio_tx_fifo_size_13 0
14313 +                       #define default_param_perio_tx_fifo_size_14 0
14314 +                       #define default_param_perio_tx_fifo_size_15 0
14315 +               #endif //__IS_DEVICE__
14316 +
14317 +       #elif defined(__IS_AMAZON_SE__)
14318 +               //#include <asm/amazon_se/amazon_se.h>
14319 +               //#include <asm/amazon_se/irq.h>
14320 +
14321 +//             #define IFXUSB_IRQ          31
14322 +               #define IFXUSB_IOMEM_BASE   0x1e101000
14323 +               #define IFXUSB_FIFOMEM_BASE 0x1e120000
14324 +               #define IFXUSB_FIFODBG_BASE 0x1e140000
14325 +//             #define IFXUSB_OC_IRQ       20
14326 +
14327 +               #ifndef AMAZON_SE_RCU_BASE_ADDR
14328 +                       #define AMAZON_SE_RCU_BASE_ADDR            (0xBF203000)
14329 +               #endif
14330 +               #define AMAZON_SE_RCU_USBCFG  ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x18))
14331 +               #define AMAZON_SE_RCU_RESET   ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x10))
14332 +               #define AMAZON_SE_USBCFG_HDSEL_BIT    11        // 0:host, 1:device
14333 +               #define AMAZON_SE_USBCFG_HOST_END_BIT 10        // 0:little_end, 1:big_end
14334 +               #define AMAZON_SE_USBCFG_SLV_END_BIT  9         // 0:little_end, 1:big_end
14335 +
14336 +               #ifndef AMAZON_SE_GPIO_P0_OUT
14337 +                       #define AMAZON_SE_GPIO_P0_OUT                      (0xBF103000+0x10)
14338 +                       #define AMAZON_SE_GPIO_P0_DIR                      (0xBF103000+0x18)
14339 +                       #define AMAZON_SE_GPIO_P0_ALTSEL0                  (0xBF103000+0x1C)
14340 +                       #define AMAZON_SE_GPIO_P0_ALTSEL1                  (0xBF103000+0x20)
14341 +                       #define AMAZON_SE_GPIO_P0_OD                       (0xBF103000+0x24)
14342 +                       #define AMAZON_SE_GPIO_P0_PUDSEL                   (0xBF103000+0x2C)
14343 +                       #define AMAZON_SE_GPIO_P0_PUDEN                    (0xBF103000+0x30)
14344 +                       #define AMAZON_SE_GPIO_P1_OUT                      (0xBF103000+0x40)
14345 +                       #define AMAZON_SE_GPIO_P1_DIR                      (0xBF103000+0x48)
14346 +                       #define AMAZON_SE_GPIO_P1_ALTSEL0                  (0xBF103000+0x4C)
14347 +                       #define AMAZON_SE_GPIO_P1_ALTSEL1                  (0xBF103000+0x50)
14348 +                       #define AMAZON_SE_GPIO_P1_OD                       (0xBF103000+0x54)
14349 +                       #define AMAZON_SE_GPIO_P1_PUDSEL                   (0xBF103000+0x5C)
14350 +                       #define AMAZON_SE_GPIO_P1_PUDEN                    (0xBF103000+0x60)
14351 +               #endif
14352 +
14353 +               #ifndef AMAZON_SE_CGU
14354 +                       #define AMAZON_SE_CGU                      (0xBF103000)
14355 +               #endif
14356 +               #ifndef AMAZON_SE_CGU_IFCCR
14357 +                       #define AMAZON_SE_CGU_IFCCR                ((volatile unsigned long *)(AMAZON_SE_CGU+ 0x0018))
14358 +               #endif
14359 +               #ifndef AMAZON_SE_PMU
14360 +                       #define AMAZON_SE_PMU                      (KSEG1+0x1F102000)
14361 +               #endif
14362 +               #ifndef AMAZON_SE_PMU_PWDCR
14363 +                       #define AMAZON_SE_PMU_PWDCR                ((volatile unsigned long *)(AMAZON_SE_PMU+0x001C))
14364 +               #endif
14365 +
14366 +               #define default_param_dma_burst_size      4
14367 +
14368 +               #define default_param_speed               IFXUSB_PARAM_SPEED_HIGH
14369 +
14370 +               #define default_param_max_transfer_size   -1  //(Max, hwcfg)
14371 +               #define default_param_max_packet_count    -1  //(Max, hwcfg)
14372 +               #define default_param_phy_utmi_width      16
14373 +
14374 +               #define default_param_turn_around_time_hs 4 //(NoChange)
14375 +               #define default_param_turn_around_time_fs 4 //(NoChange)
14376 +               #define default_param_timeout_cal_hs      -1 //(NoChange)
14377 +               #define default_param_timeout_cal_fs      -1 //(NoChange)
14378 +
14379 +               #define default_param_data_fifo_size      -1 //(Max, hwcfg)
14380 +
14381 +               #ifdef __IS_HOST__
14382 +                       #define default_param_host_channels       -1 //(Max, hwcfg)
14383 +                       #define default_param_rx_fifo_size        240
14384 +                       #define default_param_nperio_tx_fifo_size 240
14385 +                       #define default_param_perio_tx_fifo_size  32
14386 +               #endif //__IS_HOST__
14387 +               #ifdef __IS_DEVICE__
14388 +                       #ifdef __DED_INTR__
14389 +                               #define default_param_rx_fifo_size          256
14390 +                               #define default_param_nperio_tx_fifo_size   248
14391 +                               #define default_param_perio_tx_fifo_size_01 8
14392 +                       #else
14393 +                               #define default_param_rx_fifo_size          256
14394 +                               #define default_param_nperio_tx_fifo_size   256
14395 +                               #define default_param_perio_tx_fifo_size_01 0
14396 +                       #endif
14397 +                       #define default_param_perio_tx_fifo_size_02 0
14398 +                       #define default_param_perio_tx_fifo_size_03 0
14399 +                       #define default_param_perio_tx_fifo_size_04 0
14400 +                       #define default_param_perio_tx_fifo_size_05 0
14401 +                       #define default_param_perio_tx_fifo_size_06 0
14402 +                       #define default_param_perio_tx_fifo_size_07 0
14403 +                       #define default_param_perio_tx_fifo_size_08 0
14404 +                       #define default_param_perio_tx_fifo_size_09 0
14405 +                       #define default_param_perio_tx_fifo_size_10 0
14406 +                       #define default_param_perio_tx_fifo_size_11 0
14407 +                       #define default_param_perio_tx_fifo_size_12 0
14408 +                       #define default_param_perio_tx_fifo_size_13 0
14409 +                       #define default_param_perio_tx_fifo_size_14 0
14410 +                       #define default_param_perio_tx_fifo_size_15 0
14411 +               #endif //__IS_DEVICE__
14412 +
14413 +       #elif defined(__IS_AR9__)
14414 +//             #define IFXUSB1_IRQ 54
14415 +               #define IFXUSB1_IOMEM_BASE   0x1E101000
14416 +               #define IFXUSB1_FIFOMEM_BASE 0x1E120000
14417 +               #define IFXUSB1_FIFODBG_BASE 0x1E140000
14418 +
14419 +//             #define IFXUSB2_IRQ 83
14420 +               #define IFXUSB2_IOMEM_BASE   0x1E106000
14421 +               #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000
14422 +               #define IFXUSB2_FIFODBG_BASE 0x1E1C0000
14423 +
14424 +//             #define IFXUSB_OC_IRQ 60
14425 +
14426 +               #ifndef AR9_RCU_BASE_ADDR
14427 +                       #define AR9_RCU_BASE_ADDR                (0xBF203000)
14428 +               #endif
14429 +
14430 +               #ifndef AR9_CGU
14431 +                       #define AR9_CGU                          (0xBF103000)
14432 +               #endif
14433 +               #ifndef AR9_CGU_IFCCR
14434 +                       #define AR9_CGU_IFCCR                        ((volatile unsigned long *)(AR9_CGU+ 0x0018))
14435 +               #endif
14436 +
14437 +               #ifndef AR9_PMU
14438 +                       #define AR9_PMU                              (KSEG1+0x1F102000)
14439 +               #endif
14440 +               #ifndef AR9_PMU_PWDCR
14441 +                       #define AR9_PMU_PWDCR                        ((volatile unsigned long *)(AR9_PMU+0x001C))
14442 +               #endif
14443 +
14444 +               #ifndef AR9_GPIO_P0_OUT
14445 +                       #define AR9_GPIO_P0_OUT                      (0xBF103000+0x10)
14446 +                       #define AR9_GPIO_P0_DIR                      (0xBF103000+0x18)
14447 +                       #define AR9_GPIO_P0_ALTSEL0                  (0xBF103000+0x1C)
14448 +                       #define AR9_GPIO_P0_ALTSEL1                  (0xBF103000+0x20)
14449 +                       #define AR9_GPIO_P0_OD                       (0xBF103000+0x24)
14450 +                       #define AR9_GPIO_P0_PUDSEL                   (0xBF103000+0x2C)
14451 +                       #define AR9_GPIO_P0_PUDEN                    (0xBF103000+0x30)
14452 +                       #define AR9_GPIO_P1_OUT                      (0xBF103000+0x40)
14453 +                       #define AR9_GPIO_P1_DIR                      (0xBF103000+0x48)
14454 +                       #define AR9_GPIO_P1_ALTSEL0                  (0xBF103000+0x4C)
14455 +                       #define AR9_GPIO_P1_ALTSEL1                  (0xBF103000+0x50)
14456 +                       #define AR9_GPIO_P1_OD                       (0xBF103000+0x54)
14457 +                       #define AR9_GPIO_P1_PUDSEL                   (0xBF103000+0x5C)
14458 +                       #define AR9_GPIO_P1_PUDEN                    (0xBF103000+0x60)
14459 +               #endif
14460 +
14461 +               #define AR9_RCU_USB1CFG  ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x18))
14462 +               #define AR9_RCU_USB2CFG  ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x34))
14463 +               #define AR9_RCU_USBRESET ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x10))
14464 +               #define AR9_USBCFG_ARB          7       //
14465 +               #define AR9_USBCFG_HDSEL_BIT    11      // 0:host, 1:device
14466 +               #define AR9_USBCFG_HOST_END_BIT 10      // 0:little_end, 1:big_end
14467 +               #define AR9_USBCFG_SLV_END_BIT  17      // 0:little_end, 1:big_end
14468 +
14469 +               #define default_param_dma_burst_size      4
14470 +
14471 +               #define default_param_speed               IFXUSB_PARAM_SPEED_HIGH
14472 +
14473 +               #define default_param_max_transfer_size   -1  //(Max, hwcfg)
14474 +               #define default_param_max_packet_count    -1  //(Max, hwcfg)
14475 +               #define default_param_phy_utmi_width      16
14476 +
14477 +               #define default_param_turn_around_time_hs 4 //(NoChange)
14478 +               #define default_param_turn_around_time_fs 4 //(NoChange)
14479 +               #define default_param_timeout_cal_hs      -1 //(NoChange)
14480 +               #define default_param_timeout_cal_fs      -1 //(NoChange)
14481 +
14482 +               #define default_param_data_fifo_size      -1 //(Max, hwcfg)
14483 +
14484 +               #ifdef __IS_HOST__
14485 +                       #define default_param_host_channels       -1 //(Max, hwcfg)
14486 +                       #define default_param_rx_fifo_size        240
14487 +                       #define default_param_nperio_tx_fifo_size 240
14488 +                       #define default_param_perio_tx_fifo_size  32
14489 +               #endif //__IS_HOST__
14490 +               #ifdef __IS_DEVICE__
14491 +                       #ifdef __DED_INTR__
14492 +                               #define default_param_rx_fifo_size          256
14493 +//                             #define default_param_nperio_tx_fifo_size   248
14494 +//                             #define default_param_perio_tx_fifo_size_01 8
14495 +                               #define default_param_nperio_tx_fifo_size   252
14496 +                               #define default_param_perio_tx_fifo_size_01 4
14497 +                       #else
14498 +                               #define default_param_rx_fifo_size          256
14499 +                               #define default_param_nperio_tx_fifo_size   256
14500 +                               #define default_param_perio_tx_fifo_size_01 0
14501 +                       #endif
14502 +                       #define default_param_perio_tx_fifo_size_02 0
14503 +                       #define default_param_perio_tx_fifo_size_03 0
14504 +                       #define default_param_perio_tx_fifo_size_04 0
14505 +                       #define default_param_perio_tx_fifo_size_05 0
14506 +                       #define default_param_perio_tx_fifo_size_06 0
14507 +                       #define default_param_perio_tx_fifo_size_07 0
14508 +                       #define default_param_perio_tx_fifo_size_08 0
14509 +                       #define default_param_perio_tx_fifo_size_09 0
14510 +                       #define default_param_perio_tx_fifo_size_10 0
14511 +                       #define default_param_perio_tx_fifo_size_11 0
14512 +                       #define default_param_perio_tx_fifo_size_12 0
14513 +                       #define default_param_perio_tx_fifo_size_13 0
14514 +                       #define default_param_perio_tx_fifo_size_14 0
14515 +                       #define default_param_perio_tx_fifo_size_15 0
14516 +               #endif //__IS_DEVICE__
14517 +
14518 +       #elif defined(__IS_VR9__)
14519 +//             #define IFXUSB1_IRQ 54
14520 +               #define IFXUSB1_IOMEM_BASE   0x1E101000
14521 +               #define IFXUSB1_FIFOMEM_BASE 0x1E120000
14522 +               #define IFXUSB1_FIFODBG_BASE 0x1E140000
14523 +
14524 +//             #define IFXUSB2_IRQ 83
14525 +               #define IFXUSB2_IOMEM_BASE   0x1E106000
14526 +               #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000
14527 +               #define IFXUSB2_FIFODBG_BASE 0x1E1C0000
14528 +//             #define IFXUSB_OC_IRQ 60
14529 +
14530 +               #ifndef VR9_RCU_BASE_ADDR
14531 +                       #define VR9_RCU_BASE_ADDR            (0xBF203000)
14532 +               #endif
14533 +
14534 +               #ifndef VR9_CGU
14535 +                       #define VR9_CGU                          (0xBF103000)
14536 +               #endif
14537 +               #ifndef VR9_CGU_IFCCR
14538 +                       #define VR9_CGU_IFCCR                        ((volatile unsigned long *)(VR9_CGU+ 0x0018))
14539 +               #endif
14540 +
14541 +               #ifndef VR9_PMU
14542 +                       #define VR9_PMU                              (KSEG1+0x1F102000)
14543 +               #endif
14544 +               #ifndef VR9_PMU_PWDCR
14545 +                       #define VR9_PMU_PWDCR                        ((volatile unsigned long *)(VR9_PMU+0x001C))
14546 +               #endif
14547 +
14548 +               #ifndef VR9_GPIO_P0_OUT
14549 +                       #define VR9_GPIO_P0_OUT                      (0xBF103000+0x10)
14550 +                       #define VR9_GPIO_P0_DIR                      (0xBF103000+0x18)
14551 +                       #define VR9_GPIO_P0_ALTSEL0                  (0xBF103000+0x1C)
14552 +                       #define VR9_GPIO_P0_ALTSEL1                  (0xBF103000+0x20)
14553 +                       #define VR9_GPIO_P0_OD                       (0xBF103000+0x24)
14554 +                       #define VR9_GPIO_P0_PUDSEL                   (0xBF103000+0x2C)
14555 +                       #define VR9_GPIO_P0_PUDEN                    (0xBF103000+0x30)
14556 +                       #define VR9_GPIO_P1_OUT                      (0xBF103000+0x40)
14557 +                       #define VR9_GPIO_P1_DIR                      (0xBF103000+0x48)
14558 +                       #define VR9_GPIO_P1_ALTSEL0                  (0xBF103000+0x4C)
14559 +                       #define VR9_GPIO_P1_ALTSEL1                  (0xBF103000+0x50)
14560 +                       #define VR9_GPIO_P1_OD                       (0xBF103000+0x54)
14561 +                       #define VR9_GPIO_P1_PUDSEL                   (0xBF103000+0x5C)
14562 +                       #define VR9_GPIO_P1_PUDEN                    (0xBF103000+0x60)
14563 +               #endif
14564 +
14565 +               #define VR9_RCU_USB1CFG   ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x18))
14566 +               #define VR9_RCU_USB2CFG   ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x34))
14567 +               #define VR9_RCU_USB_ANA_CFG1A  ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x38))
14568 +               #define VR9_RCU_USB_ANA_CFG1B  ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x3C))
14569 +               #define VR9_RCU_USBRESET  ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x10))
14570 +               #define VR9_RCU_USBRESET2 ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x48))
14571 +               #define VR9_USBCFG_ARB          7       //
14572 +               #define VR9_USBCFG_HDSEL_BIT    11      // 0:host, 1:device
14573 +               #define VR9_USBCFG_HOST_END_BIT 10      // 0:little_end, 1:big_end
14574 +               #define VR9_USBCFG_SLV_END_BIT  9       // 0:little_end, 1:big_end
14575 +
14576 +               /*== AVM/BC 20101220 Workaround VR9 DMA burst size ==
14577 +                * Using 2 Devices in diferent ports cause a general USB Host Error.
14578 +                * Workaround found in UGW4.3
14579 +                */
14580 +//             #define default_param_dma_burst_size 4      //(ALL)
14581 +               //WA for AHB
14582 +               #define default_param_dma_burst_size 0      //(ALL)
14583 +
14584 +               #define default_param_speed               IFXUSB_PARAM_SPEED_HIGH
14585 +
14586 +               #define default_param_max_transfer_size -1  //(Max, hwcfg)
14587 +               #define default_param_max_packet_count  -1  //(Max, hwcfg)
14588 +               #define default_param_phy_utmi_width    16
14589 +
14590 +               #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a
14591 +               #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a
14592 +               #define default_param_timeout_cal_hs      -1 //(NoChange)
14593 +               #define default_param_timeout_cal_fs      -1 //(NoChange)
14594 +
14595 +               #define default_param_data_fifo_size      -1 //(Max, hwcfg)
14596 +
14597 +               #ifdef __IS_HOST__
14598 +                       #define default_param_host_channels       -1 //(Max, hwcfg)
14599 +                       #define default_param_rx_fifo_size        240
14600 +                       #define default_param_nperio_tx_fifo_size 240
14601 +                       #define default_param_perio_tx_fifo_size  32
14602 +               #endif //__IS_HOST__
14603 +               #ifdef __IS_DEVICE__
14604 +#if 0
14605 +                       #define default_param_rx_fifo_size    256
14606 +                       #define default_param_tx_fifo_size_00 -1
14607 +                       #define default_param_tx_fifo_size_01 -1
14608 +                       #define default_param_tx_fifo_size_02 -1
14609 +#else
14610 +                       #define default_param_rx_fifo_size    256
14611 +                       #define default_param_tx_fifo_size_00 32
14612 +                       #define default_param_tx_fifo_size_01 200
14613 +                       #define default_param_tx_fifo_size_02 8
14614 +#endif
14615 +                       #define default_param_tx_fifo_size_03 -1
14616 +                       #define default_param_tx_fifo_size_04 -1
14617 +                       #define default_param_tx_fifo_size_05 -1
14618 +                       #define default_param_tx_fifo_size_06 -1
14619 +                       #define default_param_tx_fifo_size_07 -1
14620 +                       #define default_param_tx_fifo_size_08 -1
14621 +                       #define default_param_tx_fifo_size_09 -1
14622 +                       #define default_param_tx_fifo_size_10 -1
14623 +                       #define default_param_tx_fifo_size_11 -1
14624 +                       #define default_param_tx_fifo_size_12 -1
14625 +                       #define default_param_tx_fifo_size_13 -1
14626 +                       #define default_param_tx_fifo_size_14 -1
14627 +                       #define default_param_tx_fifo_size_15 -1
14628 +                       #define default_param_dma_unalgned_tx -1
14629 +                       #define default_param_dma_unalgned_rx -1
14630 +                       #define default_param_thr_ctl         -1
14631 +                       #define default_param_tx_thr_length   -1
14632 +                       #define default_param_rx_thr_length   -1
14633 +               #endif //__IS_DEVICE__
14634 +       #else // __IS_VR9__
14635 +               #error "Please choose one platform!!"
14636 +       #endif // __IS_VR9__
14637 +
14638 +#else //UEIP
14639 +       #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
14640 +//             #define IFXUSB_IRQ          54
14641 +               #define IFXUSB_IOMEM_BASE   0x1e101000
14642 +               #define IFXUSB_FIFOMEM_BASE 0x1e120000
14643 +               #define IFXUSB_FIFODBG_BASE 0x1e140000
14644 +//             #define IFXUSB_OC_IRQ       151
14645 +
14646 +
14647 +               #ifndef DANUBE_RCU_BASE_ADDR
14648 +                       #define DANUBE_RCU_BASE_ADDR            (0xBF203000)
14649 +               #endif
14650 +
14651 +               #ifndef DANUBE_CGU
14652 +                       #define DANUBE_CGU                      (0xBF103000)
14653 +               #endif
14654 +               #ifndef DANUBE_CGU_IFCCR
14655 +                       #define DANUBE_CGU_IFCCR                ((volatile unsigned long *)(DANUBE_CGU+ 0x0018))
14656 +               #endif
14657 +               #ifndef DANUBE_PMU
14658 +                       #define DANUBE_PMU                      (KSEG1+0x1F102000)
14659 +               #endif
14660 +               #ifndef DANUBE_PMU_PWDCR
14661 +                       #define DANUBE_PMU_PWDCR                ((volatile unsigned long *)(DANUBE_PMU+0x001C))
14662 +               #endif
14663 +
14664 +               #ifndef DANUBE_GPIO_P0_OUT
14665 +                       #define DANUBE_GPIO_P0_OUT                      (0xBF103000+0x10)
14666 +                       #define DANUBE_GPIO_P0_DIR                      (0xBF103000+0x18)
14667 +                       #define DANUBE_GPIO_P0_ALTSEL0                  (0xBF103000+0x1C)
14668 +                       #define DANUBE_GPIO_P0_ALTSEL1                  (0xBF103000+0x20)
14669 +                       #define DANUBE_GPIO_P0_OD                       (0xBF103000+0x24)
14670 +                       #define DANUBE_GPIO_P0_PUDSEL                   (0xBF103000+0x2C)
14671 +                       #define DANUBE_GPIO_P0_PUDEN                    (0xBF103000+0x30)
14672 +                       #define DANUBE_GPIO_P1_OUT                      (0xBF103000+0x40)
14673 +                       #define DANUBE_GPIO_P1_DIR                      (0xBF103000+0x48)
14674 +                       #define DANUBE_GPIO_P1_ALTSEL0                  (0xBF103000+0x4C)
14675 +                       #define DANUBE_GPIO_P1_ALTSEL1                  (0xBF103000+0x50)
14676 +                       #define DANUBE_GPIO_P1_OD                       (0xBF103000+0x54)
14677 +                       #define DANUBE_GPIO_P1_PUDSEL                   (0xBF103000+0x5C)
14678 +                       #define DANUBE_GPIO_P1_PUDEN                    (0xBF103000+0x60)
14679 +               #endif
14680 +
14681 +
14682 +               #define DANUBE_RCU_USBCFG  ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x18))
14683 +               #define DANUBE_RCU_RESET   ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x10))
14684 +               #define DANUBE_USBCFG_HDSEL_BIT    11   // 0:host, 1:device
14685 +               #define DANUBE_USBCFG_HOST_END_BIT 10   // 0:little_end, 1:big_end
14686 +               #define DANUBE_USBCFG_SLV_END_BIT  9    // 0:little_end, 1:big_end
14687 +
14688 +               #define default_param_dma_burst_size      4
14689 +
14690 +               #define default_param_speed               IFXUSB_PARAM_SPEED_HIGH
14691 +
14692 +               #define default_param_max_transfer_size   -1  //(Max, hwcfg)
14693 +               #define default_param_max_packet_count    -1  //(Max, hwcfg)
14694 +               #define default_param_phy_utmi_width      16
14695 +
14696 +               #define default_param_turn_around_time_hs 4 //(NoChange)
14697 +               #define default_param_turn_around_time_fs 4 //(NoChange)
14698 +               #define default_param_timeout_cal_hs      -1 //(NoChange)
14699 +               #define default_param_timeout_cal_fs      -1 //(NoChange)
14700 +
14701 +               #define default_param_data_fifo_size      -1 //(Max, hwcfg)
14702 +               #ifdef __IS_HOST__
14703 +                       #define default_param_host_channels       -1 //(Max, hwcfg)
14704 +                       #define default_param_rx_fifo_size        640
14705 +                       #define default_param_nperio_tx_fifo_size 640
14706 +                       #define default_param_perio_tx_fifo_size  768
14707 +               #endif //__IS_HOST__
14708 +
14709 +               #ifdef __IS_DEVICE__
14710 +                       #ifdef __DED_INTR__
14711 +                               #define default_param_rx_fifo_size          1024
14712 +                               #define default_param_nperio_tx_fifo_size   1016
14713 +                               #define default_param_perio_tx_fifo_size_01 8
14714 +                       #else
14715 +                               #define default_param_rx_fifo_size          1024
14716 +                               #define default_param_nperio_tx_fifo_size   1024
14717 +                               #define default_param_perio_tx_fifo_size_01 0
14718 +                       #endif
14719 +                       #define default_param_perio_tx_fifo_size_02 0
14720 +                       #define default_param_perio_tx_fifo_size_03 0
14721 +                       #define default_param_perio_tx_fifo_size_04 0
14722 +                       #define default_param_perio_tx_fifo_size_05 0
14723 +                       #define default_param_perio_tx_fifo_size_06 0
14724 +                       #define default_param_perio_tx_fifo_size_07 0
14725 +                       #define default_param_perio_tx_fifo_size_08 0
14726 +                       #define default_param_perio_tx_fifo_size_09 0
14727 +                       #define default_param_perio_tx_fifo_size_10 0
14728 +                       #define default_param_perio_tx_fifo_size_11 0
14729 +                       #define default_param_perio_tx_fifo_size_12 0
14730 +                       #define default_param_perio_tx_fifo_size_13 0
14731 +                       #define default_param_perio_tx_fifo_size_14 0
14732 +                       #define default_param_perio_tx_fifo_size_15 0
14733 +               #endif //__IS_DEVICE__
14734 +
14735 +       #elif defined(__IS_AMAZON_SE__)
14736 +               #include <asm/amazon_se/amazon_se.h>
14737 +               //#include <asm/amazon_se/irq.h>
14738 +
14739 +//             #define IFXUSB_IRQ          31
14740 +               #define IFXUSB_IOMEM_BASE   0x1e101000
14741 +               #define IFXUSB_FIFOMEM_BASE 0x1e120000
14742 +               #define IFXUSB_FIFODBG_BASE 0x1e140000
14743 +//             #define IFXUSB_OC_IRQ       20
14744 +
14745 +               #define AMAZON_SE_RCU_USBCFG  ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x18))
14746 +               #define AMAZON_SE_RCU_RESET   ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x10))
14747 +               #define AMAZON_SE_USBCFG_HDSEL_BIT    11        // 0:host, 1:device
14748 +               #define AMAZON_SE_USBCFG_HOST_END_BIT 10        // 0:little_end, 1:big_end
14749 +               #define AMAZON_SE_USBCFG_SLV_END_BIT  9         // 0:little_end, 1:big_end
14750 +
14751 +               #ifndef AMAZON_SE_GPIO_P0_OUT
14752 +                       #define AMAZON_SE_GPIO_P0_OUT                      (0xBF103000+0x10)
14753 +                       #define AMAZON_SE_GPIO_P0_DIR                      (0xBF103000+0x18)
14754 +                       #define AMAZON_SE_GPIO_P0_ALTSEL0                  (0xBF103000+0x1C)
14755 +                       #define AMAZON_SE_GPIO_P0_ALTSEL1                  (0xBF103000+0x20)
14756 +                       #define AMAZON_SE_GPIO_P0_OD                       (0xBF103000+0x24)
14757 +                       #define AMAZON_SE_GPIO_P0_PUDSEL                   (0xBF103000+0x2C)
14758 +                       #define AMAZON_SE_GPIO_P0_PUDEN                    (0xBF103000+0x30)
14759 +                       #define AMAZON_SE_GPIO_P1_OUT                      (0xBF103000+0x40)
14760 +                       #define AMAZON_SE_GPIO_P1_DIR                      (0xBF103000+0x48)
14761 +                       #define AMAZON_SE_GPIO_P1_ALTSEL0                  (0xBF103000+0x4C)
14762 +                       #define AMAZON_SE_GPIO_P1_ALTSEL1                  (0xBF103000+0x50)
14763 +                       #define AMAZON_SE_GPIO_P1_OD                       (0xBF103000+0x54)
14764 +                       #define AMAZON_SE_GPIO_P1_PUDSEL                   (0xBF103000+0x5C)
14765 +                       #define AMAZON_SE_GPIO_P1_PUDEN                    (0xBF103000+0x60)
14766 +               #endif
14767 +
14768 +
14769 +               #ifndef AMAZON_SE_CGU
14770 +                       #define AMAZON_SE_CGU                      (0xBF103000)
14771 +               #endif
14772 +               #ifndef AMAZON_SE_CGU_IFCCR
14773 +                       #define AMAZON_SE_CGU_IFCCR                ((volatile unsigned long *)(AMAZON_SE_CGU+ 0x0018))
14774 +               #endif
14775 +               #ifndef AMAZON_SE_PMU
14776 +                       #define AMAZON_SE_PMU                      (KSEG1+0x1F102000)
14777 +               #endif
14778 +               #ifndef AMAZON_SE_PMU_PWDCR
14779 +                       #define AMAZON_SE_PMU_PWDCR                ((volatile unsigned long *)(AMAZON_SE_PMU+0x001C))
14780 +               #endif
14781 +
14782 +               #define default_param_dma_burst_size      4
14783 +
14784 +               #define default_param_speed               IFXUSB_PARAM_SPEED_HIGH
14785 +
14786 +               #define default_param_max_transfer_size   -1  //(Max, hwcfg)
14787 +               #define default_param_max_packet_count    -1  //(Max, hwcfg)
14788 +               #define default_param_phy_utmi_width      16
14789 +
14790 +               #define default_param_turn_around_time_hs 4 //(NoChange)
14791 +               #define default_param_turn_around_time_fs 4 //(NoChange)
14792 +               #define default_param_timeout_cal_hs      -1 //(NoChange)
14793 +               #define default_param_timeout_cal_fs      -1 //(NoChange)
14794 +
14795 +               #define default_param_data_fifo_size      -1 //(Max, hwcfg)
14796 +
14797 +               #ifdef __IS_HOST__
14798 +                       #define default_param_host_channels       -1 //(Max, hwcfg)
14799 +                       #define default_param_rx_fifo_size        240
14800 +                       #define default_param_nperio_tx_fifo_size 240
14801 +                       #define default_param_perio_tx_fifo_size  32
14802 +               #endif //__IS_HOST__
14803 +               #ifdef __IS_DEVICE__
14804 +                       #ifdef __DED_INTR__
14805 +                               #define default_param_rx_fifo_size          256
14806 +                               #define default_param_nperio_tx_fifo_size   248
14807 +                               #define default_param_perio_tx_fifo_size_01 8
14808 +                       #else
14809 +                               #define default_param_rx_fifo_size          256
14810 +                               #define default_param_nperio_tx_fifo_size   256
14811 +                               #define default_param_perio_tx_fifo_size_01 0
14812 +                       #endif
14813 +                       #define default_param_perio_tx_fifo_size_02 0
14814 +                       #define default_param_perio_tx_fifo_size_03 0
14815 +                       #define default_param_perio_tx_fifo_size_04 0
14816 +                       #define default_param_perio_tx_fifo_size_05 0
14817 +                       #define default_param_perio_tx_fifo_size_06 0
14818 +                       #define default_param_perio_tx_fifo_size_07 0
14819 +                       #define default_param_perio_tx_fifo_size_08 0
14820 +                       #define default_param_perio_tx_fifo_size_09 0
14821 +                       #define default_param_perio_tx_fifo_size_10 0
14822 +                       #define default_param_perio_tx_fifo_size_11 0
14823 +                       #define default_param_perio_tx_fifo_size_12 0
14824 +                       #define default_param_perio_tx_fifo_size_13 0
14825 +                       #define default_param_perio_tx_fifo_size_14 0
14826 +                       #define default_param_perio_tx_fifo_size_15 0
14827 +               #endif //__IS_DEVICE__
14828 +
14829 +       #elif defined(__IS_AR9__)
14830 +//             #define IFXUSB1_IRQ 54
14831 +               #define IFXUSB1_IOMEM_BASE   0x1E101000
14832 +               #define IFXUSB1_FIFOMEM_BASE 0x1E120000
14833 +               #define IFXUSB1_FIFODBG_BASE 0x1E140000
14834 +
14835 +//             #define IFXUSB2_IRQ 83
14836 +               #define IFXUSB2_IOMEM_BASE   0x1E106000
14837 +               #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000
14838 +               #define IFXUSB2_FIFODBG_BASE 0x1E1C0000
14839 +
14840 +//             #define IFXUSB_OC_IRQ 60
14841 +
14842 +               #ifndef AMAZON_S_RCU_BASE_ADDR
14843 +                       #define AMAZON_S_RCU_BASE_ADDR                (0xBF203000)
14844 +               #endif
14845 +
14846 +               #ifndef AMAZON_S_CGU
14847 +                       #define AMAZON_S_CGU                          (0xBF103000)
14848 +               #endif
14849 +               #ifndef AMAZON_S_CGU_IFCCR
14850 +                       #define AMAZON_S_CGU_IFCCR                        ((volatile unsigned long *)(AMAZON_S_CGU+ 0x0018))
14851 +               #endif
14852 +
14853 +               #ifndef AMAZON_S_PMU
14854 +                       #define AMAZON_S_PMU                              (KSEG1+0x1F102000)
14855 +               #endif
14856 +               #ifndef AMAZON_S_PMU_PWDCR
14857 +                       #define AMAZON_S_PMU_PWDCR                        ((volatile unsigned long *)(AMAZON_S_PMU+0x001C))
14858 +               #endif
14859 +
14860 +               #ifndef AMAZON_S_GPIO_P0_OUT
14861 +                       #define AMAZON_S_GPIO_P0_OUT                      (0xBF103000+0x10)
14862 +                       #define AMAZON_S_GPIO_P0_DIR                      (0xBF103000+0x18)
14863 +                       #define AMAZON_S_GPIO_P0_ALTSEL0                  (0xBF103000+0x1C)
14864 +                       #define AMAZON_S_GPIO_P0_ALTSEL1                  (0xBF103000+0x20)
14865 +                       #define AMAZON_S_GPIO_P0_OD                       (0xBF103000+0x24)
14866 +                       #define AMAZON_S_GPIO_P0_PUDSEL                   (0xBF103000+0x2C)
14867 +                       #define AMAZON_S_GPIO_P0_PUDEN                    (0xBF103000+0x30)
14868 +                       #define AMAZON_S_GPIO_P1_OUT                      (0xBF103000+0x40)
14869 +                       #define AMAZON_S_GPIO_P1_DIR                      (0xBF103000+0x48)
14870 +                       #define AMAZON_S_GPIO_P1_ALTSEL0                  (0xBF103000+0x4C)
14871 +                       #define AMAZON_S_GPIO_P1_ALTSEL1                  (0xBF103000+0x50)
14872 +                       #define AMAZON_S_GPIO_P1_OD                       (0xBF103000+0x54)
14873 +                       #define AMAZON_S_GPIO_P1_PUDSEL                   (0xBF103000+0x5C)
14874 +                       #define AMAZON_S_GPIO_P1_PUDEN                    (0xBF103000+0x60)
14875 +               #endif
14876 +
14877 +               #define AMAZON_S_RCU_USB1CFG  ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x18))
14878 +               #define AMAZON_S_RCU_USB2CFG  ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x34))
14879 +               #define AMAZON_S_RCU_USBRESET ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x10))
14880 +               #define AMAZON_S_USBCFG_ARB          7  //
14881 +               #define AMAZON_S_USBCFG_HDSEL_BIT    11 // 0:host, 1:device
14882 +               #define AMAZON_S_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end
14883 +               #define AMAZON_S_USBCFG_SLV_END_BIT  17 // 0:little_end, 1:big_end
14884 +
14885 +               #define default_param_dma_burst_size      4
14886 +
14887 +               #define default_param_speed               IFXUSB_PARAM_SPEED_HIGH
14888 +
14889 +               #define default_param_max_transfer_size   -1  //(Max, hwcfg)
14890 +               #define default_param_max_packet_count    -1  //(Max, hwcfg)
14891 +               #define default_param_phy_utmi_width      16
14892 +
14893 +               #define default_param_turn_around_time_hs 4 //(NoChange)
14894 +               #define default_param_turn_around_time_fs 4 //(NoChange)
14895 +               #define default_param_timeout_cal_hs      -1 //(NoChange)
14896 +               #define default_param_timeout_cal_fs      -1 //(NoChange)
14897 +
14898 +               #define default_param_data_fifo_size      -1 //(Max, hwcfg)
14899 +
14900 +               #ifdef __IS_HOST__
14901 +                       #define default_param_host_channels       -1 //(Max, hwcfg)
14902 +                       #define default_param_rx_fifo_size        240
14903 +                       #define default_param_nperio_tx_fifo_size 240
14904 +                       #define default_param_perio_tx_fifo_size  32
14905 +               #endif //__IS_HOST__
14906 +               #ifdef __IS_DEVICE__
14907 +                       #ifdef __DED_INTR__
14908 +                               #define default_param_rx_fifo_size          256
14909 +                               #define default_param_nperio_tx_fifo_size   248
14910 +                               #define default_param_perio_tx_fifo_size_01 8
14911 +                       #else
14912 +                               #define default_param_rx_fifo_size          256
14913 +                               #define default_param_nperio_tx_fifo_size   256
14914 +                               #define default_param_perio_tx_fifo_size_01 0
14915 +                       #endif
14916 +                       #define default_param_perio_tx_fifo_size_02 0
14917 +                       #define default_param_perio_tx_fifo_size_03 0
14918 +                       #define default_param_perio_tx_fifo_size_04 0
14919 +                       #define default_param_perio_tx_fifo_size_05 0
14920 +                       #define default_param_perio_tx_fifo_size_06 0
14921 +                       #define default_param_perio_tx_fifo_size_07 0
14922 +                       #define default_param_perio_tx_fifo_size_08 0
14923 +                       #define default_param_perio_tx_fifo_size_09 0
14924 +                       #define default_param_perio_tx_fifo_size_10 0
14925 +                       #define default_param_perio_tx_fifo_size_11 0
14926 +                       #define default_param_perio_tx_fifo_size_12 0
14927 +                       #define default_param_perio_tx_fifo_size_13 0
14928 +                       #define default_param_perio_tx_fifo_size_14 0
14929 +                       #define default_param_perio_tx_fifo_size_15 0
14930 +               #endif //__IS_DEVICE__
14931 +
14932 +       #elif defined(__IS_VR9__)
14933 +//             #define IFXUSB1_IRQ 54
14934 +               #define IFXUSB1_IOMEM_BASE   0x1E101000
14935 +               #define IFXUSB1_FIFOMEM_BASE 0x1E120000
14936 +               #define IFXUSB1_FIFODBG_BASE 0x1E140000
14937 +
14938 +//             #define IFXUSB2_IRQ 83
14939 +               #define IFXUSB2_IOMEM_BASE   0x1E106000
14940 +               #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000
14941 +               #define IFXUSB2_FIFODBG_BASE 0x1E1C0000
14942 +//             #define IFXUSB_OC_IRQ 60
14943 +
14944 +               #ifndef AMAZON_S_RCU_BASE_ADDR
14945 +                       #define AMAZON_S_RCU_BASE_ADDR            (0xBF203000)
14946 +               #endif
14947 +
14948 +               #ifndef AMAZON_S_CGU
14949 +                       #define AMAZON_S_CGU                          (0xBF103000)
14950 +               #endif
14951 +               #ifndef AMAZON_S_CGU_IFCCR
14952 +                       #define AMAZON_S_CGU_IFCCR                        ((volatile unsigned long *)(AMAZON_S_CGU+ 0x0018))
14953 +               #endif
14954 +
14955 +               #ifndef AMAZON_S_PMU
14956 +                       #define AMAZON_S_PMU                              (KSEG1+0x1F102000)
14957 +               #endif
14958 +               #ifndef AMAZON_S_PMU_PWDCR
14959 +                       #define AMAZON_S_PMU_PWDCR                        ((volatile unsigned long *)(AMAZON_S_PMU+0x001C))
14960 +               #endif
14961 +
14962 +               #ifndef AMAZON_S_GPIO_P0_OUT
14963 +                       #define AMAZON_S_GPIO_P0_OUT                      (0xBF103000+0x10)
14964 +                       #define AMAZON_S_GPIO_P0_DIR                      (0xBF103000+0x18)
14965 +                       #define AMAZON_S_GPIO_P0_ALTSEL0                  (0xBF103000+0x1C)
14966 +                       #define AMAZON_S_GPIO_P0_ALTSEL1                  (0xBF103000+0x20)
14967 +                       #define AMAZON_S_GPIO_P0_OD                       (0xBF103000+0x24)
14968 +                       #define AMAZON_S_GPIO_P0_PUDSEL                   (0xBF103000+0x2C)
14969 +                       #define AMAZON_S_GPIO_P0_PUDEN                    (0xBF103000+0x30)
14970 +                       #define AMAZON_S_GPIO_P1_OUT                      (0xBF103000+0x40)
14971 +                       #define AMAZON_S_GPIO_P1_DIR                      (0xBF103000+0x48)
14972 +                       #define AMAZON_S_GPIO_P1_ALTSEL0                  (0xBF103000+0x4C)
14973 +                       #define AMAZON_S_GPIO_P1_ALTSEL1                  (0xBF103000+0x50)
14974 +                       #define AMAZON_S_GPIO_P1_OD                       (0xBF103000+0x54)
14975 +                       #define AMAZON_S_GPIO_P1_PUDSEL                   (0xBF103000+0x5C)
14976 +                       #define AMAZON_S_GPIO_P1_PUDEN                    (0xBF103000+0x60)
14977 +               #endif
14978 +
14979 +               #define AMAZON_S_RCU_USB1CFG  ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x18))
14980 +               #define AMAZON_S_RCU_USB2CFG  ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x34))
14981 +               #define AMAZON_S_RCU_USBRESET ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x10))
14982 +               #define AMAZON_S_USBCFG_ARB          7  //
14983 +               #define AMAZON_S_USBCFG_HDSEL_BIT    11 // 0:host, 1:device
14984 +               #define AMAZON_S_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end
14985 +               #define AMAZON_S_USBCFG_SLV_END_BIT  17 // 0:little_end, 1:big_end
14986 +
14987 +               #define default_param_dma_burst_size 4      //(ALL)
14988 +
14989 +               #define default_param_speed               IFXUSB_PARAM_SPEED_HIGH
14990 +
14991 +               #define default_param_max_transfer_size -1  //(Max, hwcfg)
14992 +               #define default_param_max_packet_count  -1  //(Max, hwcfg)
14993 +               #define default_param_phy_utmi_width    16
14994 +
14995 +               #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a
14996 +               #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a
14997 +               #define default_param_timeout_cal_hs      -1 //(NoChange)
14998 +               #define default_param_timeout_cal_fs      -1 //(NoChange)
14999 +
15000 +               #define default_param_data_fifo_size      -1 //(Max, hwcfg)
15001 +
15002 +               #ifdef __IS_HOST__
15003 +                       #define default_param_host_channels       -1 //(Max, hwcfg)
15004 +                       #define default_param_rx_fifo_size        240
15005 +                       #define default_param_nperio_tx_fifo_size 240
15006 +                       #define default_param_perio_tx_fifo_size  32
15007 +               #endif //__IS_HOST__
15008 +               #ifdef __IS_DEVICE__
15009 +                               #define default_param_rx_fifo_size          256
15010 +                       #define default_param_tx_fifo_size_00 -1
15011 +                       #define default_param_tx_fifo_size_01 -1
15012 +                       #define default_param_tx_fifo_size_02 -1
15013 +                       #define default_param_tx_fifo_size_03 -1
15014 +                       #define default_param_tx_fifo_size_04 -1
15015 +                       #define default_param_tx_fifo_size_05 -1
15016 +                       #define default_param_tx_fifo_size_06 -1
15017 +                       #define default_param_tx_fifo_size_07 -1
15018 +                       #define default_param_tx_fifo_size_08 -1
15019 +                       #define default_param_tx_fifo_size_09 -1
15020 +                       #define default_param_tx_fifo_size_10 -1
15021 +                       #define default_param_tx_fifo_size_11 -1
15022 +                       #define default_param_tx_fifo_size_12 -1
15023 +                       #define default_param_tx_fifo_size_13 -1
15024 +                       #define default_param_tx_fifo_size_14 -1
15025 +                       #define default_param_tx_fifo_size_15 -1
15026 +                       #define default_param_dma_unalgned_tx -1
15027 +                       #define default_param_dma_unalgned_rx -1
15028 +                       #define default_param_thr_ctl         -1
15029 +                       #define default_param_tx_thr_length   -1
15030 +                       #define default_param_rx_thr_length   -1
15031 +               #endif //__IS_DEVICE__
15032 +       #else // __IS_VR9__
15033 +               #error "Please choose one platform!!"
15034 +       #endif // __IS_VR9__
15035 +#endif //UEIP
15036 +
15037 +/*@}*//*IFXUSB_PLATEFORM_MEM_ADDR*/
15038 +
15039 +/////////////////////////////////////////////////////////////////////////
15040 +
15041 +#ifdef __IS_HOST__
15042 +       #ifdef CONFIG_USB_HOST_IFX_FORCE_USB11
15043 +               #undef  default_param_speed
15044 +               #define default_param_speed               IFXUSB_PARAM_SPEED_FULL
15045 +       #endif
15046 +#endif
15047 +#ifdef __IS_DEVICE__
15048 +       #ifndef CONFIG_USB_GADGET_DUALSPEED
15049 +               #undef  default_param_speed
15050 +               #define default_param_speed               IFXUSB_PARAM_SPEED_FULL
15051 +       #endif
15052 +#endif
15053 +
15054 +/////////////////////////////////////////////////////////////////////////
15055 +
15056 +static __inline__ void UDELAY( const uint32_t _usecs )
15057 +{
15058 +       udelay( _usecs );
15059 +}
15060 +
15061 +static __inline__ void MDELAY( const uint32_t _msecs )
15062 +{
15063 +       mdelay( _msecs );
15064 +}
15065 +
15066 +static __inline__ void SPIN_LOCK( spinlock_t *_lock )
15067 +{
15068 +       spin_lock(_lock);
15069 +}
15070 +
15071 +static __inline__ void SPIN_UNLOCK( spinlock_t *_lock )
15072 +{
15073 +       spin_unlock(_lock);
15074 +}
15075 +
15076 +#define SPIN_LOCK_IRQSAVE( _l, _f )  \
15077 +       { \
15078 +       spin_lock_irqsave(_l,_f); \
15079 +       }
15080 +
15081 +#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) \
15082 +       { \
15083 +       spin_unlock_irqrestore(_l,_f); \
15084 +       }
15085 +
15086 +/////////////////////////////////////////////////////////////////////////
15087 +/*!
15088 +  \addtogroup IFXUSB_DBG_ROUTINE
15089 + */
15090 +/*@{*/
15091 +#ifdef __IS_HOST__
15092 +       extern uint32_t h_dbg_lvl;
15093 +#endif
15094 +
15095 +#ifdef __IS_DEVICE__
15096 +       extern uint32_t d_dbg_lvl;
15097 +#endif
15098 +
15099 +/*! \brief When debug level has the DBG_CIL bit set, display CIL Debug messages. */
15100 +#define DBG_CIL                (0x2)
15101 +/*! \brief When debug level has the DBG_CILV bit set, display CIL Verbose debug messages */
15102 +#define DBG_CILV       (0x20)
15103 +/*! \brief When debug level has the DBG_PCD bit set, display PCD (Device) debug messages */
15104 +#define DBG_PCD                (0x4)
15105 +/*! \brief When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug messages */
15106 +#define DBG_PCDV       (0x40)
15107 +/*! \brief When debug level has the DBG_HCD bit set, display Host debug messages */
15108 +#define DBG_HCD                (0x8)
15109 +/*! \brief When debug level has the DBG_HCDV bit set, display Verbose Host debug messages */
15110 +#define DBG_HCDV       (0x80)
15111 +/*! \brief When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host mode. */
15112 +#define DBG_HCD_URB    (0x800)
15113 +/*! \brief When debug level has any bit set, display debug messages */
15114 +#define DBG_ANY                (0xFF)
15115 +/*! \brief All debug messages off */
15116 +#define DBG_OFF                0
15117 +
15118 +#define DBG_ENTRY      (0x8000)
15119 +
15120 +#define IFXUSB "IFXUSB: "
15121 +
15122 +/*!
15123 +   \fn    inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new )
15124 +   \brief Set the Debug Level variable.
15125 +   \param _new 32-bit mask of debug level.
15126 +   \return previous debug level
15127 + */
15128 +static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new )
15129 +{
15130 +       #ifdef __IS_HOST__
15131 +               uint32_t old = h_dbg_lvl;
15132 +               h_dbg_lvl = _new;
15133 +       #endif
15134 +
15135 +       #ifdef __IS_DEVICE__
15136 +               uint32_t old = d_dbg_lvl;
15137 +               d_dbg_lvl = _new;
15138 +       #endif
15139 +       return old;
15140 +}
15141 +
15142 +#ifdef __DEBUG__
15143 +       #ifdef __IS_HOST__
15144 +               # define IFX_DEBUGPL(lvl, x...) do{ if ((lvl)&h_dbg_lvl)printk( KERN_DEBUG IFXUSB x ); }while(0)
15145 +               # define CHK_DEBUG_LEVEL(level) ((level) & h_dbg_lvl)
15146 +       #endif
15147 +
15148 +       #ifdef __IS_DEVICE__
15149 +               # define IFX_DEBUGPL(lvl, x...) do{ if ((lvl)&d_dbg_lvl)printk( KERN_DEBUG IFXUSB x ); }while(0)
15150 +               # define CHK_DEBUG_LEVEL(level) ((level) & d_dbg_lvl)
15151 +       #endif
15152 +
15153 +       # define IFX_DEBUGP(x...)       IFX_DEBUGPL(DBG_ANY, x )
15154 +#else
15155 +       # define IFX_DEBUGPL(lvl, x...) do{}while(0)
15156 +       # define IFX_DEBUGP(x...)
15157 +       # define CHK_DEBUG_LEVEL(level) (0)
15158 +#endif //__DEBUG__
15159 +
15160 +/* Print an Error message. */
15161 +#define IFX_ERROR(x...) printk( KERN_ERR IFXUSB x )
15162 +/* Print a Warning message. */
15163 +#define IFX_WARN(x...) printk( KERN_WARNING IFXUSB x )
15164 +/* Print a notice (normal but significant message). */
15165 +#define IFX_NOTICE(x...) printk( KERN_NOTICE IFXUSB x )
15166 +/*  Basic message printing. */
15167 +#define IFX_PRINT(x...) printk( KERN_INFO IFXUSB x )
15168 +
15169 +/*@}*//*IFXUSB_DBG_ROUTINE*/
15170 +
15171 +
15172 +#endif //__IFXUSB_PLAT_H__
15173 +
15174 --- /dev/null
15175 +++ b/drivers/usb/ifxhcd/ifxusb_regs.h
15176 @@ -0,0 +1,1420 @@
15177 +/*****************************************************************************
15178 + **   FILE NAME       : ifxusb_regs.h
15179 + **   PROJECT         : IFX USB sub-system V3
15180 + **   MODULES         : IFX USB sub-system Host and Device driver
15181 + **   SRC VERSION     : 1.0
15182 + **   DATE            : 1/Jan/2009
15183 + **   AUTHOR          : Chen, Howard
15184 + **   DESCRIPTION     : This file contains the data structures for accessing the IFXUSB core
15185 + **                     registers.
15186 + **                     The application interfaces with the USB core by reading from and
15187 + **                     writing to the Control and Status Register (CSR) space through the
15188 + **                     AHB Slave interface. These registers are 32 bits wide, and the
15189 + **                     addresses are 32-bit-block aligned.
15190 + **                     CSRs are classified as follows:
15191 + **                     - Core Global Registers
15192 + **                     - Device Mode Registers
15193 + **                     - Device Global Registers
15194 + **                     - Device Endpoint Specific Registers
15195 + **                     - Host Mode Registers
15196 + **                     - Host Global Registers
15197 + **                     - Host Port CSRs
15198 + **                     - Host Channel Specific Registers
15199 + **
15200 + **                     Only the Core Global registers can be accessed in both Device and
15201 + **                     Host modes. When the USB core is operating in one mode, either
15202 + **                     Device or Host, the application must not access registers from the
15203 + **                     other mode. When the core switches from one mode to another, the
15204 + **                     registers in the new mode of operation must be reprogrammed as they
15205 + **                     would be after a power-on reset.
15206 + **   FUNCTIONS       :
15207 + **   COMPILER        : gcc
15208 + **   REFERENCE       : Synopsys DWC-OTG Driver 2.7
15209 + **   COPYRIGHT       :
15210 + **  Version Control Section  **
15211 + **   $Author$
15212 + **   $Date$
15213 + **   $Revisions$
15214 + **   $Log$       Revision history
15215 +*****************************************************************************/
15216 +
15217 +
15218 +
15219 +/*!
15220 +  \defgroup IFXUSB_CSR_DEFINITION Control and Status Register bit-map definition
15221 +  \ingroup IFXUSB_DRIVER_V3
15222 +   \brief Data structures for accessing the IFXUSB core registers.
15223 +          The application interfaces with the USB core by reading from and
15224 +          writing to the Control and Status Register (CSR) space through the
15225 +          AHB Slave interface. These registers are 32 bits wide, and the
15226 +          addresses are 32-bit-block aligned.
15227 +          CSRs are classified as follows:
15228 +           - Core Global Registers
15229 +           - Device Mode Registers
15230 +           - Device Global Registers
15231 +           - Device Endpoint Specific Registers
15232 +           - Host Mode Registers
15233 +           - Host Global Registers
15234 +           - Host Port CSRs
15235 +           - Host Channel Specific Registers
15236 +
15237 +          Only the Core Global registers can be accessed in both Device andHost modes.
15238 +          When the USB core is operating in one mode, either Device or Host, the
15239 +          application must not access registers from the other mode. When the core
15240 +          switches from one mode to another, the registers in the new mode of operation
15241 +          must be reprogrammed as they would be after a power-on reset.
15242 + */
15243 +
15244 +/*!
15245 +  \defgroup IFXUSB_CSR_DEVICE_GLOBAL_REG Device Mode Registers
15246 +  \ingroup IFXUSB_CSR_DEFINITION
15247 +  \brief Bit-mapped structure to access Device Mode Global Registers
15248 + */
15249 +
15250 +/*!
15251 +  \defgroup IFXUSB_CSR_DEVICE_EP_REG Device Mode EP Registers
15252 +  \ingroup IFXUSB_CSR_DEFINITION
15253 +    \brief Bit-mapped structure to access Device Mode EP Registers
15254 +     There will be one set of endpoint registers per logical endpoint
15255 +     implemented.
15256 +     These registers are visible only in Device mode and must not be
15257 +     accessed in Host mode, as the results are unknown.
15258 + */
15259 +
15260 +/*!
15261 +  \defgroup IFXUSB_CSR_DEVICE_DMA_DESC Device mode scatter dma descriptor strusture
15262 +  \ingroup IFXUSB_CSR_DEFINITION
15263 +  \brief Bit-mapped structure to DMA descriptor
15264 + */
15265 +
15266 +
15267 +/*!
15268 +  \defgroup IFXUSB_CSR_HOST_GLOBAL_REG Host Mode Registers
15269 +  \ingroup IFXUSB_CSR_DEFINITION
15270 +  \brief Bit-mapped structure to access Host Mode Global Registers
15271 + */
15272 +
15273 +/*!
15274 +  \defgroup IFXUSB_CSR_HOST_HC_REG Host Mode HC Registers
15275 +  \ingroup IFXUSB_CSR_DEFINITION
15276 +    \brief Bit-mapped structure to access Host Mode Host Channel Registers
15277 +     There will be one set of endpoint registers per host channel
15278 +     implemented.
15279 +     These registers are visible only in Host mode and must not be
15280 +     accessed in Device mode, as the results are unknown.
15281 + */
15282 +
15283 +/*!
15284 +  \defgroup IFXUSB_CSR_PWR_CLK_GATING_REG Power and Clock Gating Control Register
15285 +  \ingroup IFXUSB_CSR_DEFINITION
15286 +  \brief Bit-mapped structure to Power and Clock Gating Control Register
15287 + */
15288 +
15289 +
15290 +
15291 +
15292 +
15293 +
15294 +
15295 +
15296 +/*!
15297 +  \defgroup IFXUSB_CSR_CORE_GLOBAL_REG Core Global Registers
15298 +  \ingroup IFXUSB_CSR_DEFINITION
15299 +  \brief Bit-mapped structure to access Core Global Registers
15300 + */
15301 +/*!
15302 +  \defgroup IFXUSB_CSR_CORE_GLOBAL_REG Core Global Registers
15303 +  \ingroup IFXUSB_CSR_DEFINITION
15304 +  \brief Bit-mapped structure to access Core Global Registers
15305 + */
15306 +
15307 +
15308 +
15309 +
15310 +
15311 +
15312 +
15313 +
15314 +
15315 +/*!
15316 +  \file ifxusb_regs.h
15317 +  \ingroup IFXUSB_DRIVER_V3
15318 +  \brief This file contains the data structures for accessing the IFXUSB core registers.
15319 + */
15320 +
15321 +
15322 +#ifndef __IFXUSB_REGS_H__
15323 +#define __IFXUSB_REGS_H__
15324 +
15325 +/****************************************************************************/
15326 +
15327 +#define MAX_PERIO_FIFOS  15  /** Maximum number of Periodic FIFOs */
15328 +#define MAX_TX_FIFOS     15  /** Maximum number of Periodic FIFOs */
15329 +#define MAX_EPS_CHANNELS 16  /** Maximum number of Endpoints/HostChannels */
15330 +
15331 +/****************************************************************************/
15332 +
15333 +/*!
15334 +  \addtogroup IFXUSB_CSR_ACCESS_MACROS
15335 + */
15336 +/*@{*/
15337 +
15338 +//#define RecordRegRW
15339 +
15340 +/*!
15341 +   \fn    static __inline__ uint32_t ifxusb_rreg( volatile uint32_t *_reg)
15342 +   \brief Reads the content of a register.
15343 +   \param  _reg address of register to read.
15344 +   \return contents of the register.
15345 + */
15346 +static __inline__ uint32_t ifxusb_rreg( volatile uint32_t *_reg)
15347 +{
15348 +       #ifdef RecordRegRW
15349 +               uint32_t r;
15350 +               r=*(_reg);
15351 +               return (r);
15352 +       #else
15353 +               return (*(_reg));
15354 +       #endif
15355 +};
15356 +
15357 +
15358 +/*!
15359 +   \fn    static __inline__ void ifxusb_wreg( volatile uint32_t *_reg, const uint32_t _value)
15360 +   \brief Writes a register with a 32 bit value.
15361 +   \param _reg   address of register to write.
15362 +   \param _value value to write to _reg.
15363 + */
15364 +static __inline__ void ifxusb_wreg( volatile uint32_t *_reg, const uint32_t _value)
15365 +{
15366 +       #ifdef RecordRegRW
15367 +               printk(KERN_INFO "[W %p<-%08X]\n",_reg,_value);
15368 +       #else
15369 +               *(_reg)=_value;
15370 +       #endif
15371 +};
15372 +
15373 +/*!
15374 +   \fn    static __inline__ void ifxusb_mreg( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
15375 +   \brief Modifies bit values in a register.  Using the
15376 +          algorithm: (reg_contents & ~clear_mask) | set_mask.
15377 +   \param _reg        address of register to modify.
15378 +   \param _clear_mask bit mask to be cleared.
15379 +   \param _set_mask   bit mask to be set.
15380 + */
15381 +static __inline__ void ifxusb_mreg( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
15382 +{
15383 +       uint32_t v;
15384 +       #ifdef RecordRegRW
15385 +               uint32_t r;
15386 +               v=  *(_reg);
15387 +               r=v;
15388 +               r&=(~_clear_mask);
15389 +               r|= _set_mask;
15390 +               *(_reg)=r ;
15391 +               printk(KERN_INFO "[M %p->%08X+%08X/%08X<-%08X]\n",_reg,r,_clear_mask,_set_mask,r);
15392 +       #else
15393 +               v=  *(_reg);
15394 +               v&=(~_clear_mask);
15395 +               v|= _set_mask;
15396 +               *(_reg)=v ;
15397 +       #endif
15398 +};
15399 +
15400 +/*@}*//*IFXUSB_CSR_ACCESS_MACROS*/
15401 +/****************************************************************************/
15402 +
15403 +/*!
15404 +  \addtogroup IFXUSB_CSR_CORE_GLOBAL_REG
15405 + */
15406 +/*@{*/
15407 +
15408 +/*!
15409 + \struct ifxusb_core_global_regs
15410 + \brief IFXUSB Core registers .
15411 +         The ifxusb_core_global_regs structure defines the size
15412 +         and relative field offsets for the Core Global registers.
15413 + */
15414 +typedef struct ifxusb_core_global_regs
15415 +{
15416 +       volatile uint32_t gotgctl;             /*!< 000h OTG Control and Status Register. */
15417 +       volatile uint32_t gotgint;             /*!< 004h OTG Interrupt Register. */
15418 +       volatile uint32_t gahbcfg;             /*!< 008h Core AHB Configuration Register. */
15419 +       volatile uint32_t gusbcfg;             /*!< 00Ch Core USB Configuration Register. */
15420 +       volatile uint32_t grstctl;             /*!< 010h Core Reset Register. */
15421 +       volatile uint32_t gintsts;             /*!< 014h Core Interrupt Register. */
15422 +       volatile uint32_t gintmsk;             /*!< 018h Core Interrupt Mask Register. */
15423 +       volatile uint32_t grxstsr;             /*!< 01Ch Receive Status Queue Read Register (Read Only). */
15424 +       volatile uint32_t grxstsp;             /*!< 020h Receive Status Queue Read & POP Register (Read Only). */
15425 +       volatile uint32_t grxfsiz;             /*!< 024h Receive FIFO Size Register. */
15426 +       volatile uint32_t gnptxfsiz;           /*!< 028h Non Periodic Transmit FIFO Size Register. */
15427 +       volatile uint32_t gnptxsts;            /*!< 02Ch Non Periodic Transmit FIFO/Queue Status Register (Read Only). */
15428 +       volatile uint32_t gi2cctl;             /*!< 030h I2C Access Register. */
15429 +       volatile uint32_t gpvndctl;            /*!< 034h PHY Vendor Control Register. */
15430 +       volatile uint32_t ggpio;               /*!< 038h General Purpose Input/Output Register. */
15431 +       volatile uint32_t guid;                /*!< 03Ch User ID Register. */
15432 +       volatile uint32_t gsnpsid;             /*!< 040h Synopsys ID Register (Read Only). */
15433 +       volatile uint32_t ghwcfg1;             /*!< 044h User HW Config1 Register (Read Only). */
15434 +       volatile uint32_t ghwcfg2;             /*!< 048h User HW Config2 Register (Read Only). */
15435 +       volatile uint32_t ghwcfg3;             /*!< 04Ch User HW Config3 Register (Read Only). */
15436 +       volatile uint32_t ghwcfg4;             /*!< 050h User HW Config4 Register (Read Only). */
15437 +       volatile uint32_t reserved[43];        /*!< 054h Reserved  054h-0FFh */
15438 +       volatile uint32_t hptxfsiz;            /*!< 100h Host Periodic Transmit FIFO Size Register. */
15439 +       volatile uint32_t dptxfsiz_dieptxf[15];/*!< 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15.
15440 +                                                  Device Periodic Transmit FIFO#n Register if dedicated
15441 +                                                  fifos are disabled, otherwise Device Transmit FIFO#n
15442 +                                                  Register.
15443 +                                                */
15444 +} ifxusb_core_global_regs_t;
15445 +
15446 +/*!
15447 + \brief Bits of the Core OTG Control and Status Register (GOTGCTL).
15448 + */
15449 +typedef union gotgctl_data
15450 +{
15451 +       uint32_t d32;
15452 +       struct{
15453 +               unsigned reserved21_31 : 11;
15454 +               unsigned currmod       : 1 ; /*!< 20 */
15455 +               unsigned bsesvld       : 1 ; /*!< 19 */
15456 +               unsigned asesvld       : 1 ; /*!< 18 */
15457 +               unsigned reserved17    : 1 ;
15458 +               unsigned conidsts      : 1 ; /*!< 16 */
15459 +               unsigned reserved12_15 : 4 ;
15460 +               unsigned devhnpen      : 1 ; /*!< 11 */
15461 +               unsigned hstsethnpen   : 1 ; /*!< 10 */
15462 +               unsigned hnpreq        : 1 ; /*!< 09 */
15463 +               unsigned hstnegscs     : 1 ; /*!< 08 */
15464 +               unsigned reserved2_7   : 6 ;
15465 +               unsigned sesreq        : 1 ; /*!< 01 */
15466 +               unsigned sesreqscs     : 1 ; /*!< 00 */
15467 +       } b;
15468 +} gotgctl_data_t;
15469 +
15470 +/*!
15471 + \brief Bit fields of the Core OTG Interrupt Register (GOTGINT).
15472 + */
15473 +typedef union gotgint_data
15474 +{
15475 +       uint32_t d32;
15476 +       struct
15477 +       {
15478 +               unsigned reserved31_20     : 12;
15479 +               unsigned debdone           : 1 ; /*!< 19 Debounce Done */
15480 +               unsigned adevtoutchng      : 1 ; /*!< 18 A-Device Timeout Change */
15481 +               unsigned hstnegdet         : 1 ; /*!< 17 Host Negotiation Detected */
15482 +               unsigned reserver10_16     : 7 ;
15483 +               unsigned hstnegsucstschng  : 1 ; /*!< 09 Host Negotiation Success Status Change */
15484 +               unsigned sesreqsucstschng  : 1 ; /*!< 08 Session Request Success Status Change */
15485 +               unsigned reserved3_7       : 5 ;
15486 +               unsigned sesenddet         : 1 ; /*!< 02 Session End Detected */
15487 +               unsigned reserved0_1       : 2 ;
15488 +       } b;
15489 +} gotgint_data_t;
15490 +
15491 +/*!
15492 + \brief Bit fields of the Core AHB Configuration Register (GAHBCFG).
15493 + */
15494 +typedef union gahbcfg_data
15495 +{
15496 +       uint32_t d32;
15497 +       struct
15498 +       {
15499 +               unsigned reserved9_31      : 23;
15500 +               unsigned ptxfemplvl        : 1 ; /*!< 08    Periodic FIFO empty level trigger condition*/
15501 +               unsigned nptxfemplvl       : 1 ; /*!< 07    Non-Periodic FIFO empty level trigger condition*/
15502 +                       #define IFXUSB_GAHBCFG_TXFEMPTYLVL_EMPTY     1
15503 +                       #define IFXUSB_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
15504 +               unsigned reserved          : 1 ;
15505 +               unsigned dmaenable         : 1 ; /*!< 05    DMA enable*/
15506 +                       #define IFXUSB_GAHBCFG_DMAENABLE             1
15507 +               unsigned hburstlen         : 4 ; /*!< 01-04 DMA Burst-length*/
15508 +                       #define IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE  0
15509 +                       #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR    1
15510 +                       #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4   3
15511 +                       #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8   5
15512 +                       #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16  7
15513 +               unsigned glblintrmsk       : 1 ;  /*!< 00    USB Global Interrupt Enable */
15514 +                       #define IFXUSB_GAHBCFG_GLBINT_ENABLE         1
15515 +       } b;
15516 +} gahbcfg_data_t;
15517 +
15518 +/*!
15519 + \brief Bit fields of the Core USB Configuration Register (GUSBCFG).
15520 +*/
15521 +typedef union gusbcfg_data
15522 +{
15523 +       uint32_t d32;
15524 +       struct
15525 +       {
15526 +               unsigned reserved31              : 1;
15527 +               unsigned ForceDevMode            : 1; /*!< 30 Force Device Mode */
15528 +               unsigned ForceHstMode            : 1; /*!< 29 Force Host Mode */
15529 +               unsigned TxEndDelay              : 1; /*!< 28 Tx End Delay */
15530 +               unsigned reserved2723            : 5;
15531 +               unsigned term_sel_dl_pulse       : 1; /*!< 22 TermSel DLine Pulsing Selection */
15532 +               unsigned reserved2117            : 5;
15533 +               unsigned otgutmifssel            : 1; /*!< 16 UTMIFS Select */
15534 +               unsigned phylpwrclksel           : 1; /*!< 15 PHY Low-Power Clock Select */
15535 +               unsigned reserved14              : 1;
15536 +               unsigned usbtrdtim               : 4; /*!< 13-10 USB Turnaround Time */
15537 +               unsigned hnpcap                  : 1; /*!< 09 HNP-Capable */
15538 +               unsigned srpcap                  : 1; /*!< 08 SRP-Capable */
15539 +               unsigned reserved07              : 1;
15540 +               unsigned physel                  : 1; /*!< 06 USB 2.0 High-Speed PHY or
15541 +                                                            USB 1.1 Full-Speed Serial
15542 +                                                            Transceiver Select */
15543 +               unsigned fsintf                  : 1; /*!< 05 Full-Speed Serial Interface Select */
15544 +               unsigned ulpi_utmi_sel           : 1; /*!< 04 ULPI or UTMI+ Select */
15545 +               unsigned phyif                   : 1; /*!< 03 PHY Interface */
15546 +               unsigned toutcal                 : 3; /*!< 00-02 HS/FS Timeout Calibration */
15547 +       }b;
15548 +} gusbcfg_data_t;
15549 +
15550 +/*!
15551 + \brief Bit fields of the Core Reset Register (GRSTCTL).
15552 + */
15553 +typedef union grstctl_data
15554 +{
15555 +       uint32_t d32;
15556 +       struct
15557 +       {
15558 +               unsigned ahbidle         : 1; /*!< 31 AHB Master Idle.  Indicates the AHB Master State
15559 +                                                    Machine is in IDLE condition. */
15560 +               unsigned dmareq          : 1; /*!< 30 DMA Request Signal.  Indicated DMA request is in
15561 +                                                    probress.  Used for debug purpose. */
15562 +               unsigned reserved11_29   :19;
15563 +               unsigned txfnum          : 5; /*!< 10-06 TxFIFO Number (TxFNum) to be flushed.
15564 +                                                 0x00: Non Periodic TxFIFO Flush or TxFIFO 0
15565 +                                                 0x01-0x0F: Periodic TxFIFO Flush or TxFIFO n
15566 +                                                 0x10: Flush all TxFIFO
15567 +                                              */
15568 +               unsigned txfflsh         : 1; /*!< 05 TxFIFO Flush */
15569 +               unsigned rxfflsh         : 1; /*!< 04 RxFIFO Flush */
15570 +               unsigned intknqflsh      : 1; /*!< 03 In Token Sequence Learning Queue Flush (Device Only) */
15571 +               unsigned hstfrm          : 1; /*!< 02 Host Frame Counter Reset (Host Only) */
15572 +               unsigned hsftrst         : 1; /*!< 01 Hclk Soft Reset */
15573 +
15574 +               unsigned csftrst         : 1; /*!< 00 Core Soft Reset
15575 +                                                    The application can flush the control logic in the
15576 +                                                    entire core using this bit. This bit resets the
15577 +                                                    pipelines in the AHB Clock domain as well as the
15578 +                                                    PHY Clock domain.
15579 +                                                    The state machines are reset to an IDLE state, the
15580 +                                                    control bits in the CSRs are cleared, all the
15581 +                                                    transmit FIFOs and the receive FIFO are flushed.
15582 +                                                    The status mask bits that control the generation of
15583 +                                                    the interrupt, are cleared, to clear the
15584 +                                                    interrupt. The interrupt status bits are not
15585 +                                                    cleared, so the application can get the status of
15586 +                                                    any events that occurred in the core after it has
15587 +                                                    set this bit.
15588 +                                                    Any transactions on the AHB are terminated as soon
15589 +                                                    as possible following the protocol. Any
15590 +                                                    transactions on the USB are terminated immediately.
15591 +                                                    The configuration settings in the CSRs are
15592 +                                                    unchanged, so the software doesn't have to
15593 +                                                    reprogram these registers (Device
15594 +                                                    Configuration/Host Configuration/Core System
15595 +                                                    Configuration/Core PHY Configuration).
15596 +                                                    The application can write to this bit, any time it
15597 +                                                    wants to reset the core. This is a self clearing
15598 +                                                    bit and the core clears this bit after all the
15599 +                                                    necessary logic is reset in the core, which may
15600 +                                                    take several clocks, depending on the current state
15601 +                                                    of the core.
15602 +                                              */
15603 +       }b;
15604 +} grstctl_t;
15605 +
15606 +/*!
15607 + \brief Bit fields of the Core Interrupt Mask Register (GINTMSK) and
15608 +        Core Interrupt Register (GINTSTS).
15609 + */
15610 +typedef union gint_data
15611 +{
15612 +       uint32_t d32;
15613 +               #define IFXUSB_SOF_INTR_MASK 0x0008
15614 +       struct
15615 +       {
15616 +               unsigned wkupintr      : 1; /*!< 31 Resume/Remote Wakeup Detected Interrupt */
15617 +               unsigned sessreqintr   : 1; /*!< 30 Session Request/New Session Detected Interrupt */
15618 +               unsigned disconnect    : 1; /*!< 29 Disconnect Detected Interrupt */
15619 +               unsigned conidstschng  : 1; /*!< 28 Connector ID Status Change */
15620 +               unsigned reserved27    : 1;
15621 +               unsigned ptxfempty     : 1; /*!< 26 Periodic TxFIFO Empty */
15622 +               unsigned hcintr        : 1; /*!< 25 Host Channels Interrupt */
15623 +               unsigned portintr      : 1; /*!< 24 Host Port Interrupt */
15624 +               unsigned reserved23    : 1;
15625 +               unsigned fetsuspmsk    : 1; /*!< 22 Data Fetch Suspended */
15626 +               unsigned incomplisoout : 1; /*!< 21 Incomplete IsochronousOUT/Period Transfer */
15627 +               unsigned incomplisoin  : 1; /*!< 20 Incomplete Isochronous IN Transfer */
15628 +               unsigned outepintr     : 1; /*!< 19 OUT Endpoints Interrupt */
15629 +               unsigned inepintr      : 1; /*!< 18 IN Endpoints Interrupt */
15630 +               unsigned epmismatch    : 1; /*!< 17 Endpoint Mismatch Interrupt */
15631 +               unsigned reserved16    : 1;
15632 +               unsigned eopframe      : 1; /*!< 15 End of Periodic Frame Interrupt */
15633 +               unsigned isooutdrop    : 1; /*!< 14 Isochronous OUT Packet Dropped Interrupt */
15634 +               unsigned enumdone      : 1; /*!< 13 Enumeration Done */
15635 +               unsigned usbreset      : 1; /*!< 12 USB Reset */
15636 +               unsigned usbsuspend    : 1; /*!< 11 USB Suspend */
15637 +               unsigned erlysuspend   : 1; /*!< 10 Early Suspend */
15638 +               unsigned i2cintr       : 1; /*!< 09 I2C Interrupt */
15639 +               unsigned reserved8     : 1;
15640 +               unsigned goutnakeff    : 1; /*!< 07 Global OUT NAK Effective */
15641 +               unsigned ginnakeff     : 1; /*!< 06 Global Non-periodic IN NAK Effective */
15642 +               unsigned nptxfempty    : 1; /*!< 05 Non-periodic TxFIFO Empty */
15643 +               unsigned rxstsqlvl     : 1; /*!< 04 Receive FIFO Non-Empty */
15644 +               unsigned sofintr       : 1; /*!< 03 Start of (u)Frame */
15645 +               unsigned otgintr       : 1; /*!< 02 OTG Interrupt */
15646 +               unsigned modemismatch  : 1; /*!< 01 Mode Mismatch Interrupt */
15647 +               unsigned reserved0     : 1;
15648 +       } b;
15649 +} gint_data_t;
15650 +
15651 +/*!
15652 +  \brief Bit fields in the Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP)
15653 + */
15654 +typedef union grxsts_data
15655 +{
15656 +       uint32_t d32;
15657 +       struct
15658 +       {
15659 +               unsigned reserved : 7;
15660 +               unsigned fn       : 4; /*!< 24-21 Frame Number */
15661 +               unsigned pktsts   : 4; /*!< 20-17 Packet Status */
15662 +                       #define IFXUSB_DSTS_DATA_UPDT   0x2               // OUT Data Packet
15663 +                       #define IFXUSB_DSTS_XFER_COMP   0x3               // OUT Data Transfer Complete
15664 +                       #define IFXUSB_DSTS_GOUT_NAK    0x1               // Global OUT NAK
15665 +                       #define IFXUSB_DSTS_SETUP_COMP  0x4               // Setup Phase Complete
15666 +                       #define IFXUSB_DSTS_SETUP_UPDT  0x6               // SETUP Packet
15667 +               unsigned dpid     : 2; /*!< 16-15 Data PID */
15668 +               unsigned bcnt     :11; /*!< 14-04 Byte Count */
15669 +               unsigned epnum    : 4; /*!< 03-00 Endpoint Number */
15670 +       } db;
15671 +       struct
15672 +       {
15673 +               unsigned reserved :11;
15674 +               unsigned pktsts   : 4; /*!< 20-17 Packet Status */
15675 +                       #define IFXUSB_HSTS_DATA_UPDT        0x2 // OUT Data Packet
15676 +                       #define IFXUSB_HSTS_XFER_COMP        0x3 // OUT Data Transfer Complete
15677 +                       #define IFXUSB_HSTS_DATA_TOGGLE_ERR  0x5 // DATA TOGGLE Error
15678 +                       #define IFXUSB_HSTS_CH_HALTED        0x7 // Channel Halted
15679 +               unsigned dpid     : 2; /*!< 16-15 Data PID */
15680 +               unsigned bcnt     :11; /*!< 14-04 Byte Count */
15681 +               unsigned chnum    : 4; /*!< 03-00 Channel Number */
15682 +       } hb;
15683 +} grxsts_data_t;
15684 +
15685 +/*!
15686 +  \brief Bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn).
15687 + */
15688 +typedef union fifosize_data
15689 +{
15690 +       uint32_t d32;
15691 +       struct
15692 +       {
15693 +               unsigned depth     : 16; /*!< 31-16 TxFIFO Depth (in DWord)*/
15694 +               unsigned startaddr : 16; /*!< 15-00 RAM Starting address */
15695 +       } b;
15696 +} fifosize_data_t;
15697 +
15698 +/*!
15699 +  \brief Bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).
15700 + */
15701 +
15702 +typedef union gnptxsts_data
15703 +{
15704 +       uint32_t d32;
15705 +       struct
15706 +       {
15707 +               unsigned reserved           : 1;
15708 +               unsigned nptxqtop_chnep     : 4; /*!< 30-27 Channel/EP Number of top of the Non-Periodic
15709 +                                                    Transmit Request Queue
15710 +                                                 */
15711 +               unsigned nptxqtop_token     : 2; /*!< 26-25 Token Type top of the Non-Periodic
15712 +                                                    Transmit Request Queue
15713 +                                                 0 - IN/OUT
15714 +                                                 1 - Zero Length OUT
15715 +                                                 2 - PING/Complete Split
15716 +                                                 3 - Channel Halt
15717 +                                                 */
15718 +               unsigned nptxqtop_terminate : 1; /*!< 24    Terminate (Last entry for the selected
15719 +                                                          channel/EP)*/
15720 +               unsigned nptxqspcavail      : 8; /*!< 23-16 Transmit Request Queue Space Available */
15721 +               unsigned nptxfspcavail      :16; /*!< 15-00 TxFIFO Space Avail (in DWord)*/
15722 +       }b;
15723 +} gnptxsts_data_t;
15724 +
15725 +
15726 +/*!
15727 +  \brief Bit fields in the Transmit FIFO Status Register (DTXFSTS).
15728 + */
15729 +typedef union dtxfsts_data
15730 +{
15731 +       uint32_t d32;
15732 +       struct
15733 +       {
15734 +               unsigned reserved    : 16;
15735 +               unsigned txfspcavail : 16; /*!< 15-00 TxFIFO Space Avail (in DWord)*/
15736 +       }b;
15737 +} dtxfsts_data_t;
15738 +
15739 +
15740 +/*!
15741 +  \brief Bit fields in the I2C Control Register (I2CCTL).
15742 + */
15743 +typedef union gi2cctl_data
15744 +{
15745 +       uint32_t d32;
15746 +       struct
15747 +       {
15748 +               unsigned bsydne     : 1; /*!< 31    I2C Busy/Done*/
15749 +               unsigned rw         : 1; /*!< 30    Read/Write Indicator */
15750 +               unsigned reserved   : 2;
15751 +               unsigned i2cdevaddr : 2; /*!< 27-26 I2C Device Address */
15752 +               unsigned i2csuspctl : 1; /*!< 25    I2C Suspend Control */
15753 +               unsigned ack        : 1; /*!< 24    I2C ACK */
15754 +               unsigned i2cen      : 1; /*!< 23    I2C Enable */
15755 +               unsigned addr       : 7; /*!< 22-16 I2C Address */
15756 +               unsigned regaddr    : 8; /*!< 15-08 I2C Register Addr */
15757 +               unsigned rwdata     : 8; /*!< I2C Read/Write Data */
15758 +       } b;
15759 +} gi2cctl_data_t;
15760 +
15761 +
15762 +/*!
15763 +  \brief Bit fields in the User HW Config1 Register.
15764 + */
15765 +typedef union hwcfg1_data
15766 +{
15767 +       uint32_t d32;
15768 +       struct
15769 +       {
15770 +               unsigned ep_dir15 : 2; /*!< Direction of each EP
15771 +                                          0: BIDIR (IN and OUT) endpoint
15772 +                                      1: IN endpoint
15773 +                                      2: OUT endpoint
15774 +                                      3: Reserved
15775 +                                   */
15776 +               unsigned ep_dir14 : 2;
15777 +               unsigned ep_dir13 : 2;
15778 +               unsigned ep_dir12 : 2;
15779 +               unsigned ep_dir11 : 2;
15780 +               unsigned ep_dir10 : 2;
15781 +               unsigned ep_dir09 : 2;
15782 +               unsigned ep_dir08 : 2;
15783 +               unsigned ep_dir07 : 2;
15784 +               unsigned ep_dir06 : 2;
15785 +               unsigned ep_dir05 : 2;
15786 +               unsigned ep_dir04 : 2;
15787 +               unsigned ep_dir03 : 2;
15788 +               unsigned ep_dir02 : 2;
15789 +               unsigned ep_dir01 : 2;
15790 +               unsigned ep_dir00 : 2;
15791 +       }b;
15792 +} hwcfg1_data_t;
15793 +
15794 +/*!
15795 +  \brief Bit fields in the User HW Config2 Register.
15796 + */
15797 +typedef union hwcfg2_data
15798 +{
15799 +       uint32_t d32;
15800 +       struct
15801 +       {
15802 +               unsigned reserved31             : 1;
15803 +               unsigned dev_token_q_depth      : 5; /*!< 30-26 Device Mode IN Token Sequence Learning Queue Depth */
15804 +               unsigned host_perio_tx_q_depth  : 2; /*!< 25-24 Host Mode Periodic Request Queue Depth */
15805 +               unsigned nonperio_tx_q_depth    : 2; /*!< 23-22 Non-periodic Request Queue Depth */
15806 +               unsigned rx_status_q_depth      : 2; /*!< 21-20 Multi Processor Interrupt Enabled */
15807 +               unsigned dynamic_fifo           : 1; /*!< 19    Dynamic FIFO Sizing Enabled */
15808 +               unsigned perio_ep_supported     : 1; /*!< 18    Periodic OUT Channels Supported in Host Mode */
15809 +               unsigned num_host_chan          : 4; /*!< 17-14 Number of Host Channels */
15810 +               unsigned num_dev_ep             : 4; /*!< 13-10 Number of Device Endpoints */
15811 +               unsigned fs_phy_type            : 2; /*!< 09-08 Full-Speed PHY Interface Type */
15812 +                       #define IFXUSB_HWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
15813 +                       #define IFXUSB_HWCFG2_FS_PHY_TYPE_DEDICATE      1
15814 +                       #define IFXUSB_HWCFG2_FS_PHY_TYPE_UTMI          2
15815 +                       #define IFXUSB_HWCFG2_FS_PHY_TYPE_ULPI          3
15816 +               unsigned hs_phy_type            : 2; /*!< 07-06 High-Speed PHY Interface Type */
15817 +                       #define IFXUSB_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
15818 +                       #define IFXUSB_HWCFG2_HS_PHY_TYPE_UTMI          1
15819 +                       #define IFXUSB_HWCFG2_HS_PHY_TYPE_ULPI          2
15820 +                       #define IFXUSB_HWCFG2_HS_PHY_TYPE_UTMI_ULPI     3
15821 +               unsigned point2point            : 1; /*!< 05    Point-to-Point */
15822 +               unsigned architecture           : 2; /*!< 04-03 Architecture */
15823 +                       #define IFXUSB_HWCFG2_ARCH_SLAVE_ONLY  0
15824 +                       #define IFXUSB_HWCFG2_ARCH_EXT_DMA     1
15825 +                       #define IFXUSB_HWCFG2_ARCH_INT_DMA     2
15826 +               unsigned op_mode                : 3; /*!< 02-00 Mode of Operation */
15827 +                       #define IFXUSB_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG    0
15828 +                       #define IFXUSB_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG   1
15829 +                       #define IFXUSB_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
15830 +                       #define IFXUSB_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE     3
15831 +                       #define IFXUSB_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE  4
15832 +                       #define IFXUSB_HWCFG2_OP_MODE_SRP_CAPABLE_HOST       5
15833 +                       #define IFXUSB_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST    6
15834 +       } b;
15835 +} hwcfg2_data_t;
15836 +
15837 +/*!
15838 +  \brief Bit fields in the User HW Config3 Register.
15839 + */
15840 +typedef union hwcfg3_data
15841 +{
15842 +       uint32_t d32;
15843 +       struct
15844 +       {
15845 +               unsigned dfifo_depth            :16; /*!< 31-16 DFIFO Depth  */
15846 +               unsigned reserved15_12          : 4;
15847 +               unsigned synch_reset_type       : 1; /*!< 11    Reset Style for Clocked always Blocks in RTL */
15848 +               unsigned optional_features      : 1; /*!< 10    Optional Features Removed */
15849 +               unsigned vendor_ctrl_if         : 1; /*!< 09    Vendor Control Interface Support */
15850 +               unsigned i2c                    : 1; /*!< 08    I2C Selection */
15851 +               unsigned otg_func               : 1; /*!< 07    OTG Function Enabled */
15852 +               unsigned packet_size_cntr_width : 3; /*!< 06-04 Width of Packet Size Counters */
15853 +               unsigned xfer_size_cntr_width   : 4; /*!< 03-00 Width of Transfer Size Counters */
15854 +       } b;
15855 +} hwcfg3_data_t;
15856 +
15857 +/*!
15858 +  \brief Bit fields in the User HW Config4
15859 + * Register.  Read the register into the <i>d32</i> element then read
15860 + * out the bits using the <i>b</i>it elements.
15861 + */
15862 +typedef union hwcfg4_data
15863 +{
15864 +       uint32_t d32;
15865 +       struct
15866 +       {
15867 +               unsigned desc_dma_dyn         : 1; /*!< 31    Scatter/Gather DMA */
15868 +               unsigned desc_dma             : 1; /*!< 30    Scatter/Gather DMA configuration */
15869 +               unsigned num_in_eps           : 4; /*!< 29-26 Number of Device Mode IN Endpoints Including Control Endpoints */
15870 +               unsigned ded_fifo_en          : 1; /*!< 25    Enable Dedicated Transmit FIFO for device IN Endpoints */
15871 +               unsigned session_end_filt_en  : 1; /*!< 24    session_end Filter Enabled */
15872 +               unsigned b_valid_filt_en      : 1; /*!< 23    b_valid Filter Enabled */
15873 +               unsigned a_valid_filt_en      : 1; /*!< 22    a_valid Filter Enabled */
15874 +               unsigned vbus_valid_filt_en   : 1; /*!< 21    vbus_valid Filter Enabled */
15875 +               unsigned iddig_filt_en        : 1; /*!< 20    iddig Filter Enable */
15876 +               unsigned num_dev_mode_ctrl_ep : 4; /*!< 19-16 Number of Device Mode Control Endpoints in Addition to Endpoint 0 */
15877 +               unsigned utmi_phy_data_width  : 2; /*!< 15-14 UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width */
15878 +               unsigned reserved13_06        : 8;
15879 +               unsigned min_ahb_freq         : 1; /*!< 05    Minimum AHB Frequency Less Than 60 MHz */
15880 +               unsigned power_optimiz        : 1; /*!< 04    Enable Power Optimization? */
15881 +               unsigned num_dev_perio_in_ep  : 4; /*!< 03-00 Number of Device Mode Periodic IN Endpoints */
15882 +       } b;
15883 +} hwcfg4_data_t;
15884 +
15885 +/*@}*//*IFXUSB_CSR_CORE_GLOBAL_REG*/
15886 +
15887 +/****************************************************************************/
15888 +/*!
15889 +  \addtogroup IFXUSB_CSR_DEVICE_GLOBAL_REG
15890 + */
15891 +/*@{*/
15892 +
15893 +/*!
15894 + \struct ifxusb_dev_global_regs
15895 + \brief IFXUSB Device Mode Global registers. Offsets 800h-BFFh
15896 +        The ifxusb_dev_global_regs structure defines the size
15897 +        and relative field offsets for the Device Global registers.
15898 +        These registers are visible only in Device mode and must not be
15899 +        accessed in Host mode, as the results are unknown.
15900 + */
15901 +typedef struct ifxusb_dev_global_regs
15902 +{
15903 +       volatile uint32_t dcfg;                 /*!< 800h Device Configuration Register. */
15904 +       volatile uint32_t dctl;                 /*!< 804h Device Control Register. */
15905 +       volatile uint32_t dsts;                 /*!< 808h Device Status Register (Read Only). */
15906 +       uint32_t unused;
15907 +       volatile uint32_t diepmsk;              /*!< 810h Device IN Endpoint Common Interrupt Mask Register. */
15908 +       volatile uint32_t doepmsk;              /*!< 814h Device OUT Endpoint Common Interrupt Mask Register. */
15909 +       volatile uint32_t daint;                /*!< 818h Device All Endpoints Interrupt Register. */
15910 +       volatile uint32_t daintmsk;             /*!< 81Ch Device All Endpoints Interrupt Mask Register. */
15911 +       volatile uint32_t dtknqr1;              /*!< 820h Device IN Token Queue Read Register-1 (Read Only). */
15912 +       volatile uint32_t dtknqr2;              /*!< 824h Device IN Token Queue Read Register-2 (Read Only). */
15913 +       volatile uint32_t dvbusdis;             /*!< 828h Device VBUS discharge Register.*/
15914 +       volatile uint32_t dvbuspulse;           /*!< 82Ch Device VBUS Pulse Register. */
15915 +       volatile uint32_t dtknqr3_dthrctl;      /*!< 830h Device IN Token Queue Read Register-3 (Read Only).
15916 +                                                        Device Thresholding control register (Read/Write)
15917 +                                                */
15918 +       volatile uint32_t dtknqr4_fifoemptymsk; /*!< 834h Device IN Token Queue Read Register-4 (Read Only).
15919 +                                                            Device IN EPs empty Inr. Mask Register (Read/Write)
15920 +                                                */
15921 +} ifxusb_device_global_regs_t;
15922 +
15923 +/*!
15924 +  \brief Bit fields in the Device Configuration Register.
15925 + */
15926 +
15927 +typedef union dcfg_data
15928 +{
15929 +       uint32_t d32;
15930 +       struct
15931 +       {
15932 +               unsigned reserved31_26   : 6;
15933 +               unsigned perschintvl     : 2; /*!< 25-24 Periodic Scheduling Interval */
15934 +               unsigned descdma         : 1; /*!< 23    Enable Descriptor DMA in Device mode */
15935 +               unsigned epmscnt         : 5; /*!< 22-18 In Endpoint Mis-match count */
15936 +               unsigned reserved13_17   : 5;
15937 +               unsigned perfrint        : 2; /*!< 12-11 Periodic Frame Interval */
15938 +                       #define IFXUSB_DCFG_FRAME_INTERVAL_80 0
15939 +                       #define IFXUSB_DCFG_FRAME_INTERVAL_85 1
15940 +                       #define IFXUSB_DCFG_FRAME_INTERVAL_90 2
15941 +                       #define IFXUSB_DCFG_FRAME_INTERVAL_95 3
15942 +               unsigned devaddr         : 7; /*!< 10-04 Device Addresses */
15943 +               unsigned reserved3       : 1;
15944 +               unsigned nzstsouthshk    : 1; /*!< 02    Non Zero Length Status OUT Handshake */
15945 +                       #define IFXUSB_DCFG_SEND_STALL 1
15946 +               unsigned devspd          : 2; /*!< 01-00 Device Speed */
15947 +       } b;
15948 +} dcfg_data_t;
15949 +
15950 +/*!
15951 +  \brief Bit fields in the Device Control Register.
15952 + */
15953 +typedef union dctl_data
15954 +{
15955 +       uint32_t d32;
15956 +       struct
15957 +       {
15958 +               unsigned reserved16_31  :16;
15959 +               unsigned ifrmnum        : 1; /*!< 15    Ignore Frame Number for ISOC EPs */
15960 +               unsigned gmc            : 2; /*!< 14-13 Global Multi Count */
15961 +               unsigned gcontbna       : 1; /*!< 12    Global Continue on BNA */
15962 +               unsigned pwronprgdone   : 1; /*!< 11    Power-On Programming Done */
15963 +               unsigned cgoutnak       : 1; /*!< 10    Clear Global OUT NAK */
15964 +               unsigned sgoutnak       : 1; /*!< 09    Set Global OUT NAK */
15965 +               unsigned cgnpinnak      : 1; /*!< 08    Clear Global Non-Periodic IN NAK */
15966 +               unsigned sgnpinnak      : 1; /*!< 07    Set Global Non-Periodic IN NAK */
15967 +               unsigned tstctl         : 3; /*!< 06-04 Test Control */
15968 +               unsigned goutnaksts     : 1; /*!< 03    Global OUT NAK Status */
15969 +               unsigned gnpinnaksts    : 1; /*!< 02    Global Non-Periodic IN NAK Status */
15970 +               unsigned sftdiscon      : 1; /*!< 01    Soft Disconnect */
15971 +               unsigned rmtwkupsig     : 1; /*!< 00    Remote Wakeup */
15972 +       } b;
15973 +} dctl_data_t;
15974 +
15975 +
15976 +/*!
15977 +  \brief Bit fields in the Device Status Register.
15978 + */
15979 +typedef union dsts_data
15980 +{
15981 +       uint32_t d32;
15982 +       struct
15983 +       {
15984 +               unsigned reserved22_31  :10;
15985 +               unsigned soffn          :14; /*!< 21-08 Frame or Microframe Number of the received SOF */
15986 +               unsigned reserved4_7    : 4;
15987 +               unsigned errticerr      : 1; /*!< 03    Erratic Error */
15988 +               unsigned enumspd        : 2; /*!< 02-01 Enumerated Speed */
15989 +                       #define IFXUSB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
15990 +                       #define IFXUSB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
15991 +                       #define IFXUSB_DSTS_ENUMSPD_LS_PHY_6MHZ           2
15992 +                       #define IFXUSB_DSTS_ENUMSPD_FS_PHY_48MHZ          3
15993 +               unsigned suspsts        : 1; /*!< 00    Suspend Status */
15994 +       } b;
15995 +} dsts_data_t;
15996 +
15997 +/*!
15998 +  \brief Bit fields in the Device IN EP Interrupt Register
15999 +         and the Device IN EP Common Mask Register.
16000 + */
16001 +typedef union diepint_data
16002 +{
16003 +       uint32_t d32;
16004 +       struct
16005 +       {
16006 +               unsigned reserved14_31   :18;
16007 +               unsigned nakmsk          : 1; /*!< 13 NAK interrupt Mask */
16008 +               unsigned reserved10_12   : 3;
16009 +               unsigned bna             : 1; /*!< 09 BNA Interrupt mask */
16010 +               unsigned txfifoundrn     : 1; /*!< 08 Fifo Underrun Mask */
16011 +               unsigned emptyintr       : 1; /*!< 07 IN Endpoint HAK Effective mask */
16012 +               unsigned inepnakeff      : 1; /*!< 06 IN Endpoint HAK Effective mask */
16013 +               unsigned intknepmis      : 1; /*!< 05 IN Token Received with EP mismatch mask */
16014 +               unsigned intktxfemp      : 1; /*!< 04 IN Token received with TxF Empty mask */
16015 +               unsigned timeout         : 1; /*!< 03 TimeOUT Handshake mask (non-ISOC EPs) */
16016 +               unsigned ahberr          : 1; /*!< 02 AHB Error mask */
16017 +               unsigned epdisabled      : 1; /*!< 01 Endpoint disable mask */
16018 +               unsigned xfercompl       : 1; /*!< 00 Transfer complete mask */
16019 +       } b;
16020 +} diepint_data_t;
16021 +
16022 +
16023 +/*!
16024 +  \brief Bit fields in the Device OUT EP Interrupt Register and
16025 +         Device OUT EP Common Interrupt Mask Register.
16026 +  */
16027 +typedef union doepint_data
16028 +{
16029 +       uint32_t d32;
16030 +       struct
16031 +       {
16032 +               unsigned reserved15_31  :17;
16033 +               unsigned nyetmsk        : 1; /*!< 14 NYET Interrupt */
16034 +               unsigned nakmsk         : 1; /*!< 13 NAK Interrupt */
16035 +               unsigned bbleerrmsk     : 1; /*!< 12 Babble Interrupt */
16036 +               unsigned reserved10_11  : 2;
16037 +               unsigned bna            : 1; /*!< 09 BNA Interrupt */
16038 +               unsigned outpkterr      : 1; /*!< 08 OUT packet Error */
16039 +               unsigned reserved07     : 1;
16040 +               unsigned back2backsetup : 1; /*!< 06 Back-to-Back SETUP Packets Received */
16041 +               unsigned stsphsercvd    : 1; /*!< 05 */
16042 +               unsigned outtknepdis    : 1; /*!< 04 OUT Token Received when Endpoint Disabled */
16043 +               unsigned setup          : 1; /*!< 03 Setup Phase Done (contorl EPs) */
16044 +               unsigned ahberr         : 1; /*!< 02 AHB Error */
16045 +               unsigned epdisabled     : 1; /*!< 01 Endpoint disable */
16046 +               unsigned xfercompl      : 1; /*!< 00 Transfer complete */
16047 +       } b;
16048 +} doepint_data_t;
16049 +
16050 +
16051 +/*!
16052 +  \brief Bit fields in the Device All EP Interrupt Registers.
16053 + */
16054 +typedef union daint_data
16055 +{
16056 +       uint32_t d32;
16057 +       struct
16058 +       {
16059 +               unsigned out : 16; /*!< 31-16 OUT Endpoint bits */
16060 +               unsigned in  : 16; /*!< 15-00 IN Endpoint bits */
16061 +       } eps;
16062 +       struct
16063 +       {
16064 +               /** OUT Endpoint bits */
16065 +               unsigned outep15 : 1;
16066 +               unsigned outep14 : 1;
16067 +               unsigned outep13 : 1;
16068 +               unsigned outep12 : 1;
16069 +               unsigned outep11 : 1;
16070 +               unsigned outep10 : 1;
16071 +               unsigned outep09 : 1;
16072 +               unsigned outep08 : 1;
16073 +               unsigned outep07 : 1;
16074 +               unsigned outep06 : 1;
16075 +               unsigned outep05 : 1;
16076 +               unsigned outep04 : 1;
16077 +               unsigned outep03 : 1;
16078 +               unsigned outep02 : 1;
16079 +               unsigned outep01 : 1;
16080 +               unsigned outep00 : 1;
16081 +               /** IN Endpoint bits */
16082 +               unsigned inep15 : 1;
16083 +               unsigned inep14 : 1;
16084 +               unsigned inep13 : 1;
16085 +               unsigned inep12 : 1;
16086 +               unsigned inep11 : 1;
16087 +               unsigned inep10 : 1;
16088 +               unsigned inep09 : 1;
16089 +               unsigned inep08 : 1;
16090 +               unsigned inep07 : 1;
16091 +               unsigned inep06 : 1;
16092 +               unsigned inep05 : 1;
16093 +               unsigned inep04 : 1;
16094 +               unsigned inep03 : 1;
16095 +               unsigned inep02 : 1;
16096 +               unsigned inep01 : 1;
16097 +               unsigned inep00 : 1;
16098 +       } ep;
16099 +} daint_data_t;
16100 +
16101 +
16102 +/*!
16103 +  \brief Bit fields in the Device IN Token Queue Read Registers.
16104 + */
16105 +typedef union dtknq1_data
16106 +{
16107 +       uint32_t d32;
16108 +       struct
16109 +       {
16110 +               unsigned epnums0_5     :24; /*!< 31-08 EP Numbers of IN Tokens 0 ... 4 */
16111 +               unsigned wrap_bit      : 1; /*!< 07    write pointer has wrapped */
16112 +               unsigned reserved05_06 : 2;
16113 +               unsigned intknwptr     : 5; /*!< 04-00 In Token Queue Write Pointer */
16114 +       }b;
16115 +} dtknq1_data_t;
16116 +
16117 +
16118 +/*!
16119 +  \brief Bit fields in Threshold control Register
16120 + */
16121 +typedef union dthrctl_data
16122 +{
16123 +       uint32_t d32;
16124 +       struct
16125 +       {
16126 +               unsigned reserved26_31  : 6;
16127 +               unsigned rx_thr_len     : 9; /*!< 25-17 Rx Thr. Length */
16128 +               unsigned rx_thr_en      : 1; /*!< 16    Rx Thr. Enable */
16129 +               unsigned reserved11_15  : 5;
16130 +               unsigned tx_thr_len     : 9; /*!< 10-02 Tx Thr. Length */
16131 +               unsigned iso_thr_en     : 1; /*!< 01    ISO Tx Thr. Enable */
16132 +               unsigned non_iso_thr_en : 1; /*!< 00    non ISO Tx Thr. Enable */
16133 +       } b;
16134 +} dthrctl_data_t;
16135 +
16136 +/*@}*//*IFXUSB_CSR_DEVICE_GLOBAL_REG*/
16137 +
16138 +/****************************************************************************/
16139 +
16140 +/*!
16141 +  \addtogroup IFXUSB_CSR_DEVICE_EP_REG
16142 + */
16143 +/*@{*/
16144 +
16145 +/*!
16146 +  \struct ifxusb_dev_in_ep_regs
16147 +  \brief Device Logical IN Endpoint-Specific Registers.
16148 +   There will be one set of endpoint registers per logical endpoint
16149 +   implemented.
16150 +   each EP's IN EP Register are offset at :
16151 +              900h + * (ep_num * 20h)
16152 + */
16153 +
16154 +typedef struct ifxusb_dev_in_ep_regs
16155 +{
16156 +       volatile uint32_t diepctl;    /*!< 00h: Endpoint Control Register */
16157 +       uint32_t reserved04;          /*!< 04h: */
16158 +       volatile uint32_t diepint;    /*!< 08h: Endpoint Interrupt Register */
16159 +       uint32_t reserved0C;          /*!< 0Ch: */
16160 +       volatile uint32_t dieptsiz;   /*!< 10h: Endpoint Transfer Size Register.*/
16161 +       volatile uint32_t diepdma;    /*!< 14h: Endpoint DMA Address Register. */
16162 +       volatile uint32_t dtxfsts;    /*!< 18h: Endpoint Transmit FIFO Status Register. */
16163 +       volatile uint32_t diepdmab;   /*!< 1Ch: Endpoint DMA Buffer Register. */
16164 +} ifxusb_dev_in_ep_regs_t;
16165 +
16166 +/*!
16167 +  \brief Device Logical OUT Endpoint-Specific Registers.
16168 +   There will be one set of endpoint registers per logical endpoint
16169 +   implemented.
16170 +   each EP's OUT EP Register are offset at :
16171 +              B00h + * (ep_num * 20h) + 00h
16172 + */
16173 +typedef struct ifxusb_dev_out_ep_regs
16174 +{
16175 +       volatile uint32_t doepctl;    /*!< 00h: Endpoint Control Register */
16176 +       volatile uint32_t doepfn;     /*!< 04h: Endpoint Frame number Register */
16177 +       volatile uint32_t doepint;    /*!< 08h: Endpoint Interrupt Register */
16178 +       uint32_t reserved0C;          /*!< 0Ch: */
16179 +       volatile uint32_t doeptsiz;   /*!< 10h: Endpoint Transfer Size Register.*/
16180 +       volatile uint32_t doepdma;    /*!< 14h: Endpoint DMA Address Register. */
16181 +       uint32_t reserved18;          /*!< 18h: */
16182 +       volatile uint32_t doepdmab;   /*!< 1Ch: Endpoint DMA Buffer Register. */
16183 +} ifxusb_dev_out_ep_regs_t;
16184 +
16185 +
16186 +/*!
16187 +  \brief Bit fields in the Device EP Control
16188 +  Register.
16189 + */
16190 +typedef union depctl_data
16191 +{
16192 +       uint32_t d32;
16193 +       struct
16194 +       {
16195 +               unsigned epena     : 1; /*!< 31    Endpoint Enable */
16196 +               unsigned epdis     : 1; /*!< 30    Endpoint Disable */
16197 +               unsigned setd1pid  : 1; /*!< 29    Set DATA1 PID (INTR/Bulk IN and OUT endpoints) */
16198 +               unsigned setd0pid  : 1; /*!< 28    Set DATA0 PID (INTR/Bulk IN and OUT endpoints) */
16199 +               unsigned snak      : 1; /*!< 27    Set NAK */
16200 +               unsigned cnak      : 1; /*!< 26    Clear NAK */
16201 +               unsigned txfnum    : 4; /*!< 25-22 Tx Fifo Number */
16202 +               unsigned stall     : 1; /*!< 21    Stall Handshake */
16203 +               unsigned snp       : 1; /*!< 20    Snoop Mode */
16204 +               unsigned eptype    : 2; /*!< 19-18 Endpoint Type
16205 +                                                 0: Control
16206 +                                                 1: Isochronous
16207 +                                                 2: Bulk
16208 +                                                 3: Interrupt
16209 +                                        */
16210 +               unsigned naksts    : 1; /*!< 17    NAK Status */
16211 +               unsigned dpid      : 1; /*!< 16    Endpoint DPID (INTR/Bulk IN and OUT endpoints) */
16212 +               unsigned usbactep  : 1; /*!< 15    USB Active Endpoint */
16213 +               unsigned nextep    : 4; /*!< 14-11 Next Endpoint */
16214 +               unsigned mps       :11; /*!< 10-00 Maximum Packet Size */
16215 +                       #define IFXUSB_DEP0CTL_MPS_64   0
16216 +                       #define IFXUSB_DEP0CTL_MPS_32   1
16217 +                       #define IFXUSB_DEP0CTL_MPS_16   2
16218 +                       #define IFXUSB_DEP0CTL_MPS_8    3
16219 +       } b;
16220 +} depctl_data_t;
16221 +
16222 +
16223 +/*!
16224 +  \brief Bit fields in the Device EP Transfer Size Register. (EP0 and EPn)
16225 + */
16226 +typedef union deptsiz_data
16227 +{
16228 +       uint32_t d32;
16229 +       struct
16230 +       {
16231 +               unsigned reserved31    : 1;
16232 +               unsigned supcnt        : 2; /*!< 30-29 Setup Packet Count */
16233 +               unsigned reserved20_28 : 9;
16234 +               unsigned pktcnt        : 1; /*!< 19    Packet Count */
16235 +               unsigned reserved7_18  :12;
16236 +               unsigned xfersize      : 7; /*!< 06-00 Transfer size */
16237 +       }b0;
16238 +       struct
16239 +       {
16240 +               unsigned reserved      : 1;
16241 +               unsigned mc            : 2; /*!< 30-29 Multi Count */
16242 +               unsigned pktcnt        :10; /*!< 28-19 Packet Count */
16243 +               unsigned xfersize      :19; /*!< 18-00 Transfer size */
16244 +       } b;
16245 +} deptsiz_data_t;
16246 +
16247 +/*@}*//*IFXUSB_CSR_DEVICE_EP_REG*/
16248 +/****************************************************************************/
16249 +
16250 +/*!
16251 +  \addtogroup IFXUSB_CSR_DEVICE_DMA_DESC
16252 + */
16253 +/*@{*/
16254 +/*!
16255 +  \struct desc_sts_data
16256 +  \brief Bit fields in the DMA Descriptor status quadlet.
16257 + */
16258 +typedef union desc_sts_data
16259 +{
16260 +       struct
16261 +       {
16262 +               unsigned bs            : 2; /*!< 31-30 Buffer Status */
16263 +                       #define BS_HOST_READY   0x0
16264 +                       #define BS_DMA_BUSY             0x1
16265 +                       #define BS_DMA_DONE             0x2
16266 +                       #define BS_HOST_BUSY    0x3
16267 +               unsigned sts           : 2; /*!< 29-28 Receive/Trasmit Status */
16268 +                       #define RTS_SUCCESS             0x0
16269 +                       #define RTS_BUFFLUSH    0x1
16270 +                       #define RTS_RESERVED    0x2
16271 +                       #define RTS_BUFERR              0x3
16272 +               unsigned l             : 1; /*!< 27    Last */
16273 +               unsigned sp            : 1; /*!< 26    Short Packet */
16274 +               unsigned ioc           : 1; /*!< 25    Interrupt On Complete */
16275 +               unsigned sr            : 1; /*!< 24    Setup Packet received */
16276 +               unsigned mtrf          : 1; /*!< 23    Multiple Transfer */
16277 +               unsigned reserved16_22 : 7;
16278 +               unsigned bytes         :16; /*!< 15-00 Transfer size in bytes */
16279 +       } b;
16280 +       uint32_t d32;    /*!< DMA Descriptor data buffer pointer */
16281 +} desc_sts_data_t;
16282 +
16283 +/*@}*//*IFXUSB_CSR_DEVICE_DMA_DESC*/
16284 +/****************************************************************************/
16285 +
16286 +/*!
16287 +  \addtogroup IFXUSB_CSR_HOST_GLOBAL_REG
16288 + */
16289 +/*@{*/
16290 +/*!
16291 + \struct ifxusb_host_global_regs
16292 + \brief IFXUSB Host Mode Global registers. Offsets 400h-7FFh
16293 +        The ifxusb_host_global_regs structure defines the size
16294 +        and relative field offsets for the Host Global registers.
16295 +        These registers are visible only in Host mode and must not be
16296 +        accessed in Device mode, as the results are unknown.
16297 + */
16298 +typedef struct ifxusb_host_global_regs
16299 +{
16300 +       volatile uint32_t hcfg;      /*!< 400h Host Configuration Register. */
16301 +       volatile uint32_t hfir;      /*!< 404h Host Frame Interval Register. */
16302 +       volatile uint32_t hfnum;     /*!< 408h Host Frame Number / Frame Remaining Register. */
16303 +       uint32_t reserved40C;
16304 +       volatile uint32_t hptxsts;   /*!< 410h Host Periodic Transmit FIFO/ Queue Status Register. */
16305 +       volatile uint32_t haint;     /*!< 414h Host All Channels Interrupt Register. */
16306 +       volatile uint32_t haintmsk;  /*!< 418h Host All Channels Interrupt Mask Register. */
16307 +} ifxusb_host_global_regs_t;
16308 +
16309 +/*!
16310 +  \brief Bit fields in the Host Configuration Register.
16311 + */
16312 +typedef union hcfg_data
16313 +{
16314 +       uint32_t d32;
16315 +       struct
16316 +       {
16317 +               unsigned reserved31_03 :29;
16318 +               unsigned fslssupp      : 1; /*!< 02    FS/LS Only Support */
16319 +               unsigned fslspclksel   : 2; /*!< 01-00 FS/LS Phy Clock Select */
16320 +                       #define IFXUSB_HCFG_30_60_MHZ 0
16321 +                       #define IFXUSB_HCFG_48_MHZ    1
16322 +                       #define IFXUSB_HCFG_6_MHZ     2
16323 +       } b;
16324 +} hcfg_data_t;
16325 +
16326 +/*!
16327 +  \brief Bit fields in the Host Frame Interval Register.
16328 + */
16329 +typedef union hfir_data
16330 +{
16331 +       uint32_t d32;
16332 +       struct
16333 +       {
16334 +               unsigned reserved : 16;
16335 +               unsigned frint    : 16; /*!< 15-00 Frame Interval */
16336 +       } b;
16337 +} hfir_data_t;
16338 +
16339 +/*!
16340 + \brief Bit fields in the Host Frame Time Remaing/Number Register.
16341 + */
16342 +typedef union hfnum_data
16343 +{
16344 +       uint32_t d32;
16345 +       struct
16346 +       {
16347 +               unsigned frrem : 16; /*!< 31-16 Frame Time Remaining */
16348 +               unsigned frnum : 16; /*!< 15-00 Frame Number*/
16349 +                       #define IFXUSB_HFNUM_MAX_FRNUM 0x3FFF
16350 +       } b;
16351 +} hfnum_data_t;
16352 +
16353 +/*!
16354 +  \brief Bit fields in the Host Periodic Transmit FIFO/Queue Status Register
16355 + */
16356 +typedef union hptxsts_data
16357 +{
16358 +       /** raw register data */
16359 +       uint32_t d32;
16360 +       struct
16361 +       {
16362 +               /** Top of the Periodic Transmit Request Queue
16363 +                *  - bit 24 - Terminate (last entry for the selected channel)
16364 +                */
16365 +               unsigned ptxqtop_odd       : 1; /*!< 31    Top of the Periodic Transmit Request
16366 +                                                         Queue Odd/even microframe*/
16367 +               unsigned ptxqtop_chnum     : 4; /*!< 30-27 Top of the Periodic Transmit Request
16368 +                                                         Channel Number */
16369 +               unsigned ptxqtop_token     : 2; /*!< 26-25 Top of the Periodic Transmit Request
16370 +                                                         Token Type
16371 +                                                         0 - Zero length
16372 +                                                         1 - Ping
16373 +                                                         2 - Disable
16374 +                                                */
16375 +               unsigned ptxqtop_terminate : 1; /*!< 24    Top of the Periodic Transmit Request
16376 +                                                         Terminate (last entry for the selected channel)*/
16377 +               unsigned ptxqspcavail      : 8; /*!< 23-16 Periodic Transmit Request Queue Space Available */
16378 +               unsigned ptxfspcavail      :16; /*!< 15-00 Periodic Transmit Data FIFO Space Available */
16379 +       } b;
16380 +} hptxsts_data_t;
16381 +
16382 +/*!
16383 +  \brief Bit fields in the Host Port Control and Status Register.
16384 + */
16385 +typedef union hprt0_data
16386 +{
16387 +       uint32_t d32;
16388 +       struct
16389 +       {
16390 +               unsigned reserved19_31   :13;
16391 +               unsigned prtspd          : 2; /*!< 18-17 Port Speed */
16392 +                       #define IFXUSB_HPRT0_PRTSPD_HIGH_SPEED 0
16393 +                       #define IFXUSB_HPRT0_PRTSPD_FULL_SPEED 1
16394 +                       #define IFXUSB_HPRT0_PRTSPD_LOW_SPEED  2
16395 +               unsigned prttstctl       : 4; /*!< 16-13 Port Test Control */
16396 +               unsigned prtpwr          : 1; /*!< 12    Port Power */
16397 +               unsigned prtlnsts        : 2; /*!< 11-10 Port Line Status */
16398 +               unsigned reserved9       : 1;
16399 +               unsigned prtrst          : 1; /*!< 08    Port Reset */
16400 +               unsigned prtsusp         : 1; /*!< 07    Port Suspend */
16401 +               unsigned prtres          : 1; /*!< 06    Port Resume */
16402 +               unsigned prtovrcurrchng  : 1; /*!< 05    Port Overcurrent Change */
16403 +               unsigned prtovrcurract   : 1; /*!< 04    Port Overcurrent Active */
16404 +               unsigned prtenchng       : 1; /*!< 03    Port Enable/Disable Change */
16405 +               unsigned prtena          : 1; /*!< 02    Port Enable */
16406 +               unsigned prtconndet      : 1; /*!< 01    Port Connect Detected */
16407 +               unsigned prtconnsts      : 1; /*!< 00    Port Connect Status */
16408 +       }b;
16409 +} hprt0_data_t;
16410 +
16411 +/*!
16412 +  \brief Bit fields in the Host All Interrupt Register.
16413 + */
16414 +typedef union haint_data
16415 +{
16416 +       uint32_t d32;
16417 +       struct
16418 +       {
16419 +               unsigned reserved : 16;
16420 +               unsigned ch15 : 1;
16421 +               unsigned ch14 : 1;
16422 +               unsigned ch13 : 1;
16423 +               unsigned ch12 : 1;
16424 +               unsigned ch11 : 1;
16425 +               unsigned ch10 : 1;
16426 +               unsigned ch09 : 1;
16427 +               unsigned ch08 : 1;
16428 +               unsigned ch07 : 1;
16429 +               unsigned ch06 : 1;
16430 +               unsigned ch05 : 1;
16431 +               unsigned ch04 : 1;
16432 +               unsigned ch03 : 1;
16433 +               unsigned ch02 : 1;
16434 +               unsigned ch01 : 1;
16435 +               unsigned ch00 : 1;
16436 +       } b;
16437 +       struct
16438 +       {
16439 +               unsigned reserved : 16;
16440 +               unsigned chint    : 16;
16441 +       } b2;
16442 +} haint_data_t;
16443 +/*@}*//*IFXUSB_CSR_HOST_GLOBAL_REG*/
16444 +/****************************************************************************/
16445 +/*!
16446 +  \addtogroup IFXUSB_CSR_HOST_HC_REG
16447 + */
16448 +/*@{*/
16449 +/*!
16450 +  \brief Host Channel Specific Registers
16451 +   There will be one set of hc registers per host channelimplemented.
16452 +   each HC's Register are offset at :
16453 +              500h + * (hc_num * 20h)
16454 + */
16455 +typedef struct ifxusb_hc_regs
16456 +{
16457 +       volatile uint32_t hcchar;   /*!< 00h Host Channel Characteristic Register.*/
16458 +       volatile uint32_t hcsplt;   /*!< 04h Host Channel Split Control Register.*/
16459 +       volatile uint32_t hcint;    /*!< 08h Host Channel Interrupt Register. */
16460 +       volatile uint32_t hcintmsk; /*!< 0Ch Host Channel Interrupt Mask Register. */
16461 +       volatile uint32_t hctsiz;   /*!< 10h Host Channel Transfer Size Register. */
16462 +       volatile uint32_t hcdma;    /*!< 14h Host Channel DMA Address Register. */
16463 +       uint32_t reserved[2];       /*!< 18h Reserved.   */
16464 +} ifxusb_hc_regs_t;
16465 +
16466 +
16467 +/*!
16468 +  \brief Bit fields in the Host Channel Characteristics Register.
16469 + */
16470 +typedef union hcchar_data
16471 +{
16472 +       uint32_t d32;
16473 +       struct
16474 +       {
16475 +               unsigned chen      : 1; /*!< 31    Channel enable */
16476 +               unsigned chdis     : 1; /*!< 30    Channel disable */
16477 +               unsigned oddfrm    : 1; /*!< 29    Frame to transmit periodic transaction */
16478 +               unsigned devaddr   : 7; /*!< 28-22 Device address */
16479 +               unsigned multicnt  : 2; /*!< 21-20 Packets per frame for periodic transfers */
16480 +               unsigned eptype    : 2; /*!< 19-18 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
16481 +               unsigned lspddev   : 1; /*!< 17    0: Full/high speed device, 1: Low speed device */
16482 +               unsigned reserved  : 1;
16483 +               unsigned epdir     : 1; /*!< 15    0: OUT, 1: IN */
16484 +               unsigned epnum     : 4; /*!< 14-11 Endpoint number */
16485 +               unsigned mps       :11; /*!< 10-00 Maximum packet size in bytes */
16486 +       } b;
16487 +} hcchar_data_t;
16488 +
16489 +/*!
16490 +  \brief Bit fields in the Host Channel Split Control Register
16491 + */
16492 +typedef union hcsplt_data
16493 +{
16494 +       uint32_t d32;
16495 +       struct
16496 +       {
16497 +               unsigned spltena  : 1; /*!< 31    Split Enble */
16498 +               unsigned reserved :14;
16499 +               unsigned compsplt : 1; /*!< 16    Do Complete Split */
16500 +               unsigned xactpos  : 2; /*!< 15-14 Transaction Position */
16501 +                       #define IFXUSB_HCSPLIT_XACTPOS_MID 0
16502 +                       #define IFXUSB_HCSPLIT_XACTPOS_END 1
16503 +                       #define IFXUSB_HCSPLIT_XACTPOS_BEGIN 2
16504 +                       #define IFXUSB_HCSPLIT_XACTPOS_ALL 3
16505 +               unsigned hubaddr  : 7; /*!< 13-07 Hub Address */
16506 +               unsigned prtaddr  : 7; /*!< 06-00 Port Address */
16507 +       } b;
16508 +} hcsplt_data_t;
16509 +
16510 +/*!
16511 +  \brief Bit fields in the Host Interrupt Register.
16512 + */
16513 +typedef union hcint_data
16514 +{
16515 +       uint32_t d32;
16516 +       struct
16517 +       {
16518 +               unsigned reserved   :21;
16519 +               unsigned datatglerr : 1; /*!< 10 Data Toggle Error */
16520 +               unsigned frmovrun   : 1; /*!< 09 Frame Overrun */
16521 +               unsigned bblerr     : 1; /*!< 08 Babble Error */
16522 +               unsigned xacterr    : 1; /*!< 07 Transaction Err */
16523 +               unsigned nyet       : 1; /*!< 06 NYET Response Received */
16524 +               unsigned ack        : 1; /*!< 05 ACK Response Received */
16525 +               unsigned nak        : 1; /*!< 04 NAK Response Received */
16526 +               unsigned stall      : 1; /*!< 03 STALL Response Received */
16527 +               unsigned ahberr     : 1; /*!< 02 AHB Error */
16528 +               unsigned chhltd     : 1; /*!< 01 Channel Halted */
16529 +               unsigned xfercomp   : 1; /*!< 00 Channel Halted */
16530 +       }b;
16531 +} hcint_data_t;
16532 +
16533 +
16534 +/*!
16535 + \brief Bit fields in the Host Channel Transfer Size
16536 +  Register.
16537 + */
16538 +typedef union hctsiz_data
16539 +{
16540 +       uint32_t d32;
16541 +       struct
16542 +       {
16543 +               /** */
16544 +               unsigned dopng     : 1; /*!< 31    Do PING protocol when 1  */
16545 +               /**
16546 +                * Packet ID for next data packet
16547 +                * 0: DATA0
16548 +                * 1: DATA2
16549 +                * 2: DATA1
16550 +                * 3: MDATA (non-Control), SETUP (Control)
16551 +                */
16552 +               unsigned pid       : 2; /*!< 30-29 Packet ID for next data packet
16553 +                                                 0: DATA0
16554 +                                                 1: DATA2
16555 +                                                 2: DATA1
16556 +                                                 3: MDATA (non-Control), SETUP (Control)
16557 +                                        */
16558 +                       #define IFXUSB_HCTSIZ_DATA0 0
16559 +                       #define IFXUSB_HCTSIZ_DATA1 2
16560 +                       #define IFXUSB_HCTSIZ_DATA2 1
16561 +                       #define IFXUSB_HCTSIZ_MDATA 3
16562 +                       #define IFXUSB_HCTSIZ_SETUP 3
16563 +               unsigned pktcnt    :10; /*!< 28-19 Data packets to transfer */
16564 +               unsigned xfersize  :19; /*!< 18-00 Total transfer size in bytes */
16565 +       }b;
16566 +} hctsiz_data_t;
16567 +
16568 +/*@}*//*IFXUSB_CSR_HOST_HC_REG*/
16569 +
16570 +/****************************************************************************/
16571 +
16572 +/*!
16573 +  \addtogroup IFXUSB_CSR_PWR_CLK_GATING_REG
16574 + */
16575 +/*@{*/
16576 +/*!
16577 +  \brief Bit fields in the Power and Clock Gating Control Register
16578 + */
16579 +typedef union pcgcctl_data
16580 +{
16581 +       uint32_t d32;
16582 +       struct
16583 +       {
16584 +               unsigned reserved      : 27;
16585 +               unsigned physuspended  : 1; /*!< 04 PHY Suspended */
16586 +               unsigned rstpdwnmodule : 1; /*!< 03 Reset Power Down Modules */
16587 +               unsigned pwrclmp       : 1; /*!< 02 Power Clamp */
16588 +               unsigned gatehclk      : 1; /*!< 01 Gate Hclk */
16589 +               unsigned stoppclk      : 1; /*!< 00 Stop Pclk */
16590 +       } b;
16591 +} pcgcctl_data_t;
16592 +/*@}*//*IFXUSB_CSR_PWR_CLK_GATING_REG*/
16593 +
16594 +/****************************************************************************/
16595 +
16596 +#endif //__IFXUSB_REGS_H__
16597 --- /dev/null
16598 +++ b/drivers/usb/ifxhcd/ifxusb_version.h
16599 @@ -0,0 +1,5 @@
16600 +
16601 +#ifndef IFXUSB_VERSION
16602 +#define IFXUSB_VERSION "3.0alpha B100312"
16603 +#endif
16604 +