target/linux/lantiq/patches-3.2/0033-NET-MIPS-lantiq-convert-etop-driver-to-clkdev-api.patch

   1 From c96f5cae05788c326f63c8b769e53c6e15215e70 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 8 Mar 2012 11:23:00 +0100
   4 Subject: [PATCH 33/70] NET: MIPS: lantiq: convert etop driver to clkdev api
   5
   6 Update from old pmu_{dis,en}able() to ckldev api.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 Cc: netdev@vger.kernel.org
  10 ---
  11  drivers/net/ethernet/lantiq_etop.c |   49 ++++++++++++++++++++++++++++++-----
  12  1 files changed, 42 insertions(+), 7 deletions(-)
  13
  14 --- a/drivers/net/ethernet/lantiq_etop.c
  15 +++ b/drivers/net/ethernet/lantiq_etop.c
  16 @@ -36,6 +36,7 @@
  17  #include <linux/io.h>
  18  #include <linux/dma-mapping.h>
  19  #include <linux/module.h>
  20 +#include <linux/clk.h>
  21
  22  #include <asm/checksum.h>
  23
  24 @@ -147,6 +148,11 @@ struct ltq_etop_priv {
  25         int tx_free[MAX_DMA_CHAN >> 1];
  26
  27         spinlock_t lock;
  28 +
  29 +       struct clk *clk_ppe;
  30 +       struct clk *clk_switch;
  31 +       struct clk *clk_ephy;
  32 +       struct clk *clk_ephycgu;
  33  };
  34
  35  static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
  36 @@ -280,16 +286,27 @@ ltq_etop_hw_exit(struct net_device *dev)
  37         struct ltq_etop_priv *priv = netdev_priv(dev);
  38         int i;
  39
  40 -       ltq_pmu_disable(PMU_PPE);
  41 +       clk_disable(priv->clk_ppe);
  42 +
  43 +       if (ltq_has_gbit())
  44 +               clk_disable(priv->clk_switch);
  45 +
  46 +       if (ltq_is_ase()) {
  47 +               clk_disable(priv->clk_ephy);
  48 +               clk_disable(priv->clk_ephycgu);
  49 +       }
  50 +
  51         for (i = 0; i < MAX_DMA_CHAN; i++)
  52                 if (IS_TX(i) || IS_RX(i))
  53                         ltq_etop_free_channel(dev, &priv->ch[i]);
  54  }
  55
  56  static void
  57 -ltq_etop_gbit_init(void)
  58 +ltq_etop_gbit_init(struct net_device *dev)
  59  {
  60 -       ltq_pmu_enable(PMU_SWITCH);
  61 +       struct ltq_etop_priv *priv = netdev_priv(dev);
  62 +
  63 +       clk_enable(priv->clk_switch);
  64
  65         ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
  66         /** Disable MDIO auto polling mode */
  67 @@ -312,10 +329,10 @@ ltq_etop_hw_init(struct net_device *dev)
  68         int err = 0;
  69         int i;
  70
  71 -       ltq_pmu_enable(PMU_PPE);
  72 +       clk_enable(priv->clk_ppe);
  73
  74         if (ltq_has_gbit()) {
  75 -               ltq_etop_gbit_init();
  76 +               ltq_etop_gbit_init(dev);
  77                 /* force the etops link to the gbit to MII */
  78                 mii_mode = PHY_INTERFACE_MODE_MII;
  79         }
  80 @@ -333,11 +350,11 @@ ltq_etop_hw_init(struct net_device *dev)
  81
  82         default:
  83                 if (ltq_is_ase()) {
  84 -                       ltq_pmu_enable(PMU_EPHY);
  85 +                       clk_enable(priv->clk_ephy);
  86                         /* disable external MII */
  87                         ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
  88                         /* enable clock for internal PHY */
  89 -                       ltq_cgu_enable(CGU_EPHY);
  90 +                       clk_enable(priv->clk_ephycgu);
  91                         /* we need to write this magic to the internal phy to
  92                            make it work */
  93                         ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
  94 @@ -880,6 +897,24 @@ ltq_etop_probe(struct platform_device *p
  95         priv->res = res;
  96         priv->pldata = dev_get_platdata(&pdev->dev);
  97         priv->netdev = dev;
  98 +
  99 +       priv->clk_ppe = clk_get(&pdev->dev, NULL);
 100 +       if (IS_ERR(priv->clk_ppe))
 101 +               return PTR_ERR(priv->clk_ppe);
 102 +       if (ltq_has_gbit()) {
 103 +               priv->clk_switch = clk_get(&pdev->dev, "switch");
 104 +               if (IS_ERR(priv->clk_switch))
 105 +                       return PTR_ERR(priv->clk_switch);
 106 +       }
 107 +       if (ltq_is_ase()) {
 108 +               priv->clk_ephy = clk_get(&pdev->dev, "ephy");
 109 +               if (IS_ERR(priv->clk_ephy))
 110 +                       return PTR_ERR(priv->clk_ephy);
 111 +               priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
 112 +               if (IS_ERR(priv->clk_ephycgu))
 113 +                       return PTR_ERR(priv->clk_ephycgu);
 114 +       }
 115 +
 116         spin_lock_init(&priv->lock);
 117
 118         for (i = 0; i < MAX_DMA_CHAN; i++) {