target/linux/lantiq/patches-3.2/0011-MIPS-lantiq-fix-early-printk.patch

   1 From 68e9e86dda22c491e5e3c44271a91aefcf636434 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 20 Aug 2011 18:55:13 +0200
   4 Subject: [PATCH 11/70] MIPS: lantiq: fix early printk
   5
   6 The code was using a 32bit write operations in the early_printk code. This
   7 resulted in 3 zero bytes also being written to the serial port. This patch
   8 changes the memory access to 8bit.
   9
  10 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 ---
  13  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    6 ++++++
  14  arch/mips/lantiq/early_printk.c                    |   14 ++++++++------
  15  2 files changed, 14 insertions(+), 6 deletions(-)
  16
  17 diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  18 index 87f6d24..e31f52d 100644
  19 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  20 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  21 @@ -34,6 +34,12 @@
  22  #define LTQ_ASC1_BASE_ADDR     0x1E100C00
  23  #define LTQ_ASC_SIZE           0x400
  24
  25 +/*
  26 + * during early_printk no ioremap is possible
  27 + * lets use KSEG1 instead
  28 + */
  29 +#define LTQ_EARLY_ASC          KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
  30 +
  31  /* RCU - reset control unit */
  32  #define LTQ_RCU_BASE_ADDR      0x1F203000
  33  #define LTQ_RCU_SIZE           0x1000
  34 diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c
  35 index 972e05f..5089075 100644
  36 --- a/arch/mips/lantiq/early_printk.c
  37 +++ b/arch/mips/lantiq/early_printk.c
  38 @@ -12,11 +12,13 @@
  39  #include <lantiq.h>
  40  #include <lantiq_soc.h>
  41
  42 -/* no ioremap possible at this early stage, lets use KSEG1 instead  */
  43 -#define LTQ_ASC_BASE   KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
  44  #define ASC_BUF                1024
  45 -#define LTQ_ASC_FSTAT  ((u32 *)(LTQ_ASC_BASE + 0x0048))
  46 -#define LTQ_ASC_TBUF   ((u32 *)(LTQ_ASC_BASE + 0x0020))
  47 +#define LTQ_ASC_FSTAT  ((u32 *)(LTQ_EARLY_ASC + 0x0048))
  48 +#ifdef __BIG_ENDIAN
  49 +#define LTQ_ASC_TBUF   ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3))
  50 +#else
  51 +#define LTQ_ASC_TBUF   ((u32 *)(LTQ_EARLY_ASC + 0x0020))
  52 +#endif
  53  #define TXMASK         0x3F00
  54  #define TXOFFSET       8
  55
  56 @@ -27,7 +29,7 @@ void prom_putchar(char c)
  57         local_irq_save(flags);
  58         do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
  59         if (c == '\n')
  60 -               ltq_w32('\r', LTQ_ASC_TBUF);
  61 -       ltq_w32(c, LTQ_ASC_TBUF);
  62 +               ltq_w8('\r', LTQ_ASC_TBUF);
  63 +       ltq_w8(c, LTQ_ASC_TBUF);
  64         local_irq_restore(flags);
  65  }
  66 --
  67 1.7.7.1
  68