target/linux/lantiq/patches-3.2/0008-MIPS-lantiq-add-basic-support-for-FALC-ON.patch

   1 From d54a53bc8bc25bf2f9076013f89b30cb9103f99f Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 11 Aug 2011 14:33:04 +0200
   4 Subject: [PATCH 08/70] MIPS: lantiq: add basic support for FALC-ON
   5
   6 Adds support for the FALC-ON SoC. This SoC is from the FTTH/GPON SoC family.
   7
   8 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  .../include/asm/mach-lantiq/falcon/falcon_irq.h    |  268 ++++++++++++++++++++
  12  arch/mips/include/asm/mach-lantiq/falcon/irq.h     |   18 ++
  13  .../include/asm/mach-lantiq/falcon/lantiq_soc.h    |  143 +++++++++++
  14  arch/mips/include/asm/mach-lantiq/lantiq.h         |    1 +
  15  arch/mips/lantiq/Kconfig                           |    4 +
  16  arch/mips/lantiq/Makefile                          |    1 +
  17  arch/mips/lantiq/Platform                          |    1 +
  18  arch/mips/lantiq/falcon/Makefile                   |    1 +
  19  arch/mips/lantiq/falcon/clk.c                      |   44 ++++
  20  arch/mips/lantiq/falcon/devices.c                  |   87 +++++++
  21  arch/mips/lantiq/falcon/devices.h                  |   18 ++
  22  arch/mips/lantiq/falcon/prom.c                     |   93 +++++++
  23  arch/mips/lantiq/falcon/reset.c                    |   87 +++++++
  24  arch/mips/lantiq/falcon/sysctrl.c                  |  183 +++++++++++++
  25  14 files changed, 949 insertions(+), 0 deletions(-)
  26  create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
  27  create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h
  28  create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
  29  create mode 100644 arch/mips/lantiq/falcon/Makefile
  30  create mode 100644 arch/mips/lantiq/falcon/clk.c
  31  create mode 100644 arch/mips/lantiq/falcon/devices.c
  32  create mode 100644 arch/mips/lantiq/falcon/devices.h
  33  create mode 100644 arch/mips/lantiq/falcon/prom.c
  34  create mode 100644 arch/mips/lantiq/falcon/reset.c
  35  create mode 100644 arch/mips/lantiq/falcon/sysctrl.c
  36
  37 diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
  38 new file mode 100644
  39 index 0000000..4dc6466
  40 --- /dev/null
  41 +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
  42 @@ -0,0 +1,268 @@
  43 +/*
  44 + *  This program is free software; you can redistribute it and/or modify it
  45 + *  under the terms of the GNU General Public License version 2 as published
  46 + *  by the Free Software Foundation.
  47 + *
  48 + *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
  49 + */
  50 +
  51 +#ifndef _FALCON_IRQ__
  52 +#define _FALCON_IRQ__
  53 +
  54 +#define INT_NUM_IRQ0                   8
  55 +#define INT_NUM_IM0_IRL0               (INT_NUM_IRQ0 + 0)
  56 +#define INT_NUM_IM1_IRL0               (INT_NUM_IM0_IRL0 + 32)
  57 +#define INT_NUM_IM2_IRL0               (INT_NUM_IM1_IRL0 + 32)
  58 +#define INT_NUM_IM3_IRL0               (INT_NUM_IM2_IRL0 + 32)
  59 +#define INT_NUM_IM4_IRL0               (INT_NUM_IM3_IRL0 + 32)
  60 +#define INT_NUM_EXTRA_START            (INT_NUM_IM4_IRL0 + 32)
  61 +#define INT_NUM_IM_OFFSET              (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
  62 +
  63 +#define MIPS_CPU_TIMER_IRQ                     7
  64 +
  65 +/* HOST IF Event Interrupt */
  66 +#define FALCON_IRQ_HOST                                (INT_NUM_IM0_IRL0 + 0)
  67 +/* HOST IF Mailbox0 Receive Interrupt */
  68 +#define FALCON_IRQ_HOST_MB0_RX                 (INT_NUM_IM0_IRL0 + 1)
  69 +/* HOST IF Mailbox0 Transmit Interrupt */
  70 +#define FALCON_IRQ_HOST_MB0_TX                 (INT_NUM_IM0_IRL0 + 2)
  71 +/* HOST IF Mailbox1 Receive Interrupt */
  72 +#define FALCON_IRQ_HOST_MB1_RX                 (INT_NUM_IM0_IRL0 + 3)
  73 +/* HOST IF Mailbox1 Transmit Interrupt */
  74 +#define FALCON_IRQ_HOST_MB1_TX                 (INT_NUM_IM0_IRL0 + 4)
  75 +/* I2C Last Single Data Transfer Request */
  76 +#define FALCON_IRQ_I2C_LSREQ                   (INT_NUM_IM0_IRL0 + 8)
  77 +/* I2C Single Data Transfer Request */
  78 +#define FALCON_IRQ_I2C_SREQ                    (INT_NUM_IM0_IRL0 + 9)
  79 +/* I2C Last Burst Data Transfer Request */
  80 +#define FALCON_IRQ_I2C_LBREQ                   (INT_NUM_IM0_IRL0 + 10)
  81 +/* I2C Burst Data Transfer Request */
  82 +#define FALCON_IRQ_I2C_BREQ                    (INT_NUM_IM0_IRL0 + 11)
  83 +/* I2C Error Interrupt */
  84 +#define FALCON_IRQ_I2C_I2C_ERR                 (INT_NUM_IM0_IRL0 + 12)
  85 +/* I2C Protocol Interrupt */
  86 +#define FALCON_IRQ_I2C_I2C_P                   (INT_NUM_IM0_IRL0 + 13)
  87 +/* SSC Transmit Interrupt */
  88 +#define FALCON_IRQ_SSC_T                       (INT_NUM_IM0_IRL0 + 14)
  89 +/* SSC Receive Interrupt */
  90 +#define FALCON_IRQ_SSC_R                       (INT_NUM_IM0_IRL0 + 15)
  91 +/* SSC Error Interrupt */
  92 +#define FALCON_IRQ_SSC_E                       (INT_NUM_IM0_IRL0 + 16)
  93 +/* SSC Frame Interrupt */
  94 +#define FALCON_IRQ_SSC_F                       (INT_NUM_IM0_IRL0 + 17)
  95 +/* Advanced Encryption Standard Interrupt */
  96 +#define FALCON_IRQ_AES_AES                     (INT_NUM_IM0_IRL0 + 27)
  97 +/* Secure Hash Algorithm Interrupt */
  98 +#define FALCON_IRQ_SHA_HASH                    (INT_NUM_IM0_IRL0 + 28)
  99 +/* PCM Receive Interrupt */
 100 +#define FALCON_IRQ_PCM_RX                      (INT_NUM_IM0_IRL0 + 29)
 101 +/* PCM Transmit Interrupt */
 102 +#define FALCON_IRQ_PCM_TX                      (INT_NUM_IM0_IRL0 + 30)
 103 +/* PCM Transmit Crash Interrupt */
 104 +#define FALCON_IRQ_PCM_HW2_CRASH               (INT_NUM_IM0_IRL0 + 31)
 105 +
 106 +/* EBU Serial Flash Command Error */
 107 +#define FALCON_IRQ_EBU_SF_CMDERR               (INT_NUM_IM1_IRL0 + 0)
 108 +/* EBU Serial Flash Command Overwrite Error */
 109 +#define FALCON_IRQ_EBU_SF_COVERR               (INT_NUM_IM1_IRL0 + 1)
 110 +/* EBU Serial Flash Busy */
 111 +#define FALCON_IRQ_EBU_SF_BUSY                 (INT_NUM_IM1_IRL0 + 2)
 112 +/* External Interrupt from GPIO P0 */
 113 +#define FALCON_IRQ_GPIO_P0                     (INT_NUM_IM1_IRL0 + 4)
 114 +/* External Interrupt from GPIO P1 */
 115 +#define FALCON_IRQ_GPIO_P1                     (INT_NUM_IM1_IRL0 + 5)
 116 +/* External Interrupt from GPIO P2 */
 117 +#define FALCON_IRQ_GPIO_P2                     (INT_NUM_IM1_IRL0 + 6)
 118 +/* External Interrupt from GPIO P3 */
 119 +#define FALCON_IRQ_GPIO_P3                     (INT_NUM_IM1_IRL0 + 7)
 120 +/* External Interrupt from GPIO P4 */
 121 +#define FALCON_IRQ_GPIO_P4                     (INT_NUM_IM1_IRL0 + 8)
 122 +/* 8kHz backup interrupt derived from core-PLL */
 123 +#define FALCON_IRQ_FSC_BKP                     (INT_NUM_IM1_IRL0 + 10)
 124 +/* FSC Timer Interrupt 0 */
 125 +#define FALCON_IRQ_FSCT_CMP0                   (INT_NUM_IM1_IRL0 + 11)
 126 +/* FSC Timer Interrupt 1 */
 127 +#define FALCON_IRQ_FSCT_CMP1                   (INT_NUM_IM1_IRL0 + 12)
 128 +/* 8kHz root interrupt derived from GPON interface */
 129 +#define FALCON_IRQ_FSC_ROOT                    (INT_NUM_IM1_IRL0 + 13)
 130 +/* Time of Day */
 131 +#define FALCON_IRQ_TOD                         (INT_NUM_IM1_IRL0 + 14)
 132 +/* PMA Interrupt from IntNode of the 200MHz Domain */
 133 +#define FALCON_IRQ_PMA_200M                    (INT_NUM_IM1_IRL0 + 15)
 134 +/* PMA Interrupt from IntNode of the TX Clk Domain */
 135 +#define FALCON_IRQ_PMA_TX                      (INT_NUM_IM1_IRL0 + 16)
 136 +/* PMA Interrupt from IntNode of the RX Clk Domain */
 137 +#define FALCON_IRQ_PMA_RX                      (INT_NUM_IM1_IRL0 + 17)
 138 +/* SYS1 Interrupt */
 139 +#define FALCON_IRQ_SYS1                                (INT_NUM_IM1_IRL0 + 20)
 140 +/* SYS GPE Interrupt */
 141 +#define FALCON_IRQ_SYS_GPE                     (INT_NUM_IM1_IRL0 + 21)
 142 +/* Watchdog Access Error Interrupt */
 143 +#define FALCON_IRQ_WDT_AEIR                    (INT_NUM_IM1_IRL0 + 24)
 144 +/* Watchdog Prewarning Interrupt */
 145 +#define FALCON_IRQ_WDT_PIR                     (INT_NUM_IM1_IRL0 + 25)
 146 +/* SBIU interrupt */
 147 +#define FALCON_IRQ_SBIU0                       (INT_NUM_IM1_IRL0 + 27)
 148 +/* FPI Bus Control Unit Interrupt */
 149 +#define FALCON_IRQ_BCU0                                (INT_NUM_IM1_IRL0 + 29)
 150 +/* DDR Controller Interrupt */
 151 +#define FALCON_IRQ_DDR                         (INT_NUM_IM1_IRL0 + 30)
 152 +/* Crossbar Error Interrupt */
 153 +#define FALCON_IRQ_XBAR_ERROR                  (INT_NUM_IM1_IRL0 + 31)
 154 +
 155 +/* ICTRLL 0 Interrupt */
 156 +#define FALCON_IRQ_ICTRLL0                     (INT_NUM_IM2_IRL0 + 0)
 157 +/* ICTRLL 1 Interrupt */
 158 +#define FALCON_IRQ_ICTRLL1                     (INT_NUM_IM2_IRL0 + 1)
 159 +/* ICTRLL 2 Interrupt */
 160 +#define FALCON_IRQ_ICTRLL2                     (INT_NUM_IM2_IRL0 + 2)
 161 +/* ICTRLL 3 Interrupt */
 162 +#define FALCON_IRQ_ICTRLL3                     (INT_NUM_IM2_IRL0 + 3)
 163 +/* OCTRLL 0 Interrupt */
 164 +#define FALCON_IRQ_OCTRLL0                     (INT_NUM_IM2_IRL0 + 4)
 165 +/* OCTRLL 1 Interrupt */
 166 +#define FALCON_IRQ_OCTRLL1                     (INT_NUM_IM2_IRL0 + 5)
 167 +/* OCTRLL 2 Interrupt */
 168 +#define FALCON_IRQ_OCTRLL2                     (INT_NUM_IM2_IRL0 + 6)
 169 +/* OCTRLL 3 Interrupt */
 170 +#define FALCON_IRQ_OCTRLL3                     (INT_NUM_IM2_IRL0 + 7)
 171 +/* OCTRLG Interrupt */
 172 +#define FALCON_IRQ_OCTRLG                      (INT_NUM_IM2_IRL0 + 9)
 173 +/* IQM Interrupt */
 174 +#define FALCON_IRQ_IQM                         (INT_NUM_IM2_IRL0 + 10)
 175 +/* FSQM Interrupt */
 176 +#define FALCON_IRQ_FSQM                                (INT_NUM_IM2_IRL0 + 11)
 177 +/* TMU Interrupt */
 178 +#define FALCON_IRQ_TMU                         (INT_NUM_IM2_IRL0 + 12)
 179 +/* LINK1 Interrupt */
 180 +#define FALCON_IRQ_LINK1                       (INT_NUM_IM2_IRL0 + 14)
 181 +/* ICTRLC 0 Interrupt */
 182 +#define FALCON_IRQ_ICTRLC0                     (INT_NUM_IM2_IRL0 + 16)
 183 +/* ICTRLC 1 Interrupt */
 184 +#define FALCON_IRQ_ICTRLC1                     (INT_NUM_IM2_IRL0 + 17)
 185 +/* OCTRLC Interrupt */
 186 +#define FALCON_IRQ_OCTRLC                      (INT_NUM_IM2_IRL0 + 18)
 187 +/* CONFIG Break Interrupt */
 188 +#define FALCON_IRQ_CONFIG_BREAK                        (INT_NUM_IM2_IRL0 + 19)
 189 +/* CONFIG Interrupt */
 190 +#define FALCON_IRQ_CONFIG                      (INT_NUM_IM2_IRL0 + 20)
 191 +/* Dispatcher Interrupt */
 192 +#define FALCON_IRQ_DISP                                (INT_NUM_IM2_IRL0 + 21)
 193 +/* TBM Interrupt */
 194 +#define FALCON_IRQ_TBM                         (INT_NUM_IM2_IRL0 + 22)
 195 +/* GTC Downstream Interrupt */
 196 +#define FALCON_IRQ_GTC_DS                      (INT_NUM_IM2_IRL0 + 29)
 197 +/* GTC Upstream Interrupt */
 198 +#define FALCON_IRQ_GTC_US                      (INT_NUM_IM2_IRL0 + 30)
 199 +/* EIM Interrupt */
 200 +#define FALCON_IRQ_EIM                         (INT_NUM_IM2_IRL0 + 31)
 201 +
 202 +/* ASC0 Transmit Interrupt */
 203 +#define FALCON_IRQ_ASC0_T                      (INT_NUM_IM3_IRL0 + 0)
 204 +/* ASC0 Receive Interrupt */
 205 +#define FALCON_IRQ_ASC0_R                      (INT_NUM_IM3_IRL0 + 1)
 206 +/* ASC0 Error Interrupt */
 207 +#define FALCON_IRQ_ASC0_E                      (INT_NUM_IM3_IRL0 + 2)
 208 +/* ASC0 Transmit Buffer Interrupt */
 209 +#define FALCON_IRQ_ASC0_TB                     (INT_NUM_IM3_IRL0 + 3)
 210 +/* ASC0 Autobaud Start Interrupt */
 211 +#define FALCON_IRQ_ASC0_ABST                   (INT_NUM_IM3_IRL0 + 4)
 212 +/* ASC0 Autobaud Detection Interrupt */
 213 +#define FALCON_IRQ_ASC0_ABDET                  (INT_NUM_IM3_IRL0 + 5)
 214 +/* ASC1 Modem Status Interrupt */
 215 +#define FALCON_IRQ_ASC0_MS                     (INT_NUM_IM3_IRL0 + 6)
 216 +/* ASC0 Soft Flow Control Interrupt */
 217 +#define FALCON_IRQ_ASC0_SFC                    (INT_NUM_IM3_IRL0 + 7)
 218 +/* ASC1 Transmit Interrupt */
 219 +#define FALCON_IRQ_ASC1_T                      (INT_NUM_IM3_IRL0 + 8)
 220 +/* ASC1 Receive Interrupt */
 221 +#define FALCON_IRQ_ASC1_R                      (INT_NUM_IM3_IRL0 + 9)
 222 +/* ASC1 Error Interrupt */
 223 +#define FALCON_IRQ_ASC1_E                      (INT_NUM_IM3_IRL0 + 10)
 224 +/* ASC1 Transmit Buffer Interrupt */
 225 +#define FALCON_IRQ_ASC1_TB                     (INT_NUM_IM3_IRL0 + 11)
 226 +/* ASC1 Autobaud Start Interrupt */
 227 +#define FALCON_IRQ_ASC1_ABST                   (INT_NUM_IM3_IRL0 + 12)
 228 +/* ASC1 Autobaud Detection Interrupt */
 229 +#define FALCON_IRQ_ASC1_ABDET                  (INT_NUM_IM3_IRL0 + 13)
 230 +/* ASC1 Modem Status Interrupt */
 231 +#define FALCON_IRQ_ASC1_MS                     (INT_NUM_IM3_IRL0 + 14)
 232 +/* ASC1 Soft Flow Control Interrupt */
 233 +#define FALCON_IRQ_ASC1_SFC                    (INT_NUM_IM3_IRL0 + 15)
 234 +/* GPTC Timer/Counter 1A Interrupt */
 235 +#define FALCON_IRQ_GPTC_TC1A                   (INT_NUM_IM3_IRL0 + 16)
 236 +/* GPTC Timer/Counter 1B Interrupt */
 237 +#define FALCON_IRQ_GPTC_TC1B                   (INT_NUM_IM3_IRL0 + 17)
 238 +/* GPTC Timer/Counter 2A Interrupt */
 239 +#define FALCON_IRQ_GPTC_TC2A                   (INT_NUM_IM3_IRL0 + 18)
 240 +/* GPTC Timer/Counter 2B Interrupt */
 241 +#define FALCON_IRQ_GPTC_TC2B                   (INT_NUM_IM3_IRL0 + 19)
 242 +/* GPTC Timer/Counter 3A Interrupt */
 243 +#define FALCON_IRQ_GPTC_TC3A                   (INT_NUM_IM3_IRL0 + 20)
 244 +/* GPTC Timer/Counter 3B Interrupt */
 245 +#define FALCON_IRQ_GPTC_TC3B                   (INT_NUM_IM3_IRL0 + 21)
 246 +/* DFEV0, Channel 1 Transmit Interrupt */
 247 +#define FALCON_IRQ_DFEV0_2TX                   (INT_NUM_IM3_IRL0 + 26)
 248 +/* DFEV0, Channel 1 Receive Interrupt */
 249 +#define FALCON_IRQ_DFEV0_2RX                   (INT_NUM_IM3_IRL0 + 27)
 250 +/* DFEV0, Channel 1 General Purpose Interrupt */
 251 +#define FALCON_IRQ_DFEV0_2GP                   (INT_NUM_IM3_IRL0 + 28)
 252 +/* DFEV0, Channel 0 Transmit Interrupt */
 253 +#define FALCON_IRQ_DFEV0_1TX                   (INT_NUM_IM3_IRL0 + 29)
 254 +/* DFEV0, Channel 0 Receive Interrupt */
 255 +#define FALCON_IRQ_DFEV0_1RX                   (INT_NUM_IM3_IRL0 + 30)
 256 +/* DFEV0, Channel 0 General Purpose Interrupt */
 257 +#define FALCON_IRQ_DFEV0_1GP                   (INT_NUM_IM3_IRL0 + 31)
 258 +
 259 +/* ICTRLL 0 Error */
 260 +#define FALCON_IRQ_ICTRLL0_ERR                 (INT_NUM_IM4_IRL0 + 0)
 261 +/* ICTRLL 1 Error */
 262 +#define FALCON_IRQ_ICTRLL1_ERR                 (INT_NUM_IM4_IRL0 + 1)
 263 +/* ICTRLL 2 Error */
 264 +#define FALCON_IRQ_ICTRLL2_ERR                 (INT_NUM_IM4_IRL0 + 2)
 265 +/* ICTRLL 3 Error */
 266 +#define FALCON_IRQ_ICTRLL3_ERR                 (INT_NUM_IM4_IRL0 + 3)
 267 +/* OCTRLL 0 Error */
 268 +#define FALCON_IRQ_OCTRLL0_ERR                 (INT_NUM_IM4_IRL0 + 4)
 269 +/* OCTRLL 1 Error */
 270 +#define FALCON_IRQ_OCTRLL1_ERR                 (INT_NUM_IM4_IRL0 + 5)
 271 +/* OCTRLL 2 Error */
 272 +#define FALCON_IRQ_OCTRLL2_ERR                 (INT_NUM_IM4_IRL0 + 6)
 273 +/* OCTRLL 3 Error */
 274 +#define FALCON_IRQ_OCTRLL3_ERR                 (INT_NUM_IM4_IRL0 + 7)
 275 +/* ICTRLG Error */
 276 +#define FALCON_IRQ_ICTRLG_ERR                  (INT_NUM_IM4_IRL0 + 8)
 277 +/* OCTRLG Error */
 278 +#define FALCON_IRQ_OCTRLG_ERR                  (INT_NUM_IM4_IRL0 + 9)
 279 +/* IQM Error */
 280 +#define FALCON_IRQ_IQM_ERR                     (INT_NUM_IM4_IRL0 + 10)
 281 +/* FSQM Error */
 282 +#define FALCON_IRQ_FSQM_ERR                    (INT_NUM_IM4_IRL0 + 11)
 283 +/* TMU Error */
 284 +#define FALCON_IRQ_TMU_ERR                     (INT_NUM_IM4_IRL0 + 12)
 285 +/* MPS Status Interrupt #0 (VPE1 to VPE0) */
 286 +#define FALCON_IRQ_MPS_IR0                     (INT_NUM_IM4_IRL0 + 14)
 287 +/* MPS Status Interrupt #1 (VPE1 to VPE0) */
 288 +#define FALCON_IRQ_MPS_IR1                     (INT_NUM_IM4_IRL0 + 15)
 289 +/* MPS Status Interrupt #2 (VPE1 to VPE0) */
 290 +#define FALCON_IRQ_MPS_IR2                     (INT_NUM_IM4_IRL0 + 16)
 291 +/* MPS Status Interrupt #3 (VPE1 to VPE0) */
 292 +#define FALCON_IRQ_MPS_IR3                     (INT_NUM_IM4_IRL0 + 17)
 293 +/* MPS Status Interrupt #4 (VPE1 to VPE0) */
 294 +#define FALCON_IRQ_MPS_IR4                     (INT_NUM_IM4_IRL0 + 18)
 295 +/* MPS Status Interrupt #5 (VPE1 to VPE0) */
 296 +#define FALCON_IRQ_MPS_IR5                     (INT_NUM_IM4_IRL0 + 19)
 297 +/* MPS Status Interrupt #6 (VPE1 to VPE0) */
 298 +#define FALCON_IRQ_MPS_IR6                     (INT_NUM_IM4_IRL0 + 20)
 299 +/* MPS Status Interrupt #7 (VPE1 to VPE0) */
 300 +#define FALCON_IRQ_MPS_IR7                     (INT_NUM_IM4_IRL0 + 21)
 301 +/* MPS Status Interrupt #8 (VPE1 to VPE0) */
 302 +#define FALCON_IRQ_MPS_IR8                     (INT_NUM_IM4_IRL0 + 22)
 303 +/* VPE0 Exception Level Flag Interrupt */
 304 +#define FALCON_IRQ_VPE0_EXL                    (INT_NUM_IM4_IRL0 + 29)
 305 +/* VPE0 Error Level Flag Interrupt */
 306 +#define FALCON_IRQ_VPE0_ERL                    (INT_NUM_IM4_IRL0 + 30)
 307 +/* VPE0 Performance Monitoring Counter Interrupt */
 308 +#define FALCON_IRQ_VPE0_PMCIR                  (INT_NUM_IM4_IRL0 + 31)
 309 +
 310 +#endif /* _FALCON_IRQ__ */
 311 diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
 312 new file mode 100644
 313 index 0000000..2caccd9
 314 --- /dev/null
 315 +++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
 316 @@ -0,0 +1,18 @@
 317 +/*
 318 + *  This program is free software; you can redistribute it and/or modify it
 319 + *  under the terms of the GNU General Public License version 2 as published
 320 + *  by the Free Software Foundation.
 321 + *
 322 + *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 323 + */
 324 +
 325 +#ifndef __FALCON_IRQ_H
 326 +#define __FALCON_IRQ_H
 327 +
 328 +#include <falcon_irq.h>
 329 +
 330 +#define NR_IRQS 328
 331 +
 332 +#include_next <irq.h>
 333 +
 334 +#endif
 335 diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
 336 new file mode 100644
 337 index 0000000..b074748
 338 --- /dev/null
 339 +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
 340 @@ -0,0 +1,143 @@
 341 +/*
 342 + * This program is free software; you can redistribute it and/or modify it
 343 + * under the terms of the GNU General Public License version 2 as published
 344 + * by the Free Software Foundation.
 345 + *
 346 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 347 + */
 348 +
 349 +#ifndef _LTQ_FALCON_H__
 350 +#define _LTQ_FALCON_H__
 351 +
 352 +#ifdef CONFIG_SOC_FALCON
 353 +
 354 +#include <lantiq.h>
 355 +
 356 +/* Chip IDs */
 357 +#define SOC_ID_FALCON          0x01B8
 358 +
 359 +/* SoC Types */
 360 +#define SOC_TYPE_FALCON                0x01
 361 +
 362 +/* ASC0/1 - serial port */
 363 +#define LTQ_ASC0_BASE_ADDR     0x1E100C00
 364 +#define LTQ_ASC1_BASE_ADDR     0x1E100B00
 365 +#define LTQ_ASC_SIZE           0x100
 366 +
 367 +#define LTQ_ASC_TIR(x)          (INT_NUM_IM3_IRL0 + (x * 8))
 368 +#define LTQ_ASC_RIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 1)
 369 +#define LTQ_ASC_EIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 2)
 370 +
 371 +/*
 372 + * during early_printk no ioremap possible at this early stage
 373 + * lets use KSEG1 instead
 374 + */
 375 +#define LTQ_EARLY_ASC          KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
 376 +
 377 +/* ICU - interrupt control unit */
 378 +#define LTQ_ICU_BASE_ADDR      0x1F880200
 379 +#define LTQ_ICU_SIZE           0x100
 380 +
 381 +/* WDT */
 382 +#define LTQ_WDT_BASE_ADDR      0x1F8803F0
 383 +#define LTQ_WDT_SIZE           0x10
 384 +
 385 +#define LTQ_RST_CAUSE_WDTRST   0x0002
 386 +
 387 +/* EBU - external bus unit */
 388 +#define LTQ_EBU_BASE_ADDR       0x18000000
 389 +#define LTQ_EBU_SIZE            0x0100
 390 +
 391 +#define LTQ_EBU_MODCON  0x000C
 392 +
 393 +/* GPIO */
 394 +#define LTQ_GPIO0_BASE_ADDR     0x1D810000
 395 +#define LTQ_GPIO0_SIZE          0x0080
 396 +#define LTQ_GPIO1_BASE_ADDR     0x1E800100
 397 +#define LTQ_GPIO1_SIZE          0x0080
 398 +#define LTQ_GPIO2_BASE_ADDR     0x1D810100
 399 +#define LTQ_GPIO2_SIZE          0x0080
 400 +#define LTQ_GPIO3_BASE_ADDR     0x1E800200
 401 +#define LTQ_GPIO3_SIZE          0x0080
 402 +#define LTQ_GPIO4_BASE_ADDR     0x1E800300
 403 +#define LTQ_GPIO4_SIZE          0x0080
 404 +#define LTQ_PADCTRL0_BASE_ADDR  0x1DB01000
 405 +#define LTQ_PADCTRL0_SIZE       0x0100
 406 +#define LTQ_PADCTRL1_BASE_ADDR  0x1E800400
 407 +#define LTQ_PADCTRL1_SIZE       0x0100
 408 +#define LTQ_PADCTRL2_BASE_ADDR  0x1DB02000
 409 +#define LTQ_PADCTRL2_SIZE       0x0100
 410 +#define LTQ_PADCTRL3_BASE_ADDR  0x1E800500
 411 +#define LTQ_PADCTRL3_SIZE       0x0100
 412 +#define LTQ_PADCTRL4_BASE_ADDR  0x1E800600
 413 +#define LTQ_PADCTRL4_SIZE       0x0100
 414 +
 415 +/* CHIP ID */
 416 +#define LTQ_STATUS_BASE_ADDR   0x1E802000
 417 +
 418 +#define LTQ_FALCON_CHIPID      ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
 419 +#define LTQ_FALCON_CHIPTYPE    ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
 420 +#define LTQ_FALCON_CHIPCONF    ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
 421 +
 422 +/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
 423 +#define LTQ_SYS1_BASE_ADDR      0x1EF00000
 424 +#define LTQ_SYS1_SIZE           0x0100
 425 +#define LTQ_STATUS_BASE_ADDR   0x1E802000
 426 +#define LTQ_STATUS_SIZE                0x0080
 427 +#define LTQ_SYS_ETH_BASE_ADDR  0x1DB00000
 428 +#define LTQ_SYS_ETH_SIZE       0x0100
 429 +#define LTQ_SYS_GPE_BASE_ADDR  0x1D700000
 430 +#define LTQ_SYS_GPE_SIZE       0x0100
 431 +
 432 +#define SYSCTL_SYS1            0
 433 +#define SYSCTL_SYSETH          1
 434 +#define SYSCTL_SYSGPE          2
 435 +
 436 +/* Activation Status Register */
 437 +#define ACTS_ASC1_ACT  0x00000800
 438 +#define ACTS_P0                0x00010000
 439 +#define ACTS_P1                0x00010000
 440 +#define ACTS_P2                0x00020000
 441 +#define ACTS_P3                0x00020000
 442 +#define ACTS_P4                0x00040000
 443 +#define ACTS_PADCTRL0  0x00100000
 444 +#define ACTS_PADCTRL1  0x00100000
 445 +#define ACTS_PADCTRL2  0x00200000
 446 +#define ACTS_PADCTRL3  0x00200000
 447 +#define ACTS_PADCTRL4  0x00400000
 448 +
 449 +extern void ltq_sysctl_activate(int module, unsigned int mask);
 450 +extern void ltq_sysctl_deactivate(int module, unsigned int mask);
 451 +extern void ltq_sysctl_clken(int module, unsigned int mask);
 452 +extern void ltq_sysctl_clkdis(int module, unsigned int mask);
 453 +extern void ltq_sysctl_reboot(int module, unsigned int mask);
 454 +extern int ltq_gpe_is_activated(unsigned int mask);
 455 +
 456 +/* global register ranges */
 457 +extern __iomem void *ltq_ebu_membase;
 458 +extern __iomem void *ltq_sys1_membase;
 459 +#define ltq_ebu_w32(x, y)      ltq_w32((x), ltq_ebu_membase + (y))
 460 +#define ltq_ebu_r32(x)         ltq_r32(ltq_ebu_membase + (x))
 461 +#define ltq_ebu_w32_mask(clear, set, reg)   \
 462 +       ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg)
 463 +
 464 +#define ltq_sys1_w32(x, y)     ltq_w32((x), ltq_sys1_membase + (y))
 465 +#define ltq_sys1_r32(x)                ltq_r32(ltq_sys1_membase + (x))
 466 +#define ltq_sys1_w32_mask(clear, set, reg)   \
 467 +       ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
 468 +
 469 +/* gpio_request wrapper to help configure the pin */
 470 +extern int  ltq_gpio_request(unsigned int pin, unsigned int mux,
 471 +                               unsigned int dir, const char *name);
 472 +extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
 473 +
 474 +/* to keep the irq code generic we need to define these to 0 as falcon
 475 +   has no EIU/EBU */
 476 +#define LTQ_EIU_BASE_ADDR      0
 477 +#define LTQ_EBU_PCC_ISTAT      0
 478 +
 479 +#define ltq_is_ar9()   0
 480 +#define ltq_is_vr9()   0
 481 +
 482 +#endif /* CONFIG_SOC_FALCON */
 483 +#endif /* _LTQ_XWAY_H__ */
 484 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
 485 index 66d7300..188de0f 100644
 486 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
 487 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
 488 @@ -25,6 +25,7 @@ extern unsigned int ltq_get_soc_type(void);
 489  /* clock speeds */
 490  #define CLOCK_60M      60000000
 491  #define CLOCK_83M      83333333
 492 +#define CLOCK_100M     100000000
 493  #define CLOCK_111M     111111111
 494  #define CLOCK_133M     133333333
 495  #define CLOCK_167M     166666667
 496 diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
 497 index 3fccf21..cb6b39f 100644
 498 --- a/arch/mips/lantiq/Kconfig
 499 +++ b/arch/mips/lantiq/Kconfig
 500 @@ -16,8 +16,12 @@ config SOC_XWAY
 501         bool "XWAY"
 502         select SOC_TYPE_XWAY
 503         select HW_HAS_PCI
 504 +
 505 +config SOC_FALCON
 506 +       bool "FALCON"
 507  endchoice
 508
 509  source "arch/mips/lantiq/xway/Kconfig"
 510 +source "arch/mips/lantiq/falcon/Kconfig"
 511
 512  endif
 513 diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile
 514 index e5dae0e..7e9c69e 100644
 515 --- a/arch/mips/lantiq/Makefile
 516 +++ b/arch/mips/lantiq/Makefile
 517 @@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devices.o
 518  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 519
 520  obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
 521 +obj-$(CONFIG_SOC_FALCON) += falcon/
 522 diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform
 523 index f3dff05..b3ec498 100644
 524 --- a/arch/mips/lantiq/Platform
 525 +++ b/arch/mips/lantiq/Platform
 526 @@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ)       += lantiq/
 527  cflags-$(CONFIG_LANTIQ)                += -I$(srctree)/arch/mips/include/asm/mach-lantiq
 528  load-$(CONFIG_LANTIQ)          = 0xffffffff80002000
 529  cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
 530 +cflags-$(CONFIG_SOC_FALCON)    += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
 531 diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
 532 new file mode 100644
 533 index 0000000..e9c7455
 534 --- /dev/null
 535 +++ b/arch/mips/lantiq/falcon/Makefile
 536 @@ -0,0 +1 @@
 537 +obj-y := clk.o prom.o reset.o sysctrl.o devices.o
 538 diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c
 539 new file mode 100644
 540 index 0000000..afe1b52
 541 --- /dev/null
 542 +++ b/arch/mips/lantiq/falcon/clk.c
 543 @@ -0,0 +1,44 @@
 544 +/*
 545 + * This program is free software; you can redistribute it and/or modify it
 546 + * under the terms of the GNU General Public License version 2 as published
 547 + * by the Free Software Foundation.
 548 + *
 549 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 550 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 551 + */
 552 +
 553 +#include <linux/ioport.h>
 554 +#include <linux/export.h>
 555 +
 556 +#include <lantiq_soc.h>
 557 +
 558 +#include "devices.h"
 559 +
 560 +/* CPU0 Clock Control Register */
 561 +#define LTQ_SYS1_CPU0CC                0x0040
 562 +/* clock divider bit */
 563 +#define LTQ_CPU0CC_CPUDIV      0x0001
 564 +
 565 +unsigned int
 566 +ltq_get_io_region_clock(void)
 567 +{
 568 +       return CLOCK_200M;
 569 +}
 570 +EXPORT_SYMBOL(ltq_get_io_region_clock);
 571 +
 572 +unsigned int
 573 +ltq_get_cpu_hz(void)
 574 +{
 575 +       if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
 576 +               return CLOCK_200M;
 577 +       else
 578 +               return CLOCK_400M;
 579 +}
 580 +EXPORT_SYMBOL(ltq_get_cpu_hz);
 581 +
 582 +unsigned int
 583 +ltq_get_fpi_hz(void)
 584 +{
 585 +       return CLOCK_100M;
 586 +}
 587 +EXPORT_SYMBOL(ltq_get_fpi_hz);
 588 diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
 589 new file mode 100644
 590 index 0000000..c4606f2
 591 --- /dev/null
 592 +++ b/arch/mips/lantiq/falcon/devices.c
 593 @@ -0,0 +1,87 @@
 594 +/*
 595 + * This program is free software; you can redistribute it and/or modify it
 596 + * under the terms of the GNU General Public License version 2 as published
 597 + * by the Free Software Foundation.
 598 + *
 599 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 600 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 601 + */
 602 +
 603 +#include <linux/platform_device.h>
 604 +#include <linux/mtd/nand.h>
 605 +
 606 +#include <lantiq_soc.h>
 607 +
 608 +#include "devices.h"
 609 +
 610 +/* nand flash */
 611 +/* address lines used for NAND control signals */
 612 +#define NAND_ADDR_ALE          0x10000
 613 +#define NAND_ADDR_CLE          0x20000
 614 +/* Ready/Busy Status */
 615 +#define MODCON_STS             0x0002
 616 +/* Ready/Busy Status Edge */
 617 +#define MODCON_STSEDGE         0x0004
 618 +
 619 +static const char *part_probes[] = { "cmdlinepart", NULL };
 620 +
 621 +static int
 622 +falcon_nand_ready(struct mtd_info *mtd)
 623 +{
 624 +       u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON);
 625 +
 626 +       return (((modcon & (MODCON_STS | MODCON_STSEDGE)) ==
 627 +                                               (MODCON_STS | MODCON_STSEDGE)));
 628 +}
 629 +
 630 +static void
 631 +falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 632 +{
 633 +       struct nand_chip *this = mtd->priv;
 634 +       unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
 635 +
 636 +       if (ctrl & NAND_CTRL_CHANGE) {
 637 +               nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
 638 +
 639 +               if (ctrl & NAND_CLE)
 640 +                       nandaddr |= NAND_ADDR_CLE;
 641 +               if (ctrl & NAND_ALE)
 642 +                       nandaddr |= NAND_ADDR_ALE;
 643 +
 644 +               this->IO_ADDR_W = (void __iomem *) nandaddr;
 645 +       }
 646 +
 647 +       if (cmd != NAND_CMD_NONE)
 648 +               writeb(cmd, this->IO_ADDR_W);
 649 +}
 650 +
 651 +static struct platform_nand_data falcon_flash_nand_data = {
 652 +       .chip = {
 653 +               .nr_chips               = 1,
 654 +               .chip_delay             = 25,
 655 +               .part_probe_types       = part_probes,
 656 +       },
 657 +       .ctrl = {
 658 +               .cmd_ctrl               = falcon_hwcontrol,
 659 +               .dev_ready              = falcon_nand_ready,
 660 +       }
 661 +};
 662 +
 663 +static struct resource ltq_nand_res =
 664 +       MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX);
 665 +
 666 +static struct platform_device ltq_flash_nand = {
 667 +       .name           = "gen_nand",
 668 +       .id             = -1,
 669 +       .num_resources  = 1,
 670 +       .resource       = &ltq_nand_res,
 671 +       .dev            = {
 672 +               .platform_data = &falcon_flash_nand_data,
 673 +       },
 674 +};
 675 +
 676 +void __init
 677 +falcon_register_nand(void)
 678 +{
 679 +       platform_device_register(&ltq_flash_nand);
 680 +}
 681 diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
 682 new file mode 100644
 683 index 0000000..e802a7c
 684 --- /dev/null
 685 +++ b/arch/mips/lantiq/falcon/devices.h
 686 @@ -0,0 +1,18 @@
 687 +/*
 688 + * This program is free software; you can redistribute it and/or modify
 689 + * it under the terms of the GNU General Public License as published by
 690 + * the Free Software Foundation; either version 2 of the License, or
 691 + * (at your option) any later version.
 692 + *
 693 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 694 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 695 + */
 696 +
 697 +#ifndef _FALCON_DEVICES_H__
 698 +#define _FALCON_DEVICES_H__
 699 +
 700 +#include "../devices.h"
 701 +
 702 +extern void falcon_register_nand(void);
 703 +
 704 +#endif
 705 diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
 706 new file mode 100644
 707 index 0000000..b50d6f9
 708 --- /dev/null
 709 +++ b/arch/mips/lantiq/falcon/prom.c
 710 @@ -0,0 +1,93 @@
 711 +/*
 712 + * This program is free software; you can redistribute it and/or modify it
 713 + * under the terms of the GNU General Public License version 2 as published
 714 + * by the Free Software Foundation.
 715 + *
 716 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 717 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 718 + */
 719 +
 720 +#include <lantiq_soc.h>
 721 +
 722 +#include "devices.h"
 723 +
 724 +#include "../prom.h"
 725 +
 726 +#define SOC_FALCON             "Falcon"
 727 +#define SOC_FALCON_D           "Falcon-D"
 728 +#define SOC_FALCON_V           "Falcon-V"
 729 +#define SOC_FALCON_M           "Falcon-M"
 730 +
 731 +#define PART_SHIFT     12
 732 +#define PART_MASK      0x0FFFF000
 733 +#define REV_SHIFT      28
 734 +#define REV_MASK       0xF0000000
 735 +#define SREV_SHIFT     22
 736 +#define SREV_MASK      0x03C00000
 737 +#define TYPE_SHIFT     26
 738 +#define TYPE_MASK      0x3C000000
 739 +
 740 +#define MUXC_SIF_RX_PIN                112
 741 +#define MUXC_SIF_TX_PIN                113
 742 +
 743 +/* this parameter allows us enable/disable asc1 via commandline */
 744 +static int register_asc1;
 745 +static int __init
 746 +ltq_parse_asc1(char *p)
 747 +{
 748 +       register_asc1 = 1;
 749 +       return 0;
 750 +}
 751 +__setup("use_asc1", ltq_parse_asc1);
 752 +
 753 +void __init
 754 +ltq_soc_setup(void)
 755 +{
 756 +       ltq_register_asc(0);
 757 +       ltq_register_wdt();
 758 +       falcon_register_gpio();
 759 +       if (register_asc1) {
 760 +               ltq_register_asc(1);
 761 +               if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx"))
 762 +                       pr_err("failed to request asc1-rx");
 763 +               if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx"))
 764 +                       pr_err("failed to request asc1-tx");
 765 +               ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT);
 766 +       }
 767 +}
 768 +
 769 +void __init
 770 +ltq_soc_detect(struct ltq_soc_info *i)
 771 +{
 772 +       u32 type;
 773 +       i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
 774 +       i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
 775 +       i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT);
 776 +       sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
 777 +               i->rev & 0x7, (i->srev & 0x3) + 1);
 778 +
 779 +       switch (i->partnum) {
 780 +       case SOC_ID_FALCON:
 781 +               type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT;
 782 +               switch (type) {
 783 +               case 0:
 784 +                       i->name = SOC_FALCON_D;
 785 +                       break;
 786 +               case 1:
 787 +                       i->name = SOC_FALCON_V;
 788 +                       break;
 789 +               case 2:
 790 +                       i->name = SOC_FALCON_M;
 791 +                       break;
 792 +               default:
 793 +                       i->name = SOC_FALCON;
 794 +                       break;
 795 +               }
 796 +               i->type = SOC_TYPE_FALCON;
 797 +               break;
 798 +
 799 +       default:
 800 +               unreachable();
 801 +               break;
 802 +       }
 803 +}
 804 diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
 805 new file mode 100644
 806 index 0000000..cbcadc5
 807 --- /dev/null
 808 +++ b/arch/mips/lantiq/falcon/reset.c
 809 @@ -0,0 +1,87 @@
 810 +/*
 811 + * This program is free software; you can redistribute it and/or modify it
 812 + * under the terms of the GNU General Public License version 2 as published
 813 + * by the Free Software Foundation.
 814 + *
 815 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 816 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 817 + */
 818 +
 819 +#include <linux/init.h>
 820 +#include <linux/io.h>
 821 +#include <linux/pm.h>
 822 +#include <asm/reboot.h>
 823 +#include <linux/export.h>
 824 +
 825 +#include <lantiq_soc.h>
 826 +
 827 +/* CPU0 Reset Source Register */
 828 +#define LTQ_SYS1_CPU0RS                0x0040
 829 +/* reset cause mask */
 830 +#define LTQ_CPU0RS_MASK                0x0003
 831 +
 832 +int
 833 +ltq_reset_cause(void)
 834 +{
 835 +       return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK;
 836 +}
 837 +EXPORT_SYMBOL_GPL(ltq_reset_cause);
 838 +
 839 +#define BOOT_REG_BASE  (KSEG1 | 0x1F200000)
 840 +#define BOOT_PW1_REG   (BOOT_REG_BASE | 0x20)
 841 +#define BOOT_PW2_REG   (BOOT_REG_BASE | 0x24)
 842 +#define BOOT_PW1       0x4C545100
 843 +#define BOOT_PW2       0x0051544C
 844 +
 845 +#define WDT_REG_BASE   (KSEG1 | 0x1F8803F0)
 846 +#define WDT_PW1                0x00BE0000
 847 +#define WDT_PW2                0x00DC0000
 848 +
 849 +static void
 850 +ltq_machine_restart(char *command)
 851 +{
 852 +       pr_notice("System restart\n");
 853 +       local_irq_disable();
 854 +
 855 +       /* reboot magic */
 856 +       ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
 857 +       ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
 858 +       ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
 859 +
 860 +       /* watchdog magic */
 861 +       ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
 862 +       ltq_w32(WDT_PW2 |
 863 +               (0x3 << 26) | /* PWL */
 864 +               (0x2 << 24) | /* CLKDIV */
 865 +               (0x1 << 31) | /* enable */
 866 +               (1), /* reload */
 867 +               (void *)WDT_REG_BASE);
 868 +       unreachable();
 869 +}
 870 +
 871 +static void
 872 +ltq_machine_halt(void)
 873 +{
 874 +       pr_notice("System halted.\n");
 875 +       local_irq_disable();
 876 +       unreachable();
 877 +}
 878 +
 879 +static void
 880 +ltq_machine_power_off(void)
 881 +{
 882 +       pr_notice("Please turn off the power now.\n");
 883 +       local_irq_disable();
 884 +       unreachable();
 885 +}
 886 +
 887 +static int __init
 888 +mips_reboot_setup(void)
 889 +{
 890 +       _machine_restart = ltq_machine_restart;
 891 +       _machine_halt = ltq_machine_halt;
 892 +       pm_power_off = ltq_machine_power_off;
 893 +       return 0;
 894 +}
 895 +
 896 +arch_initcall(mips_reboot_setup);
 897 diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
 898 new file mode 100644
 899 index 0000000..905a142
 900 --- /dev/null
 901 +++ b/arch/mips/lantiq/falcon/sysctrl.c
 902 @@ -0,0 +1,183 @@
 903 +/*
 904 + * This program is free software; you can redistribute it and/or modify it
 905 + * under the terms of the GNU General Public License version 2 as published
 906 + * by the Free Software Foundation.
 907 + *
 908 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 909 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 910 + */
 911 +
 912 +#include <linux/ioport.h>
 913 +#include <linux/export.h>
 914 +#include <asm/delay.h>
 915 +
 916 +#include <lantiq_soc.h>
 917 +
 918 +#include "devices.h"
 919 +
 920 +/* infrastructure control register */
 921 +#define SYS1_INFRAC            0x00bc
 922 +/* Configuration fuses for drivers and pll */
 923 +#define STATUS_CONFIG          0x0040
 924 +
 925 +/* GPE frequency selection */
 926 +#define GPPC_OFFSET            24
 927 +#define GPEFREQ_MASK           0x00000C0
 928 +#define GPEFREQ_OFFSET         10
 929 +/* Clock status register */
 930 +#define LTQ_SYSCTL_CLKS                0x0000
 931 +/* Clock enable register */
 932 +#define LTQ_SYSCTL_CLKEN       0x0004
 933 +/* Clock clear register */
 934 +#define LTQ_SYSCTL_CLKCLR      0x0008
 935 +/* Activation Status Register */
 936 +#define LTQ_SYSCTL_ACTS                0x0020
 937 +/* Activation Register */
 938 +#define LTQ_SYSCTL_ACT         0x0024
 939 +/* Deactivation Register */
 940 +#define LTQ_SYSCTL_DEACT       0x0028
 941 +/* reboot Register */
 942 +#define LTQ_SYSCTL_RBT         0x002c
 943 +
 944 +static struct resource ltq_sysctl_res[] = {
 945 +       MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE),
 946 +       MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE),
 947 +       MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE),
 948 +};
 949 +
 950 +static struct resource ltq_status_res =
 951 +       MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE);
 952 +static struct resource ltq_ebu_res =
 953 +       MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
 954 +
 955 +static void __iomem *ltq_sysctl[3];
 956 +static void __iomem *ltq_status_membase;
 957 +void __iomem *ltq_sys1_membase;
 958 +void __iomem *ltq_ebu_membase;
 959 +
 960 +#define ltq_reg_w32(m, x, y)   ltq_w32((x), ltq_sysctl[m] + (y))
 961 +#define ltq_reg_r32(m, x)      ltq_r32(ltq_sysctl[m] + (x))
 962 +#define ltq_reg_w32_mask(m, clear, set, reg)   \
 963 +               ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg)
 964 +
 965 +#define ltq_status_w32(x, y)   ltq_w32((x), ltq_status_membase + (y))
 966 +#define ltq_status_r32(x)      ltq_r32(ltq_status_membase + (x))
 967 +
 968 +static inline void
 969 +ltq_sysctl_wait(int module, unsigned int mask,
 970 +               unsigned int test, unsigned int reg)
 971 +{
 972 +       int err = 1000000;
 973 +
 974 +       do {} while (--err && ((ltq_reg_r32(module, reg)
 975 +                                       & mask) != test));
 976 +       if (!err)
 977 +               pr_err("module de/activation failed %d %08X %08X\n",
 978 +                                                       module, mask, test);
 979 +}
 980 +
 981 +void
 982 +ltq_sysctl_activate(int module, unsigned int mask)
 983 +{
 984 +       if (module > SYSCTL_SYSGPE)
 985 +               return;
 986 +
 987 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
 988 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT);
 989 +       ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
 990 +}
 991 +EXPORT_SYMBOL(ltq_sysctl_activate);
 992 +
 993 +void
 994 +ltq_sysctl_deactivate(int module, unsigned int mask)
 995 +{
 996 +       if (module > SYSCTL_SYSGPE)
 997 +               return;
 998 +
 999 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
1000 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT);
1001 +       ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS);
1002 +}
1003 +EXPORT_SYMBOL(ltq_sysctl_deactivate);
1004 +
1005 +void
1006 +ltq_sysctl_clken(int module, unsigned int mask)
1007 +{
1008 +       if (module > SYSCTL_SYSGPE)
1009 +               return;
1010 +
1011 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
1012 +       ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS);
1013 +}
1014 +EXPORT_SYMBOL(ltq_sysctl_clken);
1015 +
1016 +void
1017 +ltq_sysctl_clkdis(int module, unsigned int mask)
1018 +{
1019 +       if (module > SYSCTL_SYSGPE)
1020 +               return;
1021 +
1022 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
1023 +       ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS);
1024 +}
1025 +EXPORT_SYMBOL(ltq_sysctl_clkdis);
1026 +
1027 +void
1028 +ltq_sysctl_reboot(int module, unsigned int mask)
1029 +{
1030 +       unsigned int act;
1031 +
1032 +       if (module > SYSCTL_SYSGPE)
1033 +               return;
1034 +
1035 +       act = ltq_reg_r32(module, LTQ_SYSCTL_ACT);
1036 +       if ((~act & mask) != 0)
1037 +               ltq_sysctl_activate(module, ~act & mask);
1038 +       ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT);
1039 +       ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
1040 +}
1041 +EXPORT_SYMBOL(ltq_sysctl_reboot);
1042 +
1043 +/* enable the ONU core */
1044 +static void
1045 +ltq_gpe_enable(void)
1046 +{
1047 +       unsigned int freq;
1048 +       unsigned int status;
1049 +
1050 +       /* if if the clock is already enabled */
1051 +       status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC);
1052 +       if (status & (1 << (GPPC_OFFSET + 1)))
1053 +               return;
1054 +
1055 +       if (ltq_status_r32(STATUS_CONFIG) == 0)
1056 +               freq = 1; /* use 625MHz on unfused chip */
1057 +       else
1058 +               freq = (ltq_status_r32(STATUS_CONFIG) &
1059 +                       GPEFREQ_MASK) >>
1060 +                       GPEFREQ_OFFSET;
1061 +
1062 +       /* apply new frequency */
1063 +       ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
1064 +               freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
1065 +       udelay(1);
1066 +
1067 +       /* enable new frequency */
1068 +       ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
1069 +       udelay(1);
1070 +}
1071 +
1072 +void __init
1073 +ltq_soc_init(void)
1074 +{
1075 +       int i;
1076 +
1077 +       for (i = 0; i < 3; i++)
1078 +               ltq_sysctl[i] = ltq_remap_resource(&ltq_sysctl_res[i]);
1079 +
1080 +       ltq_sys1_membase = ltq_sysctl[0];
1081 +       ltq_status_membase = ltq_remap_resource(&ltq_status_res);
1082 +       ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_res);
1083 +
1084 +       ltq_gpe_enable();
1085 +}
1086 --
1087 1.7.7.1
1088