target/linux/lantiq/patches/104-board_xway.patch

   1
   2 --- /dev/null
   3 +++ b/arch/mips/lantiq/xway/Kconfig
   4 @@ -0,0 +1,19 @@
   5 +if SOC_LANTIQ_XWAY
   6 +
   7 +menu "Mips Machine"
   8 +
   9 +config LANTIQ_MACH_EASY50812
  10 +       bool "Easy50812"
  11 +       default y
  12 +
  13 +config LANTIQ_MACH_EASY50712
  14 +       bool "Easy50712"
  15 +       default y
  16 +
  17 +config LANTIQ_MACH_EASY4010
  18 +       bool "Easy4010"
  19 +       default y
  20 +
  21 +endmenu
  22 +
  23 +endif
  24 --- /dev/null
  25 +++ b/arch/mips/lantiq/xway/gpio_ebu.c
  26 @@ -0,0 +1,107 @@
  27 +/*
  28 + *  This program is free software; you can redistribute it and/or modify it
  29 + *  under the terms of the GNU General Public License version 2 as published
  30 + *  by the Free Software Foundation.
  31 + *
  32 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  33 + */
  34 +
  35 +#include <linux/init.h>
  36 +#include <linux/module.h>
  37 +#include <linux/types.h>
  38 +#include <linux/platform_device.h>
  39 +#include <linux/mutex.h>
  40 +#include <linux/gpio.h>
  41 +
  42 +#include <xway.h>
  43 +
  44 +#define LQ_EBU_BUSCON  0x1e7ff
  45 +#define LQ_EBU_WP              0x80000000
  46 +
  47 +static int shadow = 0x0000;
  48 +static void __iomem *virt;
  49 +
  50 +static int
  51 +lq_ebu_direction_output(struct gpio_chip *chip, unsigned offset, int value)
  52 +{
  53 +       return 0;
  54 +}
  55 +
  56 +static void
  57 +lq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
  58 +{
  59 +       unsigned long flags;
  60 +       if(value)
  61 +               shadow |= (1 << offset);
  62 +       else
  63 +               shadow &= ~(1 << offset);
  64 +       spin_lock_irqsave(&ebu_lock, flags);
  65 +       lq_w32(LQ_EBU_BUSCON, LQ_EBU_BUSCON1);
  66 +       *((__u16*)virt) = shadow;
  67 +       lq_w32(LQ_EBU_BUSCON | LQ_EBU_WP, LQ_EBU_BUSCON1);
  68 +       spin_unlock_irqrestore(&ebu_lock, flags);
  69 +}
  70 +
  71 +static struct gpio_chip
  72 +lq_ebu_chip =
  73 +{
  74 +       .label = "lq_ebu",
  75 +       .direction_output = lq_ebu_direction_output,
  76 +       .set = lq_ebu_set,
  77 +       .base = 32,
  78 +       .ngpio = 16,
  79 +       .can_sleep = 1,
  80 +       .owner = THIS_MODULE,
  81 +};
  82 +
  83 +static int __devinit
  84 +lq_ebu_probe(struct platform_device *pdev)
  85 +{
  86 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  87 +       int ret = 0;
  88 +       if (!res)
  89 +               return -ENOENT;
  90 +       res = request_mem_region(res->start, resource_size(res),
  91 +               dev_name(&pdev->dev));
  92 +       if (!res)
  93 +               return -EBUSY;
  94 +
  95 +       /* tell the ebu controller which mem addr we will be using */
  96 +       lq_w32(pdev->resource->start | 0x1, LQ_EBU_ADDRSEL1);
  97 +       lq_w32(LQ_EBU_BUSCON | LQ_EBU_WP, LQ_EBU_BUSCON1);
  98 +
  99 +       virt = ioremap_nocache(res->start, resource_size(res));
 100 +       if (!virt)
 101 +       {
 102 +               dev_err(&pdev->dev, "Failed to ioremap mem region\n");
 103 +               ret = -ENOMEM;
 104 +               goto err_release_mem_region;
 105 +       }
 106 +       /* grab the default settings passed form the platform code */
 107 +       shadow = (unsigned int) pdev->dev.platform_data;
 108 +
 109 +       ret = gpiochip_add(&lq_ebu_chip);
 110 +       if (!ret)
 111 +               return 0;
 112 +
 113 +err_release_mem_region:
 114 +       release_mem_region(res->start, resource_size(res));
 115 +       return ret;
 116 +}
 117 +
 118 +static struct platform_driver
 119 +lq_ebu_driver = {
 120 +       .probe = lq_ebu_probe,
 121 +       .driver = {
 122 +               .name = "lq_ebu",
 123 +               .owner = THIS_MODULE,
 124 +       },
 125 +};
 126 +
 127 +static int __init
 128 +init_lq_ebu(void)
 129 +{
 130 +       return platform_driver_register(&lq_ebu_driver);
 131 +}
 132 +
 133 +arch_initcall(init_lq_ebu);
 134 --- /dev/null
 135 +++ b/arch/mips/lantiq/xway/gpio_leds.c
 136 @@ -0,0 +1,161 @@
 137 +/*
 138 + *  This program is free software; you can redistribute it and/or modify it
 139 + *  under the terms of the GNU General Public License version 2 as published
 140 + *  by the Free Software Foundation.
 141 + *
 142 + *  Copyright (C) 2007 John Crispin <blogic@openwrt.org>
 143 + *
 144 + */
 145 +
 146 +#include <linux/slab.h>
 147 +#include <linux/init.h>
 148 +#include <linux/module.h>
 149 +#include <linux/types.h>
 150 +#include <linux/platform_device.h>
 151 +#include <linux/mutex.h>
 152 +#include <linux/gpio.h>
 153 +
 154 +#include <xway.h>
 155 +
 156 +#define LQ_STP_BASE                    0x1E100BB0
 157 +#define LQ_STP_SIZE                    0x40
 158 +
 159 +#define LQ_STP_CON0                    0x00
 160 +#define LQ_STP_CON1                    0x04
 161 +#define LQ_STP_CPU0                    0x08
 162 +#define LQ_STP_CPU1                    0x0C
 163 +#define LQ_STP_AR                      0x10
 164 +
 165 +#define STP_CON0_SWU           (1 << 31)
 166 +
 167 +#define LQ_STP_2HZ                     (0)
 168 +#define LQ_STP_4HZ                     (1 << 23)
 169 +#define LQ_STP_8HZ                     (2 << 23)
 170 +#define LQ_STP_10HZ                    (3 << 23)
 171 +#define LQ_STP_MASK                    (0xf << 23)
 172 +
 173 +#define LQ_STP_UPD_SRC_FPI     (1 << 31)
 174 +#define LQ_STP_UPD_MASK                (3 << 30)
 175 +#define LQ_STP_ADSL_SRC                (3 << 24)
 176 +
 177 +#define LQ_STP_GROUP0          (1 << 0)
 178 +
 179 +#define LQ_STP_RISING          0
 180 +#define LQ_STP_FALLING         (1 << 26)
 181 +#define LQ_STP_EDGE_MASK       (1 << 26)
 182 +
 183 +#define lq_stp_r32(reg)                                __raw_readl(virt + reg)
 184 +#define lq_stp_w32(val, reg)           __raw_writel(val, virt + reg)
 185 +#define lq_stp_w32_mask(clear, set, reg) \
 186 +        lq_w32((lq_r32(virt + reg) & ~clear) | set, virt + reg)
 187 +
 188 +static int shadow = 0xffff;
 189 +static void __iomem *virt;
 190 +
 191 +static int
 192 +lq_stp_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 193 +{
 194 +       return 0;
 195 +}
 196 +
 197 +static void
 198 +lq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
 199 +{
 200 +       if(value)
 201 +               shadow |= (1 << offset);
 202 +       else
 203 +               shadow &= ~(1 << offset);
 204 +       lq_stp_w32(shadow, LQ_STP_CPU0);
 205 +}
 206 +
 207 +static struct gpio_chip lq_stp_chip =
 208 +{
 209 +       .label = "lq_stp",
 210 +       .direction_output = lq_stp_direction_output,
 211 +       .set = lq_stp_set,
 212 +       .base = 48,
 213 +       .ngpio = 24,
 214 +       .can_sleep = 1,
 215 +       .owner = THIS_MODULE,
 216 +};
 217 +
 218 +static int
 219 +lq_stp_hw_init(void)
 220 +{
 221 +       /* the 3 pins used to control the external stp */
 222 +       lq_gpio_request(4, 1, 0, 1, "stp-st");
 223 +       lq_gpio_request(5, 1, 0, 1, "stp-d");
 224 +       lq_gpio_request(6, 1, 0, 1, "stp-sh");
 225 +
 226 +       /* sane defaults */
 227 +       lq_stp_w32(0, LQ_STP_AR);
 228 +       lq_stp_w32(0, LQ_STP_CPU0);
 229 +       lq_stp_w32(0, LQ_STP_CPU1);
 230 +       lq_stp_w32(STP_CON0_SWU, LQ_STP_CON0);
 231 +       lq_stp_w32(0, LQ_STP_CON1);
 232 +
 233 +       /* rising or falling edge */
 234 +       lq_stp_w32_mask(LQ_STP_EDGE_MASK, LQ_STP_FALLING, LQ_STP_CON0);
 235 +
 236 +       /* per default stp 15-0 are set */
 237 +       lq_stp_w32_mask(0, LQ_STP_GROUP0, LQ_STP_CON1);
 238 +
 239 +       /* stp are update periodically by the FPID */
 240 +       lq_stp_w32_mask(LQ_STP_UPD_MASK, LQ_STP_UPD_SRC_FPI, LQ_STP_CON1);
 241 +
 242 +       /* set stp update speed */
 243 +       lq_stp_w32_mask(LQ_STP_MASK, LQ_STP_8HZ, LQ_STP_CON1);
 244 +
 245 +       /* adsl 0 and 1 stp are updated by the arc */
 246 +       lq_stp_w32_mask(0, LQ_STP_ADSL_SRC, LQ_STP_CON0);
 247 +
 248 +       lq_pmu_enable(PMU_LED);
 249 +       return 0;
 250 +}
 251 +
 252 +static int
 253 +lq_stp_probe(struct platform_device *pdev)
 254 +{
 255 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 256 +       int ret = 0;
 257 +       if (!res)
 258 +               return -ENOENT;
 259 +       res = request_mem_region(res->start, resource_size(res),
 260 +               dev_name(&pdev->dev));
 261 +       if (!res)
 262 +               return -EBUSY;
 263 +       virt = ioremap_nocache(res->start, resource_size(res));
 264 +       if(!virt)
 265 +       {
 266 +               ret = -ENOMEM;
 267 +               goto err_release_mem_region;
 268 +       }
 269 +       ret = gpiochip_add(&lq_stp_chip);
 270 +       if(!ret)
 271 +               return lq_stp_hw_init();
 272 +
 273 +       iounmap(virt);
 274 +err_release_mem_region:
 275 +       release_mem_region(res->start, resource_size(res));
 276 +       return ret;
 277 +}
 278 +
 279 +static struct platform_driver lq_stp_driver = {
 280 +       .probe = lq_stp_probe,
 281 +       .driver = {
 282 +               .name = "lq_stp",
 283 +               .owner = THIS_MODULE,
 284 +       },
 285 +};
 286 +
 287 +int __init
 288 +init_lq_stp(void)
 289 +{
 290 +       int ret = platform_driver_register(&lq_stp_driver);
 291 +       if (ret)
 292 +               printk(KERN_INFO
 293 +                       "lq_stp: error registering platfom driver");
 294 +       return ret;
 295 +}
 296 +
 297 +arch_initcall(init_lq_stp);
 298 --- /dev/null
 299 +++ b/arch/mips/lantiq/xway/mach-easy4010.c
 300 @@ -0,0 +1,79 @@
 301 +/*
 302 + *  This program is free software; you can redistribute it and/or modify it
 303 + *  under the terms of the GNU General Public License version 2 as published
 304 + *  by the Free Software Foundation.
 305 + *
 306 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 307 + */
 308 +
 309 +#include <linux/init.h>
 310 +#include <linux/platform_device.h>
 311 +#include <linux/leds.h>
 312 +#include <linux/gpio.h>
 313 +#include <linux/gpio_buttons.h>
 314 +#include <linux/mtd/mtd.h>
 315 +#include <linux/mtd/partitions.h>
 316 +#include <linux/mtd/physmap.h>
 317 +#include <linux/input.h>
 318 +
 319 +#include <machine.h>
 320 +
 321 +#include <xway.h>
 322 +#include <lantiq_platform.h>
 323 +
 324 +#include "devices.h"
 325 +
 326 +#ifdef CONFIG_MTD_PARTITIONS
 327 +static struct mtd_partition easy4010_partitions[] =
 328 +{
 329 +       {
 330 +               .name   = "uboot",
 331 +               .offset = 0x0,
 332 +               .size   = 0x20000,
 333 +       },
 334 +       {
 335 +               .name   = "uboot_env",
 336 +               .offset = 0x20000,
 337 +               .size   = 0x10000,
 338 +       },
 339 +       {
 340 +               .name   = "linux",
 341 +               .offset = 0x30000,
 342 +               .size   = 0x3D0000,
 343 +       },
 344 +};
 345 +#endif
 346 +
 347 +static struct physmap_flash_data easy4010_flash_data = {
 348 +#ifdef CONFIG_MTD_PARTITIONS
 349 +       .nr_parts       = ARRAY_SIZE(easy4010_partitions),
 350 +       .parts          = easy4010_partitions,
 351 +#endif
 352 +};
 353 +
 354 +static struct lq_pci_data lq_pci_data = {
 355 +       .clock      = PCI_CLOCK_INT,
 356 +       .req_mask   = 0xf,
 357 +};
 358 +
 359 +static struct lq_eth_data lq_eth_data = {
 360 +       .mii_mode = REV_MII_MODE,
 361 +};
 362 +
 363 +static void __init
 364 +easy4010_init(void)
 365 +{
 366 +       lq_register_gpio();
 367 +       lq_register_gpio_stp();
 368 +       lq_register_asc(0);
 369 +       lq_register_asc(1);
 370 +       lq_register_nor(&easy4010_flash_data);
 371 +       lq_register_wdt();
 372 +       lq_register_pci(&lq_pci_data);
 373 +       lq_register_ethernet(&lq_eth_data);
 374 +}
 375 +
 376 +MIPS_MACHINE(LANTIQ_MACH_EASY4010,
 377 +                       "EASY4010",
 378 +                       "EASY4010 Eval Board",
 379 +                       easy4010_init);
 380 --- /dev/null
 381 +++ b/arch/mips/lantiq/xway/mach-easy50712.c
 382 @@ -0,0 +1,79 @@
 383 +/*
 384 + *  This program is free software; you can redistribute it and/or modify it
 385 + *  under the terms of the GNU General Public License version 2 as published
 386 + *  by the Free Software Foundation.
 387 + *
 388 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 389 + */
 390 +
 391 +#include <linux/init.h>
 392 +#include <linux/platform_device.h>
 393 +#include <linux/leds.h>
 394 +#include <linux/gpio.h>
 395 +#include <linux/gpio_buttons.h>
 396 +#include <linux/mtd/mtd.h>
 397 +#include <linux/mtd/partitions.h>
 398 +#include <linux/mtd/physmap.h>
 399 +#include <linux/input.h>
 400 +
 401 +#include <machine.h>
 402 +
 403 +#include <xway.h>
 404 +#include <lantiq_platform.h>
 405 +
 406 +#include "devices.h"
 407 +
 408 +#ifdef CONFIG_MTD_PARTITIONS
 409 +static struct mtd_partition easy50712_partitions[] =
 410 +{
 411 +       {
 412 +               .name   = "uboot",
 413 +               .offset = 0x0,
 414 +               .size   = 0x20000,
 415 +       },
 416 +       {
 417 +               .name   = "uboot_env",
 418 +               .offset = 0x20000,
 419 +               .size   = 0x10000,
 420 +       },
 421 +       {
 422 +               .name   = "linux",
 423 +               .offset = 0x30000,
 424 +               .size   = 0x3D0000,
 425 +       },
 426 +};
 427 +#endif
 428 +
 429 +static struct physmap_flash_data easy50712_flash_data = {
 430 +#ifdef CONFIG_MTD_PARTITIONS
 431 +       .nr_parts       = ARRAY_SIZE(easy50712_partitions),
 432 +       .parts          = easy50712_partitions,
 433 +#endif
 434 +};
 435 +
 436 +static struct lq_pci_data lq_pci_data = {
 437 +       .clock      = PCI_CLOCK_INT,
 438 +       .req_mask   = 0xf,
 439 +};
 440 +
 441 +static struct lq_eth_data lq_eth_data = {
 442 +       .mii_mode = REV_MII_MODE,
 443 +};
 444 +
 445 +static void __init
 446 +easy50712_init(void)
 447 +{
 448 +       lq_register_asc(0);
 449 +       lq_register_asc(1);
 450 +       lq_register_gpio();
 451 +       lq_register_gpio_stp();
 452 +       lq_register_nor(&easy50712_flash_data);
 453 +       lq_register_wdt();
 454 +       lq_register_pci(&lq_pci_data);
 455 +       lq_register_ethernet(&lq_eth_data);
 456 +}
 457 +
 458 +MIPS_MACHINE(LANTIQ_MACH_EASY50712,
 459 +                       "EASY50712",
 460 +                       "EASY50712 Eval Board",
 461 +                       easy50712_init);
 462 --- /dev/null
 463 +++ b/arch/mips/lantiq/xway/mach-easy50812.c
 464 @@ -0,0 +1,78 @@
 465 +/*
 466 + *  This program is free software; you can redistribute it and/or modify it
 467 + *  under the terms of the GNU General Public License version 2 as published
 468 + *  by the Free Software Foundation.
 469 + *
 470 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 471 + */
 472 +
 473 +#include <linux/init.h>
 474 +#include <linux/platform_device.h>
 475 +#include <linux/leds.h>
 476 +#include <linux/gpio.h>
 477 +#include <linux/gpio_buttons.h>
 478 +#include <linux/mtd/mtd.h>
 479 +#include <linux/mtd/partitions.h>
 480 +#include <linux/mtd/physmap.h>
 481 +#include <linux/input.h>
 482 +
 483 +#include <machine.h>
 484 +
 485 +#include <xway.h>
 486 +#include <lantiq_platform.h>
 487 +
 488 +#include "devices.h"
 489 +
 490 +#ifdef CONFIG_MTD_PARTITIONS
 491 +static struct mtd_partition easy50812_partitions[] =
 492 +{
 493 +       {
 494 +               .name   = "uboot",
 495 +               .offset = 0x0,
 496 +               .size   = 0x40000,
 497 +       },
 498 +       {
 499 +               .name   = "uboot_env",
 500 +               .offset = 0x40000,
 501 +               .size   = 0x10000,
 502 +       },
 503 +       {
 504 +               .name   = "linux",
 505 +               .offset = 0x50000,
 506 +               .size   = 0x3B0000,
 507 +       },
 508 +};
 509 +#endif
 510 +
 511 +static struct physmap_flash_data easy50812_flash_data = {
 512 +#ifdef CONFIG_MTD_PARTITIONS
 513 +       .nr_parts       = ARRAY_SIZE(easy50812_partitions),
 514 +       .parts          = easy50812_partitions,
 515 +#endif
 516 +};
 517 +
 518 +static struct lq_pci_data lq_pci_data = {
 519 +       .clock      = PCI_CLOCK_INT,
 520 +       .req_mask   = 0xf,
 521 +};
 522 +
 523 +static struct lq_eth_data lq_eth_data = {
 524 +       .mii_mode = REV_MII_MODE,
 525 +};
 526 +
 527 +static void __init
 528 +easy50812_init(void)
 529 +{
 530 +       lq_register_gpio();
 531 +       lq_register_asc(0);
 532 +       lq_register_asc(1);
 533 +       lq_register_nor(&easy50812_flash_data);
 534 +       lq_register_wdt();
 535 +       lq_register_pci(&lq_pci_data);
 536 +       lq_register_ethernet(&lq_eth_data);
 537 +}
 538 +
 539 +MIPS_MACHINE(LANTIQ_MACH_EASY50812,
 540 +                       "EASY50812",
 541 +                       "EASY50812 Eval Board",
 542 +                       easy50812_init);
 543 --- /dev/null
 544 +++ b/arch/mips/lantiq/xway/prom.c
 545 @@ -0,0 +1,52 @@
 546 +/*
 547 + *  This program is free software; you can redistribute it and/or modify it
 548 + *  under the terms of the GNU General Public License version 2 as published
 549 + *  by the Free Software Foundation.
 550 + *
 551 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 552 + */
 553 +
 554 +#include <linux/module.h>
 555 +#include <linux/clk.h>
 556 +#include <asm/bootinfo.h>
 557 +#include <asm/time.h>
 558 +
 559 +#include <xway.h>
 560 +
 561 +#include "../prom.h"
 562 +
 563 +#define SOC_DANUBE             "Danube"
 564 +#define SOC_TWINPASS   "Twinpass"
 565 +#define SOC_AR9                        "AR9"
 566 +
 567 +void __init
 568 +lq_soc_detect(struct lq_soc_info *i)
 569 +{
 570 +       i->partnum = (lq_r32(LQ_MPS_CHIPID) & 0x0FFFFFFF) >> 12;
 571 +       i->rev = (lq_r32(LQ_MPS_CHIPID) & 0xF0000000) >> 28;
 572 +       switch (i->partnum)
 573 +       {
 574 +       case SOC_ID_DANUBE1:
 575 +       case SOC_ID_DANUBE2:
 576 +               i->name = SOC_DANUBE;
 577 +               i->type = SOC_TYPE_DANUBE;
 578 +               break;
 579 +
 580 +       case SOC_ID_TWINPASS:
 581 +               i->name = SOC_TWINPASS;
 582 +               i->type = SOC_TYPE_DANUBE;
 583 +               break;
 584 +
 585 +       case SOC_ID_ARX188:
 586 +       case SOC_ID_ARX168:
 587 +       case SOC_ID_ARX182:
 588 +               i->name = SOC_AR9;
 589 +               i->type = SOC_TYPE_AR9;
 590 +               break;
 591 +
 592 +       default:
 593 +               printk(KERN_ERR "unknown chiprev : 0x%08X\n", i->partnum);
 594 +               while(1) {      };
 595 +               break;
 596 +       }
 597 +}
 598 --- /dev/null
 599 +++ b/arch/mips/lantiq/xway/devices.c
 600 @@ -0,0 +1,278 @@
 601 +/*
 602 + *  This program is free software; you can redistribute it and/or modify it
 603 + *  under the terms of the GNU General Public License version 2 as published
 604 + *  by the Free Software Foundation.
 605 + *
 606 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 607 + */
 608 +
 609 +#include <linux/init.h>
 610 +#include <linux/module.h>
 611 +#include <linux/types.h>
 612 +#include <linux/string.h>
 613 +#include <linux/mtd/physmap.h>
 614 +#include <linux/kernel.h>
 615 +#include <linux/reboot.h>
 616 +#include <linux/platform_device.h>
 617 +#include <linux/leds.h>
 618 +#include <linux/etherdevice.h>
 619 +#include <linux/reboot.h>
 620 +#include <linux/time.h>
 621 +#include <linux/io.h>
 622 +#include <linux/gpio.h>
 623 +#include <linux/leds.h>
 624 +
 625 +#include <asm/bootinfo.h>
 626 +#include <asm/irq.h>
 627 +
 628 +#include <xway.h>
 629 +#include <xway_irq.h>
 630 +#include <lantiq_platform.h>
 631 +
 632 +#define IRQ_RES(resname,irq) {.name=#resname,.start=(irq),.flags=IORESOURCE_IRQ}
 633 +
 634 +/* gpio leds */
 635 +static struct gpio_led_platform_data lq_gpio_led_data;
 636 +
 637 +static struct platform_device lq_gpio_leds =
 638 +{
 639 +       .name = "leds-gpio",
 640 +       .dev = {
 641 +               .platform_data = (void *) &lq_gpio_led_data,
 642 +       }
 643 +};
 644 +
 645 +void __init
 646 +lq_register_gpio_leds(struct gpio_led *leds, int cnt)
 647 +{
 648 +       lq_gpio_led_data.leds = leds;
 649 +       lq_gpio_led_data.num_leds = cnt;
 650 +       platform_device_register(&lq_gpio_leds);
 651 +}
 652 +
 653 +/* serial to parallel conversion */
 654 +static struct resource lq_stp_resource =
 655 +{
 656 +       .name   = "stp",
 657 +       .start  = LQ_STP_BASE,
 658 +       .end    = LQ_STP_BASE + LQ_STP_SIZE - 1,
 659 +       .flags  = IORESOURCE_MEM,
 660 +};
 661 +
 662 +void __init
 663 +lq_register_gpio_stp(void)
 664 +{
 665 +       platform_device_register_simple("lq_stp", 0, &lq_stp_resource, 1);
 666 +}
 667 +
 668 +/* nor flash */
 669 +static struct resource lq_nor_resource =
 670 +{
 671 +       .name   = "nor",
 672 +       .start  = LQ_FLASH_START,
 673 +       .end    = LQ_FLASH_START + LQ_FLASH_MAX - 1,
 674 +       .flags  = IORESOURCE_MEM,
 675 +};
 676 +
 677 +static struct platform_device lq_nor =
 678 +{
 679 +       .name                   = "lq_nor",
 680 +       .resource               = &lq_nor_resource,
 681 +       .num_resources  = 1,
 682 +};
 683 +
 684 +void __init
 685 +lq_register_nor(struct physmap_flash_data *data)
 686 +{
 687 +       lq_nor.dev.platform_data = data;
 688 +       platform_device_register(&lq_nor);
 689 +}
 690 +
 691 +/* watchdog */
 692 +static struct resource lq_wdt_resource =
 693 +{
 694 +       .name   = "watchdog",
 695 +       .start  = LQ_WDT_BASE,
 696 +       .end    = LQ_WDT_BASE + LQ_WDT_SIZE - 1,
 697 +       .flags  = IORESOURCE_MEM,
 698 +};
 699 +
 700 +void __init
 701 +lq_register_wdt(void)
 702 +{
 703 +       platform_device_register_simple("lq_wdt", 0, &lq_wdt_resource, 1);
 704 +}
 705 +
 706 +/* gpio */
 707 +static struct resource lq_gpio_resource[] = {
 708 +       {
 709 +               .name   = "gpio0",
 710 +               .start  = LQ_GPIO0_BASE_ADDR,
 711 +               .end    = LQ_GPIO0_BASE_ADDR + LQ_GPIO_SIZE - 1,
 712 +               .flags  = IORESOURCE_MEM,
 713 +       }, {
 714 +               .name   = "gpio1",
 715 +               .start  = LQ_GPIO1_BASE_ADDR,
 716 +               .end    = LQ_GPIO1_BASE_ADDR + LQ_GPIO_SIZE - 1,
 717 +               .flags  = IORESOURCE_MEM,
 718 +       }
 719 +};
 720 +
 721 +void __init
 722 +lq_register_gpio(void)
 723 +{
 724 +       platform_device_register_simple("lq_gpio", 0, &lq_gpio_resource[0], 1);
 725 +       platform_device_register_simple("lq_gpio", 1, &lq_gpio_resource[1], 1);
 726 +}
 727 +
 728 +/* pci */
 729 +static struct platform_device lq_pci =
 730 +{
 731 +       .name                   = "lq_pci",
 732 +       .num_resources  = 0,
 733 +};
 734 +
 735 +void __init
 736 +lq_register_pci(struct lq_pci_data *data)
 737 +{
 738 +       lq_pci.dev.platform_data = data;
 739 +       platform_device_register(&lq_pci);
 740 +}
 741 +
 742 +/* ebu */
 743 +static struct resource lq_ebu_resource =
 744 +{
 745 +       .name   = "gpio_ebu",
 746 +       .start  = LQ_EBU_GPIO_START,
 747 +       .end    = LQ_EBU_GPIO_START + LQ_EBU_GPIO_SIZE - 1,
 748 +       .flags  = IORESOURCE_MEM,
 749 +};
 750 +
 751 +void __init
 752 +lq_register_gpio_ebu(unsigned int value)
 753 +{
 754 +       platform_device_register_simple("lq_ebu", 0, &lq_ebu_resource, 1);
 755 +}
 756 +
 757 +/* ethernet */
 758 +unsigned char lq_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 759 +
 760 +static int __init
 761 +lq_set_ethaddr(char *str)
 762 +{
 763 +       sscanf(&str[8], "0%02hhx:0%02hhx:0%02hhx:0%02hhx:0%02hhx:0%02hhx",
 764 +               &lq_ethaddr[0], &lq_ethaddr[1], &lq_ethaddr[2],
 765 +               &lq_ethaddr[3], &lq_ethaddr[4], &lq_ethaddr[5]);
 766 +       return 0;
 767 +}
 768 +__setup("ethaddr=", lq_set_ethaddr);
 769 +
 770 +static struct resource lq_ethernet_resources =
 771 +{
 772 +       .name   = "etop",
 773 +       .start  = LQ_PPE32_BASE_ADDR,
 774 +       .end    = LQ_PPE32_BASE_ADDR + LQ_PPE32_SIZE - 1,
 775 +       .flags  = IORESOURCE_MEM,
 776 +};
 777 +
 778 +static struct platform_device lq_ethernet =
 779 +{
 780 +       .name                   = "lq_etop",
 781 +       .resource               = &lq_ethernet_resources,
 782 +       .num_resources  = 1,
 783 +};
 784 +
 785 +void __init
 786 +lq_register_ethernet(struct lq_eth_data *eth)
 787 +{
 788 +       if(!eth)
 789 +               return;
 790 +       if(!eth->mac)
 791 +               eth->mac = lq_ethaddr;
 792 +       if(!is_valid_ether_addr(eth->mac))
 793 +               random_ether_addr(eth->mac);
 794 +       lq_ethernet.dev.platform_data = eth;
 795 +       platform_device_register(&lq_ethernet);
 796 +}
 797 +
 798 +/* tapi */
 799 +static struct resource mps_resources[] = {
 800 +       {
 801 +               .name = "voice-mem",
 802 +               .flags = IORESOURCE_MEM,
 803 +               .start = 0x1f107000,
 804 +               .end =   0x1f1073ff,
 805 +       },
 806 +       {
 807 +               .name = "voice-mailbox",
 808 +               .flags = IORESOURCE_MEM,
 809 +               .start = 0x1f200000,
 810 +               .end =   0x1f2007ff,
 811 +       },
 812 +};
 813 +
 814 +static struct platform_device mps_device = {
 815 +       .name = "mps",
 816 +       .resource = mps_resources,
 817 +       .num_resources = ARRAY_SIZE(mps_resources),
 818 +};
 819 +
 820 +static struct platform_device vmmc_device = {
 821 +       .name = "vmmc",
 822 +       .dev = {
 823 +               .parent = &mps_device.dev,
 824 +       },
 825 +};
 826 +
 827 +void __init
 828 +lq_register_tapi(void)
 829 +{
 830 +#define CP1_SIZE       (1 << 20)
 831 +       dma_addr_t dma;
 832 +       mps_device.dev.platform_data =
 833 +               (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
 834 +       platform_device_register(&mps_device);
 835 +       platform_device_register(&vmmc_device);
 836 +}
 837 +
 838 +/* asc ports */
 839 +static struct resource lq_asc0_resources[] =
 840 +{
 841 +       {
 842 +               .start  = LQ_ASC0_BASE,
 843 +               .end    = LQ_ASC0_BASE + LQ_ASC_SIZE - 1,
 844 +               .flags  = IORESOURCE_MEM,
 845 +       },
 846 +       IRQ_RES(tx, INT_NUM_IM3_IRL0),
 847 +       IRQ_RES(rx, INT_NUM_IM3_IRL0 + 1),
 848 +       IRQ_RES(err, INT_NUM_IM3_IRL0 + 2),
 849 +};
 850 +
 851 +static struct resource lq_asc1_resources[] =
 852 +{
 853 +       {
 854 +               .start  = LQ_ASC1_BASE,
 855 +               .end    = LQ_ASC1_BASE + LQ_ASC_SIZE - 1,
 856 +               .flags  = IORESOURCE_MEM,
 857 +       },
 858 +       IRQ_RES(tx, INT_NUM_IM3_IRL0 + 8),
 859 +       IRQ_RES(rx, INT_NUM_IM3_IRL0 + 9),
 860 +       IRQ_RES(err, INT_NUM_IM3_IRL0 + 10),
 861 +};
 862 +
 863 +void __init
 864 +lq_register_asc(int port)
 865 +{
 866 +       switch (port) {
 867 +       case 0:
 868 +               platform_device_register_simple("lq_asc", 0,
 869 +                       lq_asc0_resources, ARRAY_SIZE(lq_asc0_resources));
 870 +               break;
 871 +       case 1:
 872 +               platform_device_register_simple("lq_asc", 1,
 873 +                       lq_asc1_resources, ARRAY_SIZE(lq_asc1_resources));
 874 +               break;
 875 +       default:
 876 +               break;
 877 +       }
 878 +}
 879 --- /dev/null
 880 +++ b/arch/mips/lantiq/xway/devices.h
 881 @@ -0,0 +1,24 @@
 882 +/*
 883 + *  This program is free software; you can redistribute it and/or modify it
 884 + *  under the terms of the GNU General Public License version 2 as published
 885 + *  by the Free Software Foundation.
 886 + *
 887 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 888 + */
 889 +
 890 +#ifndef _LQ_DEVICES_H__
 891 +#define _LQ_DEVICES_H__
 892 +
 893 +#include <lantiq_platform.h>
 894 +
 895 +extern void __init lq_register_gpio(void);
 896 +extern void __init lq_register_gpio_stp(void);
 897 +extern void __init lq_register_gpio_ebu(unsigned int value);
 898 +extern void __init lq_register_gpio_leds(struct gpio_led *leds, int cnt);
 899 +extern void __init lq_register_pci(struct lq_pci_data *data);
 900 +extern void __init lq_register_nor(struct physmap_flash_data *data);
 901 +extern void __init lq_register_wdt(void);
 902 +extern void __init lq_register_ethernet(struct lq_eth_data *eth);
 903 +extern void __init lq_register_asc(int port);
 904 +
 905 +#endif
 906 --- /dev/null
 907 +++ b/arch/mips/lantiq/xway/dma.c
 908 @@ -0,0 +1,701 @@
 909 +#include <linux/module.h>
 910 +#include <linux/init.h>
 911 +#include <linux/sched.h>
 912 +#include <linux/kernel.h>
 913 +#include <linux/slab.h>
 914 +#include <linux/string.h>
 915 +#include <linux/timer.h>
 916 +#include <linux/fs.h>
 917 +#include <linux/errno.h>
 918 +#include <linux/stat.h>
 919 +#include <linux/mm.h>
 920 +#include <linux/tty.h>
 921 +#include <linux/selection.h>
 922 +#include <linux/kmod.h>
 923 +#include <linux/vmalloc.h>
 924 +#include <linux/interrupt.h>
 925 +#include <linux/delay.h>
 926 +#include <linux/uaccess.h>
 927 +#include <linux/errno.h>
 928 +#include <linux/io.h>
 929 +
 930 +#include <xway.h>
 931 +#include <xway_irq.h>
 932 +#include <xway_dma.h>
 933 +
 934 +#define LQ_DMA_CS                      ((u32 *)(LQ_DMA_BASE_ADDR + 0x18))
 935 +#define LQ_DMA_CIE                     ((u32 *)(LQ_DMA_BASE_ADDR + 0x2C))
 936 +#define LQ_DMA_IRNEN           ((u32 *)(LQ_DMA_BASE_ADDR + 0xf4))
 937 +#define LQ_DMA_CCTRL           ((u32 *)(LQ_DMA_BASE_ADDR + 0x1C))
 938 +#define LQ_DMA_CIS                     ((u32 *)(LQ_DMA_BASE_ADDR + 0x28))
 939 +#define LQ_DMA_CDLEN           ((u32 *)(LQ_DMA_BASE_ADDR + 0x24))
 940 +#define LQ_DMA_PS                      ((u32 *)(LQ_DMA_BASE_ADDR + 0x40))
 941 +#define LQ_DMA_PCTRL           ((u32 *)(LQ_DMA_BASE_ADDR + 0x44))
 942 +#define LQ_DMA_CTRL            ((u32 *)(LQ_DMA_BASE_ADDR + 0x10))
 943 +#define LQ_DMA_CPOLL           ((u32 *)(LQ_DMA_BASE_ADDR + 0x14))
 944 +#define LQ_DMA_CDBA            ((u32 *)(LQ_DMA_BASE_ADDR + 0x20))
 945 +
 946 +/*25 descriptors for each dma channel,4096/8/20=25.xx*/
 947 +#define LQ_DMA_DESCRIPTOR_OFFSET 25
 948 +
 949 +#define MAX_DMA_DEVICE_NUM  6  /*max ports connecting to dma */
 950 +#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
 951 +#define DMA_INT_BUDGET      100        /*budget for interrupt handling */
 952 +#define DMA_POLL_COUNTER    4  /*fix me, set the correct counter value here! */
 953 +
 954 +extern void lq_mask_and_ack_irq(unsigned int irq_nr);
 955 +extern void lq_enable_irq(unsigned int irq_nr);
 956 +extern void lq_disable_irq(unsigned int irq_nr);
 957 +
 958 +u64 *g_desc_list;
 959 +struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
 960 +struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
 961 +
 962 +static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
 963 +       { "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
 964 +
 965 +struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
 966 +       {"PPE", LQ_DMA_RX, 0, LQ_DMA_CH0_INT, 0},
 967 +       {"PPE", LQ_DMA_TX, 0, LQ_DMA_CH1_INT, 0},
 968 +       {"PPE", LQ_DMA_RX, 1, LQ_DMA_CH2_INT, 1},
 969 +       {"PPE", LQ_DMA_TX, 1, LQ_DMA_CH3_INT, 1},
 970 +       {"PPE", LQ_DMA_RX, 2, LQ_DMA_CH4_INT, 2},
 971 +       {"PPE", LQ_DMA_TX, 2, LQ_DMA_CH5_INT, 2},
 972 +       {"PPE", LQ_DMA_RX, 3, LQ_DMA_CH6_INT, 3},
 973 +       {"PPE", LQ_DMA_TX, 3, LQ_DMA_CH7_INT, 3},
 974 +       {"DEU", LQ_DMA_RX, 0, LQ_DMA_CH8_INT, 0},
 975 +       {"DEU", LQ_DMA_TX, 0, LQ_DMA_CH9_INT, 0},
 976 +       {"DEU", LQ_DMA_RX, 1, LQ_DMA_CH10_INT, 1},
 977 +       {"DEU", LQ_DMA_TX, 1, LQ_DMA_CH11_INT, 1},
 978 +       {"SPI", LQ_DMA_RX, 0, LQ_DMA_CH12_INT, 0},
 979 +       {"SPI", LQ_DMA_TX, 0, LQ_DMA_CH13_INT, 0},
 980 +       {"SDIO", LQ_DMA_RX, 0, LQ_DMA_CH14_INT, 0},
 981 +       {"SDIO", LQ_DMA_TX, 0, LQ_DMA_CH15_INT, 0},
 982 +       {"MCTRL0", LQ_DMA_RX, 0, LQ_DMA_CH16_INT, 0},
 983 +       {"MCTRL0", LQ_DMA_TX, 0, LQ_DMA_CH17_INT, 0},
 984 +       {"MCTRL1", LQ_DMA_RX, 1, LQ_DMA_CH18_INT, 1},
 985 +       {"MCTRL1", LQ_DMA_TX, 1, LQ_DMA_CH19_INT, 1}
 986 +};
 987 +
 988 +struct dma_chan_map *chan_map = default_dma_map;
 989 +volatile u32 g_lq_dma_int_status;
 990 +volatile int g_lq_dma_in_process; /* 0=not in process, 1=in process */
 991 +
 992 +void do_dma_tasklet(unsigned long);
 993 +DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0);
 994 +
 995 +u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
 996 +{
 997 +       u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL);
 998 +
 999 +       *byte_offset = 0;
1000 +
1001 +       return buffer;
1002 +}
1003 +
1004 +void common_buffer_free(u8 *dataptr, void *opt)
1005 +{
1006 +       kfree(dataptr);
1007 +}
1008 +
1009 +void enable_ch_irq(struct dma_channel_info *pCh)
1010 +{
1011 +       int chan_no = (int)(pCh - dma_chan);
1012 +       unsigned long flag;
1013 +
1014 +       local_irq_save(flag);
1015 +       lq_w32(chan_no, LQ_DMA_CS);
1016 +       lq_w32(0x4a, LQ_DMA_CIE);
1017 +       lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1018 +       local_irq_restore(flag);
1019 +       lq_enable_irq(pCh->irq);
1020 +}
1021 +
1022 +void disable_ch_irq(struct dma_channel_info *pCh)
1023 +{
1024 +       unsigned long flag;
1025 +       int chan_no = (int) (pCh - dma_chan);
1026 +
1027 +       local_irq_save(flag);
1028 +       g_lq_dma_int_status &= ~(1 << chan_no);
1029 +       lq_w32(chan_no, LQ_DMA_CS);
1030 +       lq_w32(0, LQ_DMA_CIE);
1031 +       lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN);
1032 +       local_irq_restore(flag);
1033 +       lq_mask_and_ack_irq(pCh->irq);
1034 +}
1035 +
1036 +void open_chan(struct dma_channel_info *pCh)
1037 +{
1038 +       unsigned long flag;
1039 +       int chan_no = (int)(pCh - dma_chan);
1040 +
1041 +       local_irq_save(flag);
1042 +       lq_w32(chan_no, LQ_DMA_CS);
1043 +       lq_w32(lq_r32(LQ_DMA_CCTRL) | 1, LQ_DMA_CCTRL);
1044 +       if (pCh->dir == LQ_DMA_RX)
1045 +               enable_ch_irq(pCh);
1046 +       local_irq_restore(flag);
1047 +}
1048 +
1049 +void close_chan(struct dma_channel_info *pCh)
1050 +{
1051 +       unsigned long flag;
1052 +       int chan_no = (int) (pCh - dma_chan);
1053 +
1054 +       local_irq_save(flag);
1055 +       lq_w32(chan_no, LQ_DMA_CS);
1056 +       lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1057 +       disable_ch_irq(pCh);
1058 +       local_irq_restore(flag);
1059 +}
1060 +
1061 +void reset_chan(struct dma_channel_info *pCh)
1062 +{
1063 +       int chan_no = (int) (pCh - dma_chan);
1064 +
1065 +       lq_w32(chan_no, LQ_DMA_CS);
1066 +       lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1067 +}
1068 +
1069 +void rx_chan_intr_handler(int chan_no)
1070 +{
1071 +       struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
1072 +       struct dma_channel_info *pCh = &dma_chan[chan_no];
1073 +       struct rx_desc *rx_desc_p;
1074 +       int tmp;
1075 +       unsigned long flag;
1076 +
1077 +       /*handle command complete interrupt */
1078 +       rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc;
1079 +       if (rx_desc_p->status.field.OWN == CPU_OWN
1080 +           && rx_desc_p->status.field.C
1081 +           && rx_desc_p->status.field.data_length < 1536){
1082 +               /* Every thing is correct, then we inform the upper layer */
1083 +               pDev->current_rx_chan = pCh->rel_chan_no;
1084 +               if (pDev->intr_handler)
1085 +                       pDev->intr_handler(pDev, RCV_INT);
1086 +               pCh->weight--;
1087 +       } else {
1088 +               local_irq_save(flag);
1089 +               tmp = lq_r32(LQ_DMA_CS);
1090 +               lq_w32(chan_no, LQ_DMA_CS);
1091 +               lq_w32(lq_r32(LQ_DMA_CIS) | 0x7e, LQ_DMA_CIS);
1092 +               lq_w32(tmp, LQ_DMA_CS);
1093 +               g_lq_dma_int_status &= ~(1 << chan_no);
1094 +               local_irq_restore(flag);
1095 +               lq_enable_irq(dma_chan[chan_no].irq);
1096 +       }
1097 +}
1098 +
1099 +inline void tx_chan_intr_handler(int chan_no)
1100 +{
1101 +       struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
1102 +       struct dma_channel_info *pCh = &dma_chan[chan_no];
1103 +       int tmp;
1104 +       unsigned long flag;
1105 +
1106 +       local_irq_save(flag);
1107 +       tmp = lq_r32(LQ_DMA_CS);
1108 +       lq_w32(chan_no, LQ_DMA_CS);
1109 +       lq_w32(lq_r32(LQ_DMA_CIS) | 0x7e, LQ_DMA_CIS);
1110 +       lq_w32(tmp, LQ_DMA_CS);
1111 +       g_lq_dma_int_status &= ~(1 << chan_no);
1112 +       local_irq_restore(flag);
1113 +       pDev->current_tx_chan = pCh->rel_chan_no;
1114 +       if (pDev->intr_handler)
1115 +               pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
1116 +}
1117 +
1118 +void do_dma_tasklet(unsigned long unused)
1119 +{
1120 +       int i;
1121 +       int chan_no = 0;
1122 +       int budget = DMA_INT_BUDGET;
1123 +       int weight = 0;
1124 +       unsigned long flag;
1125 +
1126 +       while (g_lq_dma_int_status) {
1127 +               if (budget-- < 0) {
1128 +                       tasklet_schedule(&dma_tasklet);
1129 +                       return;
1130 +               }
1131 +               chan_no = -1;
1132 +               weight = 0;
1133 +               for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1134 +                       if ((g_lq_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) {
1135 +                               if (dma_chan[i].weight > weight) {
1136 +                                       chan_no = i;
1137 +                                       weight = dma_chan[chan_no].weight;
1138 +                               }
1139 +                       }
1140 +               }
1141 +
1142 +               if (chan_no >= 0) {
1143 +                       if (chan_map[chan_no].dir == LQ_DMA_RX)
1144 +                               rx_chan_intr_handler(chan_no);
1145 +                       else
1146 +                               tx_chan_intr_handler(chan_no);
1147 +               } else {
1148 +                       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
1149 +                               dma_chan[i].weight = dma_chan[i].default_weight;
1150 +               }
1151 +       }
1152 +
1153 +       local_irq_save(flag);
1154 +       g_lq_dma_in_process = 0;
1155 +       if (g_lq_dma_int_status) {
1156 +               g_lq_dma_in_process = 1;
1157 +               tasklet_schedule(&dma_tasklet);
1158 +       }
1159 +       local_irq_restore(flag);
1160 +}
1161 +
1162 +irqreturn_t dma_interrupt(int irq, void *dev_id)
1163 +{
1164 +       struct dma_channel_info *pCh;
1165 +       int chan_no = 0;
1166 +       int tmp;
1167 +
1168 +       pCh = (struct dma_channel_info *)dev_id;
1169 +       chan_no = (int)(pCh - dma_chan);
1170 +       if (chan_no < 0 || chan_no > 19)
1171 +               BUG();
1172 +
1173 +       tmp = lq_r32(LQ_DMA_IRNEN);
1174 +       lq_w32(0, LQ_DMA_IRNEN);
1175 +       g_lq_dma_int_status |= 1 << chan_no;
1176 +       lq_w32(tmp, LQ_DMA_IRNEN);
1177 +       lq_mask_and_ack_irq(irq);
1178 +
1179 +       if (!g_lq_dma_in_process) {
1180 +               g_lq_dma_in_process = 1;
1181 +               tasklet_schedule(&dma_tasklet);
1182 +       }
1183 +
1184 +       return IRQ_HANDLED;
1185 +}
1186 +
1187 +struct dma_device_info *dma_device_reserve(char *dev_name)
1188 +{
1189 +       int i;
1190 +
1191 +       for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
1192 +               if (strcmp(dev_name, dma_devs[i].device_name) == 0) {
1193 +                       if (dma_devs[i].reserved)
1194 +                               return NULL;
1195 +                       dma_devs[i].reserved = 1;
1196 +                       break;
1197 +               }
1198 +       }
1199 +
1200 +       return &dma_devs[i];
1201 +}
1202 +EXPORT_SYMBOL(dma_device_reserve);
1203 +
1204 +void dma_device_release(struct dma_device_info *dev)
1205 +{
1206 +       dev->reserved = 0;
1207 +}
1208 +EXPORT_SYMBOL(dma_device_release);
1209 +
1210 +void dma_device_register(struct dma_device_info *dev)
1211 +{
1212 +       int i, j;
1213 +       int chan_no = 0;
1214 +       u8 *buffer;
1215 +       int byte_offset;
1216 +       unsigned long flag;
1217 +       struct dma_device_info *pDev;
1218 +       struct dma_channel_info *pCh;
1219 +       struct rx_desc *rx_desc_p;
1220 +       struct tx_desc *tx_desc_p;
1221 +
1222 +       for (i = 0; i < dev->max_tx_chan_num; i++) {
1223 +               pCh = dev->tx_chan[i];
1224 +               if (pCh->control == LQ_DMA_CH_ON) {
1225 +                       chan_no = (int)(pCh - dma_chan);
1226 +                       for (j = 0; j < pCh->desc_len; j++) {
1227 +                               tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
1228 +                               memset(tx_desc_p, 0, sizeof(struct tx_desc));
1229 +                       }
1230 +                       local_irq_save(flag);
1231 +                       lq_w32(chan_no, LQ_DMA_CS);
1232 +                       /* check if the descriptor length is changed */
1233 +                       if (lq_r32(LQ_DMA_CDLEN) != pCh->desc_len)
1234 +                               lq_w32(pCh->desc_len, LQ_DMA_CDLEN);
1235 +
1236 +                       lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1237 +                       lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1238 +                       while (lq_r32(LQ_DMA_CCTRL) & 2)
1239 +                               ;
1240 +                       lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1241 +                       lq_w32(0x30100, LQ_DMA_CCTRL); /* reset and enable channel,enable channel later */
1242 +                       local_irq_restore(flag);
1243 +               }
1244 +       }
1245 +
1246 +       for (i = 0; i < dev->max_rx_chan_num; i++) {
1247 +               pCh = dev->rx_chan[i];
1248 +               if (pCh->control == LQ_DMA_CH_ON) {
1249 +                       chan_no = (int)(pCh - dma_chan);
1250 +
1251 +                       for (j = 0; j < pCh->desc_len; j++) {
1252 +                               rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
1253 +                               pDev = (struct dma_device_info *)(pCh->dma_dev);
1254 +                               buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
1255 +                               if (!buffer)
1256 +                                       break;
1257 +
1258 +                               dma_cache_inv((unsigned long) buffer, pCh->packet_size);
1259 +
1260 +                               rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
1261 +                               rx_desc_p->status.word = 0;
1262 +                               rx_desc_p->status.field.byte_offset = byte_offset;
1263 +                               rx_desc_p->status.field.OWN = DMA_OWN;
1264 +                               rx_desc_p->status.field.data_length = pCh->packet_size;
1265 +                       }
1266 +
1267 +                       local_irq_save(flag);
1268 +                       lq_w32(chan_no, LQ_DMA_CS);
1269 +                       /* check if the descriptor length is changed */
1270 +                       if (lq_r32(LQ_DMA_CDLEN) != pCh->desc_len)
1271 +                               lq_w32(pCh->desc_len, LQ_DMA_CDLEN);
1272 +                       lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1273 +                       lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1274 +                       while (lq_r32(LQ_DMA_CCTRL) & 2)
1275 +                               ;
1276 +                       lq_w32(0x0a, LQ_DMA_CIE); /* fix me, should enable all the interrupts here? */
1277 +                       lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1278 +                       lq_w32(0x30000, LQ_DMA_CCTRL);
1279 +                       local_irq_restore(flag);
1280 +                       lq_enable_irq(dma_chan[chan_no].irq);
1281 +               }
1282 +       }
1283 +}
1284 +EXPORT_SYMBOL(dma_device_register);
1285 +
1286 +void dma_device_unregister(struct dma_device_info *dev)
1287 +{
1288 +       int i, j;
1289 +       int chan_no;
1290 +       struct dma_channel_info *pCh;
1291 +       struct rx_desc *rx_desc_p;
1292 +       struct tx_desc *tx_desc_p;
1293 +       unsigned long flag;
1294 +
1295 +       for (i = 0; i < dev->max_tx_chan_num; i++) {
1296 +               pCh = dev->tx_chan[i];
1297 +               if (pCh->control == LQ_DMA_CH_ON) {
1298 +                       chan_no = (int)(dev->tx_chan[i] - dma_chan);
1299 +                       local_irq_save(flag);
1300 +                       lq_w32(chan_no, LQ_DMA_CS);
1301 +                       pCh->curr_desc = 0;
1302 +                       pCh->prev_desc = 0;
1303 +                       pCh->control = LQ_DMA_CH_OFF;
1304 +                       lq_w32(0, LQ_DMA_CIE); /* fix me, should disable all the interrupts here? */
1305 +                       lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN); /* disable interrupts */
1306 +                       lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1307 +                       while (lq_r32(LQ_DMA_CCTRL) & 1)
1308 +                               ;
1309 +                       local_irq_restore(flag);
1310 +
1311 +                       for (j = 0; j < pCh->desc_len; j++) {
1312 +                               tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
1313 +                               if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
1314 +                                               || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) {
1315 +                                       dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]);
1316 +                               }
1317 +                               tx_desc_p->status.field.OWN = CPU_OWN;
1318 +                               memset(tx_desc_p, 0, sizeof(struct tx_desc));
1319 +                       }
1320 +                       /* TODO should free buffer that is not transferred by dma */
1321 +               }
1322 +       }
1323 +
1324 +       for (i = 0; i < dev->max_rx_chan_num; i++) {
1325 +               pCh = dev->rx_chan[i];
1326 +               chan_no = (int)(dev->rx_chan[i] - dma_chan);
1327 +               lq_disable_irq(pCh->irq);
1328 +
1329 +               local_irq_save(flag);
1330 +               g_lq_dma_int_status &= ~(1 << chan_no);
1331 +               pCh->curr_desc = 0;
1332 +               pCh->prev_desc = 0;
1333 +               pCh->control = LQ_DMA_CH_OFF;
1334 +
1335 +               lq_w32(chan_no, LQ_DMA_CS);
1336 +               lq_w32(0, LQ_DMA_CIE); /* fix me, should disable all the interrupts here? */
1337 +               lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN); /* disable interrupts */
1338 +               lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1339 +               while (lq_r32(LQ_DMA_CCTRL) & 1)
1340 +                       ;
1341 +
1342 +               local_irq_restore(flag);
1343 +               for (j = 0; j < pCh->desc_len; j++) {
1344 +                       rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
1345 +                       if ((rx_desc_p->status.field.OWN == CPU_OWN
1346 +                            && rx_desc_p->status.field.C)
1347 +                           || (rx_desc_p->status.field.OWN == DMA_OWN
1348 +                               && rx_desc_p->status.field.data_length > 0)) {
1349 +                               dev->buffer_free((u8 *)
1350 +                                                __va(rx_desc_p->Data_Pointer),
1351 +                                                (void *) pCh->opt[j]);
1352 +                       }
1353 +               }
1354 +       }
1355 +}
1356 +EXPORT_SYMBOL(dma_device_unregister);
1357 +
1358 +int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
1359 +{
1360 +       u8 *buf;
1361 +       int len;
1362 +       int byte_offset = 0;
1363 +       void *p = NULL;
1364 +       struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
1365 +       struct rx_desc *rx_desc_p;
1366 +
1367 +       /* get the rx data first */
1368 +       rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
1369 +       if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
1370 +               return 0;
1371 +
1372 +       buf = (u8 *) __va(rx_desc_p->Data_Pointer);
1373 +       *(u32 *)dataptr = (u32)buf;
1374 +       len = rx_desc_p->status.field.data_length;
1375 +
1376 +       if (opt)
1377 +               *(int *)opt = (int)pCh->opt[pCh->curr_desc];
1378 +
1379 +       /* replace with a new allocated buffer */
1380 +       buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
1381 +
1382 +       if (buf) {
1383 +               dma_cache_inv((unsigned long) buf, pCh->packet_size);
1384 +               pCh->opt[pCh->curr_desc] = p;
1385 +               wmb();
1386 +
1387 +               rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
1388 +               rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
1389 +               wmb();
1390 +       } else {
1391 +               *(u32 *) dataptr = 0;
1392 +               if (opt)
1393 +                       *(int *) opt = 0;
1394 +               len = 0;
1395 +       }
1396 +
1397 +       /* increase the curr_desc pointer */
1398 +       pCh->curr_desc++;
1399 +       if (pCh->curr_desc == pCh->desc_len)
1400 +               pCh->curr_desc = 0;
1401 +
1402 +       return len;
1403 +}
1404 +EXPORT_SYMBOL(dma_device_read);
1405 +
1406 +int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt)
1407 +{
1408 +       unsigned long flag;
1409 +       u32 tmp, byte_offset;
1410 +       struct dma_channel_info *pCh;
1411 +       int chan_no;
1412 +       struct tx_desc *tx_desc_p;
1413 +       local_irq_save(flag);
1414 +
1415 +       pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
1416 +       chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
1417 +
1418 +       tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
1419 +       while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
1420 +               dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
1421 +               memset(tx_desc_p, 0, sizeof(struct tx_desc));
1422 +               pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
1423 +               tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
1424 +       }
1425 +       tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc;
1426 +       /* Check whether this descriptor is available */
1427 +       if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) {
1428 +               /* if not, the tell the upper layer device */
1429 +               dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
1430 +               local_irq_restore(flag);
1431 +               printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
1432 +
1433 +               return 0;
1434 +       }
1435 +       pCh->opt[pCh->curr_desc] = opt;
1436 +       /* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
1437 +       byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
1438 +       dma_cache_wback((unsigned long) dataptr, len);
1439 +       wmb();
1440 +       tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
1441 +       wmb();
1442 +       tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
1443 +       wmb();
1444 +
1445 +       pCh->curr_desc++;
1446 +       if (pCh->curr_desc == pCh->desc_len)
1447 +               pCh->curr_desc = 0;
1448 +
1449 +       /*Check whether this descriptor is available */
1450 +       tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
1451 +       if (tx_desc_p->status.field.OWN == DMA_OWN) {
1452 +               /*if not , the tell the upper layer device */
1453 +               dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
1454 +       }
1455 +
1456 +       lq_w32(chan_no, LQ_DMA_CS);
1457 +       tmp = lq_r32(LQ_DMA_CCTRL);
1458 +
1459 +       if (!(tmp & 1))
1460 +               pCh->open(pCh);
1461 +
1462 +       local_irq_restore(flag);
1463 +
1464 +       return len;
1465 +}
1466 +EXPORT_SYMBOL(dma_device_write);
1467 +
1468 +int map_dma_chan(struct dma_chan_map *map)
1469 +{
1470 +       int i, j;
1471 +       int result;
1472 +
1473 +       for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
1474 +               strcpy(dma_devs[i].device_name, global_device_name[i]);
1475 +
1476 +       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1477 +               dma_chan[i].irq = map[i].irq;
1478 +               result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]);
1479 +               if (result) {
1480 +                       printk(KERN_WARNING "error, cannot get dma_irq!\n");
1481 +                       free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
1482 +
1483 +                       return -EFAULT;
1484 +               }
1485 +       }
1486 +
1487 +       for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
1488 +               dma_devs[i].num_tx_chan = 0;    /*set default tx channel number to be one */
1489 +               dma_devs[i].num_rx_chan = 0;    /*set default rx channel number to be one */
1490 +               dma_devs[i].max_rx_chan_num = 0;
1491 +               dma_devs[i].max_tx_chan_num = 0;
1492 +               dma_devs[i].buffer_alloc = &common_buffer_alloc;
1493 +               dma_devs[i].buffer_free = &common_buffer_free;
1494 +               dma_devs[i].intr_handler = NULL;
1495 +               dma_devs[i].tx_burst_len = 4;
1496 +               dma_devs[i].rx_burst_len = 4;
1497 +               if (i == 0) {
1498 +                       lq_w32(0, LQ_DMA_PS);
1499 +                       lq_w32(lq_r32(LQ_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), LQ_DMA_PCTRL);   /*enable dma drop */
1500 +               }
1501 +
1502 +               if (i == 1) {
1503 +                       lq_w32(1, LQ_DMA_PS);
1504 +                       lq_w32(0x14, LQ_DMA_PCTRL);     /*deu port setting */
1505 +               }
1506 +
1507 +               for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
1508 +                       dma_chan[j].byte_offset = 0;
1509 +                       dma_chan[j].open = &open_chan;
1510 +                       dma_chan[j].close = &close_chan;
1511 +                       dma_chan[j].reset = &reset_chan;
1512 +                       dma_chan[j].enable_irq = &enable_ch_irq;
1513 +                       dma_chan[j].disable_irq = &disable_ch_irq;
1514 +                       dma_chan[j].rel_chan_no = map[j].rel_chan_no;
1515 +                       dma_chan[j].control = LQ_DMA_CH_OFF;
1516 +                       dma_chan[j].default_weight = LQ_DMA_CH_DEFAULT_WEIGHT;
1517 +                       dma_chan[j].weight = dma_chan[j].default_weight;
1518 +                       dma_chan[j].curr_desc = 0;
1519 +                       dma_chan[j].prev_desc = 0;
1520 +               }
1521 +
1522 +               for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
1523 +                       if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) {
1524 +                               if (map[j].dir == LQ_DMA_RX) {
1525 +                                       dma_chan[j].dir = LQ_DMA_RX;
1526 +                                       dma_devs[i].max_rx_chan_num++;
1527 +                                       dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
1528 +                                       dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
1529 +                                       dma_chan[j].dma_dev = (void *)&dma_devs[i];
1530 +                               } else if (map[j].dir == LQ_DMA_TX) {
1531 +                                       /*TX direction */
1532 +                                       dma_chan[j].dir = LQ_DMA_TX;
1533 +                                       dma_devs[i].max_tx_chan_num++;
1534 +                                       dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
1535 +                                       dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
1536 +                                       dma_chan[j].dma_dev = (void *)&dma_devs[i];
1537 +                               } else {
1538 +                                       printk(KERN_WARNING "WRONG DMA MAP!\n");
1539 +                               }
1540 +                       }
1541 +               }
1542 +       }
1543 +
1544 +       return 0;
1545 +}
1546 +
1547 +void dma_chip_init(void)
1548 +{
1549 +       int i;
1550 +
1551 +       /* enable DMA from PMU */
1552 +       lq_pmu_enable(PMU_DMA);
1553 +
1554 +       /* reset DMA */
1555 +       lq_w32(lq_r32(LQ_DMA_CTRL) | 1, LQ_DMA_CTRL);
1556 +
1557 +       /* disable all interrupts */
1558 +       lq_w32(0, LQ_DMA_IRNEN);
1559 +
1560 +       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1561 +               lq_w32(i, LQ_DMA_CS);
1562 +               lq_w32(0x2, LQ_DMA_CCTRL);
1563 +               lq_w32(0x80000040, LQ_DMA_CPOLL);
1564 +               lq_w32(lq_r32(LQ_DMA_CCTRL) & ~0x1, LQ_DMA_CCTRL);
1565 +       }
1566 +}
1567 +
1568 +int lq_dma_init(void)
1569 +{
1570 +       int i;
1571 +
1572 +       dma_chip_init();
1573 +
1574 +       if (map_dma_chan(default_dma_map))
1575 +               BUG();
1576 +
1577 +       g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA));
1578 +
1579 +       if (g_desc_list == NULL) {
1580 +               printk(KERN_WARNING "no memory for desriptor\n");
1581 +               return -ENOMEM;
1582 +       }
1583 +
1584 +       memset(g_desc_list, 0, PAGE_SIZE);
1585 +
1586 +       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1587 +               dma_chan[i].desc_base = (u32)g_desc_list + i * LQ_DMA_DESCRIPTOR_OFFSET * 8;
1588 +               dma_chan[i].curr_desc = 0;
1589 +               dma_chan[i].desc_len = LQ_DMA_DESCRIPTOR_OFFSET;
1590 +
1591 +               lq_w32(i, LQ_DMA_CS);
1592 +               lq_w32((u32)CPHYSADDR(dma_chan[i].desc_base), LQ_DMA_CDBA);
1593 +               lq_w32(dma_chan[i].desc_len, LQ_DMA_CDLEN);
1594 +       }
1595 +       return 0;
1596 +}
1597 +
1598 +arch_initcall(lq_dma_init);
1599 +
1600 +void dma_cleanup(void)
1601 +{
1602 +       int i;
1603 +
1604 +       free_page(KSEG0ADDR((unsigned long) g_desc_list));
1605 +       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
1606 +               free_irq(dma_chan[i].irq, (void  *)&dma_interrupt);
1607 +}
1608 +
1609 +MODULE_LICENSE("GPL");
1610 --- /dev/null
1611 +++ b/arch/mips/lantiq/xway/pmu.c
1612 @@ -0,0 +1,36 @@
1613 +/*
1614 + *  This program is free software; you can redistribute it and/or modify it
1615 + *  under the terms of the GNU General Public License version 2 as published
1616 + *  by the Free Software Foundation.
1617 + *
1618 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1619 + */
1620 +
1621 +#include <linux/kernel.h>
1622 +#include <linux/module.h>
1623 +#include <linux/version.h>
1624 +
1625 +#include <xway.h>
1626 +
1627 +#define LQ_PMU_PWDCR        ((u32 *)(LQ_PMU_BASE_ADDR + 0x001C))
1628 +#define LQ_PMU_PWDSR        ((u32 *)(LQ_PMU_BASE_ADDR + 0x0020))
1629 +
1630 +void
1631 +lq_pmu_enable(unsigned int module)
1632 +{
1633 +       int err = 1000000;
1634 +
1635 +       lq_w32(lq_r32(LQ_PMU_PWDCR) & ~module, LQ_PMU_PWDCR);
1636 +       while (--err && (lq_r32(LQ_PMU_PWDSR) & module));
1637 +
1638 +       if (!err)
1639 +               panic("activating PMU module failed!");
1640 +}
1641 +EXPORT_SYMBOL(lq_pmu_enable);
1642 +
1643 +void
1644 +lq_pmu_disable(unsigned int module)
1645 +{
1646 +       lq_w32(lq_r32(LQ_PMU_PWDCR) | module, LQ_PMU_PWDCR);
1647 +}
1648 +EXPORT_SYMBOL(lq_pmu_disable);
1649 --- /dev/null
1650 +++ b/arch/mips/lantiq/xway/timer.c
1651 @@ -0,0 +1,828 @@
1652 +#include <linux/kernel.h>
1653 +#include <linux/module.h>
1654 +#include <linux/version.h>
1655 +#include <linux/types.h>
1656 +#include <linux/fs.h>
1657 +#include <linux/miscdevice.h>
1658 +#include <linux/init.h>
1659 +#include <linux/uaccess.h>
1660 +#include <linux/unistd.h>
1661 +#include <linux/errno.h>
1662 +#include <linux/interrupt.h>
1663 +#include <linux/sched.h>
1664 +
1665 +#include <asm/irq.h>
1666 +#include <asm/div64.h>
1667 +
1668 +#include <xway.h>
1669 +#include <xway_irq.h>
1670 +#include <lantiq_timer.h>
1671 +
1672 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
1673 +
1674 +#ifdef TIMER1A
1675 +#define FIRST_TIMER                    TIMER1A
1676 +#else
1677 +#define FIRST_TIMER                    2
1678 +#endif
1679 +
1680 +/*
1681 + *  GPTC divider is set or not.
1682 + */
1683 +#define GPTU_CLC_RMC_IS_SET            0
1684 +
1685 +/*
1686 + *  Timer Interrupt (IRQ)
1687 + */
1688 +/*  Must be adjusted when ICU driver is available */
1689 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
1690 +
1691 +/*
1692 + *  Bits Operation
1693 + */
1694 +#define GET_BITS(x, msb, lsb)          \
1695 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
1696 +#define SET_BITS(x, msb, lsb, value)   \
1697 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
1698 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
1699 +
1700 +/*
1701 + *  GPTU Register Mapping
1702 + */
1703 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
1704 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
1705 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
1706 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
1707 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
1708 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
1709 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
1710 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
1711 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
1712 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
1713 +
1714 +/*
1715 + *  Clock Control Register
1716 + */
1717 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
1718 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
1719 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
1720 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
1721 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
1722 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
1723 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
1724 +
1725 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
1726 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
1727 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
1728 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
1729 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
1730 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
1731 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
1732 +
1733 +/*
1734 + *  ID Register
1735 + */
1736 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
1737 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
1738 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
1739 +
1740 +/*
1741 + *  Control Register of Timer/Counter nX
1742 + *    n is the index of block (1 based index)
1743 + *    X is either A or B
1744 + */
1745 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
1746 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
1747 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
1748 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
1749 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
1750 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
1751 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
1752 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
1753 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
1754 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
1755 +
1756 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
1757 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
1758 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
1759 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
1760 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
1761 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
1762 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
1763 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
1764 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
1765 +
1766 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
1767 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
1768 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
1769 +
1770 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
1771 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
1772 +
1773 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
1774 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
1775 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
1776 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
1777 +#define TIMER_FLAG_NONE_EDGE           0x0000
1778 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
1779 +#define TIMER_FLAG_REAL                        0x0000
1780 +#define TIMER_FLAG_INVERT              0x0040
1781 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
1782 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
1783 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
1784 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
1785 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
1786 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
1787 +
1788 +struct timer_dev_timer {
1789 +       unsigned int f_irq_on;
1790 +       unsigned int irq;
1791 +       unsigned int flag;
1792 +       unsigned long arg1;
1793 +       unsigned long arg2;
1794 +};
1795 +
1796 +struct timer_dev {
1797 +       struct mutex gptu_mutex;
1798 +       unsigned int number_of_timers;
1799 +       unsigned int occupation;
1800 +       unsigned int f_gptu_on;
1801 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
1802 +};
1803 +
1804 +static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
1805 +static int gptu_open(struct inode *, struct file *);
1806 +static int gptu_release(struct inode *, struct file *);
1807 +
1808 +static struct file_operations gptu_fops = {
1809 +       .owner = THIS_MODULE,
1810 +       .ioctl = gptu_ioctl,
1811 +       .open = gptu_open,
1812 +       .release = gptu_release
1813 +};
1814 +
1815 +static struct miscdevice gptu_miscdev = {
1816 +       .minor = MISC_DYNAMIC_MINOR,
1817 +       .name = "gptu",
1818 +       .fops = &gptu_fops,
1819 +};
1820 +
1821 +static struct timer_dev timer_dev;
1822 +
1823 +static irqreturn_t timer_irq_handler(int irq, void *p)
1824 +{
1825 +       unsigned int timer;
1826 +       unsigned int flag;
1827 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
1828 +
1829 +       timer = irq - TIMER_INTERRUPT;
1830 +       if (timer < timer_dev.number_of_timers
1831 +               && dev_timer == &timer_dev.timer[timer]) {
1832 +               /*  Clear interrupt.    */
1833 +               lq_w32(1 << timer, LQ_GPTU_IRNCR);
1834 +
1835 +               /*  Call user hanler or signal. */
1836 +               flag = dev_timer->flag;
1837 +               if (!(timer & 0x01)
1838 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
1839 +                       /* 16-bit timer or timer A of 32-bit timer  */
1840 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
1841 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
1842 +                       case TIMER_FLAG_CALLBACK_IN_HB:
1843 +                               if (dev_timer->arg1)
1844 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
1845 +                               break;
1846 +                       case TIMER_FLAG_SIGNAL:
1847 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
1848 +                               break;
1849 +                       }
1850 +               }
1851 +       }
1852 +       return IRQ_HANDLED;
1853 +}
1854 +
1855 +static inline void lq_enable_gptu(void)
1856 +{
1857 +       lq_pmu_enable(PMU_GPT);
1858 +
1859 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
1860 +       *LQ_GPTU_CLC =
1861 +               GPTU_CLC_SMC_SET(0x00) |
1862 +               GPTU_CLC_RMC_SET(0x01) |
1863 +               GPTU_CLC_FSOE_SET(0) |
1864 +               GPTU_CLC_SBWE_SET(1) |
1865 +               GPTU_CLC_EDIS_SET(0) |
1866 +               GPTU_CLC_SPEN_SET(0) |
1867 +               GPTU_CLC_DISR_SET(0);
1868 +}
1869 +
1870 +static inline void lq_disable_gptu(void)
1871 +{
1872 +       lq_w32(0x00, LQ_GPTU_IRNEN);
1873 +       lq_w32(0xfff, LQ_GPTU_IRNCR);
1874 +
1875 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
1876 +       *LQ_GPTU_CLC =
1877 +               GPTU_CLC_SMC_SET(0x00) |
1878 +               GPTU_CLC_RMC_SET(0x00) |
1879 +               GPTU_CLC_FSOE_SET(0) |
1880 +               GPTU_CLC_SBWE_SET(0) |
1881 +               GPTU_CLC_EDIS_SET(0) |
1882 +               GPTU_CLC_SPEN_SET(0) |
1883 +               GPTU_CLC_DISR_SET(1);
1884 +
1885 +       lq_pmu_disable(PMU_GPT);
1886 +}
1887 +
1888 +int lq_request_timer(unsigned int timer, unsigned int flag,
1889 +       unsigned long value, unsigned long arg1, unsigned long arg2)
1890 +{
1891 +       int ret = 0;
1892 +       unsigned int con_reg, irnen_reg;
1893 +       int n, X;
1894 +
1895 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
1896 +               return -EINVAL;
1897 +
1898 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
1899 +               timer, flag, value);
1900 +
1901 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
1902 +               value &= 0xFFFF;
1903 +       else
1904 +               timer &= ~0x01;
1905 +
1906 +       mutex_lock(&timer_dev.gptu_mutex);
1907 +
1908 +       /*
1909 +        *  Allocate timer.
1910 +        */
1911 +       if (timer < FIRST_TIMER) {
1912 +               unsigned int mask;
1913 +               unsigned int shift;
1914 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
1915 +               unsigned int offset = TIMER2A;
1916 +
1917 +               /*
1918 +                *  Pick up a free timer.
1919 +                */
1920 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
1921 +                       mask = 1 << offset;
1922 +                       shift = 1;
1923 +               } else {
1924 +                       mask = 3 << offset;
1925 +                       shift = 2;
1926 +               }
1927 +               for (timer = offset;
1928 +                    timer < offset + timer_dev.number_of_timers;
1929 +                    timer += shift, mask <<= shift)
1930 +                       if (!(timer_dev.occupation & mask)) {
1931 +                               timer_dev.occupation |= mask;
1932 +                               break;
1933 +                       }
1934 +               if (timer >= offset + timer_dev.number_of_timers) {
1935 +                       printk("failed![%d]\n", __LINE__);
1936 +                       mutex_unlock(&timer_dev.gptu_mutex);
1937 +                       return -EINVAL;
1938 +               } else
1939 +                       ret = timer;
1940 +       } else {
1941 +               register unsigned int mask;
1942 +
1943 +               /*
1944 +                *  Check if the requested timer is free.
1945 +                */
1946 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
1947 +               if ((timer_dev.occupation & mask)) {
1948 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
1949 +                               __LINE__, mask, timer_dev.occupation);
1950 +                       mutex_unlock(&timer_dev.gptu_mutex);
1951 +                       return -EBUSY;
1952 +               } else {
1953 +                       timer_dev.occupation |= mask;
1954 +                       ret = 0;
1955 +               }
1956 +       }
1957 +
1958 +       /*
1959 +        *  Prepare control register value.
1960 +        */
1961 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
1962 +       default:
1963 +       case TIMER_FLAG_NONE_EDGE:
1964 +               con_reg = GPTU_CON_EDGE_SET(0x00);
1965 +               break;
1966 +       case TIMER_FLAG_RISE_EDGE:
1967 +               con_reg = GPTU_CON_EDGE_SET(0x01);
1968 +               break;
1969 +       case TIMER_FLAG_FALL_EDGE:
1970 +               con_reg = GPTU_CON_EDGE_SET(0x02);
1971 +               break;
1972 +       case TIMER_FLAG_ANY_EDGE:
1973 +               con_reg = GPTU_CON_EDGE_SET(0x03);
1974 +               break;
1975 +       }
1976 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
1977 +               con_reg |=
1978 +                       TIMER_FLAG_MASK_SRC(flag) ==
1979 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
1980 +                       GPTU_CON_SRC_EXT_SET(0);
1981 +       else
1982 +               con_reg |=
1983 +                       TIMER_FLAG_MASK_SRC(flag) ==
1984 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
1985 +                       GPTU_CON_SRC_EG_SET(0);
1986 +       con_reg |=
1987 +               TIMER_FLAG_MASK_SYNC(flag) ==
1988 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
1989 +               GPTU_CON_SYNC_SET(1);
1990 +       con_reg |=
1991 +               TIMER_FLAG_MASK_INVERT(flag) ==
1992 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
1993 +       con_reg |=
1994 +               TIMER_FLAG_MASK_SIZE(flag) ==
1995 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
1996 +               GPTU_CON_EXT_SET(1);
1997 +       con_reg |=
1998 +               TIMER_FLAG_MASK_STOP(flag) ==
1999 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
2000 +       con_reg |=
2001 +               TIMER_FLAG_MASK_TYPE(flag) ==
2002 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
2003 +               GPTU_CON_CNT_SET(1);
2004 +       con_reg |=
2005 +               TIMER_FLAG_MASK_DIR(flag) ==
2006 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
2007 +
2008 +       /*
2009 +        *  Fill up running data.
2010 +        */
2011 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
2012 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
2013 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
2014 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2015 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
2016 +
2017 +       /*
2018 +        *  Enable GPTU module.
2019 +        */
2020 +       if (!timer_dev.f_gptu_on) {
2021 +               lq_enable_gptu();
2022 +               timer_dev.f_gptu_on = 1;
2023 +       }
2024 +
2025 +       /*
2026 +        *  Enable IRQ.
2027 +        */
2028 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
2029 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
2030 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
2031 +                               (unsigned long) find_task_by_vpid((int) arg1);
2032 +
2033 +               irnen_reg = 1 << (timer - FIRST_TIMER);
2034 +
2035 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
2036 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
2037 +                       TIMER_FLAG_CALLBACK_IN_IRQ
2038 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
2039 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
2040 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
2041 +               }
2042 +       } else
2043 +               irnen_reg = 0;
2044 +
2045 +       /*
2046 +        *  Write config register, reload value and enable interrupt.
2047 +        */
2048 +       n = timer >> 1;
2049 +       X = timer & 0x01;
2050 +       *LQ_GPTU_CON(n, X) = con_reg;
2051 +       *LQ_GPTU_RELOAD(n, X) = value;
2052 +       /* printk("reload value = %d\n", (u32)value); */
2053 +       *LQ_GPTU_IRNEN |= irnen_reg;
2054 +
2055 +       mutex_unlock(&timer_dev.gptu_mutex);
2056 +       printk("successful!\n");
2057 +       return ret;
2058 +}
2059 +EXPORT_SYMBOL(lq_request_timer);
2060 +
2061 +int lq_free_timer(unsigned int timer)
2062 +{
2063 +       unsigned int flag;
2064 +       unsigned int mask;
2065 +       int n, X;
2066 +
2067 +       if (!timer_dev.f_gptu_on)
2068 +               return -EINVAL;
2069 +
2070 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2071 +               return -EINVAL;
2072 +
2073 +       mutex_lock(&timer_dev.gptu_mutex);
2074 +
2075 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2076 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2077 +               timer &= ~0x01;
2078 +
2079 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2080 +       if (((timer_dev.occupation & mask) ^ mask)) {
2081 +               mutex_unlock(&timer_dev.gptu_mutex);
2082 +               return -EINVAL;
2083 +       }
2084 +
2085 +       n = timer >> 1;
2086 +       X = timer & 0x01;
2087 +
2088 +       if (GPTU_CON_EN(n, X))
2089 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
2090 +
2091 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
2092 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
2093 +
2094 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
2095 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
2096 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
2097 +       }
2098 +
2099 +       timer_dev.occupation &= ~mask;
2100 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
2101 +               lq_disable_gptu();
2102 +               timer_dev.f_gptu_on = 0;
2103 +       }
2104 +
2105 +       mutex_unlock(&timer_dev.gptu_mutex);
2106 +
2107 +       return 0;
2108 +}
2109 +EXPORT_SYMBOL(lq_free_timer);
2110 +
2111 +int lq_start_timer(unsigned int timer, int is_resume)
2112 +{
2113 +       unsigned int flag;
2114 +       unsigned int mask;
2115 +       int n, X;
2116 +
2117 +       if (!timer_dev.f_gptu_on)
2118 +               return -EINVAL;
2119 +
2120 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2121 +               return -EINVAL;
2122 +
2123 +       mutex_lock(&timer_dev.gptu_mutex);
2124 +
2125 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2126 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2127 +               timer &= ~0x01;
2128 +
2129 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
2130 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
2131 +       if (((timer_dev.occupation & mask) ^ mask)) {
2132 +               mutex_unlock(&timer_dev.gptu_mutex);
2133 +               return -EINVAL;
2134 +       }
2135 +
2136 +       n = timer >> 1;
2137 +       X = timer & 0x01;
2138 +
2139 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
2140 +
2141 +       mutex_unlock(&timer_dev.gptu_mutex);
2142 +
2143 +       return 0;
2144 +}
2145 +EXPORT_SYMBOL(lq_start_timer);
2146 +
2147 +int lq_stop_timer(unsigned int timer)
2148 +{
2149 +       unsigned int flag;
2150 +       unsigned int mask;
2151 +       int n, X;
2152 +
2153 +       if (!timer_dev.f_gptu_on)
2154 +               return -EINVAL;
2155 +
2156 +       if (timer < FIRST_TIMER
2157 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2158 +               return -EINVAL;
2159 +
2160 +       mutex_lock(&timer_dev.gptu_mutex);
2161 +
2162 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2163 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2164 +               timer &= ~0x01;
2165 +
2166 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2167 +       if (((timer_dev.occupation & mask) ^ mask)) {
2168 +               mutex_unlock(&timer_dev.gptu_mutex);
2169 +               return -EINVAL;
2170 +       }
2171 +
2172 +       n = timer >> 1;
2173 +       X = timer & 0x01;
2174 +
2175 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
2176 +
2177 +       mutex_unlock(&timer_dev.gptu_mutex);
2178 +
2179 +       return 0;
2180 +}
2181 +EXPORT_SYMBOL(lq_stop_timer);
2182 +
2183 +int lq_reset_counter_flags(u32 timer, u32 flags)
2184 +{
2185 +       unsigned int oflag;
2186 +       unsigned int mask, con_reg;
2187 +       int n, X;
2188 +
2189 +       if (!timer_dev.f_gptu_on)
2190 +               return -EINVAL;
2191 +
2192 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2193 +               return -EINVAL;
2194 +
2195 +       mutex_lock(&timer_dev.gptu_mutex);
2196 +
2197 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
2198 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
2199 +               timer &= ~0x01;
2200 +
2201 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2202 +       if (((timer_dev.occupation & mask) ^ mask)) {
2203 +               mutex_unlock(&timer_dev.gptu_mutex);
2204 +               return -EINVAL;
2205 +       }
2206 +
2207 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
2208 +       default:
2209 +       case TIMER_FLAG_NONE_EDGE:
2210 +               con_reg = GPTU_CON_EDGE_SET(0x00);
2211 +               break;
2212 +       case TIMER_FLAG_RISE_EDGE:
2213 +               con_reg = GPTU_CON_EDGE_SET(0x01);
2214 +               break;
2215 +       case TIMER_FLAG_FALL_EDGE:
2216 +               con_reg = GPTU_CON_EDGE_SET(0x02);
2217 +               break;
2218 +       case TIMER_FLAG_ANY_EDGE:
2219 +               con_reg = GPTU_CON_EDGE_SET(0x03);
2220 +               break;
2221 +       }
2222 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
2223 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
2224 +       else
2225 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
2226 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
2227 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
2228 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
2229 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
2230 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
2231 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
2232 +
2233 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
2234 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
2235 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
2236 +
2237 +       n = timer >> 1;
2238 +       X = timer & 0x01;
2239 +
2240 +       *LQ_GPTU_CON(n, X) = con_reg;
2241 +       smp_wmb();
2242 +       printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
2243 +       mutex_unlock(&timer_dev.gptu_mutex);
2244 +       return 0;
2245 +}
2246 +EXPORT_SYMBOL(lq_reset_counter_flags);
2247 +
2248 +int lq_get_count_value(unsigned int timer, unsigned long *value)
2249 +{
2250 +       unsigned int flag;
2251 +       unsigned int mask;
2252 +       int n, X;
2253 +
2254 +       if (!timer_dev.f_gptu_on)
2255 +               return -EINVAL;
2256 +
2257 +       if (timer < FIRST_TIMER
2258 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2259 +               return -EINVAL;
2260 +
2261 +       mutex_lock(&timer_dev.gptu_mutex);
2262 +
2263 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2264 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2265 +               timer &= ~0x01;
2266 +
2267 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2268 +       if (((timer_dev.occupation & mask) ^ mask)) {
2269 +               mutex_unlock(&timer_dev.gptu_mutex);
2270 +               return -EINVAL;
2271 +       }
2272 +
2273 +       n = timer >> 1;
2274 +       X = timer & 0x01;
2275 +
2276 +       *value = *LQ_GPTU_COUNT(n, X);
2277 +
2278 +       mutex_unlock(&timer_dev.gptu_mutex);
2279 +
2280 +       return 0;
2281 +}
2282 +EXPORT_SYMBOL(lq_get_count_value);
2283 +
2284 +u32 lq_cal_divider(unsigned long freq)
2285 +{
2286 +       u64 module_freq, fpi = lq_get_fpi_bus_clock(2);
2287 +       u32 clock_divider = 1;
2288 +       module_freq = fpi * 1000;
2289 +       do_div(module_freq, clock_divider * freq);
2290 +       return module_freq;
2291 +}
2292 +EXPORT_SYMBOL(lq_cal_divider);
2293 +
2294 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
2295 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
2296 +       unsigned long arg2)
2297 +{
2298 +       unsigned long divider;
2299 +       unsigned int flag;
2300 +
2301 +       divider = lq_cal_divider(freq);
2302 +       if (divider == 0)
2303 +               return -EINVAL;
2304 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
2305 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
2306 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
2307 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
2308 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
2309 +
2310 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
2311 +               timer, freq, divider);
2312 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
2313 +}
2314 +EXPORT_SYMBOL(lq_set_timer);
2315 +
2316 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
2317 +       unsigned long arg1, unsigned long arg2)
2318 +{
2319 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
2320 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
2321 +}
2322 +EXPORT_SYMBOL(lq_set_counter);
2323 +
2324 +static int gptu_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
2325 +       unsigned long arg)
2326 +{
2327 +       int ret;
2328 +       struct gptu_ioctl_param param;
2329 +
2330 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
2331 +               return -EFAULT;
2332 +       copy_from_user(&param, (void *) arg, sizeof(param));
2333 +
2334 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
2335 +              || GPTU_SET_COUNTER) && param.timer < 2)
2336 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
2337 +           && !access_ok(VERIFY_WRITE, arg,
2338 +                          sizeof(struct gptu_ioctl_param)))
2339 +               return -EFAULT;
2340 +
2341 +       switch (cmd) {
2342 +       case GPTU_REQUEST_TIMER:
2343 +               ret = lq_request_timer(param.timer, param.flag, param.value,
2344 +                                    (unsigned long) param.pid,
2345 +                                    (unsigned long) param.sig);
2346 +               if (ret > 0) {
2347 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
2348 +                                     timer, &ret, sizeof(&ret));
2349 +                       ret = 0;
2350 +               }
2351 +               break;
2352 +       case GPTU_FREE_TIMER:
2353 +               ret = lq_free_timer(param.timer);
2354 +               break;
2355 +       case GPTU_START_TIMER:
2356 +               ret = lq_start_timer(param.timer, param.flag);
2357 +               break;
2358 +       case GPTU_STOP_TIMER:
2359 +               ret = lq_stop_timer(param.timer);
2360 +               break;
2361 +       case GPTU_GET_COUNT_VALUE:
2362 +               ret = lq_get_count_value(param.timer, &param.value);
2363 +               if (!ret)
2364 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
2365 +                                     value, &param.value,
2366 +                                     sizeof(param.value));
2367 +               break;
2368 +       case GPTU_CALCULATE_DIVIDER:
2369 +               param.value = lq_cal_divider(param.value);
2370 +               if (param.value == 0)
2371 +                       ret = -EINVAL;
2372 +               else {
2373 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
2374 +                                     value, &param.value,
2375 +                                     sizeof(param.value));
2376 +                       ret = 0;
2377 +               }
2378 +               break;
2379 +       case GPTU_SET_TIMER:
2380 +               ret = lq_set_timer(param.timer, param.value,
2381 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
2382 +                                TIMER_FLAG_ONCE ? 1 : 0,
2383 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
2384 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
2385 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
2386 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
2387 +                                TIMER_FLAG_NO_HANDLE,
2388 +                                (unsigned long) param.pid,
2389 +                                (unsigned long) param.sig);
2390 +               if (ret > 0) {
2391 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
2392 +                                     timer, &ret, sizeof(&ret));
2393 +                       ret = 0;
2394 +               }
2395 +               break;
2396 +       case GPTU_SET_COUNTER:
2397 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
2398 +               if (ret > 0) {
2399 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
2400 +                                     timer, &ret, sizeof(&ret));
2401 +                       ret = 0;
2402 +               }
2403 +               break;
2404 +       default:
2405 +               ret = -ENOTTY;
2406 +       }
2407 +
2408 +       return ret;
2409 +}
2410 +
2411 +static int gptu_open(struct inode *inode, struct file *file)
2412 +{
2413 +       return 0;
2414 +}
2415 +
2416 +static int gptu_release(struct inode *inode, struct file *file)
2417 +{
2418 +       return 0;
2419 +}
2420 +
2421 +int __init lq_gptu_init(void)
2422 +{
2423 +       int ret;
2424 +       unsigned int i;
2425 +
2426 +       lq_w32(0, LQ_GPTU_IRNEN);
2427 +       lq_w32(0xfff, LQ_GPTU_IRNCR);
2428 +
2429 +       memset(&timer_dev, 0, sizeof(timer_dev));
2430 +       mutex_init(&timer_dev.gptu_mutex);
2431 +
2432 +       lq_enable_gptu();
2433 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
2434 +       lq_disable_gptu();
2435 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
2436 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
2437 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
2438 +
2439 +       ret = misc_register(&gptu_miscdev);
2440 +       if (ret) {
2441 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
2442 +               return ret;
2443 +       } else {
2444 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
2445 +       }
2446 +
2447 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
2448 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
2449 +               if (ret) {
2450 +                       for (; i >= 0; i--)
2451 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
2452 +                       misc_deregister(&gptu_miscdev);
2453 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
2454 +                       return ret;
2455 +               } else {
2456 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
2457 +                       disable_irq(timer_dev.timer[i].irq);
2458 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
2459 +               }
2460 +       }
2461 +
2462 +       return 0;
2463 +}
2464 +
2465 +void __exit lq_gptu_exit(void)
2466 +{
2467 +       unsigned int i;
2468 +
2469 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
2470 +               if (timer_dev.timer[i].f_irq_on)
2471 +                       disable_irq(timer_dev.timer[i].irq);
2472 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
2473 +       }
2474 +       lq_disable_gptu();
2475 +       misc_deregister(&gptu_miscdev);
2476 +}
2477 +
2478 +module_init(lq_gptu_init);
2479 +module_exit(lq_gptu_exit);
2480 --- /dev/null
2481 +++ b/arch/mips/lantiq/xway/timer.h
2482 @@ -0,0 +1,155 @@
2483 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
2484 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
2485 +
2486 +
2487 +/******************************************************************************
2488 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
2489 +
2490 +                               No Warranty
2491 +   Because the program is licensed free of charge, there is no warranty for
2492 +   the program, to the extent permitted by applicable law.  Except when
2493 +   otherwise stated in writing the copyright holders and/or other parties
2494 +   provide the program "as is" without warranty of any kind, either
2495 +   expressed or implied, including, but not limited to, the implied
2496 +   warranties of merchantability and fitness for a particular purpose. The
2497 +   entire risk as to the quality and performance of the program is with
2498 +   you.  should the program prove defective, you assume the cost of all
2499 +   necessary servicing, repair or correction.
2500 +
2501 +   In no event unless required by applicable law or agreed to in writing
2502 +   will any copyright holder, or any other party who may modify and/or
2503 +   redistribute the program as permitted above, be liable to you for
2504 +   damages, including any general, special, incidental or consequential
2505 +   damages arising out of the use or inability to use the program
2506 +   (including but not limited to loss of data or data being rendered
2507 +   inaccurate or losses sustained by you or third parties or a failure of
2508 +   the program to operate with any other programs), even if such holder or
2509 +   other party has been advised of the possibility of such damages.
2510 +******************************************************************************/
2511 +
2512 +
2513 +/*
2514 + * ####################################
2515 + *              Definition
2516 + * ####################################
2517 + */
2518 +
2519 +/*
2520 + *  Available Timer/Counter Index
2521 + */
2522 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
2523 +#define TIMER_ANY                       0x00
2524 +#define TIMER1A                         TIMER(1, 0)
2525 +#define TIMER1B                         TIMER(1, 1)
2526 +#define TIMER2A                         TIMER(2, 0)
2527 +#define TIMER2B                         TIMER(2, 1)
2528 +#define TIMER3A                         TIMER(3, 0)
2529 +#define TIMER3B                         TIMER(3, 1)
2530 +
2531 +/*
2532 + *  Flag of Timer/Counter
2533 + *  These flags specify the way in which timer is configured.
2534 + */
2535 +/*  Bit size of timer/counter.                      */
2536 +#define TIMER_FLAG_16BIT                0x0000
2537 +#define TIMER_FLAG_32BIT                0x0001
2538 +/*  Switch between timer and counter.               */
2539 +#define TIMER_FLAG_TIMER                0x0000
2540 +#define TIMER_FLAG_COUNTER              0x0002
2541 +/*  Stop or continue when overflowing/underflowing. */
2542 +#define TIMER_FLAG_ONCE                 0x0000
2543 +#define TIMER_FLAG_CYCLIC               0x0004
2544 +/*  Count up or counter down.                       */
2545 +#define TIMER_FLAG_UP                   0x0000
2546 +#define TIMER_FLAG_DOWN                 0x0008
2547 +/*  Count on specific level or edge.                */
2548 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
2549 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
2550 +#define TIMER_FLAG_RISE_EDGE            0x0010
2551 +#define TIMER_FLAG_FALL_EDGE            0x0020
2552 +#define TIMER_FLAG_ANY_EDGE             0x0030
2553 +/*  Signal is syncronous to module clock or not.    */
2554 +#define TIMER_FLAG_UNSYNC               0x0000
2555 +#define TIMER_FLAG_SYNC                 0x0080
2556 +/*  Different interrupt handle type.                */
2557 +#define TIMER_FLAG_NO_HANDLE            0x0000
2558 +#if defined(__KERNEL__)
2559 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
2560 +#endif  //  defined(__KERNEL__)
2561 +#define TIMER_FLAG_SIGNAL               0x0300
2562 +/*  Internal clock source or external clock source  */
2563 +#define TIMER_FLAG_INT_SRC              0x0000
2564 +#define TIMER_FLAG_EXT_SRC              0x1000
2565 +
2566 +
2567 +/*
2568 + *  ioctl Command
2569 + */
2570 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
2571 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
2572 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
2573 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
2574 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
2575 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
2576 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
2577 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
2578 +
2579 +/*
2580 + *  Data Type Used to Call ioctl
2581 + */
2582 +struct gptu_ioctl_param {
2583 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
2584 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
2585 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
2586 +                                                 *  be dynamically allocated and ID would be stored in  *
2587 +                                                 *  this field.                                         *
2588 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
2589 +                                                 *  ignored.                                            *
2590 +                                                 *  In other command, this field is ID of timer/counter *
2591 +                                                 *  allocated.                                          */
2592 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
2593 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
2594 +                                                 *  specify how to configure timer/counter.             *
2595 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
2596 +                                                 *  and non-zero indicate resume timer/counter.         *
2597 +                                                 *  In other command, this field is ignored.            */
2598 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
2599 +                                                 *  init/reload value.                                  *
2600 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
2601 +                                                 *  frequency (0.001Hz) of timer.                       *
2602 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
2603 +                                                 *  value would be stored in this field.                *
2604 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
2605 +                                                 *  contains frequency wanted, and after calculation,   *
2606 +                                                 *  divider would be stored in this field to overwrite  *
2607 +                                                 *  the frequency.                                      *
2608 +                                                 *  In other command, this field is ignored.            */
2609 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
2610 +                                                 *  if signal is required, this field contains process  *
2611 +                                                 *  ID to which signal would be sent.                   *
2612 +                                                 *  In other command, this field is ignored.            */
2613 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
2614 +                                                 *  if signal is required, this field contains signal   *
2615 +                                                 *  number which would be sent.                         *
2616 +                                                 *  In other command, this field is ignored.            */
2617 +};
2618 +
2619 +/*
2620 + * ####################################
2621 + *              Data Type
2622 + * ####################################
2623 + */
2624 +typedef void (*timer_callback)(unsigned long arg);
2625 +
2626 +extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
2627 +extern int ifxmips_free_timer(unsigned int);
2628 +extern int ifxmips_start_timer(unsigned int, int);
2629 +extern int ifxmips_stop_timer(unsigned int);
2630 +extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
2631 +extern int ifxmips_get_count_value(unsigned int, unsigned long *);
2632 +extern u32 ifxmips_cal_divider(unsigned long);
2633 +extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
2634 +extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
2635 +       u32 reload, unsigned long arg1, unsigned long arg2);
2636 +
2637 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
2638 --- /dev/null
2639 +++ b/arch/mips/lantiq/xway/Makefile
2640 @@ -0,0 +1,5 @@
2641 +obj-y := pmu.o prom.o dma.o timer.o reset.o clk-xway.o
2642 +obj-y += gpio.o gpio_ebu.o gpio_leds.o devices.o
2643 +obj-$(CONFIG_LANTIQ_MACH_EASY50812) += mach-easy50812.o
2644 +obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
2645 +obj-$(CONFIG_LANTIQ_MACH_EASY4010) += mach-easy4010.o
2646 --- /dev/null
2647 +++ b/arch/mips/lantiq/xway/clk-xway.c
2648 @@ -0,0 +1,219 @@
2649 +/*
2650 + *  This program is free software; you can redistribute it and/or modify it
2651 + *  under the terms of the GNU General Public License version 2 as published
2652 + *  by the Free Software Foundation.
2653 + *
2654 + *  Copyright (C) 2007 Xu Liang, infineon
2655 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2656 + */
2657 +
2658 +#include <linux/io.h>
2659 +#include <linux/module.h>
2660 +#include <linux/init.h>
2661 +#include <linux/clk.h>
2662 +
2663 +#include <asm/time.h>
2664 +#include <asm/irq.h>
2665 +#include <asm/div64.h>
2666 +
2667 +#include <xway.h>
2668 +
2669 +static unsigned int lq_ram_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
2670 +#define DDR_HZ lq_ram_clocks[lq_r32(LQ_CGU_SYS) & 0x3]
2671 +
2672 +#define BASIC_FREQUENCY_1      35328000
2673 +#define BASIC_FREQUENCY_2      36000000
2674 +#define BASIS_REQUENCY_USB     12000000
2675 +
2676 +#define GET_BITS(x, msb, lsb)           (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
2677 +
2678 +#define CGU_PLL0_PHASE_DIVIDER_ENABLE   (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 31))
2679 +#define CGU_PLL0_BYPASS                 (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 30))
2680 +#define CGU_PLL0_CFG_DSMSEL             (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 28))
2681 +#define CGU_PLL0_CFG_FRAC_EN            (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 27))
2682 +#define CGU_PLL1_SRC                    (lq_r32(LQ_CGU_PLL1_CFG) & (1 << 31))
2683 +#define CGU_PLL2_PHASE_DIVIDER_ENABLE   (lq_r32(LQ_CGU_PLL2_CFG) & (1 << 20))
2684 +#define CGU_SYS_FPI_SEL                 (1 << 6)
2685 +#define CGU_SYS_DDR_SEL                 0x3
2686 +#define CGU_PLL0_SRC                    (1 << 29)
2687 +
2688 +#define CGU_PLL0_CFG_PLLK               GET_BITS(*LQ_CGU_PLL0_CFG, 26, 17)
2689 +#define CGU_PLL0_CFG_PLLN               GET_BITS(*LQ_CGU_PLL0_CFG, 12, 6)
2690 +#define CGU_PLL0_CFG_PLLM               GET_BITS(*LQ_CGU_PLL0_CFG, 5, 2)
2691 +#define CGU_PLL2_SRC                    GET_BITS(*LQ_CGU_PLL2_CFG, 18, 17)
2692 +#define CGU_PLL2_CFG_INPUT_DIV          GET_BITS(*LQ_CGU_PLL2_CFG, 16, 13)
2693 +
2694 +#define LQ_GPTU_GPT_CLC                ((u32 *)(LQ_GPTU_BASE_ADDR + 0x0000))
2695 +#define LQ_CGU_PLL0_CFG                ((u32 *)(LQ_CGU_BASE_ADDR + 0x0004))
2696 +#define LQ_CGU_PLL1_CFG                ((u32 *)(LQ_CGU_BASE_ADDR + 0x0008))
2697 +#define LQ_CGU_PLL2_CFG                ((u32 *)(LQ_CGU_BASE_ADDR + 0x000C))
2698 +#define LQ_CGU_SYS                     ((u32 *)(LQ_CGU_BASE_ADDR + 0x0010))
2699 +#define LQ_CGU_UPDATE          ((u32 *)(LQ_CGU_BASE_ADDR + 0x0014))
2700 +#define LQ_CGU_IF_CLK          ((u32 *)(LQ_CGU_BASE_ADDR + 0x0018))
2701 +#define LQ_CGU_OSC_CON         ((u32 *)(LQ_CGU_BASE_ADDR + 0x001C))
2702 +#define LQ_CGU_SMD                     ((u32 *)(LQ_CGU_BASE_ADDR + 0x0020))
2703 +#define LQ_CGU_CT1SR           ((u32 *)(LQ_CGU_BASE_ADDR + 0x0028))
2704 +#define LQ_CGU_CT2SR           ((u32 *)(LQ_CGU_BASE_ADDR + 0x002C))
2705 +#define LQ_CGU_PCMCR           ((u32 *)(LQ_CGU_BASE_ADDR + 0x0030))
2706 +#define LQ_CGU_PCI_CR          ((u32 *)(LQ_CGU_BASE_ADDR + 0x0034))
2707 +#define LQ_CGU_PD_PC           ((u32 *)(LQ_CGU_BASE_ADDR + 0x0038))
2708 +#define LQ_CGU_FMR                     ((u32 *)(LQ_CGU_BASE_ADDR + 0x003C))
2709 +
2710 +static unsigned int lq_get_pll0_fdiv(void);
2711 +
2712 +static inline unsigned int
2713 +get_input_clock(int pll)
2714 +{
2715 +       switch (pll) {
2716 +       case 0:
2717 +               if (lq_r32(LQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
2718 +                       return BASIS_REQUENCY_USB;
2719 +               else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
2720 +                       return BASIC_FREQUENCY_1;
2721 +               else
2722 +                       return BASIC_FREQUENCY_2;
2723 +       case 1:
2724 +               if (CGU_PLL1_SRC)
2725 +                       return BASIS_REQUENCY_USB;
2726 +               else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
2727 +                       return BASIC_FREQUENCY_1;
2728 +               else
2729 +                       return BASIC_FREQUENCY_2;
2730 +       case 2:
2731 +               switch (CGU_PLL2_SRC) {
2732 +               case 0:
2733 +                       return lq_get_pll0_fdiv();
2734 +               case 1:
2735 +                       return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
2736 +                               BASIC_FREQUENCY_1 :
2737 +                               BASIC_FREQUENCY_2;
2738 +               case 2:
2739 +                       return BASIS_REQUENCY_USB;
2740 +               }
2741 +       default:
2742 +               return 0;
2743 +       }
2744 +}
2745 +
2746 +static inline unsigned int
2747 +cal_dsm(int pll, unsigned int num, unsigned int den)
2748 +{
2749 +       u64 res, clock = get_input_clock(pll);
2750 +       res = num * clock;
2751 +       do_div(res, den);
2752 +       return res;
2753 +}
2754 +
2755 +static inline unsigned int
2756 +mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
2757 +{
2758 +       unsigned int num = ((N + 1) << 10) + K;
2759 +       unsigned int den = (M + 1) << 10;
2760 +       return cal_dsm(pll, num, den);
2761 +}
2762 +
2763 +static inline unsigned int
2764 +ssff_dsm_1(int pll, unsigned int M, unsigned int N,    unsigned int K)
2765 +{
2766 +       unsigned int num = ((N + 1) << 11) + K + 512;
2767 +       unsigned int den = (M + 1) << 11;
2768 +       return cal_dsm(pll, num, den);
2769 +}
2770 +
2771 +static inline unsigned int
2772 +ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
2773 +{
2774 +       unsigned int num = K >= 512 ?
2775 +               ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
2776 +       unsigned int den = (M + 1) << 12;
2777 +       return cal_dsm(pll, num, den);
2778 +}
2779 +
2780 +static inline unsigned int
2781 +dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
2782 +       unsigned int dsmsel, unsigned int phase_div_en)
2783 +{
2784 +       if (!dsmsel)
2785 +               return mash_dsm(pll, M, N, K);
2786 +       else if (!phase_div_en)
2787 +               return mash_dsm(pll, M, N, K);
2788 +       else
2789 +               return ssff_dsm_2(pll, M, N, K);
2790 +}
2791 +
2792 +static inline unsigned int
2793 +lq_get_pll0_fosc(void)
2794 +{
2795 +       if (CGU_PLL0_BYPASS)
2796 +               return get_input_clock(0);
2797 +       else
2798 +               return !CGU_PLL0_CFG_FRAC_EN
2799 +                       ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
2800 +                               CGU_PLL0_PHASE_DIVIDER_ENABLE)
2801 +                       : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
2802 +                               CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
2803 +}
2804 +
2805 +static unsigned int
2806 +lq_get_pll0_fdiv(void)
2807 +{
2808 +       unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
2809 +       return (lq_get_pll0_fosc() + (div >> 1)) / div;
2810 +}
2811 +
2812 +unsigned int
2813 +lq_get_io_region_clock(void)
2814 +{
2815 +       unsigned int ret = lq_get_pll0_fosc();
2816 +       switch (lq_r32(LQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
2817 +       default:
2818 +       case 0:
2819 +               return (ret + 1) / 2;
2820 +       case 1:
2821 +               return (ret * 2 + 2) / 5;
2822 +       case 2:
2823 +               return (ret + 1) / 3;
2824 +       case 3:
2825 +               return (ret + 2) / 4;
2826 +       }
2827 +}
2828 +EXPORT_SYMBOL(lq_get_io_region_clock);
2829 +
2830 +unsigned int
2831 +lq_get_fpi_bus_clock(int fpi)
2832 +{
2833 +       unsigned int ret = lq_get_io_region_clock();
2834 +       if ((fpi == 2) && (lq_r32(LQ_CGU_SYS) & CGU_SYS_FPI_SEL))
2835 +               ret >>= 1;
2836 +       return ret;
2837 +}
2838 +EXPORT_SYMBOL(lq_get_fpi_bus_clock);
2839 +
2840 +unsigned int
2841 +lq_get_cpu_hz(void)
2842 +{
2843 +       switch (lq_r32(LQ_CGU_SYS) & 0xc)
2844 +       {
2845 +       case 0:
2846 +               return CLOCK_333M;
2847 +       case 4:
2848 +               return DDR_HZ;
2849 +       case 8:
2850 +               return DDR_HZ << 1;
2851 +       default:
2852 +               return DDR_HZ >> 1;
2853 +       }
2854 +}
2855 +EXPORT_SYMBOL(lq_get_cpu_hz);
2856 +
2857 +unsigned int
2858 +lq_get_fpi_hz(void)
2859 +{
2860 +       unsigned int ddr_clock = DDR_HZ;
2861 +       if (lq_r32(LQ_CGU_SYS) & 0x40)
2862 +               return ddr_clock >> 1;
2863 +       return ddr_clock;
2864 +}
2865 +EXPORT_SYMBOL(lq_get_fpi_hz);
2866 +
2867 +
2868 --- /dev/null
2869 +++ b/arch/mips/lantiq/xway/gpio.c
2870 @@ -0,0 +1,203 @@
2871 +/*
2872 + *  This program is free software; you can redistribute it and/or modify it
2873 + *  under the terms of the GNU General Public License version 2 as published
2874 + *  by the Free Software Foundation.
2875 + *
2876 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2877 + */
2878 +
2879 +#include <linux/slab.h>
2880 +#include <linux/module.h>
2881 +#include <linux/platform_device.h>
2882 +#include <linux/gpio.h>
2883 +
2884 +#include <lantiq.h>
2885 +
2886 +#define LQ_GPIO0_BASE_ADDR     0x1E100B10
2887 +#define LQ_GPIO1_BASE_ADDR     0x1E100B40
2888 +#define LQ_GPIO_SIZE           0x30
2889 +
2890 +#define LQ_GPIO_OUT                    0x00
2891 +#define LQ_GPIO_IN                     0x04
2892 +#define LQ_GPIO_DIR                    0x08
2893 +#define LQ_GPIO_ALTSEL0                0x0C
2894 +#define LQ_GPIO_ALTSEL1                0x10
2895 +#define LQ_GPIO_OD                     0x14
2896 +
2897 +#define PINS_PER_PORT          16
2898 +
2899 +#define lq_gpio_getbit(m, r, p)                !!(lq_r32(m + r) & (1 << p))
2900 +#define lq_gpio_setbit(m, r, p)                lq_w32_mask(0, (1 << p), m + r)
2901 +#define lq_gpio_clearbit(m, r, p)      lq_w32_mask((1 << p), 0, m + r)
2902 +
2903 +struct lq_gpio
2904 +{
2905 +       void __iomem *membase;
2906 +       struct gpio_chip chip;
2907 +};
2908 +
2909 +int
2910 +gpio_to_irq(unsigned int gpio)
2911 +{
2912 +       return -EINVAL;
2913 +}
2914 +EXPORT_SYMBOL(gpio_to_irq);
2915 +
2916 +int
2917 +lq_gpio_setconfig(unsigned int pin, unsigned int reg, unsigned int val)
2918 +{
2919 +       void __iomem *membase = (void*)KSEG1ADDR(LQ_GPIO0_BASE_ADDR);
2920 +       if(pin >= (2 * PINS_PER_PORT))
2921 +               return -EINVAL;
2922 +       if(pin >= PINS_PER_PORT)
2923 +       {
2924 +               pin -= PINS_PER_PORT;
2925 +               membase += LQ_GPIO_SIZE;
2926 +       }
2927 +       if(val)
2928 +               lq_w32_mask(0, (1 << pin), membase + reg);
2929 +       else
2930 +               lq_w32_mask((1 << pin), 0, membase + reg);
2931 +       return 0;
2932 +}
2933 +EXPORT_SYMBOL(lq_gpio_setconfig);
2934 +
2935 +int
2936 +lq_gpio_request(unsigned int pin, unsigned int alt0,
2937 +       unsigned int alt1, unsigned int dir, const char *name)
2938 +{
2939 +       void __iomem *membase = (void*)KSEG1ADDR(LQ_GPIO0_BASE_ADDR);
2940 +       if(pin >= (2 * PINS_PER_PORT))
2941 +               return -EINVAL;
2942 +       if(gpio_request(pin, name))
2943 +       {
2944 +               printk("failed to register %s gpio\n", name);
2945 +               return -EBUSY;
2946 +       }
2947 +       gpio_direction_output(pin, dir);
2948 +       if(pin >= PINS_PER_PORT)
2949 +       {
2950 +               pin -= PINS_PER_PORT;
2951 +               membase += LQ_GPIO_SIZE;
2952 +       }
2953 +       if(alt0)
2954 +               lq_gpio_setbit(membase, LQ_GPIO_ALTSEL0, pin);
2955 +       else
2956 +               lq_gpio_clearbit(membase, LQ_GPIO_ALTSEL0, pin);
2957 +       if(alt1)
2958 +               lq_gpio_setbit(membase, LQ_GPIO_ALTSEL1, pin);
2959 +       else
2960 +               lq_gpio_clearbit(membase, LQ_GPIO_ALTSEL1, pin);
2961 +       return 0;
2962 +}
2963 +EXPORT_SYMBOL(lq_gpio_request);
2964 +
2965 +static void
2966 +lq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
2967 +{
2968 +       struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
2969 +       if(value)
2970 +               lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_OUT, offset);
2971 +       else
2972 +               lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_OUT, offset);
2973 +}
2974 +
2975 +static int
2976 +lq_gpio_get(struct gpio_chip *chip, unsigned int offset)
2977 +{
2978 +       struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
2979 +       return lq_gpio_getbit(lq_gpio->membase, LQ_GPIO_IN, offset);
2980 +}
2981 +
2982 +static int
2983 +lq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
2984 +{
2985 +       struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
2986 +       lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_OD, offset);
2987 +       lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_DIR, offset);
2988 +       return 0;
2989 +}
2990 +
2991 +static int
2992 +lq_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
2993 +{
2994 +       struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
2995 +       lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_OD, offset);
2996 +       lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_DIR, offset);
2997 +       lq_gpio_set(chip, offset, value);
2998 +       return 0;
2999 +}
3000 +
3001 +static int
3002 +lq_gpio_req(struct gpio_chip *chip, unsigned offset)
3003 +{
3004 +       struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3005 +       lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_ALTSEL0, offset);
3006 +       lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_ALTSEL1, offset);
3007 +       return 0;
3008 +}
3009 +
3010 +static int
3011 +lq_gpio_probe(struct platform_device *pdev)
3012 +{
3013 +       struct lq_gpio *lq_gpio = kzalloc(sizeof(struct lq_gpio), GFP_KERNEL);
3014 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3015 +       int ret = 0;
3016 +       if(!res)
3017 +       {
3018 +               ret = -ENOENT;
3019 +               goto err_free;
3020 +       }
3021 +       res = request_mem_region(res->start, resource_size(res),
3022 +               dev_name(&pdev->dev));
3023 +       if(!res)
3024 +       {
3025 +               ret = -EBUSY;
3026 +               goto err_free;
3027 +       }
3028 +       lq_gpio->membase = ioremap_nocache(res->start, resource_size(res));
3029 +       if(!lq_gpio->membase)
3030 +       {
3031 +               ret = -ENOMEM;
3032 +               goto err_release_mem_region;
3033 +       }
3034 +       lq_gpio->chip.label = "lq_gpio";
3035 +       lq_gpio->chip.direction_input = lq_gpio_direction_input;
3036 +       lq_gpio->chip.direction_output = lq_gpio_direction_output;
3037 +       lq_gpio->chip.get = lq_gpio_get;
3038 +       lq_gpio->chip.set = lq_gpio_set;
3039 +       lq_gpio->chip.request = lq_gpio_req;
3040 +       lq_gpio->chip.base = PINS_PER_PORT * pdev->id;
3041 +       lq_gpio->chip.ngpio = PINS_PER_PORT;
3042 +       platform_set_drvdata(pdev, lq_gpio);
3043 +       ret = gpiochip_add(&lq_gpio->chip);
3044 +       if(!ret)
3045 +               return 0;
3046 +
3047 +       iounmap(lq_gpio->membase);
3048 +err_release_mem_region:
3049 +       release_mem_region(res->start, resource_size(res));
3050 +err_free:
3051 +    kfree(lq_gpio);
3052 +       return ret;
3053 +}
3054 +
3055 +static struct platform_driver
3056 +lq_gpio_driver = {
3057 +       .probe = lq_gpio_probe,
3058 +       .driver = {
3059 +               .name = "lq_gpio",
3060 +               .owner = THIS_MODULE,
3061 +       },
3062 +};
3063 +
3064 +int __init
3065 +lq_gpio_init(void)
3066 +{
3067 +       int ret = platform_driver_register(&lq_gpio_driver);
3068 +       if(ret)
3069 +               printk(KERN_INFO "lq_gpio : Error registering platfom driver!");
3070 +       return ret;
3071 +}
3072 +
3073 +arch_initcall(lq_gpio_init);
3074 --- /dev/null
3075 +++ b/arch/mips/lantiq/xway/reset.c
3076 @@ -0,0 +1,53 @@
3077 +/*
3078 + *  This program is free software; you can redistribute it and/or modify it
3079 + *  under the terms of the GNU General Public License version 2 as published
3080 + *  by the Free Software Foundation.
3081 + *
3082 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
3083 + */
3084 +
3085 +#include <linux/init.h>
3086 +#include <linux/io.h>
3087 +#include <linux/pm.h>
3088 +#include <asm/reboot.h>
3089 +
3090 +#include <xway.h>
3091 +
3092 +#define LQ_RCU_RST                     ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
3093 +#define LQ_RCU_RST_ALL         0x40000000
3094 +
3095 +static void
3096 +lq_machine_restart(char *command)
3097 +{
3098 +       printk(KERN_NOTICE "System restart\n");
3099 +       local_irq_disable();
3100 +       lq_w32(lq_r32(LQ_RCU_RST) | LQ_RCU_RST_ALL,     LQ_RCU_RST);
3101 +       for(;;);
3102 +}
3103 +
3104 +static void
3105 +lq_machine_halt(void)
3106 +{
3107 +       printk(KERN_NOTICE "System halted.\n");
3108 +       local_irq_disable();
3109 +       for(;;);
3110 +}
3111 +
3112 +static void
3113 +lq_machine_power_off(void)
3114 +{
3115 +       printk(KERN_NOTICE "Please turn off the power now.\n");
3116 +       local_irq_disable();
3117 +       for(;;);
3118 +}
3119 +
3120 +static int __init
3121 +mips_reboot_setup(void)
3122 +{
3123 +       _machine_restart = lq_machine_restart;
3124 +       _machine_halt = lq_machine_halt;
3125 +       pm_power_off = lq_machine_power_off;
3126 +       return 0;
3127 +}
3128 +
3129 +arch_initcall(mips_reboot_setup);