target/linux/ipq806x/patches-4.1/156-dmaengine-Add-ADM-driver.patch

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   4 Subject: [v6,2/2] dmaengine: Add ADM driver
   5 From: Andy Gross <agross@codeaurora.org>
   6 X-Patchwork-Id: 6027351
   7 Message-Id: <1426571172-9711-3-git-send-email-agross@codeaurora.org>
   8 To: Vinod Koul <vinod.koul@intel.com>
   9 Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org,
  10         linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
  11         linux-arm-kernel@lists.infradead.org, Kumar Gala <galak@codeaurora.org>,
  12         Bjorn Andersson <bjorn.andersson@sonymobile.com>,
  13         Andy Gross <agross@codeaurora.org>
  14 Date: Tue, 17 Mar 2015 00:46:12 -0500
  15
  16 Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
  17 controller found in the MSM8x60 and IPQ/APQ8064 platforms.
  18
  19 The ADM supports both memory to memory transactions and memory
  20 to/from peripheral device transactions.  The controller also provides flow
  21 control capabilities for transactions to/from peripheral devices.
  22
  23 The initial release of this driver supports slave transfers to/from peripherals
  24 and also incorporates CRCI (client rate control interface) flow control.
  25
  26 Signed-off-by: Andy Gross <agross@codeaurora.org>
  27 Reviewed-by: sricharan <sricharan@codeaurora.org>
  28
  29 ---
  30 drivers/dma/Kconfig    |   10 +
  31  drivers/dma/Makefile   |    1 +
  32  drivers/dma/qcom_adm.c |  900 ++++++++++++++++++++++++++++++++++++++++++++++++
  33  3 files changed, 911 insertions(+)
  34  create mode 100644 drivers/dma/qcom_adm.c
  35
  36 --- a/drivers/dma/Kconfig
  37 +++ b/drivers/dma/Kconfig
  38 @@ -492,4 +492,14 @@ config QCOM_BAM_DMA
  39           Enable support for the QCOM BAM DMA controller.  This controller
  40           provides DMA capabilities for a variety of on-chip devices.
  41
  42 +config QCOM_ADM
  43 +       tristate "Qualcomm ADM support"
  44 +       depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM)
  45 +       select DMA_ENGINE
  46 +       select DMA_VIRTUAL_CHANNELS
  47 +       ---help---
  48 +         Enable support for the Qualcomm ADM DMA controller.  This controller
  49 +         provides DMA capabilities for both general purpose and on-chip
  50 +         peripheral devices.
  51 +
  52  endif
  53 --- /dev/null
  54 +++ b/drivers/dma/qcom_adm.c
  55 @@ -0,0 +1,900 @@
  56 +/*
  57 + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  58 + *
  59 + * This program is free software; you can redistribute it and/or modify
  60 + * it under the terms of the GNU General Public License version 2 and
  61 + * only version 2 as published by the Free Software Foundation.
  62 + *
  63 + * This program is distributed in the hope that it will be useful,
  64 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  65 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  66 + * GNU General Public License for more details.
  67 + *
  68 + */
  69 +
  70 +#include <linux/kernel.h>
  71 +#include <linux/io.h>
  72 +#include <linux/init.h>
  73 +#include <linux/slab.h>
  74 +#include <linux/module.h>
  75 +#include <linux/interrupt.h>
  76 +#include <linux/dma-mapping.h>
  77 +#include <linux/scatterlist.h>
  78 +#include <linux/device.h>
  79 +#include <linux/platform_device.h>
  80 +#include <linux/of.h>
  81 +#include <linux/of_address.h>
  82 +#include <linux/of_irq.h>
  83 +#include <linux/of_dma.h>
  84 +#include <linux/reset.h>
  85 +#include <linux/clk.h>
  86 +#include <linux/dmaengine.h>
  87 +
  88 +#include "dmaengine.h"
  89 +#include "virt-dma.h"
  90 +
  91 +/* ADM registers - calculated from channel number and security domain */
  92 +#define ADM_CHAN_MULTI                 0x4
  93 +#define ADM_CI_MULTI                   0x4
  94 +#define ADM_CRCI_MULTI                 0x4
  95 +#define ADM_EE_MULTI                   0x800
  96 +#define ADM_CHAN_OFFS(chan)            (ADM_CHAN_MULTI * chan)
  97 +#define ADM_EE_OFFS(ee)                        (ADM_EE_MULTI * ee)
  98 +#define ADM_CHAN_EE_OFFS(chan, ee)     (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee))
  99 +#define ADM_CHAN_OFFS(chan)            (ADM_CHAN_MULTI * chan)
 100 +#define ADM_CI_OFFS(ci)                        (ADM_CHAN_OFF(ci))
 101 +#define ADM_CH_CMD_PTR(chan, ee)       (ADM_CHAN_EE_OFFS(chan, ee))
 102 +#define ADM_CH_RSLT(chan, ee)          (0x40 + ADM_CHAN_EE_OFFS(chan, ee))
 103 +#define ADM_CH_FLUSH_STATE0(chan, ee)  (0x80 + ADM_CHAN_EE_OFFS(chan, ee))
 104 +#define ADM_CH_STATUS_SD(chan, ee)     (0x200 + ADM_CHAN_EE_OFFS(chan, ee))
 105 +#define ADM_CH_CONF(chan)              (0x240 + ADM_CHAN_OFFS(chan))
 106 +#define ADM_CH_RSLT_CONF(chan, ee)     (0x300 + ADM_CHAN_EE_OFFS(chan, ee))
 107 +#define ADM_SEC_DOMAIN_IRQ_STATUS(ee)  (0x380 + ADM_EE_OFFS(ee))
 108 +#define ADM_CI_CONF(ci)                        (0x390 + ci * ADM_CI_MULTI)
 109 +#define ADM_GP_CTL                     0x3d8
 110 +#define ADM_CRCI_CTL(crci, ee)         (0x400 + crci * ADM_CRCI_MULTI + \
 111 +                                               ADM_EE_OFFS(ee))
 112 +
 113 +/* channel status */
 114 +#define ADM_CH_STATUS_VALID    BIT(1)
 115 +
 116 +/* channel result */
 117 +#define ADM_CH_RSLT_VALID      BIT(31)
 118 +#define ADM_CH_RSLT_ERR                BIT(3)
 119 +#define ADM_CH_RSLT_FLUSH      BIT(2)
 120 +#define ADM_CH_RSLT_TPD                BIT(1)
 121 +
 122 +/* channel conf */
 123 +#define ADM_CH_CONF_SHADOW_EN          BIT(12)
 124 +#define ADM_CH_CONF_MPU_DISABLE                BIT(11)
 125 +#define ADM_CH_CONF_PERM_MPU_CONF      BIT(9)
 126 +#define ADM_CH_CONF_FORCE_RSLT_EN      BIT(7)
 127 +#define ADM_CH_CONF_SEC_DOMAIN(ee)     (((ee & 0x3) << 4) | ((ee & 0x4) << 11))
 128 +
 129 +/* channel result conf */
 130 +#define ADM_CH_RSLT_CONF_FLUSH_EN      BIT(1)
 131 +#define ADM_CH_RSLT_CONF_IRQ_EN                BIT(0)
 132 +
 133 +/* CRCI CTL */
 134 +#define ADM_CRCI_CTL_MUX_SEL   BIT(18)
 135 +#define ADM_CRCI_CTL_RST       BIT(17)
 136 +
 137 +/* CI configuration */
 138 +#define ADM_CI_RANGE_END(x)    (x << 24)
 139 +#define ADM_CI_RANGE_START(x)  (x << 16)
 140 +#define ADM_CI_BURST_4_WORDS   BIT(2)
 141 +#define ADM_CI_BURST_8_WORDS   BIT(3)
 142 +
 143 +/* GP CTL */
 144 +#define ADM_GP_CTL_LP_EN       BIT(12)
 145 +#define ADM_GP_CTL_LP_CNT(x)   (x << 8)
 146 +
 147 +/* Command pointer list entry */
 148 +#define ADM_CPLE_LP            BIT(31)
 149 +#define ADM_CPLE_CMD_PTR_LIST  BIT(29)
 150 +
 151 +/* Command list entry */
 152 +#define ADM_CMD_LC             BIT(31)
 153 +#define ADM_CMD_DST_CRCI(n)    (((n) & 0xf) << 7)
 154 +#define ADM_CMD_SRC_CRCI(n)    (((n) & 0xf) << 3)
 155 +
 156 +#define ADM_CMD_TYPE_SINGLE    0x0
 157 +#define ADM_CMD_TYPE_BOX       0x3
 158 +
 159 +#define ADM_CRCI_MUX_SEL       BIT(4)
 160 +#define ADM_DESC_ALIGN         8
 161 +#define ADM_MAX_XFER           (SZ_64K-1)
 162 +#define ADM_MAX_ROWS           (SZ_64K-1)
 163 +#define ADM_MAX_CHANNELS       16
 164 +
 165 +struct adm_desc_hw_box {
 166 +       u32 cmd;
 167 +       u32 src_addr;
 168 +       u32 dst_addr;
 169 +       u32 row_len;
 170 +       u32 num_rows;
 171 +       u32 row_offset;
 172 +};
 173 +
 174 +struct adm_desc_hw_single {
 175 +       u32 cmd;
 176 +       u32 src_addr;
 177 +       u32 dst_addr;
 178 +       u32 len;
 179 +};
 180 +
 181 +struct adm_async_desc {
 182 +       struct virt_dma_desc vd;
 183 +       struct adm_device *adev;
 184 +
 185 +       size_t length;
 186 +       enum dma_transfer_direction dir;
 187 +       dma_addr_t dma_addr;
 188 +       size_t dma_len;
 189 +
 190 +       void *cpl;
 191 +       dma_addr_t cp_addr;
 192 +       u32 crci;
 193 +       u32 mux;
 194 +       u32 blk_size;
 195 +};
 196 +
 197 +struct adm_chan {
 198 +       struct virt_dma_chan vc;
 199 +       struct adm_device *adev;
 200 +
 201 +       /* parsed from DT */
 202 +       u32 id;                 /* channel id */
 203 +
 204 +       struct adm_async_desc *curr_txd;
 205 +       struct dma_slave_config slave;
 206 +       struct list_head node;
 207 +
 208 +       int error;
 209 +       int initialized;
 210 +};
 211 +
 212 +static inline struct adm_chan *to_adm_chan(struct dma_chan *common)
 213 +{
 214 +       return container_of(common, struct adm_chan, vc.chan);
 215 +}
 216 +
 217 +struct adm_device {
 218 +       void __iomem *regs;
 219 +       struct device *dev;
 220 +       struct dma_device common;
 221 +       struct device_dma_parameters dma_parms;
 222 +       struct adm_chan *channels;
 223 +
 224 +       u32 ee;
 225 +
 226 +       struct clk *core_clk;
 227 +       struct clk *iface_clk;
 228 +
 229 +       struct reset_control *clk_reset;
 230 +       struct reset_control *c0_reset;
 231 +       struct reset_control *c1_reset;
 232 +       struct reset_control *c2_reset;
 233 +       int irq;
 234 +};
 235 +
 236 +/**
 237 + * adm_free_chan - Frees dma resources associated with the specific channel
 238 + *
 239 + * Free all allocated descriptors associated with this channel
 240 + *
 241 + */
 242 +static void adm_free_chan(struct dma_chan *chan)
 243 +{
 244 +       /* free all queued descriptors */
 245 +       vchan_free_chan_resources(to_virt_chan(chan));
 246 +}
 247 +
 248 +/**
 249 + * adm_get_blksize - Get block size from burst value
 250 + *
 251 + */
 252 +static int adm_get_blksize(unsigned int burst)
 253 +{
 254 +       int ret;
 255 +
 256 +       switch (burst) {
 257 +       case 16:
 258 +       case 32:
 259 +       case 64:
 260 +       case 128:
 261 +               ret = ffs(burst>>4) - 1;
 262 +               break;
 263 +       case 192:
 264 +               ret = 4;
 265 +               break;
 266 +       case 256:
 267 +               ret = 5;
 268 +               break;
 269 +       default:
 270 +               ret = -EINVAL;
 271 +               break;
 272 +       }
 273 +
 274 +       return ret;
 275 +}
 276 +
 277 +/**
 278 + * adm_process_fc_descriptors - Process descriptors for flow controlled xfers
 279 + *
 280 + * @achan: ADM channel
 281 + * @desc: Descriptor memory pointer
 282 + * @sg: Scatterlist entry
 283 + * @crci: CRCI value
 284 + * @burst: Burst size of transaction
 285 + * @direction: DMA transfer direction
 286 + */
 287 +static void *adm_process_fc_descriptors(struct adm_chan *achan,
 288 +       void *desc, struct scatterlist *sg, u32 crci, u32 burst,
 289 +       enum dma_transfer_direction direction)
 290 +{
 291 +       struct adm_desc_hw_box *box_desc = NULL;
 292 +       struct adm_desc_hw_single *single_desc;
 293 +       u32 remainder = sg_dma_len(sg);
 294 +       u32 rows, row_offset, crci_cmd;
 295 +       u32 mem_addr = sg_dma_address(sg);
 296 +       u32 *incr_addr = &mem_addr;
 297 +       u32 *src, *dst;
 298 +
 299 +       if (direction == DMA_DEV_TO_MEM) {
 300 +               crci_cmd = ADM_CMD_SRC_CRCI(crci);
 301 +               row_offset = burst;
 302 +               src = &achan->slave.src_addr;
 303 +               dst = &mem_addr;
 304 +       } else {
 305 +               crci_cmd = ADM_CMD_DST_CRCI(crci);
 306 +               row_offset = burst << 16;
 307 +               src = &mem_addr;
 308 +               dst = &achan->slave.dst_addr;
 309 +       }
 310 +
 311 +       while (remainder >= burst) {
 312 +               box_desc = desc;
 313 +               box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd;
 314 +               box_desc->row_offset = row_offset;
 315 +               box_desc->src_addr = *src;
 316 +               box_desc->dst_addr = *dst;
 317 +
 318 +               rows = remainder / burst;
 319 +               rows = min_t(u32, rows, ADM_MAX_ROWS);
 320 +               box_desc->num_rows = rows << 16 | rows;
 321 +               box_desc->row_len = burst << 16 | burst;
 322 +
 323 +               *incr_addr += burst * rows;
 324 +               remainder -= burst * rows;
 325 +               desc += sizeof(*box_desc);
 326 +       }
 327 +
 328 +       /* if leftover bytes, do one single descriptor */
 329 +       if (remainder) {
 330 +               single_desc = desc;
 331 +               single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd;
 332 +               single_desc->len = remainder;
 333 +               single_desc->src_addr = *src;
 334 +               single_desc->dst_addr = *dst;
 335 +               desc += sizeof(*single_desc);
 336 +
 337 +               if (sg_is_last(sg))
 338 +                       single_desc->cmd |= ADM_CMD_LC;
 339 +       } else {
 340 +               if (box_desc && sg_is_last(sg))
 341 +                       box_desc->cmd |= ADM_CMD_LC;
 342 +       }
 343 +
 344 +       return desc;
 345 +}
 346 +
 347 +/**
 348 + * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers
 349 + *
 350 + * @achan: ADM channel
 351 + * @desc: Descriptor memory pointer
 352 + * @sg: Scatterlist entry
 353 + * @direction: DMA transfer direction
 354 + */
 355 +static void *adm_process_non_fc_descriptors(struct adm_chan *achan,
 356 +       void *desc, struct scatterlist *sg,
 357 +       enum dma_transfer_direction direction)
 358 +{
 359 +       struct adm_desc_hw_single *single_desc;
 360 +       u32 remainder = sg_dma_len(sg);
 361 +       u32 mem_addr = sg_dma_address(sg);
 362 +       u32 *incr_addr = &mem_addr;
 363 +       u32 *src, *dst;
 364 +
 365 +       if (direction == DMA_DEV_TO_MEM) {
 366 +               src = &achan->slave.src_addr;
 367 +               dst = &mem_addr;
 368 +       } else {
 369 +               src = &mem_addr;
 370 +               dst = &achan->slave.dst_addr;
 371 +       }
 372 +
 373 +       do {
 374 +               single_desc = desc;
 375 +               single_desc->cmd = ADM_CMD_TYPE_SINGLE;
 376 +               single_desc->src_addr = *src;
 377 +               single_desc->dst_addr = *dst;
 378 +               single_desc->len = (remainder > ADM_MAX_XFER) ?
 379 +                               ADM_MAX_XFER : remainder;
 380 +
 381 +               remainder -= single_desc->len;
 382 +               *incr_addr += single_desc->len;
 383 +               desc += sizeof(*single_desc);
 384 +       } while (remainder);
 385 +
 386 +       /* set last command if this is the end of the whole transaction */
 387 +       if (sg_is_last(sg))
 388 +               single_desc->cmd |= ADM_CMD_LC;
 389 +
 390 +       return desc;
 391 +}
 392 +
 393 +/**
 394 + * adm_prep_slave_sg - Prep slave sg transaction
 395 + *
 396 + * @chan: dma channel
 397 + * @sgl: scatter gather list
 398 + * @sg_len: length of sg
 399 + * @direction: DMA transfer direction
 400 + * @flags: DMA flags
 401 + * @context: transfer context (unused)
 402 + */
 403 +static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
 404 +       struct scatterlist *sgl, unsigned int sg_len,
 405 +       enum dma_transfer_direction direction, unsigned long flags,
 406 +       void *context)
 407 +{
 408 +       struct adm_chan *achan = to_adm_chan(chan);
 409 +       struct adm_device *adev = achan->adev;
 410 +       struct adm_async_desc *async_desc;
 411 +       struct scatterlist *sg;
 412 +       u32 i, burst;
 413 +       u32 single_count = 0, box_count = 0, crci = 0;
 414 +       void *desc;
 415 +       u32 *cple;
 416 +       int blk_size = 0;
 417 +
 418 +       if (!is_slave_direction(direction)) {
 419 +               dev_err(adev->dev, "invalid dma direction\n");
 420 +               return NULL;
 421 +       }
 422 +
 423 +       /*
 424 +        * get burst value from slave configuration
 425 +        */
 426 +       burst = (direction == DMA_MEM_TO_DEV) ?
 427 +               achan->slave.dst_maxburst :
 428 +               achan->slave.src_maxburst;
 429 +
 430 +       /* if using flow control, validate burst and crci values */
 431 +       if (achan->slave.device_fc) {
 432 +
 433 +               blk_size = adm_get_blksize(burst);
 434 +               if (blk_size < 0) {
 435 +                       dev_err(adev->dev, "invalid burst value: %d\n",
 436 +                               burst);
 437 +                       return ERR_PTR(-EINVAL);
 438 +               }
 439 +
 440 +               crci = achan->slave.slave_id & 0xf;
 441 +               if (!crci || achan->slave.slave_id > 0x1f) {
 442 +                       dev_err(adev->dev, "invalid crci value\n");
 443 +                       return ERR_PTR(-EINVAL);
 444 +               }
 445 +       }
 446 +
 447 +       /* iterate through sgs and compute allocation size of structures */
 448 +       for_each_sg(sgl, sg, sg_len, i) {
 449 +               if (achan->slave.device_fc) {
 450 +                       box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst,
 451 +                                                 ADM_MAX_ROWS);
 452 +                       if (sg_dma_len(sg) % burst)
 453 +                               single_count++;
 454 +               } else {
 455 +                       single_count += DIV_ROUND_UP(sg_dma_len(sg),
 456 +                                                    ADM_MAX_XFER);
 457 +               }
 458 +       }
 459 +
 460 +       async_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT);
 461 +       if (!async_desc)
 462 +               return ERR_PTR(-ENOMEM);
 463 +
 464 +       if (crci)
 465 +               async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ?
 466 +                                       ADM_CRCI_CTL_MUX_SEL : 0;
 467 +       async_desc->crci = crci;
 468 +       async_desc->blk_size = blk_size;
 469 +       async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) +
 470 +                               box_count * sizeof(struct adm_desc_hw_box) +
 471 +                               sizeof(*cple) + 2 * ADM_DESC_ALIGN;
 472 +
 473 +       async_desc->cpl = dma_alloc_writecombine(adev->dev, async_desc->dma_len,
 474 +                               &async_desc->dma_addr, GFP_NOWAIT);
 475 +
 476 +       if (!async_desc->cpl) {
 477 +               kfree(async_desc);
 478 +               return ERR_PTR(-ENOMEM);
 479 +       }
 480 +
 481 +       async_desc->adev = adev;
 482 +
 483 +       /* both command list entry and descriptors must be 8 byte aligned */
 484 +       cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN);
 485 +       desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN);
 486 +
 487 +       /* init cmd list */
 488 +       *cple = ADM_CPLE_LP;
 489 +       *cple |= (desc - async_desc->cpl + async_desc->dma_addr) >> 3;
 490 +
 491 +       for_each_sg(sgl, sg, sg_len, i) {
 492 +               async_desc->length += sg_dma_len(sg);
 493 +
 494 +               if (achan->slave.device_fc)
 495 +                       desc = adm_process_fc_descriptors(achan, desc, sg, crci,
 496 +                                                       burst, direction);
 497 +               else
 498 +                       desc = adm_process_non_fc_descriptors(achan, desc, sg,
 499 +                                                          direction);
 500 +       }
 501 +
 502 +       return vchan_tx_prep(&achan->vc, &async_desc->vd, flags);
 503 +}
 504 +
 505 +/**
 506 + * adm_terminate_all - terminate all transactions on a channel
 507 + * @achan: adm dma channel
 508 + *
 509 + * Dequeues and frees all transactions, aborts current transaction
 510 + * No callbacks are done
 511 + *
 512 + */
 513 +static int adm_terminate_all(struct dma_chan *chan)
 514 +{
 515 +       struct adm_chan *achan = to_adm_chan(chan);
 516 +       struct adm_device *adev = achan->adev;
 517 +       unsigned long flags;
 518 +       LIST_HEAD(head);
 519 +
 520 +       spin_lock_irqsave(&achan->vc.lock, flags);
 521 +       vchan_get_all_descriptors(&achan->vc, &head);
 522 +
 523 +       /* send flush command to terminate current transaction */
 524 +       writel_relaxed(0x0,
 525 +               adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee));
 526 +
 527 +       spin_unlock_irqrestore(&achan->vc.lock, flags);
 528 +
 529 +       vchan_dma_desc_free_list(&achan->vc, &head);
 530 +
 531 +       return 0;
 532 +}
 533 +
 534 +static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
 535 +{
 536 +       struct adm_chan *achan = to_adm_chan(chan);
 537 +       unsigned long flag;
 538 +
 539 +       spin_lock_irqsave(&achan->vc.lock, flag);
 540 +       memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config));
 541 +       spin_unlock_irqrestore(&achan->vc.lock, flag);
 542 +
 543 +       return 0;
 544 +}
 545 +
 546 +/**
 547 + * adm_start_dma - start next transaction
 548 + * @achan - ADM dma channel
 549 + */
 550 +static void adm_start_dma(struct adm_chan *achan)
 551 +{
 552 +       struct virt_dma_desc *vd = vchan_next_desc(&achan->vc);
 553 +       struct adm_device *adev = achan->adev;
 554 +       struct adm_async_desc *async_desc;
 555 +
 556 +       lockdep_assert_held(&achan->vc.lock);
 557 +
 558 +       if (!vd)
 559 +               return;
 560 +
 561 +       list_del(&vd->node);
 562 +
 563 +       /* write next command list out to the CMD FIFO */
 564 +       async_desc = container_of(vd, struct adm_async_desc, vd);
 565 +       achan->curr_txd = async_desc;
 566 +
 567 +       /* reset channel error */
 568 +       achan->error = 0;
 569 +
 570 +       if (!achan->initialized) {
 571 +               /* enable interrupts */
 572 +               writel(ADM_CH_CONF_SHADOW_EN |
 573 +                      ADM_CH_CONF_PERM_MPU_CONF |
 574 +                      ADM_CH_CONF_MPU_DISABLE |
 575 +                      ADM_CH_CONF_SEC_DOMAIN(adev->ee),
 576 +                      adev->regs + ADM_CH_CONF(achan->id));
 577 +
 578 +               writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN,
 579 +                       adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
 580 +
 581 +               achan->initialized = 1;
 582 +       }
 583 +
 584 +       /* set the crci block size if this transaction requires CRCI */
 585 +       if (async_desc->crci) {
 586 +               writel(async_desc->mux | async_desc->blk_size,
 587 +                       adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee));
 588 +       }
 589 +
 590 +       /* make sure IRQ enable doesn't get reordered */
 591 +       wmb();
 592 +
 593 +       /* write next command list out to the CMD FIFO */
 594 +       writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3,
 595 +               adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee));
 596 +}
 597 +
 598 +/**
 599 + * adm_dma_irq - irq handler for ADM controller
 600 + * @irq: IRQ of interrupt
 601 + * @data: callback data
 602 + *
 603 + * IRQ handler for the bam controller
 604 + */
 605 +static irqreturn_t adm_dma_irq(int irq, void *data)
 606 +{
 607 +       struct adm_device *adev = data;
 608 +       u32 srcs, i;
 609 +       struct adm_async_desc *async_desc;
 610 +       unsigned long flags;
 611 +
 612 +       srcs = readl_relaxed(adev->regs +
 613 +                       ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee));
 614 +
 615 +       for (i = 0; i < ADM_MAX_CHANNELS; i++) {
 616 +               struct adm_chan *achan = &adev->channels[i];
 617 +               u32 status, result;
 618 +
 619 +               if (srcs & BIT(i)) {
 620 +                       status = readl_relaxed(adev->regs +
 621 +                               ADM_CH_STATUS_SD(i, adev->ee));
 622 +
 623 +                       /* if no result present, skip */
 624 +                       if (!(status & ADM_CH_STATUS_VALID))
 625 +                               continue;
 626 +
 627 +                       result = readl_relaxed(adev->regs +
 628 +                               ADM_CH_RSLT(i, adev->ee));
 629 +
 630 +                       /* no valid results, skip */
 631 +                       if (!(result & ADM_CH_RSLT_VALID))
 632 +                               continue;
 633 +
 634 +                       /* flag error if transaction was flushed or failed */
 635 +                       if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH))
 636 +                               achan->error = 1;
 637 +
 638 +                       spin_lock_irqsave(&achan->vc.lock, flags);
 639 +                       async_desc = achan->curr_txd;
 640 +
 641 +                       achan->curr_txd = NULL;
 642 +
 643 +                       if (async_desc) {
 644 +                               vchan_cookie_complete(&async_desc->vd);
 645 +
 646 +                               /* kick off next DMA */
 647 +                               adm_start_dma(achan);
 648 +                       }
 649 +
 650 +                       spin_unlock_irqrestore(&achan->vc.lock, flags);
 651 +               }
 652 +       }
 653 +
 654 +       return IRQ_HANDLED;
 655 +}
 656 +
 657 +/**
 658 + * adm_tx_status - returns status of transaction
 659 + * @chan: dma channel
 660 + * @cookie: transaction cookie
 661 + * @txstate: DMA transaction state
 662 + *
 663 + * Return status of dma transaction
 664 + */
 665 +static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 666 +       struct dma_tx_state *txstate)
 667 +{
 668 +       struct adm_chan *achan = to_adm_chan(chan);
 669 +       struct virt_dma_desc *vd;
 670 +       enum dma_status ret;
 671 +       unsigned long flags;
 672 +       size_t residue = 0;
 673 +
 674 +       ret = dma_cookie_status(chan, cookie, txstate);
 675 +       if (ret == DMA_COMPLETE || !txstate)
 676 +               return ret;
 677 +
 678 +       spin_lock_irqsave(&achan->vc.lock, flags);
 679 +
 680 +       vd = vchan_find_desc(&achan->vc, cookie);
 681 +       if (vd)
 682 +               residue = container_of(vd, struct adm_async_desc, vd)->length;
 683 +
 684 +       spin_unlock_irqrestore(&achan->vc.lock, flags);
 685 +
 686 +       /*
 687 +        * residue is either the full length if it is in the issued list, or 0
 688 +        * if it is in progress.  We have no reliable way of determining
 689 +        * anything inbetween
 690 +       */
 691 +       dma_set_residue(txstate, residue);
 692 +
 693 +       if (achan->error)
 694 +               return DMA_ERROR;
 695 +
 696 +       return ret;
 697 +}
 698 +
 699 +/**
 700 + * adm_issue_pending - starts pending transactions
 701 + * @chan: dma channel
 702 + *
 703 + * Issues all pending transactions and starts DMA
 704 + */
 705 +static void adm_issue_pending(struct dma_chan *chan)
 706 +{
 707 +       struct adm_chan *achan = to_adm_chan(chan);
 708 +       unsigned long flags;
 709 +
 710 +       spin_lock_irqsave(&achan->vc.lock, flags);
 711 +
 712 +       if (vchan_issue_pending(&achan->vc) && !achan->curr_txd)
 713 +               adm_start_dma(achan);
 714 +       spin_unlock_irqrestore(&achan->vc.lock, flags);
 715 +}
 716 +
 717 +/**
 718 + * adm_dma_free_desc - free descriptor memory
 719 + * @vd: virtual descriptor
 720 + *
 721 + */
 722 +static void adm_dma_free_desc(struct virt_dma_desc *vd)
 723 +{
 724 +       struct adm_async_desc *async_desc = container_of(vd,
 725 +                       struct adm_async_desc, vd);
 726 +
 727 +       dma_free_writecombine(async_desc->adev->dev, async_desc->dma_len,
 728 +               async_desc->cpl, async_desc->dma_addr);
 729 +       kfree(async_desc);
 730 +}
 731 +
 732 +static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan,
 733 +       u32 index)
 734 +{
 735 +       achan->id = index;
 736 +       achan->adev = adev;
 737 +
 738 +       vchan_init(&achan->vc, &adev->common);
 739 +       achan->vc.desc_free = adm_dma_free_desc;
 740 +}
 741 +
 742 +static int adm_dma_probe(struct platform_device *pdev)
 743 +{
 744 +       struct adm_device *adev;
 745 +       struct resource *iores;
 746 +       int ret;
 747 +       u32 i;
 748 +
 749 +       adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
 750 +       if (!adev)
 751 +               return -ENOMEM;
 752 +
 753 +       adev->dev = &pdev->dev;
 754 +
 755 +       iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 756 +       adev->regs = devm_ioremap_resource(&pdev->dev, iores);
 757 +       if (IS_ERR(adev->regs))
 758 +               return PTR_ERR(adev->regs);
 759 +
 760 +       adev->irq = platform_get_irq(pdev, 0);
 761 +       if (adev->irq < 0)
 762 +               return adev->irq;
 763 +
 764 +       ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee);
 765 +       if (ret) {
 766 +               dev_err(adev->dev, "Execution environment unspecified\n");
 767 +               return ret;
 768 +       }
 769 +
 770 +       adev->core_clk = devm_clk_get(adev->dev, "core");
 771 +       if (IS_ERR(adev->core_clk))
 772 +               return PTR_ERR(adev->core_clk);
 773 +
 774 +       ret = clk_prepare_enable(adev->core_clk);
 775 +       if (ret) {
 776 +               dev_err(adev->dev, "failed to prepare/enable core clock\n");
 777 +               return ret;
 778 +       }
 779 +
 780 +       adev->iface_clk = devm_clk_get(adev->dev, "iface");
 781 +       if (IS_ERR(adev->iface_clk)) {
 782 +               ret = PTR_ERR(adev->iface_clk);
 783 +               goto err_disable_core_clk;
 784 +       }
 785 +
 786 +       ret = clk_prepare_enable(adev->iface_clk);
 787 +       if (ret) {
 788 +               dev_err(adev->dev, "failed to prepare/enable iface clock\n");
 789 +               goto err_disable_core_clk;
 790 +       }
 791 +
 792 +       adev->clk_reset = devm_reset_control_get(&pdev->dev, "clk");
 793 +       if (IS_ERR(adev->clk_reset)) {
 794 +               dev_err(adev->dev, "failed to get ADM0 reset\n");
 795 +               ret = PTR_ERR(adev->clk_reset);
 796 +               goto err_disable_clks;
 797 +       }
 798 +
 799 +       adev->c0_reset = devm_reset_control_get(&pdev->dev, "c0");
 800 +       if (IS_ERR(adev->c0_reset)) {
 801 +               dev_err(adev->dev, "failed to get ADM0 C0 reset\n");
 802 +               ret = PTR_ERR(adev->c0_reset);
 803 +               goto err_disable_clks;
 804 +       }
 805 +
 806 +       adev->c1_reset = devm_reset_control_get(&pdev->dev, "c1");
 807 +       if (IS_ERR(adev->c1_reset)) {
 808 +               dev_err(adev->dev, "failed to get ADM0 C1 reset\n");
 809 +               ret = PTR_ERR(adev->c1_reset);
 810 +               goto err_disable_clks;
 811 +       }
 812 +
 813 +       adev->c2_reset = devm_reset_control_get(&pdev->dev, "c2");
 814 +       if (IS_ERR(adev->c2_reset)) {
 815 +               dev_err(adev->dev, "failed to get ADM0 C2 reset\n");
 816 +               ret = PTR_ERR(adev->c2_reset);
 817 +               goto err_disable_clks;
 818 +       }
 819 +
 820 +       reset_control_assert(adev->clk_reset);
 821 +       reset_control_assert(adev->c0_reset);
 822 +       reset_control_assert(adev->c1_reset);
 823 +       reset_control_assert(adev->c2_reset);
 824 +
 825 +       reset_control_deassert(adev->clk_reset);
 826 +       reset_control_deassert(adev->c0_reset);
 827 +       reset_control_deassert(adev->c1_reset);
 828 +       reset_control_deassert(adev->c2_reset);
 829 +
 830 +       adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS,
 831 +                               sizeof(*adev->channels), GFP_KERNEL);
 832 +
 833 +       if (!adev->channels) {
 834 +               ret = -ENOMEM;
 835 +               goto err_disable_clks;
 836 +       }
 837 +
 838 +       /* allocate and initialize channels */
 839 +       INIT_LIST_HEAD(&adev->common.channels);
 840 +
 841 +       for (i = 0; i < ADM_MAX_CHANNELS; i++)
 842 +               adm_channel_init(adev, &adev->channels[i], i);
 843 +
 844 +       /* reset CRCIs */
 845 +       for (i = 0; i < 16; i++)
 846 +               writel(ADM_CRCI_CTL_RST, adev->regs +
 847 +                       ADM_CRCI_CTL(i, adev->ee));
 848 +
 849 +       /* configure client interfaces */
 850 +       writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) |
 851 +               ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0));
 852 +       writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) |
 853 +               ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1));
 854 +       writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) |
 855 +               ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2));
 856 +       writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf),
 857 +               adev->regs + ADM_GP_CTL);
 858 +
 859 +       ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq,
 860 +                       0, "adm_dma", adev);
 861 +       if (ret)
 862 +               goto err_disable_clks;
 863 +
 864 +       platform_set_drvdata(pdev, adev);
 865 +
 866 +       adev->common.dev = adev->dev;
 867 +       adev->common.dev->dma_parms = &adev->dma_parms;
 868 +
 869 +       /* set capabilities */
 870 +       dma_cap_zero(adev->common.cap_mask);
 871 +       dma_cap_set(DMA_SLAVE, adev->common.cap_mask);
 872 +       dma_cap_set(DMA_PRIVATE, adev->common.cap_mask);
 873 +
 874 +       /* initialize dmaengine apis */
 875 +       adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV);
 876 +       adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
 877 +       adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
 878 +       adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
 879 +       adev->common.device_free_chan_resources = adm_free_chan;
 880 +       adev->common.device_prep_slave_sg = adm_prep_slave_sg;
 881 +       adev->common.device_issue_pending = adm_issue_pending;
 882 +       adev->common.device_tx_status = adm_tx_status;
 883 +       adev->common.device_terminate_all = adm_terminate_all;
 884 +       adev->common.device_config = adm_slave_config;
 885 +
 886 +       ret = dma_async_device_register(&adev->common);
 887 +       if (ret) {
 888 +               dev_err(adev->dev, "failed to register dma async device\n");
 889 +               goto err_disable_clks;
 890 +       }
 891 +
 892 +       ret = of_dma_controller_register(pdev->dev.of_node,
 893 +                                        of_dma_xlate_by_chan_id,
 894 +                                        &adev->common);
 895 +       if (ret)
 896 +               goto err_unregister_dma;
 897 +
 898 +       return 0;
 899 +
 900 +err_unregister_dma:
 901 +       dma_async_device_unregister(&adev->common);
 902 +err_disable_clks:
 903 +       clk_disable_unprepare(adev->iface_clk);
 904 +err_disable_core_clk:
 905 +       clk_disable_unprepare(adev->core_clk);
 906 +
 907 +       return ret;
 908 +}
 909 +
 910 +static int adm_dma_remove(struct platform_device *pdev)
 911 +{
 912 +       struct adm_device *adev = platform_get_drvdata(pdev);
 913 +       struct adm_chan *achan;
 914 +       u32 i;
 915 +
 916 +       of_dma_controller_free(pdev->dev.of_node);
 917 +       dma_async_device_unregister(&adev->common);
 918 +
 919 +       for (i = 0; i < ADM_MAX_CHANNELS; i++) {
 920 +               achan = &adev->channels[i];
 921 +
 922 +               /* mask IRQs for this channel/EE pair */
 923 +               writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
 924 +
 925 +               adm_terminate_all(&adev->channels[i].vc.chan);
 926 +       }
 927 +
 928 +       devm_free_irq(adev->dev, adev->irq, adev);
 929 +
 930 +       clk_disable_unprepare(adev->core_clk);
 931 +       clk_disable_unprepare(adev->iface_clk);
 932 +
 933 +       return 0;
 934 +}
 935 +
 936 +static const struct of_device_id adm_of_match[] = {
 937 +       { .compatible = "qcom,adm", },
 938 +       {}
 939 +};
 940 +MODULE_DEVICE_TABLE(of, adm_of_match);
 941 +
 942 +static struct platform_driver adm_dma_driver = {
 943 +       .probe = adm_dma_probe,
 944 +       .remove = adm_dma_remove,
 945 +       .driver = {
 946 +               .name = "adm-dma-engine",
 947 +               .of_match_table = adm_of_match,
 948 +       },
 949 +};
 950 +
 951 +module_platform_driver(adm_dma_driver);
 952 +
 953 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 954 +MODULE_DESCRIPTION("QCOM ADM DMA engine driver");
 955 +MODULE_LICENSE("GPL v2");
 956 --- a/drivers/dma/Makefile
 957 +++ b/drivers/dma/Makefile
 958 @@ -54,3 +54,4 @@ obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o
 959  obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
 960  obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
 961  obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
 962 +obj-$(CONFIG_QCOM_ADM) += qcom_adm.o