target/linux/ipq806x/patches-4.1/022-add-db149-dts.patch

   1 From f26cc3733bdd697bd81ae505fc133fa7c9b6ea19 Mon Sep 17 00:00:00 2001
   2 From: Mathieu Olivari <mathieu@codeaurora.org>
   3 Date: Tue, 7 Apr 2015 19:58:58 -0700
   4 Subject: [PATCH] ARM: dts: qcom: add initial DB149 device-tree
   5
   6 Add basic DB149 (IPQ806x based platform) device-tree. It supports UART,
   7 SATA, USB2, USB3 and NOR flash.
   8
   9 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  10 ---
  11  arch/arm/boot/dts/Makefile               |   1 +
  12  arch/arm/boot/dts/qcom-ipq8064-db149.dts | 132 +++++++++++++++++++++++++++++++
  13  2 files changed, 133 insertions(+)
  14  create mode 100644 arch/arm/boot/dts/qcom-ipq8064-db149.dts
  15
  16 --- a/arch/arm/boot/dts/Makefile
  17 +++ b/arch/arm/boot/dts/Makefile
  18 @@ -451,6 +451,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
  19         qcom-apq8084-ifc6540.dtb \
  20         qcom-apq8084-mtp.dtb \
  21         qcom-ipq8064-ap148.dtb \
  22 +       qcom-ipq8064-db149.dtb \
  23         qcom-msm8660-surf.dtb \
  24         qcom-msm8960-cdp.dtb \
  25         qcom-msm8974-sony-xperia-honami.dtb
  26 --- /dev/null
  27 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
  28 @@ -0,0 +1,132 @@
  29 +#include "qcom-ipq8064-v1.0.dtsi"
  30 +
  31 +/ {
  32 +       model = "Qualcomm IPQ8064/DB149";
  33 +       compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
  34 +
  35 +       reserved-memory {
  36 +               #address-cells = <1>;
  37 +               #size-cells = <1>;
  38 +               ranges;
  39 +               rsvd@41200000 {
  40 +                       reg = <0x41200000 0x300000>;
  41 +                       no-map;
  42 +               };
  43 +       };
  44 +
  45 +       alias {
  46 +               serial0 = &uart2;
  47 +       };
  48 +
  49 +       chosen {
  50 +               linux,stdout-path = "serial0:115200n8";
  51 +       };
  52 +
  53 +       soc {
  54 +               pinmux@800000 {
  55 +                       i2c4_pins: i2c4_pinmux {
  56 +                               pins = "gpio12", "gpio13";
  57 +                               function = "gsbi4";
  58 +                               bias-disable;
  59 +                       };
  60 +
  61 +                       spi_pins: spi_pins {
  62 +                               mux {
  63 +                                       pins = "gpio18", "gpio19", "gpio21";
  64 +                                       function = "gsbi5";
  65 +                                       drive-strength = <10>;
  66 +                                       bias-none;
  67 +                               };
  68 +                       };
  69 +               };
  70 +
  71 +               gsbi2: gsbi@12480000 {
  72 +                       qcom,mode = <GSBI_PROT_I2C_UART>;
  73 +                       status = "ok";
  74 +                       uart2: serial@12490000 {
  75 +                               status = "ok";
  76 +                       };
  77 +               };
  78 +
  79 +               gsbi5: gsbi@1a200000 {
  80 +                       qcom,mode = <GSBI_PROT_SPI>;
  81 +                       status = "ok";
  82 +
  83 +                       spi4: spi@1a280000 {
  84 +                               status = "ok";
  85 +                               spi-max-frequency = <50000000>;
  86 +
  87 +                               pinctrl-0 = <&spi_pins>;
  88 +                               pinctrl-names = "default";
  89 +
  90 +                               cs-gpios = <&qcom_pinmux 20 0>;
  91 +
  92 +                               flash: m25p80@0 {
  93 +                                       compatible = "s25fl256s1";
  94 +                                       #address-cells = <1>;
  95 +                                       #size-cells = <1>;
  96 +                                       spi-max-frequency = <50000000>;
  97 +                                       reg = <0>;
  98 +                                       m25p,fast-read;
  99 +
 100 +                                       partition@0 {
 101 +                                               label = "lowlevel_init";
 102 +                                               reg = <0x0 0x1b0000>;
 103 +                                       };
 104 +
 105 +                                       partition@1 {
 106 +                                               label = "u-boot";
 107 +                                               reg = <0x1b0000 0x80000>;
 108 +                                       };
 109 +
 110 +                                       partition@2 {
 111 +                                               label = "u-boot-env";
 112 +                                               reg = <0x230000 0x40000>;
 113 +                                       };
 114 +
 115 +                                       partition@3 {
 116 +                                               label = "caldata";
 117 +                                               reg = <0x270000 0x40000>;
 118 +                                       };
 119 +
 120 +                                       partition@4 {
 121 +                                               label = "firmware";
 122 +                                               reg = <0x2b0000 0x1d50000>;
 123 +                                       };
 124 +                               };
 125 +                       };
 126 +               };
 127 +
 128 +               sata-phy@1b400000 {
 129 +                       status = "ok";
 130 +               };
 131 +
 132 +               sata@29000000 {
 133 +                       status = "ok";
 134 +               };
 135 +
 136 +               phy@100f8800 {          /* USB3 port 1 HS phy */
 137 +                       status = "ok";
 138 +               };
 139 +
 140 +               phy@100f8830 {          /* USB3 port 1 SS phy */
 141 +                       status = "ok";
 142 +               };
 143 +
 144 +               phy@110f8800 {          /* USB3 port 0 HS phy */
 145 +                       status = "ok";
 146 +               };
 147 +
 148 +               phy@110f8830 {          /* USB3 port 0 SS phy */
 149 +                       status = "ok";
 150 +               };
 151 +
 152 +               usb30@0 {
 153 +                       status = "ok";
 154 +               };
 155 +
 156 +               usb30@1 {
 157 +                       status = "ok";
 158 +               };
 159 +       };
 160 +};