target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch

   1 From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
   2 From: Mathieu Olivari <mathieu@codeaurora.org>
   3 Date: Tue, 21 Apr 2015 19:01:42 -0700
   4 Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
   5
   6 qcom-pcie driver now supports version 0 of the controller. This change
   7 adds the corresponding entries to the IPQ806x dtsi file and
   8 corresponding platform (AP148).
   9
  10 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  11 ---
  12  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |  30 ++++++++
  13  arch/arm/boot/dts/qcom-ipq8064.dtsi      | 124 +++++++++++++++++++++++++++++++
  14  2 files changed, 154 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  17 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  18 @@ -115,5 +115,15 @@
  19                 usb30@1 {
  20                         status = "ok";
  21                 };
  22 +
  23 +               pcie0: pci@1b500000 {
  24 +                       status = "ok";
  25 +                       phy-tx0-term-offset = <7>;
  26 +               };
  27 +
  28 +               pcie1: pci@1b700000 {
  29 +                       status = "ok";
  30 +                       phy-tx0-term-offset = <7>;
  31 +               };
  32         };
  33  };
  34 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
  35 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
  36 @@ -128,5 +128,17 @@
  37                 usb30@1 {
  38                         status = "ok";
  39                 };
  40 +
  41 +               pcie0: pci@1b500000 {
  42 +                       status = "ok";
  43 +               };
  44 +
  45 +               pcie1: pci@1b700000 {
  46 +                       status = "ok";
  47 +               };
  48 +
  49 +               pcie2: pci@1b900000 {
  50 +                       status = "ok";
  51 +               };
  52         };
  53  };
  54 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  55 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  56 @@ -3,6 +3,9 @@
  57  #include "skeleton.dtsi"
  58  #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  59  #include <dt-bindings/soc/qcom,gsbi.h>
  60 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  61 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  62 +#include <dt-bindings/gpio/gpio.h>
  63
  64  / {
  65         model = "Qualcomm IPQ8064";
  66 @@ -83,6 +86,33 @@
  67                         interrupt-controller;
  68                         #interrupt-cells = <2>;
  69                         interrupts = <0 32 0x4>;
  70 +
  71 +                       pcie0_pins: pcie0_pinmux {
  72 +                               mux {
  73 +                                       pins = "gpio3";
  74 +                                       function = "pcie1_rst";
  75 +                                       drive-strength = <12>;
  76 +                                       bias-disable;
  77 +                               };
  78 +                       };
  79 +
  80 +                       pcie1_pins: pcie1_pinmux {
  81 +                               mux {
  82 +                                       pins = "gpio48";
  83 +                                       function = "pcie2_rst";
  84 +                                       drive-strength = <12>;
  85 +                                       bias-disable;
  86 +                               };
  87 +                       };
  88 +
  89 +                       pcie2_pins: pcie2_pinmux {
  90 +                               mux {
  91 +                                       pins = "gpio63";
  92 +                                       function = "pcie3_rst";
  93 +                                       drive-strength = <12>;
  94 +                                       bias-disable;
  95 +                               };
  96 +                       };
  97                 };
  98
  99                 intc: interrupt-controller@2000000 {
 100 @@ -311,6 +341,144 @@
 101                         reg = <0x01200600 0x100>;
 102                 };
 103
 104 +               pcie0: pci@1b500000 {
 105 +                       compatible = "qcom,pcie-v0";
 106 +                       reg = <0x1b500000 0x1000
 107 +                              0x1b502000 0x80
 108 +                              0x1b600000 0x100
 109 +                              0x0ff00000 0x100000>;
 110 +                       reg-names = "dbi", "elbi", "parf", "config";
 111 +                       device_type = "pci";
 112 +                       linux,pci-domain = <0>;
 113 +                       bus-range = <0x00 0xff>;
 114 +                       num-lanes = <1>;
 115 +                       #address-cells = <3>;
 116 +                       #size-cells = <2>;
 117 +
 118 +                       ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
 119 +                                 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 120 +
 121 +                       interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 122 +                       interrupt-names = "msi";
 123 +                       #interrupt-cells = <1>;
 124 +                       interrupt-map-mask = <0 0 0 0x7>;
 125 +                       interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 126 +                                       <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 127 +                                       <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 128 +                                       <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 129 +
 130 +                       clocks = <&gcc PCIE_A_CLK>,
 131 +                                <&gcc PCIE_H_CLK>,
 132 +                                <&gcc PCIE_PHY_CLK>;
 133 +                       clock-names = "core", "iface", "phy";
 134 +
 135 +                       resets = <&gcc PCIE_ACLK_RESET>,
 136 +                                <&gcc PCIE_HCLK_RESET>,
 137 +                                <&gcc PCIE_POR_RESET>,
 138 +                                <&gcc PCIE_PCI_RESET>,
 139 +                                <&gcc PCIE_PHY_RESET>;
 140 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 141 +
 142 +                       pinctrl-0 = <&pcie0_pins>;
 143 +                       pinctrl-names = "default";
 144 +
 145 +                       perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
 146 +
 147 +                       status = "disabled";
 148 +               };
 149 +
 150 +               pcie1: pci@1b700000 {
 151 +                       compatible = "qcom,pcie-v0";
 152 +                       reg = <0x1b700000 0x1000
 153 +                              0x1b702000 0x80
 154 +                              0x1b800000 0x100
 155 +                              0x31f00000 0x100000>;
 156 +                       reg-names = "dbi", "elbi", "parf", "config";
 157 +                       device_type = "pci";
 158 +                       linux,pci-domain = <1>;
 159 +                       bus-range = <0x00 0xff>;
 160 +                       num-lanes = <1>;
 161 +                       #address-cells = <3>;
 162 +                       #size-cells = <2>;
 163 +
 164 +                       ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
 165 +                                 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 166 +
 167 +                       interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
 168 +                       interrupt-names = "msi";
 169 +                       #interrupt-cells = <1>;
 170 +                       interrupt-map-mask = <0 0 0 0x7>;
 171 +                       interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 172 +                                       <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 173 +                                       <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 174 +                                       <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 175 +
 176 +                       clocks = <&gcc PCIE_1_A_CLK>,
 177 +                                <&gcc PCIE_1_H_CLK>,
 178 +                                <&gcc PCIE_1_PHY_CLK>;
 179 +                       clock-names = "core", "iface", "phy";
 180 +
 181 +                       resets = <&gcc PCIE_1_ACLK_RESET>,
 182 +                                <&gcc PCIE_1_HCLK_RESET>,
 183 +                                <&gcc PCIE_1_POR_RESET>,
 184 +                                <&gcc PCIE_1_PCI_RESET>,
 185 +                                <&gcc PCIE_1_PHY_RESET>;
 186 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 187 +
 188 +                       pinctrl-0 = <&pcie1_pins>;
 189 +                       pinctrl-names = "default";
 190 +
 191 +                       perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
 192 +
 193 +                       status = "disabled";
 194 +               };
 195 +
 196 +               pcie2: pci@1b900000 {
 197 +                       compatible = "qcom,pcie-v0";
 198 +                       reg = <0x1b900000 0x1000
 199 +                              0x1b902000 0x80
 200 +                              0x1ba00000 0x100
 201 +                              0x35f00000 0x100000>;
 202 +                       reg-names = "dbi", "elbi", "parf", "config";
 203 +                       device_type = "pci";
 204 +                       linux,pci-domain = <2>;
 205 +                       bus-range = <0x00 0xff>;
 206 +                       num-lanes = <1>;
 207 +                       #address-cells = <3>;
 208 +                       #size-cells = <2>;
 209 +
 210 +                       ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
 211 +                                 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 212 +
 213 +                       interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
 214 +                       interrupt-names = "msi";
 215 +                       #interrupt-cells = <1>;
 216 +                       interrupt-map-mask = <0 0 0 0x7>;
 217 +                       interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 218 +                                       <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 219 +                                       <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 220 +                                       <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 221 +
 222 +                       clocks = <&gcc PCIE_2_A_CLK>,
 223 +                                <&gcc PCIE_2_H_CLK>,
 224 +                                <&gcc PCIE_2_PHY_CLK>;
 225 +                       clock-names = "core", "iface", "phy";
 226 +
 227 +                       resets = <&gcc PCIE_2_ACLK_RESET>,
 228 +                                <&gcc PCIE_2_HCLK_RESET>,
 229 +                                <&gcc PCIE_2_POR_RESET>,
 230 +                                <&gcc PCIE_2_PCI_RESET>,
 231 +                                <&gcc PCIE_2_PHY_RESET>;
 232 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 233 +
 234 +                       pinctrl-0 = <&pcie2_pins>;
 235 +                       pinctrl-names = "default";
 236 +
 237 +                       perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
 238 +
 239 +                       status = "disabled";
 240 +               };
 241 +
 242                 hs_phy_1: phy@100f8800 {
 243                         compatible = "qcom,dwc3-hs-usb-phy";
 244                         reg = <0x100f8800 0x30>;