target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch

   1 From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
   2 From: Mathieu Olivari <mathieu@codeaurora.org>
   3 Date: Tue, 21 Apr 2015 19:01:42 -0700
   4 Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
   5
   6 qcom-pcie driver now supports version 0 of the controller. This change
   7 adds the corresponding entries to the IPQ806x dtsi file and
   8 corresponding platform (AP148).
   9
  10 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  11 ---
  12  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |  30 ++++++++
  13  arch/arm/boot/dts/qcom-ipq8064.dtsi      | 124 +++++++++++++++++++++++++++++++
  14  2 files changed, 154 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  17 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  18 @@ -30,6 +30,22 @@
  19                                 bias-disable;
  20                         };
  21
  22 +                       pcie1_pins: pcie1_pinmux {
  23 +                               mux {
  24 +                                       pins = "gpio3";
  25 +                                       drive-strength = <2>;
  26 +                                       bias-disable;
  27 +                               };
  28 +                       };
  29 +
  30 +                       pcie2_pins: pcie2_pinmux {
  31 +                               mux {
  32 +                                       pins = "gpio48";
  33 +                                       drive-strength = <2>;
  34 +                                       bias-disable;
  35 +                               };
  36 +                       };
  37 +
  38                         spi_pins: spi_pins {
  39                                 mux {
  40                                         pins = "gpio18", "gpio19", "gpio21";
  41 @@ -133,5 +149,19 @@
  42                 usb30@1 {
  43                         status = "ok";
  44                 };
  45 +
  46 +               pcie0: pci@1b500000 {
  47 +                       status = "ok";
  48 +                       reset-gpio = <&qcom_pinmux 3 0>;
  49 +                       pinctrl-0 = <&pcie1_pins>;
  50 +                       pinctrl-names = "default";
  51 +               };
  52 +
  53 +               pcie1: pci@1b700000 {
  54 +                       status = "ok";
  55 +                       reset-gpio = <&qcom_pinmux 48 0>;
  56 +                       pinctrl-0 = <&pcie2_pins>;
  57 +                       pinctrl-names = "default";
  58 +               };
  59         };
  60  };
  61 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
  62 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
  63 @@ -30,6 +30,30 @@
  64                                 bias-disable;
  65                         };
  66
  67 +                       pcie1_pins: pcie1_pinmux {
  68 +                               mux {
  69 +                                       pins = "gpio3";
  70 +                                       drive-strength = <2>;
  71 +                                       bias-disable;
  72 +                               };
  73 +                       };
  74 +
  75 +                       pcie2_pins: pcie2_pinmux {
  76 +                               mux {
  77 +                                       pins = "gpio48";
  78 +                                       drive-strength = <2>;
  79 +                                       bias-disable;
  80 +                               };
  81 +                       };
  82 +
  83 +                       pcie3_pins: pcie3_pinmux {
  84 +                               mux {
  85 +                                       pins = "gpio63";
  86 +                                       drive-strength = <2>;
  87 +                                       bias-disable;
  88 +                               };
  89 +                       };
  90 +
  91                         spi_pins: spi_pins {
  92                                 mux {
  93                                         pins = "gpio18", "gpio19", "gpio21";
  94 @@ -128,5 +152,26 @@
  95                 usb30@1 {
  96                         status = "ok";
  97                 };
  98 +
  99 +               pcie0: pci@1b500000 {
 100 +                       status = "ok";
 101 +                       reset-gpio = <&qcom_pinmux 3 0>;
 102 +                       pinctrl-0 = <&pcie1_pins>;
 103 +                       pinctrl-names = "default";
 104 +               };
 105 +
 106 +               pcie1: pci@1b700000 {
 107 +                       status = "ok";
 108 +                       reset-gpio = <&qcom_pinmux 48 0>;
 109 +                       pinctrl-0 = <&pcie2_pins>;
 110 +                       pinctrl-names = "default";
 111 +               };
 112 +
 113 +               pcie2: pci@1b900000 {
 114 +                       status = "ok";
 115 +                       reset-gpio = <&qcom_pinmux 63 0>;
 116 +                       pinctrl-0 = <&pcie3_pins>;
 117 +                       pinctrl-names = "default";
 118 +               };
 119         };
 120  };
 121 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 122 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
 123 @@ -3,6 +3,8 @@
 124  #include "skeleton.dtsi"
 125  #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
 126  #include <dt-bindings/soc/qcom,gsbi.h>
 127 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
 128 +#include <dt-bindings/interrupt-controller/arm-gic.h>
 129
 130  / {
 131         model = "Qualcomm IPQ8064";
 132 @@ -306,6 +308,129 @@
 133                         #reset-cells = <1>;
 134                 };
 135
 136 +               pcie0: pci@1b500000 {
 137 +                       compatible = "qcom,pcie-v0";
 138 +                       reg = <0x1b500000 0x1000
 139 +                              0x1b502000 0x80
 140 +                              0x1b600000 0x100
 141 +                              0x0ff00000 0x100000>;
 142 +                       reg-names = "dbi", "elbi", "parf", "config";
 143 +                       device_type = "pci";
 144 +                       linux,pci-domain = <0>;
 145 +                       bus-range = <0x00 0xff>;
 146 +                       num-lanes = <1>;
 147 +                       #address-cells = <3>;
 148 +                       #size-cells = <2>;
 149 +
 150 +                       ranges = <0x81000000 0 0          0x0fe00000 0 0x00100000   /* downstream I/O */
 151 +                                 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 152 +
 153 +                       interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 154 +                       interrupt-names = "msi";
 155 +                       #interrupt-cells = <1>;
 156 +                       interrupt-map-mask = <0 0 0 0x7>;
 157 +                       interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 158 +                                       <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 159 +                                       <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 160 +                                       <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 161 +
 162 +                       clocks = <&gcc PCIE_A_CLK>,
 163 +                                <&gcc PCIE_H_CLK>,
 164 +                                <&gcc PCIE_PHY_CLK>;
 165 +                       clock-names = "core", "iface", "phy";
 166 +
 167 +                       resets = <&gcc PCIE_ACLK_RESET>,
 168 +                                <&gcc PCIE_HCLK_RESET>,
 169 +                                <&gcc PCIE_POR_RESET>,
 170 +                                <&gcc PCIE_PCI_RESET>,
 171 +                                <&gcc PCIE_PHY_RESET>;
 172 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 173 +
 174 +                       status = "disabled";
 175 +               };
 176 +
 177 +               pcie1: pci@1b700000 {
 178 +                       compatible = "qcom,pcie-v0";
 179 +                       reg = <0x1b700000 0x1000
 180 +                              0x1b702000 0x80
 181 +                              0x1b800000 0x100
 182 +                              0x31f00000 0x100000>;
 183 +                       reg-names = "dbi", "elbi", "parf", "config";
 184 +                       device_type = "pci";
 185 +                       linux,pci-domain = <1>;
 186 +                       bus-range = <0x00 0xff>;
 187 +                       num-lanes = <1>;
 188 +                       #address-cells = <3>;
 189 +                       #size-cells = <2>;
 190 +
 191 +                       ranges = <0x81000000 0 0          0x31e00000 0 0x00100000   /* downstream I/O */
 192 +                                 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 193 +
 194 +                       interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
 195 +                       interrupt-names = "msi";
 196 +                       #interrupt-cells = <1>;
 197 +                       interrupt-map-mask = <0 0 0 0x7>;
 198 +                       interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 199 +                                       <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 200 +                                       <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 201 +                                       <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 202 +
 203 +                       clocks = <&gcc PCIE_1_A_CLK>,
 204 +                                <&gcc PCIE_1_H_CLK>,
 205 +                                <&gcc PCIE_1_PHY_CLK>;
 206 +                       clock-names = "core", "iface", "phy";
 207 +
 208 +                       resets = <&gcc PCIE_1_ACLK_RESET>,
 209 +                                <&gcc PCIE_1_HCLK_RESET>,
 210 +                                <&gcc PCIE_1_POR_RESET>,
 211 +                                <&gcc PCIE_1_PCI_RESET>,
 212 +                                <&gcc PCIE_1_PHY_RESET>;
 213 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 214 +
 215 +                       status = "disabled";
 216 +               };
 217 +
 218 +               pcie2: pci@1b900000 {
 219 +                       compatible = "qcom,pcie-v0";
 220 +                       reg = <0x1b900000 0x1000
 221 +                              0x1b902000 0x80
 222 +                              0x1ba00000 0x100
 223 +                              0x35f00000 0x100000>;
 224 +                       reg-names = "dbi", "elbi", "parf", "config";
 225 +                       device_type = "pci";
 226 +                       linux,pci-domain = <2>;
 227 +                       bus-range = <0x00 0xff>;
 228 +                       num-lanes = <1>;
 229 +                       #address-cells = <3>;
 230 +                       #size-cells = <2>;
 231 +
 232 +                       ranges = <0x81000000 0 0          0x35e00000 0 0x00100000   /* downstream I/O */
 233 +                                 0x82000000 0 0x00000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 234 +
 235 +                       interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
 236 +                       interrupt-names = "msi";
 237 +                       #interrupt-cells = <1>;
 238 +                       interrupt-map-mask = <0 0 0 0x7>;
 239 +                       interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 240 +                                       <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 241 +                                       <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 242 +                                       <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 243 +
 244 +                       clocks = <&gcc PCIE_2_A_CLK>,
 245 +                                <&gcc PCIE_2_H_CLK>,
 246 +                                <&gcc PCIE_2_PHY_CLK>;
 247 +                       clock-names = "core", "iface", "phy";
 248 +
 249 +                       resets = <&gcc PCIE_2_ACLK_RESET>,
 250 +                                <&gcc PCIE_2_HCLK_RESET>,
 251 +                                <&gcc PCIE_2_POR_RESET>,
 252 +                                <&gcc PCIE_2_PCI_RESET>,
 253 +                                <&gcc PCIE_2_PHY_RESET>;
 254 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 255 +
 256 +                       status = "disabled";
 257 +               };
 258 +
 259                 hs_phy_1: phy@100f8800 {
 260                         compatible = "qcom,dwc3-hs-usb-phy";
 261                         reg = <0x100f8800 0x30>;
 262 @@ -389,6 +514,5 @@
 263                                 dr_mode = "host";
 264                         };
 265                 };
 266 -
 267         };
 268  };