1 /*****************************************************************************
3 * Copyright (c) 2005, Infineon Technologies AG, All rights reserved
5 *****************************************************************************/
9 #include <asm/danube.h>
10 #include <asm/addrspace.h>
11 #include <asm/ifx_asc.h>
14 #define ASC_FIFO_PRESENT
15 #define SET_BIT(reg, mask) reg |= (mask)
16 #define CLEAR_BIT(reg, mask) reg &= (~mask)
17 #define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
18 #define SET_BITS(reg, mask) SET_BIT(reg, mask)
19 #define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
22 typedef unsigned char u8;
23 typedef unsigned short u16;
24 typedef unsigned long u32;
25 typedef signed long s32;
26 typedef unsigned int uint;
27 typedef unsigned long ulong;
28 typedef volatile unsigned short vuint;
32 void serial_setbrg (void);
34 /*TODO: undefine this !!!*/
37 #define DEBUG_ASC_RAW_RX_BUF 0xA0800000
38 #define DEBUG_ASC_RAW_TX_BUF 0xA0900000
41 static volatile DanubeAsc_t *pAsc = (DanubeAsc_t *)DANUBE_ASC1;
44 u16 fdv; /* 0~511 fractional divider value*/
45 u16 reload; /* 13 bit reload value*/
49 /*9600 @1.25M rel 00.08*/
52 /*9600 @0.625M rel final00.01 & rtl_freeze*/
55 /* first index is DDR_SEL, second index is FPI_SEL */
57 static ifx_asc_baud_reg_t g_danube_asc_baud[4][2] =
60 {{503,3},{503,3}}, /* 1152000 @ 166.67M and half*/
61 {{503,3},{503,3}}, /* 1152000 @ 133.3M and half*/
62 {{503,3},{503,3}}, /* 1152000 @ 111.11M and half*/
63 {{503.3},{503,3}} /* 1152000 @ 83.33M and half*/
66 {{436,76},{419,36}}, /* 1152000 @ 166.67M and half*/
67 {{453,63},{453,31}}, /* 1152000 @ 133.3M and half*/
68 {{501,58},{510,29}}, /* 1152000 @ 111.11M and half*/
69 {{419.36},{453,19}} /* 1152000 @ 83.33M and half*/
72 /******************************************************************************
74 * asc_init - initialize a Danube ASC channel
76 * This routine initializes the number of data bits, parity
77 * and set the selected baud rate. Interrupts are disabled.
78 * Set the modem control signals if the option is selected.
83 int serial_init (void)
86 /* and we have to set CLC register*/
87 CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
88 SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
90 /* initialy we are in async mode */
91 pAsc->asc_con = ASCCON_M_8ASYNC;
93 /* select input port */
94 pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
96 /* TXFIFO's filling level */
97 SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
98 ASCTXFCON_TXFITLOFF, DANUBEASC_TXFIFO_FL);
100 SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
102 /* RXFIFO's filling level */
103 SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
104 ASCRXFCON_RXFITLOFF, DANUBEASC_RXFIFO_FL);
106 SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
111 /* enable error signals & Receiver enable */
112 SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
117 void serial_setbrg (void)
119 u32 uiReloadValue, fdv;
128 ddr_sel = (* DANUBE_CGU_SYS) & 0x3;
129 fpi_sel = ((* DANUBE_CGU_SYS) & 0x40)?1:0;
130 fdv= g_danube_asc_baud[ddr_sel][fpi_sel].fdv;
131 uiReloadValue=g_danube_asc_baud[ddr_sel][fpi_sel].reload;
133 /* Disable Baud Rate Generator; BG should only be written when R=0 */
134 CLEAR_BIT(pAsc->asc_con, ASCCON_R);
136 /* Enable Fractional Divider */
137 SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
139 /* Set fractional divider value */
140 pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
142 /* Set reload value in BG */
143 pAsc->asc_bg = uiReloadValue;
145 /* Enable Baud Rate Generator */
146 SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */
150 void serial_putc (const char c)
154 static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
159 /* check do we have a free space in the TX FIFO */
160 /* get current filling level */
163 txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
165 while ( txFl == DANUBEASC_TXFIFO_FULL );
167 pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
169 /* check for errors */
170 if ( pAsc->asc_state & ASCSTATE_TOE )
172 SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_CLRTOE);
177 void serial_puts (const char *s)
185 int asc_inb(int timeout)
189 while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) {
191 symbol_mask = ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
192 c = (char)(pAsc->asc_rbuf & symbol_mask);
196 int serial_getc (void)
199 while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 );
200 c = (char)(pAsc->asc_rbuf & 0xff);
203 static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
211 int serial_tstc (void)
215 #ifdef ASC_FIFO_PRESENT
216 if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
221 if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
229 else if ( pAsc->asc_con & ASCCON_FE )
231 SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
234 else if ( pAsc->asc_con & ASCCON_PE )
236 SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
239 else if ( pAsc->asc_con & ASCCON_OE )
241 SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
249 int serial_start(void)
254 int serial_stop(void)