2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2006 infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
21 // ### TO DO: general issues:
23 // - interrupt handling (direct/indirect)
24 // - pin/mux-handling (just overall concept due to project dependency)
25 // - multiple instances capability
26 // - slave functionality
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/signal.h>
31 #include <linux/sched.h>
32 #include <linux/timer.h>
33 #include <linux/interrupt.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
37 #include <linux/fcntl.h>
38 #include <linux/ptrace.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/spinlock.h>
44 #include <linux/slab.h>
46 #include <asm/system.h>
49 #include <asm/uaccess.h>
50 #include <asm/bitops.h>
52 #include <linux/types.h>
53 #include <linux/kernel.h>
54 #include <linux/version.h>
56 #include <asm/ifxmips/ifxmips.h>
57 #include <asm/ifxmips/ifxmips_irq.h>
58 #include <asm/ifxmips/ifx_ssc_defines.h>
59 #include <asm/ifxmips/ifx_ssc.h>
61 #ifdef SSC_FRAME_INT_ENABLE
62 #undef SSC_FRAME_INT_ENABLE
71 /* allow the user to set the major device number */
75 * This is the per-channel data structure containing pointers, flags
76 * and variables for the port. This driver supports a maximum of PORT_CNT.
77 * isp is allocated in ifx_ssc_init() based on the chip version.
79 static struct ifx_ssc_port *isp;
81 /* prototypes for fops */
82 static ssize_t ifx_ssc_read (struct file *, char *, size_t, loff_t *);
83 static ssize_t ifx_ssc_write (struct file *, const char *, size_t, loff_t *);
84 //static unsigned int ifx_ssc_poll(struct file *, struct poll_table_struct *);
85 int ifx_ssc_ioctl (struct inode *, struct file *, unsigned int,
87 int ifx_ssc_open (struct inode *, struct file *);
88 int ifx_ssc_close (struct inode *, struct file *);
90 /* other forward declarations */
91 static unsigned int ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info);
92 static void tx_int (struct ifx_ssc_port *);
94 extern unsigned int ifxmips_get_fpi_hz (void);
95 extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
97 static struct file_operations ifx_ssc_fops = {
100 .write = ifx_ssc_write,
101 .ioctl = ifx_ssc_ioctl,
102 .open = ifx_ssc_open,
103 .release = ifx_ssc_close,
106 static inline unsigned int
107 ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
111 rmc = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
114 printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
117 return ifxmips_get_fpi_hz () / rmc;
121 #ifdef IFX_SSC_INT_USE_BH
123 * This routine is used by the interrupt handler to schedule
124 * processing in the software interrupt portion of the driver
125 * (also known as the "bottom half"). This can be called any
126 * number of times for any channel without harm.
129 ifx_ssc_sched_event (struct ifx_ssc_port *info, int event)
131 info->event |= 1 << event; /* remember what kind of event and who */
132 queue_task (&info->tqueue, &tq_cyclades); /* it belongs to */
133 mark_bh (CYCLADES_BH); /* then trigger event */
137 do_softint (void *private_)
139 struct ifx_ssc_port *info = (struct ifx_ssc_port *) private_;
141 if (test_and_clear_bit (Cy_EVENT_HANGUP, &info->event))
143 wake_up_interruptible (&info->open_wait);
144 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CALLOUT_ACTIVE);
147 if (test_and_clear_bit (Cy_EVENT_OPEN_WAKEUP, &info->event))
148 wake_up_interruptible (&info->open_wait);
150 if (test_and_clear_bit (Cy_EVENT_DELTA_WAKEUP, &info->event))
151 wake_up_interruptible (&info->delta_msr_wait);
153 if (test_and_clear_bit (Cy_EVENT_WRITE_WAKEUP, &info->event))
154 wake_up_interruptible (&tty->write_wait);
156 if (test_and_clear_bit (Cy_EVENT_SHUTDOWN_WAKEUP, &info->event))
157 wake_up_interruptible (&info->shutdown_wait);
164 rx_int (struct ifx_ssc_port *info)
166 int fifo_fill_lev, bytes_in_buf, i;
167 unsigned long tmp_val;
168 unsigned long *tmp_ptr;
169 unsigned int rx_valid_cnt;
170 /* number of words waiting in the RX FIFO */
171 fifo_fill_lev = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
172 // Note: There are always 32 bits in a fifo-entry except for the last
173 // word of a contigous transfer block and except for not in rx-only
174 // mode and CON.ENBV set. But for this case it should be a convention
175 // in software which helps:
176 // In tx or rx/tx mode all transfers from the buffer to the FIFO are
177 // 32-bit wide, except for the last three bytes, which could be a
178 // combination of 16- and 8-bit access.
179 // => The whole block is received as 32-bit words as a contigous stream,
180 // even if there was a gap in tx which has the fifo run out of data!
181 // Just the last fifo entry *may* be partially filled (0, 1, 2 or 3 bytes)!
183 /* free space in the RX buffer */
184 bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
185 // transfer with 32 bits per entry
186 while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
187 tmp_ptr = (unsigned long *) info->rxbuf_ptr;
188 *tmp_ptr = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RB);
189 info->rxbuf_ptr += 4;
190 info->stats.rxBytes += 4;
195 // now do the rest as mentioned in STATE.RXBV
196 while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
197 rx_valid_cnt = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
198 if (rx_valid_cnt == 0)
201 if (rx_valid_cnt > bytes_in_buf)
202 rx_valid_cnt = bytes_in_buf;
204 tmp_val = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RB);
206 for (i = 0; i < rx_valid_cnt; i++)
208 *info->rxbuf_ptr = (tmp_val >> (8 * (rx_valid_cnt - i - 1))) & 0xff;
212 info->stats.rxBytes += rx_valid_cnt;
215 // check if transfer is complete
216 if (info->rxbuf_ptr >= info->rxbuf_end)
218 disable_irq(info->rxirq);
219 wake_up_interruptible (&info->rwait);
220 } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) == 0))
222 if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
223 WRITE_PERIPHERAL_REGISTER ((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
225 WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
230 tx_int (struct ifx_ssc_port *info)
233 int fifo_space, fill, i;
234 fifo_space = ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
235 - ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
240 fill = info->txbuf_end - info->txbuf_ptr;
242 if (fill > fifo_space * 4)
243 fill = fifo_space * 4;
245 for (i = 0; i < fill / 4; i++)
247 // at first 32 bit access
248 WRITE_PERIPHERAL_REGISTER (*(UINT32 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
249 info->txbuf_ptr += 4;
252 fifo_space -= fill / 4;
253 info->stats.txBytes += fill & ~0x3;
255 if ((fifo_space > 0) & (fill > 1))
257 // trailing 16 bit access
258 WRITE_PERIPHERAL_REGISTER_16 (*(UINT16 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
259 info->txbuf_ptr += 2;
260 info->stats.txBytes += 2;
265 if ((fifo_space > 0) & (fill > 0))
267 // trailing 8 bit access
268 WRITE_PERIPHERAL_REGISTER_8 (*(UINT8 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
270 info->stats.txBytes++;
273 // check if transmission complete
274 if (info->txbuf_ptr >= info->txbuf_end)
276 disable_irq(info->txirq);
284 ifx_ssc_rx_int (int irq, void *dev_id)
286 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
293 ifx_ssc_tx_int (int irq, void *dev_id)
295 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
302 ifx_ssc_err_int (int irq, void *dev_id)
304 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
306 unsigned int write_back = 0;
309 local_irq_save (flags);
310 state = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE);
312 if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
313 info->stats.rxUnErr++;
314 write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR;
317 if ((state & IFX_SSC_STATE_RX_OFL) != 0) {
318 info->stats.rxOvErr++;
319 write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR;
322 if ((state & IFX_SSC_STATE_TX_OFL) != 0) {
323 info->stats.txOvErr++;
324 write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR;
327 if ((state & IFX_SSC_STATE_TX_UFL) != 0) {
328 info->stats.txUnErr++;
329 write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR;
332 if ((state & IFX_SSC_STATE_MODE_ERR) != 0) {
333 info->stats.modeErr++;
334 write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR;
338 WRITE_PERIPHERAL_REGISTER (write_back, info->mapbase + IFX_SSC_WHBSTATE);
340 local_irq_restore (flags);
346 ifx_ssc_abort (struct ifx_ssc_port *info)
351 local_irq_save (flags);
353 disable_irq(info->rxirq);
354 disable_irq(info->txirq);
355 disable_irq(info->errirq);
357 local_irq_restore (flags);
359 // disable SSC (also aborts a receive request!)
360 // ### TO DO: Perhaps it's better to abort after the receiption of a
361 // complete word. The disable cuts the transmission immediatly and
362 // releases the chip selects. This could result in unpredictable
363 // behavior of connected external devices!
364 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
365 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
368 WRITE_PERIPHERAL_REGISTER (IFX_SSC_XFCON_FIFO_FLUSH, info->mapbase + IFX_SSC_TXFCON);
369 WRITE_PERIPHERAL_REGISTER (IFX_SSC_XFCON_FIFO_FLUSH, info->mapbase + IFX_SSC_RXFCON);
372 if (info->txbuf != NULL)
378 // wakeup read process
379 if (info->rxbuf != NULL)
380 wake_up_interruptible (&info->rwait);
382 // clear pending int's
383 mask_and_ack_ifxmips_irq(info->rxirq);
384 mask_and_ack_ifxmips_irq(info->txirq);
385 mask_and_ack_ifxmips_irq(info->errirq);
388 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ALL_ERROR, info->mapbase + IFX_SSC_WHBSTATE);
391 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
396 * This routine is called whenever a port is opened. It enforces
397 * exclusive opening of a port and enables interrupts, etc.
400 ifx_ssc_open (struct inode *inode, struct file *filp)
402 struct ifx_ssc_port *info;
406 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) {
410 line = MINOR (filp->f_dentry->d_inode->i_rdev);
411 filp->f_op = &ifx_ssc_fops;
414 /* don't open more minor devices than we can support */
415 if (line < 0 || line >= PORT_CNT)
421 if (info->port_is_open != 0)
423 info->port_is_open++;
425 disable_irq(info->rxirq);
426 disable_irq(info->txirq);
427 disable_irq(info->errirq);
429 /* Flush and enable TX/RX FIFO */
430 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, info->mapbase + IFX_SSC_TXFCON);
431 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, info->mapbase + IFX_SSC_RXFCON);
433 /* logically flush the software FIFOs */
437 /* clear all error bits */
438 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ALL_ERROR, info->mapbase + IFX_SSC_WHBSTATE);
440 // clear pending interrupts
441 mask_and_ack_ifxmips_irq(info->rxirq);
442 mask_and_ack_ifxmips_irq(info->txirq);
443 mask_and_ack_ifxmips_irq(info->errirq);
445 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
449 EXPORT_SYMBOL(ifx_ssc_open);
452 ifx_ssc_close (struct inode *inode, struct file *filp)
454 struct ifx_ssc_port *info;
457 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
460 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
462 if (idx < 0 || idx >= PORT_CNT)
469 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
473 info->port_is_open--;
477 EXPORT_SYMBOL(ifx_ssc_close);
480 ifx_ssc_read_helper_poll (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
485 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
487 local_irq_save (flags);
488 info->rxbuf_ptr = info->rxbuf;
489 info->rxbuf_end = info->rxbuf + len;
490 local_irq_restore (flags);
491 /* Vinetic driver always works in IFX_SSC_MODE_RXTX */
492 /* TXRX in poll mode */
493 while (info->rxbuf_ptr < info->rxbuf_end)
495 if (info->txbuf_ptr < info->txbuf_end)
501 ret_val = info->rxbuf_ptr - info->rxbuf;
507 ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
511 DECLARE_WAITQUEUE (wait, current);
513 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
516 local_irq_save (flags);
517 info->rxbuf_ptr = info->rxbuf;
518 info->rxbuf_end = info->rxbuf + len;
520 if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX)
522 if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf))
524 local_irq_restore (flags);
525 printk ("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__);
529 local_irq_restore(flags);
532 if (info->txbuf_ptr < info->txbuf_end)
533 enable_irq(info->txirq);
535 enable_irq(info->rxirq);
537 local_irq_restore(flags);
538 if (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
540 enable_irq(info->rxirq);
541 if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
542 WRITE_PERIPHERAL_REGISTER (len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
544 WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
547 __add_wait_queue (&info->rwait, &wait);
548 set_current_state (TASK_INTERRUPTIBLE);
551 local_irq_save (flags);
552 if (info->rxbuf_ptr >= info->rxbuf_end)
555 local_irq_restore (flags);
557 if (signal_pending (current))
559 ret_val = -ERESTARTSYS;
565 ret_val = info->rxbuf_ptr - info->rxbuf;
566 local_irq_restore (flags);
569 current->state = TASK_RUNNING;
570 __remove_wait_queue (&info->rwait, &wait);
576 ifx_ssc_write_helper (struct ifx_ssc_port *info, const char *buf,
577 size_t len, int from_kernel)
579 if (info->opts.modeRxTx == IFX_SSC_MODE_RX)
582 info->txbuf_ptr = info->txbuf;
583 info->txbuf_end = len + info->txbuf;
584 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
587 if (info->txbuf_ptr < info->txbuf_end)
589 enable_irq(info->txirq);
597 ifx_ssc_kread (int port, char *kbuf, size_t len)
599 struct ifx_ssc_port *info;
602 if (port < 0 || port >= PORT_CNT)
610 if (info->rxbuf != NULL)
612 printk ("SSC device busy\n");
617 if (info->rxbuf == NULL)
619 printk ("SSC device error\n");
623 ret_val = ifx_ssc_read_helper_poll (info, kbuf, len, 1);
626 disable_irq(info->rxirq);
630 EXPORT_SYMBOL(ifx_ssc_kread);
633 ifx_ssc_kwrite (int port, const char *kbuf, size_t len)
635 struct ifx_ssc_port *info;
638 if (port < 0 || port >= PORT_CNT)
646 // check if transmission in progress
647 if (info->txbuf != NULL)
650 info->txbuf = (char *) kbuf;
652 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 1);
659 EXPORT_SYMBOL(ifx_ssc_kwrite);
662 ifx_ssc_read (struct file *filp, char *ubuf, size_t len, loff_t * off)
666 struct ifx_ssc_port *info;
668 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
671 if (info->rxbuf != NULL)
674 info->rxbuf = kmalloc (len + 3, GFP_KERNEL);
675 if (info->rxbuf == NULL)
678 ret_val = ifx_ssc_read_helper (info, info->rxbuf, len, 0);
679 if (copy_to_user ((void *) ubuf, info->rxbuf, ret_val) != 0)
682 disable_irq(info->rxirq);
691 ifx_ssc_write (struct file *filp, const char *ubuf, size_t len, loff_t * off)
694 struct ifx_ssc_port *info;
700 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
703 if (info->txbuf != NULL)
706 info->txbuf = kmalloc (len + 3, GFP_KERNEL);
707 if (info->txbuf == NULL)
710 ret_val = copy_from_user (info->txbuf, ubuf, len);
712 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 0);
725 static struct ifx_ssc_frm_status *
726 ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
730 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFSTAT);
731 info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
732 info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
733 info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
734 info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
735 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
736 info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
737 info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
739 return &info->frm_status;
743 static struct ifx_ssc_frm_opts *
744 ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
748 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
749 info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
750 info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
751 info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
752 info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
753 info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
754 info->frm_opts.StopAfterPause = (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0;
756 return &info->frm_opts;
760 ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
765 if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX)
766 || (info->frm_opts.DataLength < 1)
767 || (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX)
768 || (info->frm_opts.PauseLength < 1)
769 || (info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET))
770 || (info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)))
773 // read interrupt bits (they're not changed here)
774 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON) &
775 (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
777 // set all values with respect to it's bit position (for data and pause
779 tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
780 tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
781 tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
782 tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
783 tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
784 tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
786 WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_SFCON);
792 ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
796 if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
799 if ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_BUSY)
800 || (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
803 tmp = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
804 WRITE_PERIPHERAL_REGISTER (tmp, info->mapbase + IFX_SSC_CON);
805 info->opts.modeRxTx = val;
811 ifx_ssc_sethwopts (struct ifx_ssc_port *info)
813 unsigned long flags, bits;
814 struct ifx_ssc_hwopts *opts = &info->opts;
816 if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH)
817 || (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH))
820 bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET;
821 bits |= IFX_SSC_CON_ENABLE_BYTE_VALID;
823 if (opts->rxOvErrDetect)
824 bits |= IFX_SSC_CON_RX_OFL_CHECK;
825 if (opts->rxUndErrDetect)
826 bits |= IFX_SSC_CON_RX_UFL_CHECK;
827 if (opts->txOvErrDetect)
828 bits |= IFX_SSC_CON_TX_OFL_CHECK;
829 if (opts->txUndErrDetect)
830 bits |= IFX_SSC_CON_TX_UFL_CHECK;
832 bits |= IFX_SSC_CON_LOOPBACK_MODE;
834 bits |= IFX_SSC_CON_ECHO_MODE_ON;
835 if (opts->headingControl)
836 bits |= IFX_SSC_CON_MSB_FIRST;
837 if (opts->clockPhase)
838 bits |= IFX_SSC_CON_LATCH_THEN_SHIFT;
839 if (opts->clockPolarity)
840 bits |= IFX_SSC_CON_CLOCK_FALL;
842 switch (opts->modeRxTx)
844 case IFX_SSC_MODE_TX:
845 bits |= IFX_SSC_CON_RX_OFF;
847 case IFX_SSC_MODE_RX:
848 bits |= IFX_SSC_CON_TX_OFF;
852 local_irq_save (flags);
854 WRITE_PERIPHERAL_REGISTER (bits, info->mapbase + IFX_SSC_CON);
855 WRITE_PERIPHERAL_REGISTER ((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
856 (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), info->mapbase + IFX_SSC_GPOCON);
858 WRITE_PERIPHERAL_REGISTER (info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, info->mapbase + IFX_SSC_WHBGPOSTAT);
861 if (opts->masterSelect)
862 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_MASTER_SELECT, info->mapbase + IFX_SSC_WHBSTATE);
864 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, info->mapbase + IFX_SSC_WHBSTATE);
866 // init serial framing
867 WRITE_PERIPHERAL_REGISTER (0, info->mapbase + IFX_SSC_SFCON);
868 /* set up the port pins */
869 //check for general requirements to switch (external) pad/pin characteristics
870 /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
871 /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
872 /* Set p0.15 to alternative 01, others to 00 (In/OUT) */
873 *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000);
874 *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
875 *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
876 *(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000;
878 /* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
879 *(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1);
880 *(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47));
881 *(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47);
882 *(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046;
885 /*TODO: CS4 CS5 CS6 */
886 *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000);
888 local_irq_restore (flags);
894 ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
896 unsigned int ifx_ssc_clock;
902 ifx_ssc_clock = ifx_ssc_get_kernel_clk(info);
903 if (ifx_ssc_clock == 0)
909 local_irq_save (flags);
911 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
912 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
914 br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
917 if (br > 0xffff || ((br == 0) &&
918 ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
919 local_irq_restore (flags);
920 printk ("%s: invalid baudrate %u\n", __func__, baud);
924 WRITE_PERIPHERAL_REGISTER (br, info->mapbase + IFX_SSC_BR);
927 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
929 local_irq_restore(flags);
936 ifx_ssc_hwinit (struct ifx_ssc_port *info)
941 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
942 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
944 if (ifx_ssc_sethwopts (info) < 0)
946 printk ("%s: setting the hardware options failed\n", __func__);
950 if (ifx_ssc_set_baud (info, info->baud) < 0)
952 printk ("%s: setting the baud rate failed\n", __func__);
956 local_irq_save (flags);
959 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE,
960 info->mapbase + IFX_SSC_TXFCON);
962 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE,
963 info->mapbase + IFX_SSC_RXFCON);
965 local_irq_restore (flags);
968 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
974 ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data)
976 struct ifx_ssc_port *info;
977 int line, ret_val = 0;
982 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
987 line = MINOR (filp->f_dentry->d_inode->i_rdev);
990 if (line < 0 || line >= PORT_CNT)
997 case IFX_SSC_STATS_READ:
998 /* data must be a pointer to a struct ifx_ssc_statistics */
1000 memcpy ((void *) data, (void *) &info->stats,
1001 sizeof (struct ifx_ssc_statistics));
1002 else if (copy_to_user ((void *) data,
1003 (void *) &info->stats,
1004 sizeof (struct ifx_ssc_statistics)))
1007 case IFX_SSC_STATS_RESET:
1008 /* just resets the statistics counters */
1009 memset ((void *) &info->stats, 0,
1010 sizeof (struct ifx_ssc_statistics));
1012 case IFX_SSC_BAUD_SET:
1013 /* if the buffers are not empty then the port is */
1014 /* busy and we shouldn't change things on-the-fly! */
1015 if (!info->txbuf || !info->rxbuf ||
1016 (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
1017 & IFX_SSC_STATE_BUSY)) {
1023 flags = *((unsigned long *) data);
1024 else if (copy_from_user ((void *) &flags,
1025 (void *) data, sizeof (flags))) {
1033 if (ifx_ssc_set_baud (info, flags) < 0) {
1039 case IFX_SSC_BAUD_GET:
1041 *((unsigned int *) data) = info->baud;
1042 else if (copy_to_user ((void *) data,
1043 (void *) &info->baud,
1044 sizeof (unsigned long)))
1047 case IFX_SSC_RXTX_MODE_SET:
1049 tmp = *((unsigned long *) data);
1050 else if (copy_from_user ((void *) &tmp,
1051 (void *) data, sizeof (tmp))) {
1055 ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
1057 case IFX_SSC_RXTX_MODE_GET:
1058 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) &
1059 (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
1061 *((unsigned int *) data) = tmp;
1062 else if (copy_to_user ((void *) data,
1063 (void *) &tmp, sizeof (tmp)))
1068 ifx_ssc_abort (info);
1071 case IFX_SSC_GPO_OUT_SET:
1073 tmp = *((unsigned long *) data);
1074 else if (copy_from_user ((void *) &tmp,
1075 (void *) data, sizeof (tmp))) {
1079 if (tmp > IFX_SSC_MAX_GPO_OUT)
1082 WRITE_PERIPHERAL_REGISTER
1083 (1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
1084 info->mapbase + IFX_SSC_WHBGPOSTAT);
1086 case IFX_SSC_GPO_OUT_CLR:
1088 tmp = *((unsigned long *) data);
1089 else if (copy_from_user ((void *) &tmp,
1090 (void *) data, sizeof (tmp))) {
1094 if (tmp > IFX_SSC_MAX_GPO_OUT)
1097 WRITE_PERIPHERAL_REGISTER
1098 (1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
1099 info->mapbase + IFX_SSC_WHBGPOSTAT);
1102 case IFX_SSC_GPO_OUT_GET:
1103 tmp = READ_PERIPHERAL_REGISTER
1104 (info->mapbase + IFX_SSC_GPOSTAT);
1106 *((unsigned int *) data) = tmp;
1107 else if (copy_to_user ((void *) data,
1108 (void *) &tmp, sizeof (tmp)))
1111 case IFX_SSC_FRM_STATUS_GET:
1112 ifx_ssc_frm_status_get (info);
1114 memcpy ((void *) data, (void *) &info->frm_status,
1115 sizeof (struct ifx_ssc_frm_status));
1116 else if (copy_to_user ((void *) data,
1117 (void *) &info->frm_status,
1118 sizeof (struct ifx_ssc_frm_status)))
1121 case IFX_SSC_FRM_CONTROL_GET:
1122 ifx_ssc_frm_control_get (info);
1124 memcpy ((void *) data, (void *) &info->frm_opts,
1125 sizeof (struct ifx_ssc_frm_opts));
1126 else if (copy_to_user ((void *) data,
1127 (void *) &info->frm_opts,
1128 sizeof (struct ifx_ssc_frm_opts)))
1131 case IFX_SSC_FRM_CONTROL_SET:
1133 memcpy ((void *) &info->frm_opts, (void *) data,
1134 sizeof (struct ifx_ssc_frm_opts));
1135 else if (copy_to_user ((void *) &info->frm_opts,
1137 sizeof (struct ifx_ssc_frm_opts))) {
1141 ret_val = ifx_ssc_frm_control_set (info);
1143 case IFX_SSC_HWOPTS_SET:
1144 /* data must be a pointer to a struct ifx_ssc_hwopts */
1145 /* if the buffers are not empty then the port is */
1146 /* busy and we shouldn't change things on-the-fly! */
1147 if (!info->txbuf || !info->rxbuf ||
1148 (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
1149 & IFX_SSC_STATE_BUSY)) {
1154 memcpy ((void *) &info->opts, (void *) data,
1155 sizeof (struct ifx_ssc_hwopts));
1156 else if (copy_from_user ((void *) &info->opts,
1158 sizeof (struct ifx_ssc_hwopts))) {
1162 if (ifx_ssc_hwinit (info) < 0) {
1166 case IFX_SSC_HWOPTS_GET:
1167 /* data must be a pointer to a struct ifx_ssc_hwopts */
1169 memcpy ((void *) data, (void *) &info->opts,
1170 sizeof (struct ifx_ssc_hwopts));
1171 else if (copy_to_user ((void *) data,
1172 (void *) &info->opts,
1173 sizeof (struct ifx_ssc_hwopts)))
1177 ret_val = -ENOIOCTLCMD;
1182 EXPORT_SYMBOL(ifx_ssc_ioctl);
1187 struct ifx_ssc_port *info;
1189 unsigned long flags;
1193 nbytes = PORT_CNT * sizeof(struct ifx_ssc_port);
1194 isp = (struct ifx_ssc_port*)kmalloc(nbytes, GFP_KERNEL);
1198 printk("%s: no memory for isp\n", __func__);
1201 memset(isp, 0, nbytes);
1204 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
1206 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1212 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
1214 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1223 /* set default values in ifx_ssc_port */
1224 for (i = 0; i < PORT_CNT; i++) {
1227 /* default values for the HwOpts */
1228 info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT;
1229 info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT;
1230 info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT;
1231 info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT;
1232 info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT;
1233 info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK;
1234 info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE;
1235 info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA;
1236 info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY;
1237 info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE;
1238 info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL;
1239 info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH;
1240 info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX;
1241 info->opts.gpoCs = IFX_SSC_DEF_GPO_CS;
1242 info->opts.gpoInv = IFX_SSC_DEF_GPO_INV;
1243 info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE;
1244 info->baud = IFX_SSC_DEF_BAUDRATE;
1247 /* values specific to SSC1 */
1249 info->mapbase = IFXMIPS_SSC1_BASE_ADDR;
1250 info->txirq = IFXMIPS_SSC_TIR;
1251 info->rxirq = IFXMIPS_SSC_RIR;
1252 info->errirq = IFXMIPS_SSC_EIR;
1255 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC);
1257 init_waitqueue_head (&info->rwait);
1259 local_irq_save (flags);
1261 // init serial framing register
1262 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_SFCON, info->mapbase + IFX_SSC_SFCON);
1264 ret_val = request_irq(info->txirq, ifx_ssc_tx_int, SA_INTERRUPT, "ifx_ssc_tx", info);
1267 printk("%s: unable to get irq %d\n", __func__, info->txirq);
1268 local_irq_restore(flags);
1272 ret_val = request_irq(info->rxirq, ifx_ssc_rx_int, SA_INTERRUPT, "ifx_ssc_rx", info);
1275 printk ("%s: unable to get irq %d\n", __func__, info->rxirq);
1276 local_irq_restore (flags);
1280 ret_val = request_irq(info->errirq, ifx_ssc_err_int, SA_INTERRUPT,"ifx_ssc_err", info);
1283 printk ("%s: unable to get irq %d\n", __func__, info->errirq);
1284 local_irq_restore (flags);
1287 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_IRNEN, info->mapbase + IFX_SSC_IRN_EN);
1289 enable_irq(info->txirq);
1290 enable_irq(info->rxirq);
1291 enable_irq(info->errirq);
1293 local_irq_restore (flags);
1296 for (i = 0; i < PORT_CNT; i++) {
1298 if (ifx_ssc_hwinit (info) < 0)
1300 printk ("%s: hardware init failed for port %d\n", __func__, i);
1309 free_irq(isp[0].txirq, &isp[0]);
1310 free_irq(isp[0].rxirq, &isp[0]);
1311 free_irq(isp[0].errirq, &isp[0]);
1318 ifx_ssc_cleanup_module (void)
1322 for (i = 0; i < PORT_CNT; i++) {
1323 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, isp[i].mapbase + IFX_SSC_WHBSTATE);
1324 free_irq(isp[i].txirq, &isp[i]);
1325 free_irq(isp[i].rxirq, &isp[i]);
1326 free_irq(isp[i].errirq, &isp[i]);
1331 module_init(ifx_ssc_init);
1332 module_exit(ifx_ssc_cleanup_module);
1336 ifx_ssc_cs_low (u32 pin)
1339 if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin)))
1340 printk ("clear CS %d fails\n", pin);
1345 EXPORT_SYMBOL(ifx_ssc_cs_low);
1348 ifx_ssc_cs_high (u32 pin)
1351 if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin)))
1352 printk ("set CS %d fails\n", pin);
1357 EXPORT_SYMBOL(ifx_ssc_cs_high);
1360 ssc_session (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1364 char *ssc_tx_buf = NULL;
1365 char *ssc_rx_buf = NULL;
1369 if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) {
1370 printk ("invalid parameters\n");
1372 goto ssc_session_exit;
1374 else if (tx_buf == NULL || tx_len == 0) {
1375 if (rx_buf != NULL && rx_len != 0) {
1376 mode = IFX_SSC_MODE_RX;
1379 printk ("invalid parameters\n");
1381 goto ssc_session_exit;
1384 else if (rx_buf == NULL || rx_len == 0) {
1385 if (tx_buf != NULL && tx_len != 0) {
1386 mode = IFX_SSC_MODE_TX;
1389 printk ("invalid parameters\n");
1391 goto ssc_session_exit;
1395 mode = IFX_SSC_MODE_RXTX;
1398 if (mode == IFX_SSC_MODE_RXTX) {
1399 eff_size = tx_len + rx_len;
1401 else if (mode == IFX_SSC_MODE_RX) {
1408 //4 bytes alignment, required by driver
1409 /* change by TaiCheng */
1413 (char *) kmalloc (sizeof (char) *
1414 ((eff_size + 3) & (~3)),
1417 (char *) kmalloc (sizeof (char) *
1418 ((eff_size + 3) & (~3)),
1423 (char *) kmalloc (sizeof (char) *
1424 ((eff_size + 3) & (~3)),
1427 (char *) kmalloc (sizeof (char) *
1428 ((eff_size + 3) & (~3)),
1431 if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) {
1432 printk ("no memory for size of %d\n", eff_size);
1434 goto ssc_session_exit;
1436 memset ((void *) ssc_tx_buf, 0, eff_size);
1437 memset ((void *) ssc_rx_buf, 0, eff_size);
1440 memcpy (ssc_tx_buf, tx_buf, tx_len);
1443 ret = ifx_ssc_kwrite (0, ssc_tx_buf, eff_size);
1446 ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite
1449 if (ret != eff_size) {
1450 printk ("ifx_ssc_write return %d\n", ret);
1451 goto ssc_session_exit;
1453 ret = ifx_ssc_kread (0, ssc_rx_buf, eff_size);
1454 if (ret != eff_size) {
1455 printk ("ifx_ssc_read return %d\n", ret);
1456 goto ssc_session_exit;
1459 memcpy (rx_buf, ssc_rx_buf + tx_len, rx_len);
1461 if (mode == IFX_SSC_MODE_TX) {
1469 if (ssc_tx_buf != NULL)
1471 if (ssc_rx_buf != NULL)
1475 printk ("ssc session fails\n");
1481 ifx_ssc_txrx (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1483 return ssc_session(tx_buf, tx_len, rx_buf, rx_len);
1485 EXPORT_SYMBOL(ifx_ssc_txrx);
1488 ifx_ssc_tx (char *tx_buf, u32 tx_len)
1490 return ssc_session(tx_buf, tx_len, NULL, 0);
1492 EXPORT_SYMBOL(ifx_ssc_tx);
1495 ifx_ssc_rx (char *rx_buf, u32 rx_len)
1497 return ssc_session(NULL, 0, rx_buf, rx_len);
1499 EXPORT_SYMBOL(ifx_ssc_rx);
1501 MODULE_LICENSE("GPL");
1502 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1503 MODULE_DESCRIPTION("ifxmips ssc driver");