target/linux/generic/patches-3.9/020-ssb_backport.patch

   1 --- a/drivers/net/wireless/b43/phy_n.c
   2 +++ b/drivers/net/wireless/b43/phy_n.c
   3 @@ -5165,7 +5165,8 @@ static void b43_nphy_pmu_spur_avoid(stru
   4  #endif
   5  #ifdef CONFIG_B43_SSB
   6         case B43_BUS_SSB:
   7 -               /* FIXME */
   8 +               ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
   9 +                                           avoid);
  10                 break;
  11  #endif
  12         }
  13 --- a/drivers/ssb/driver_chipcommon_pmu.c
  14 +++ b/drivers/ssb/driver_chipcommon_pmu.c
  15 @@ -675,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_
  16                 return 0;
  17         }
  18  }
  19 +
  20 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
  21 +{
  22 +       u32 pmu_ctl = 0;
  23 +
  24 +       switch (cc->dev->bus->chip_id) {
  25 +       case 0x4322:
  26 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
  27 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
  28 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
  29 +               if (spuravoid == 1)
  30 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
  31 +               else
  32 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
  33 +               pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
  34 +               break;
  35 +       case 43222:
  36 +               /* TODO: BCM43222 requires updating PLLs too */
  37 +               return;
  38 +       default:
  39 +               ssb_printk(KERN_ERR PFX
  40 +                          "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
  41 +                          cc->dev->bus->chip_id);
  42 +               return;
  43 +       }
  44 +
  45 +       chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
  46 +}
  47 +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
  48 --- a/drivers/ssb/pci.c
  49 +++ b/drivers/ssb/pci.c
  50 @@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_
  51         return (s8)gain;
  52  }
  53
  54 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
  55 +{
  56 +       SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
  57 +       SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
  58 +       SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
  59 +       SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
  60 +       SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
  61 +       SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
  62 +       SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
  63 +       SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
  64 +       SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
  65 +       SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
  66 +            SSB_SPROM2_MAXP_A_LO_SHIFT);
  67 +}
  68 +
  69  static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
  70  {
  71         int i;
  72 @@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss
  73              SSB_SPROM1_ITSSI_A_SHIFT);
  74         SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
  75         SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
  76 -       if (out->revision >= 2)
  77 -               SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
  78 +
  79         SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
  80         SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
  81
  82 @@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss
  83         out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
  84                                                     SSB_SPROM1_AGAIN_A,
  85                                                     SSB_SPROM1_AGAIN_A_SHIFT);
  86 +       if (out->revision >= 2)
  87 +               sprom_extract_r23(out, in);
  88  }
  89
  90  /* Revs 4 5 and 8 have partially shared layout */
  91 --- a/include/linux/ssb/ssb_driver_chipcommon.h
  92 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
  93 @@ -219,6 +219,7 @@
  94  #define SSB_CHIPCO_PMU_CTL                     0x0600 /* PMU control */
  95  #define  SSB_CHIPCO_PMU_CTL_ILP_DIV            0xFFFF0000 /* ILP div mask */
  96  #define  SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT      16
  97 +#define  SSB_CHIPCO_PMU_CTL_PLL_UPD            0x00000400
  98  #define  SSB_CHIPCO_PMU_CTL_NOILPONW           0x00000200 /* No ILP on wait */
  99  #define  SSB_CHIPCO_PMU_CTL_HTREQEN            0x00000100 /* HT req enable */
 100  #define  SSB_CHIPCO_PMU_CTL_ALPREQEN           0x00000080 /* ALP req enable */
 101 @@ -667,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
 102  void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
 103                              enum ssb_pmu_ldo_volt_id id, u32 voltage);
 104  void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
 105 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
 106
 107  #endif /* LINUX_SSB_CHIPCO_H_ */
 108 --- a/include/linux/ssb/ssb_regs.h
 109 +++ b/include/linux/ssb/ssb_regs.h
 110 @@ -289,11 +289,11 @@
 111  #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT  5
 112  #define  SSB_SPROM4_ETHPHY_ET0M                (1<<14) /* MDIO for enet0 */
 113  #define  SSB_SPROM4_ETHPHY_ET1M                (1<<15) /* MDIO for enet1 */
 114 -#define SSB_SPROM4_ANTAVAIL            0x005D  /* Antenna available bitfields */
 115 -#define  SSB_SPROM4_ANTAVAIL_A         0x00FF  /* A-PHY bitfield */
 116 -#define  SSB_SPROM4_ANTAVAIL_A_SHIFT   0
 117 -#define  SSB_SPROM4_ANTAVAIL_BG                0xFF00  /* B-PHY and G-PHY bitfield */
 118 -#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT  8
 119 +#define SSB_SPROM4_ANTAVAIL            0x005C  /* Antenna available bitfields */
 120 +#define  SSB_SPROM4_ANTAVAIL_BG                0x00FF  /* B-PHY and G-PHY bitfield */
 121 +#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT  0
 122 +#define  SSB_SPROM4_ANTAVAIL_A         0xFF00  /* A-PHY bitfield */
 123 +#define  SSB_SPROM4_ANTAVAIL_A_SHIFT   8
 124  #define SSB_SPROM4_AGAIN01             0x005E  /* Antenna Gain (in dBm Q5.2) */
 125  #define  SSB_SPROM4_AGAIN0             0x00FF  /* Antenna 0 */
 126  #define  SSB_SPROM4_AGAIN0_SHIFT       0