target/linux/generic/files/drivers/net/phy/rtl8366s.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/rtl8366s.h>
  19
  20 #include "rtl8366_smi.h"
  21
  22 #define RTL8366S_DRIVER_DESC    "Realtek RTL8366S ethernet switch driver"
  23 #define RTL8366S_DRIVER_VER     "0.2.2"
  24
  25 #define RTL8366S_PHY_NO_MAX     4
  26 #define RTL8366S_PHY_PAGE_MAX   7
  27 #define RTL8366S_PHY_ADDR_MAX   31
  28 #define RTL8366S_PHY_WAN        4
  29
  30 /* Switch Global Configuration register */
  31 #define RTL8366S_SGCR                           0x0000
  32 #define RTL8366S_SGCR_EN_BC_STORM_CTRL          BIT(0)
  33 #define RTL8366S_SGCR_MAX_LENGTH(_x)            (_x << 4)
  34 #define RTL8366S_SGCR_MAX_LENGTH_MASK           RTL8366S_SGCR_MAX_LENGTH(0x3)
  35 #define RTL8366S_SGCR_MAX_LENGTH_1522           RTL8366S_SGCR_MAX_LENGTH(0x0)
  36 #define RTL8366S_SGCR_MAX_LENGTH_1536           RTL8366S_SGCR_MAX_LENGTH(0x1)
  37 #define RTL8366S_SGCR_MAX_LENGTH_1552           RTL8366S_SGCR_MAX_LENGTH(0x2)
  38 #define RTL8366S_SGCR_MAX_LENGTH_16000          RTL8366S_SGCR_MAX_LENGTH(0x3)
  39 #define RTL8366S_SGCR_EN_VLAN                   BIT(13)
  40
  41 /* Port Enable Control register */
  42 #define RTL8366S_PECR                           0x0001
  43
  44 /* Switch Security Control registers */
  45 #define RTL8366S_SSCR0                          0x0002
  46 #define RTL8366S_SSCR1                          0x0003
  47 #define RTL8366S_SSCR2                          0x0004
  48 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA          BIT(0)
  49
  50 #define RTL8366S_RESET_CTRL_REG                 0x0100
  51 #define RTL8366S_CHIP_CTRL_RESET_HW             1
  52 #define RTL8366S_CHIP_CTRL_RESET_SW             (1 << 1)
  53
  54 #define RTL8366S_CHIP_VERSION_CTRL_REG          0x0104
  55 #define RTL8366S_CHIP_VERSION_MASK              0xf
  56 #define RTL8366S_CHIP_ID_REG                    0x0105
  57 #define RTL8366S_CHIP_ID_8366                   0x8366
  58
  59 /* PHY registers control */
  60 #define RTL8366S_PHY_ACCESS_CTRL_REG            0x8028
  61 #define RTL8366S_PHY_ACCESS_DATA_REG            0x8029
  62
  63 #define RTL8366S_PHY_CTRL_READ                  1
  64 #define RTL8366S_PHY_CTRL_WRITE                 0
  65
  66 #define RTL8366S_PHY_REG_MASK                   0x1f
  67 #define RTL8366S_PHY_PAGE_OFFSET                5
  68 #define RTL8366S_PHY_PAGE_MASK                  (0x7 << 5)
  69 #define RTL8366S_PHY_NO_OFFSET                  9
  70 #define RTL8366S_PHY_NO_MASK                    (0x1f << 9)
  71
  72 /* LED control registers */
  73 #define RTL8366S_LED_BLINKRATE_REG              0x0420
  74 #define RTL8366S_LED_BLINKRATE_BIT              0
  75 #define RTL8366S_LED_BLINKRATE_MASK             0x0007
  76
  77 #define RTL8366S_LED_CTRL_REG                   0x0421
  78 #define RTL8366S_LED_0_1_CTRL_REG               0x0422
  79 #define RTL8366S_LED_2_3_CTRL_REG               0x0423
  80
  81 #define RTL8366S_MIB_COUNT                      33
  82 #define RTL8366S_GLOBAL_MIB_COUNT               1
  83 #define RTL8366S_MIB_COUNTER_PORT_OFFSET        0x0040
  84 #define RTL8366S_MIB_COUNTER_BASE               0x1000
  85 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2       0x0008
  86 #define RTL8366S_MIB_COUNTER_BASE2              0x1180
  87 #define RTL8366S_MIB_CTRL_REG                   0x11F0
  88 #define RTL8366S_MIB_CTRL_USER_MASK             0x01FF
  89 #define RTL8366S_MIB_CTRL_BUSY_MASK             0x0001
  90 #define RTL8366S_MIB_CTRL_RESET_MASK            0x0002
  91
  92 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK     0x0004
  93 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT        0x0003
  94 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK       0x01FC
  95
  96
  97 #define RTL8366S_PORT_VLAN_CTRL_BASE            0x0058
  98 #define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \
  99                 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
 100 #define RTL8366S_PORT_VLAN_CTRL_MASK            0xf
 101 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)       (4 * ((_p) % 4))
 102
 103
 104 #define RTL8366S_VLAN_TABLE_READ_BASE           0x018B
 105 #define RTL8366S_VLAN_TABLE_WRITE_BASE          0x0185
 106
 107 #define RTL8366S_VLAN_TB_CTRL_REG               0x010F
 108
 109 #define RTL8366S_TABLE_ACCESS_CTRL_REG          0x0180
 110 #define RTL8366S_TABLE_VLAN_READ_CTRL           0x0E01
 111 #define RTL8366S_TABLE_VLAN_WRITE_CTRL          0x0F01
 112
 113 #define RTL8366S_VLAN_MC_BASE(_x)               (0x0016 + (_x) * 2)
 114
 115 #define RTL8366S_VLAN_MEMBERINGRESS_REG         0x0379
 116
 117 #define RTL8366S_PORT_LINK_STATUS_BASE          0x0060
 118 #define RTL8366S_PORT_STATUS_SPEED_MASK         0x0003
 119 #define RTL8366S_PORT_STATUS_DUPLEX_MASK        0x0004
 120 #define RTL8366S_PORT_STATUS_LINK_MASK          0x0010
 121 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK       0x0020
 122 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK       0x0040
 123 #define RTL8366S_PORT_STATUS_AN_MASK            0x0080
 124
 125
 126 #define RTL8366S_PORT_NUM_CPU           5
 127 #define RTL8366S_NUM_PORTS              6
 128 #define RTL8366S_NUM_VLANS              16
 129 #define RTL8366S_NUM_LEDGROUPS          4
 130 #define RTL8366S_NUM_VIDS               4096
 131 #define RTL8366S_PRIORITYMAX            7
 132 #define RTL8366S_FIDMAX                 7
 133
 134
 135 #define RTL8366S_PORT_1                 (1 << 0) /* In userspace port 0 */
 136 #define RTL8366S_PORT_2                 (1 << 1) /* In userspace port 1 */
 137 #define RTL8366S_PORT_3                 (1 << 2) /* In userspace port 2 */
 138 #define RTL8366S_PORT_4                 (1 << 3) /* In userspace port 3 */
 139
 140 #define RTL8366S_PORT_UNKNOWN           (1 << 4) /* No known connection */
 141 #define RTL8366S_PORT_CPU               (1 << 5) /* CPU port */
 142
 143 #define RTL8366S_PORT_ALL               (RTL8366S_PORT_1 |      \
 144                                          RTL8366S_PORT_2 |      \
 145                                          RTL8366S_PORT_3 |      \
 146                                          RTL8366S_PORT_4 |      \
 147                                          RTL8366S_PORT_UNKNOWN | \
 148                                          RTL8366S_PORT_CPU)
 149
 150 #define RTL8366S_PORT_ALL_BUT_CPU       (RTL8366S_PORT_1 |      \
 151                                          RTL8366S_PORT_2 |      \
 152                                          RTL8366S_PORT_3 |      \
 153                                          RTL8366S_PORT_4 |      \
 154                                          RTL8366S_PORT_UNKNOWN)
 155
 156 #define RTL8366S_PORT_ALL_EXTERNAL      (RTL8366S_PORT_1 |      \
 157                                          RTL8366S_PORT_2 |      \
 158                                          RTL8366S_PORT_3 |      \
 159                                          RTL8366S_PORT_4)
 160
 161 #define RTL8366S_PORT_ALL_INTERNAL      (RTL8366S_PORT_UNKNOWN | \
 162                                          RTL8366S_PORT_CPU)
 163
 164 #define RTL8366S_VLAN_VID_MASK          0xfff
 165 #define RTL8366S_VLAN_PRIORITY_SHIFT    12
 166 #define RTL8366S_VLAN_PRIORITY_MASK     0x7
 167 #define RTL8366S_VLAN_MEMBER_MASK       0x3f
 168 #define RTL8366S_VLAN_UNTAG_SHIFT       6
 169 #define RTL8366S_VLAN_UNTAG_MASK        0x3f
 170 #define RTL8366S_VLAN_FID_SHIFT         12
 171 #define RTL8366S_VLAN_FID_MASK          0x7
 172
 173 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
 174         { 0,  0, 4, "IfInOctets"                                },
 175         { 0,  4, 4, "EtherStatsOctets"                          },
 176         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 177         { 0, 10, 2, "EtherFragments"                            },
 178         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 179         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 180         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 181         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 182         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 183         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 184         { 0, 24, 2, "EtherOversizeStats"                        },
 185         { 0, 26, 2, "EtherStatsJabbers"                         },
 186         { 0, 28, 2, "IfInUcastPkts"                             },
 187         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 188         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 189         { 0, 34, 2, "EtherStatsDropEvents"                      },
 190         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 191         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 192         { 0, 40, 2, "Dot3InPauseFrames"                         },
 193         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 194         { 0, 44, 4, "IfOutOctets"                               },
 195         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 196         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 197         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 198         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 199         { 0, 56, 2, "EtherStatsCollisions"                      },
 200         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 201         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 202         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 203
 204         /*
 205          * The following counters are accessible at a different
 206          * base address.
 207          */
 208         { 1,  0, 2, "Dot1dTpPortInDiscards"                     },
 209         { 1,  2, 2, "IfOutUcastPkts"                            },
 210         { 1,  4, 2, "IfOutMulticastPkts"                        },
 211         { 1,  6, 2, "IfOutBroadcastPkts"                        },
 212 };
 213
 214 #define REG_WR(_smi, _reg, _val)                                        \
 215         do {                                                            \
 216                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 217                 if (err)                                                \
 218                         return err;                                     \
 219         } while (0)
 220
 221 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 222         do {                                                            \
 223                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 224                 if (err)                                                \
 225                         return err;                                     \
 226         } while (0)
 227
 228 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
 229 {
 230         int timeout = 10;
 231         u32 data;
 232
 233         rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
 234                               RTL8366S_CHIP_CTRL_RESET_HW);
 235         do {
 236                 msleep(1);
 237                 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
 238                         return -EIO;
 239
 240                 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
 241                         break;
 242         } while (--timeout);
 243
 244         if (!timeout) {
 245                 printk("Timeout waiting for the switch to reset\n");
 246                 return -EIO;
 247         }
 248
 249         return 0;
 250 }
 251
 252 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
 253 {
 254         struct rtl8366s_platform_data *pdata;
 255         int err;
 256
 257         pdata = smi->parent->platform_data;
 258         if (pdata->num_initvals && pdata->initvals) {
 259                 unsigned i;
 260
 261                 dev_info(smi->parent, "applying initvals\n");
 262                 for (i = 0; i < pdata->num_initvals; i++)
 263                         REG_WR(smi, pdata->initvals[i].reg,
 264                                pdata->initvals[i].val);
 265         }
 266
 267         /* set maximum packet length to 1536 bytes */
 268         REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
 269                 RTL8366S_SGCR_MAX_LENGTH_1536);
 270
 271         /* enable learning for all ports */
 272         REG_WR(smi, RTL8366S_SSCR0, 0);
 273
 274         /* enable auto ageing for all ports */
 275         REG_WR(smi, RTL8366S_SSCR1, 0);
 276
 277         /*
 278          * discard VLAN tagged packets if the port is not a member of
 279          * the VLAN with which the packets is associated.
 280          */
 281         REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
 282
 283         /* don't drop packets whose DA has not been learned */
 284         REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
 285
 286         return 0;
 287 }
 288
 289 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
 290                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 291 {
 292         u32 reg;
 293         int ret;
 294
 295         if (phy_no > RTL8366S_PHY_NO_MAX)
 296                 return -EINVAL;
 297
 298         if (page > RTL8366S_PHY_PAGE_MAX)
 299                 return -EINVAL;
 300
 301         if (addr > RTL8366S_PHY_ADDR_MAX)
 302                 return -EINVAL;
 303
 304         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 305                                     RTL8366S_PHY_CTRL_READ);
 306         if (ret)
 307                 return ret;
 308
 309         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 310               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 311               (addr & RTL8366S_PHY_REG_MASK);
 312
 313         ret = rtl8366_smi_write_reg(smi, reg, 0);
 314         if (ret)
 315                 return ret;
 316
 317         ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
 318         if (ret)
 319                 return ret;
 320
 321         return 0;
 322 }
 323
 324 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
 325                                   u32 phy_no, u32 page, u32 addr, u32 data)
 326 {
 327         u32 reg;
 328         int ret;
 329
 330         if (phy_no > RTL8366S_PHY_NO_MAX)
 331                 return -EINVAL;
 332
 333         if (page > RTL8366S_PHY_PAGE_MAX)
 334                 return -EINVAL;
 335
 336         if (addr > RTL8366S_PHY_ADDR_MAX)
 337                 return -EINVAL;
 338
 339         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 340                                     RTL8366S_PHY_CTRL_WRITE);
 341         if (ret)
 342                 return ret;
 343
 344         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 345               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 346               (addr & RTL8366S_PHY_REG_MASK);
 347
 348         ret = rtl8366_smi_write_reg(smi, reg, data);
 349         if (ret)
 350                 return ret;
 351
 352         return 0;
 353 }
 354
 355 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 356                                    int port, unsigned long long *val)
 357 {
 358         int i;
 359         int err;
 360         u32 addr, data;
 361         u64 mibvalue;
 362
 363         if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
 364                 return -EINVAL;
 365
 366         switch (rtl8366s_mib_counters[counter].base) {
 367         case 0:
 368                 addr = RTL8366S_MIB_COUNTER_BASE +
 369                        RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
 370                 break;
 371
 372         case 1:
 373                 addr = RTL8366S_MIB_COUNTER_BASE2 +
 374                         RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
 375                 break;
 376
 377         default:
 378                 return -EINVAL;
 379         }
 380
 381         addr += rtl8366s_mib_counters[counter].offset;
 382
 383         /*
 384          * Writing access counter address first
 385          * then ASIC will prepare 64bits counter wait for being retrived
 386          */
 387         data = 0; /* writing data will be discard by ASIC */
 388         err = rtl8366_smi_write_reg(smi, addr, data);
 389         if (err)
 390                 return err;
 391
 392         /* read MIB control register */
 393         err =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
 394         if (err)
 395                 return err;
 396
 397         if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
 398                 return -EBUSY;
 399
 400         if (data & RTL8366S_MIB_CTRL_RESET_MASK)
 401                 return -EIO;
 402
 403         mibvalue = 0;
 404         for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
 405                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 406                 if (err)
 407                         return err;
 408
 409                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 410         }
 411
 412         *val = mibvalue;
 413         return 0;
 414 }
 415
 416 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 417                                 struct rtl8366_vlan_4k *vlan4k)
 418 {
 419         u32 data[2];
 420         int err;
 421         int i;
 422
 423         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 424
 425         if (vid >= RTL8366S_NUM_VIDS)
 426                 return -EINVAL;
 427
 428         /* write VID */
 429         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
 430                                     vid & RTL8366S_VLAN_VID_MASK);
 431         if (err)
 432                 return err;
 433
 434         /* write table access control word */
 435         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 436                                     RTL8366S_TABLE_VLAN_READ_CTRL);
 437         if (err)
 438                 return err;
 439
 440         for (i = 0; i < 2; i++) {
 441                 err = rtl8366_smi_read_reg(smi,
 442                                            RTL8366S_VLAN_TABLE_READ_BASE + i,
 443                                            &data[i]);
 444                 if (err)
 445                         return err;
 446         }
 447
 448         vlan4k->vid = vid;
 449         vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 450                         RTL8366S_VLAN_UNTAG_MASK;
 451         vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 452         vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 453                         RTL8366S_VLAN_FID_MASK;
 454
 455         return 0;
 456 }
 457
 458 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
 459                                 const struct rtl8366_vlan_4k *vlan4k)
 460 {
 461         u32 data[2];
 462         int err;
 463         int i;
 464
 465         if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
 466             vlan4k->member > RTL8366S_VLAN_MEMBER_MASK ||
 467             vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK ||
 468             vlan4k->fid > RTL8366S_FIDMAX)
 469                 return -EINVAL;
 470
 471         data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
 472         data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
 473                   ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 474                         RTL8366S_VLAN_UNTAG_SHIFT) |
 475                   ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
 476                         RTL8366S_VLAN_FID_SHIFT);
 477
 478         for (i = 0; i < 2; i++) {
 479                 err = rtl8366_smi_write_reg(smi,
 480                                             RTL8366S_VLAN_TABLE_WRITE_BASE + i,
 481                                             data[i]);
 482                 if (err)
 483                         return err;
 484         }
 485
 486         /* write table access control word */
 487         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 488                                     RTL8366S_TABLE_VLAN_WRITE_CTRL);
 489
 490         return err;
 491 }
 492
 493 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 494                                 struct rtl8366_vlan_mc *vlanmc)
 495 {
 496         u32 data[2];
 497         int err;
 498         int i;
 499
 500         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 501
 502         if (index >= RTL8366S_NUM_VLANS)
 503                 return -EINVAL;
 504
 505         for (i = 0; i < 2; i++) {
 506                 err = rtl8366_smi_read_reg(smi,
 507                                            RTL8366S_VLAN_MC_BASE(index) + i,
 508                                            &data[i]);
 509                 if (err)
 510                         return err;
 511         }
 512
 513         vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
 514         vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
 515                            RTL8366S_VLAN_PRIORITY_MASK;
 516         vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 517                         RTL8366S_VLAN_UNTAG_MASK;
 518         vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 519         vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 520                       RTL8366S_VLAN_FID_MASK;
 521
 522         return 0;
 523 }
 524
 525 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 526                                 const struct rtl8366_vlan_mc *vlanmc)
 527 {
 528         u32 data[2];
 529         int err;
 530         int i;
 531
 532         if (index >= RTL8366S_NUM_VLANS ||
 533             vlanmc->vid >= RTL8366S_NUM_VIDS ||
 534             vlanmc->priority > RTL8366S_PRIORITYMAX ||
 535             vlanmc->member > RTL8366S_VLAN_MEMBER_MASK ||
 536             vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK ||
 537             vlanmc->fid > RTL8366S_FIDMAX)
 538                 return -EINVAL;
 539
 540         data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
 541                   ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
 542                         RTL8366S_VLAN_PRIORITY_SHIFT);
 543         data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
 544                   ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 545                         RTL8366S_VLAN_UNTAG_SHIFT) |
 546                   ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
 547                         RTL8366S_VLAN_FID_SHIFT);
 548
 549         for (i = 0; i < 2; i++) {
 550                 err = rtl8366_smi_write_reg(smi,
 551                                             RTL8366S_VLAN_MC_BASE(index) + i,
 552                                             data[i]);
 553                 if (err)
 554                         return err;
 555         }
 556
 557         return 0;
 558 }
 559
 560 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 561 {
 562         u32 data;
 563         int err;
 564
 565         if (port >= RTL8366S_NUM_PORTS)
 566                 return -EINVAL;
 567
 568         err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 569                                    &data);
 570         if (err)
 571                 return err;
 572
 573         *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
 574                RTL8366S_PORT_VLAN_CTRL_MASK;
 575
 576         return 0;
 577 }
 578
 579 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 580 {
 581         if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
 582                 return -EINVAL;
 583
 584         return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 585                                 RTL8366S_PORT_VLAN_CTRL_MASK <<
 586                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
 587                                 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
 588                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
 589 }
 590
 591 static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)
 592 {
 593         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
 594                                 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
 595 }
 596
 597 static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)
 598 {
 599         return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
 600                                 1, (enable) ? 1 : 0);
 601 }
 602
 603 static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
 604 {
 605         unsigned max = RTL8366S_NUM_VLANS;
 606
 607         if (smi->vlan4k_enabled)
 608                 max = RTL8366S_NUM_VIDS - 1;
 609
 610         if (vlan == 0 || vlan >= max)
 611                 return 0;
 612
 613         return 1;
 614 }
 615
 616 static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable)
 617 {
 618         return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port),
 619                                 (enable) ? 0 : (1 << port));
 620 }
 621
 622 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
 623                                   const struct switch_attr *attr,
 624                                   struct switch_val *val)
 625 {
 626         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 627
 628         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
 629 }
 630
 631 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
 632                                      const struct switch_attr *attr,
 633                                      struct switch_val *val)
 634 {
 635         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 636         u32 data;
 637
 638         rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
 639
 640         val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
 641
 642         return 0;
 643 }
 644
 645 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
 646                                     const struct switch_attr *attr,
 647                                     struct switch_val *val)
 648 {
 649         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 650
 651         if (val->value.i >= 6)
 652                 return -EINVAL;
 653
 654         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
 655                                 RTL8366S_LED_BLINKRATE_MASK,
 656                                 val->value.i);
 657 }
 658
 659 static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
 660                                            const struct switch_attr *attr,
 661                                            struct switch_val *val)
 662 {
 663         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 664         u32 data;
 665
 666         rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
 667         val->value.i = !data;
 668
 669         return 0;
 670 }
 671
 672
 673 static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
 674                                            const struct switch_attr *attr,
 675                                            struct switch_val *val)
 676 {
 677         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 678         u32 portmask = 0;
 679         int err = 0;
 680
 681         if (!val->value.i)
 682                 portmask = RTL8366S_PORT_ALL;
 683
 684         /* set learning for all ports */
 685         REG_WR(smi, RTL8366S_SSCR0, portmask);
 686
 687         /* set auto ageing for all ports */
 688         REG_WR(smi, RTL8366S_SSCR1, portmask);
 689
 690         return 0;
 691 }
 692
 693
 694 static const char *rtl8366s_speed_str(unsigned speed)
 695 {
 696         switch (speed) {
 697         case 0:
 698                 return "10baseT";
 699         case 1:
 700                 return "100baseT";
 701         case 2:
 702                 return "1000baseT";
 703         }
 704
 705         return "unknown";
 706 }
 707
 708 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
 709                                      const struct switch_attr *attr,
 710                                      struct switch_val *val)
 711 {
 712         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 713         u32 len = 0, data = 0;
 714
 715         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 716                 return -EINVAL;
 717
 718         memset(smi->buf, '\0', sizeof(smi->buf));
 719         rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
 720                              (val->port_vlan / 2), &data);
 721
 722         if (val->port_vlan % 2)
 723                 data = data >> 8;
 724
 725         if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
 726                 len = snprintf(smi->buf, sizeof(smi->buf),
 727                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 728                                 val->port_vlan,
 729                                 rtl8366s_speed_str(data &
 730                                           RTL8366S_PORT_STATUS_SPEED_MASK),
 731                                 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
 732                                         "full" : "half",
 733                                 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
 734                                         "tx-pause ": "",
 735                                 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
 736                                         "rx-pause " : "",
 737                                 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
 738                                         "nway ": "");
 739         } else {
 740                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 741                                 val->port_vlan);
 742         }
 743
 744         val->value.s = smi->buf;
 745         val->len = len;
 746
 747         return 0;
 748 }
 749
 750 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
 751                                     const struct switch_attr *attr,
 752                                     struct switch_val *val)
 753 {
 754         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 755         u32 data;
 756         u32 mask;
 757         u32 reg;
 758
 759         if (val->port_vlan >= RTL8366S_NUM_PORTS ||
 760             (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
 761                 return -EINVAL;
 762
 763         if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
 764                 reg = RTL8366S_LED_BLINKRATE_REG;
 765                 mask = 0xF << 4;
 766                 data = val->value.i << 4;
 767         } else {
 768                 reg = RTL8366S_LED_CTRL_REG;
 769                 mask = 0xF << (val->port_vlan * 4),
 770                 data = val->value.i << (val->port_vlan * 4);
 771         }
 772
 773         return rtl8366_smi_rmwr(smi, reg, mask, data);
 774 }
 775
 776 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
 777                                     const struct switch_attr *attr,
 778                                     struct switch_val *val)
 779 {
 780         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 781         u32 data = 0;
 782
 783         if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
 784                 return -EINVAL;
 785
 786         rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
 787         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 788
 789         return 0;
 790 }
 791
 792 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
 793                                        const struct switch_attr *attr,
 794                                        struct switch_val *val)
 795 {
 796         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 797
 798         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 799                 return -EINVAL;
 800
 801
 802         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
 803                                 0, (1 << (val->port_vlan + 3)));
 804 }
 805
 806 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
 807 {
 808         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 809         int err;
 810
 811         err = rtl8366s_reset_chip(smi);
 812         if (err)
 813                 return err;
 814
 815         err = rtl8366s_hw_init(smi);
 816         if (err)
 817                 return err;
 818
 819         err = rtl8366_reset_vlan(smi);
 820         if (err)
 821                 return err;
 822
 823         err = rtl8366_enable_vlan(smi, 1);
 824         if (err)
 825                 return err;
 826
 827         return rtl8366_enable_all_ports(smi, 1);
 828 }
 829
 830 static struct switch_attr rtl8366s_globals[] = {
 831         {
 832                 .type = SWITCH_TYPE_INT,
 833                 .name = "enable_learning",
 834                 .description = "Enable learning, enable aging",
 835                 .set = rtl8366s_sw_set_learning_enable,
 836                 .get = rtl8366s_sw_get_learning_enable,
 837                 .max = 1,
 838         }, {
 839                 .type = SWITCH_TYPE_INT,
 840                 .name = "enable_vlan",
 841                 .description = "Enable VLAN mode",
 842                 .set = rtl8366_sw_set_vlan_enable,
 843                 .get = rtl8366_sw_get_vlan_enable,
 844                 .max = 1,
 845                 .ofs = 1
 846         }, {
 847                 .type = SWITCH_TYPE_INT,
 848                 .name = "enable_vlan4k",
 849                 .description = "Enable VLAN 4K mode",
 850                 .set = rtl8366_sw_set_vlan_enable,
 851                 .get = rtl8366_sw_get_vlan_enable,
 852                 .max = 1,
 853                 .ofs = 2
 854         }, {
 855                 .type = SWITCH_TYPE_NOVAL,
 856                 .name = "reset_mibs",
 857                 .description = "Reset all MIB counters",
 858                 .set = rtl8366s_sw_reset_mibs,
 859         }, {
 860                 .type = SWITCH_TYPE_INT,
 861                 .name = "blinkrate",
 862                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
 863                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
 864                 .set = rtl8366s_sw_set_blinkrate,
 865                 .get = rtl8366s_sw_get_blinkrate,
 866                 .max = 5
 867         },
 868 };
 869
 870 static struct switch_attr rtl8366s_port[] = {
 871         {
 872                 .type = SWITCH_TYPE_STRING,
 873                 .name = "link",
 874                 .description = "Get port link information",
 875                 .max = 1,
 876                 .set = NULL,
 877                 .get = rtl8366s_sw_get_port_link,
 878         }, {
 879                 .type = SWITCH_TYPE_NOVAL,
 880                 .name = "reset_mib",
 881                 .description = "Reset single port MIB counters",
 882                 .set = rtl8366s_sw_reset_port_mibs,
 883         }, {
 884                 .type = SWITCH_TYPE_STRING,
 885                 .name = "mib",
 886                 .description = "Get MIB counters for port",
 887                 .max = 33,
 888                 .set = NULL,
 889                 .get = rtl8366_sw_get_port_mib,
 890         }, {
 891                 .type = SWITCH_TYPE_INT,
 892                 .name = "led",
 893                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
 894                 .max = 15,
 895                 .set = rtl8366s_sw_set_port_led,
 896                 .get = rtl8366s_sw_get_port_led,
 897         },
 898 };
 899
 900 static struct switch_attr rtl8366s_vlan[] = {
 901         {
 902                 .type = SWITCH_TYPE_STRING,
 903                 .name = "info",
 904                 .description = "Get vlan information",
 905                 .max = 1,
 906                 .set = NULL,
 907                 .get = rtl8366_sw_get_vlan_info,
 908         }, {
 909                 .type = SWITCH_TYPE_INT,
 910                 .name = "fid",
 911                 .description = "Get/Set vlan FID",
 912                 .max = RTL8366S_FIDMAX,
 913                 .set = rtl8366_sw_set_vlan_fid,
 914                 .get = rtl8366_sw_get_vlan_fid,
 915         },
 916 };
 917
 918 static const struct switch_dev_ops rtl8366_ops = {
 919         .attr_global = {
 920                 .attr = rtl8366s_globals,
 921                 .n_attr = ARRAY_SIZE(rtl8366s_globals),
 922         },
 923         .attr_port = {
 924                 .attr = rtl8366s_port,
 925                 .n_attr = ARRAY_SIZE(rtl8366s_port),
 926         },
 927         .attr_vlan = {
 928                 .attr = rtl8366s_vlan,
 929                 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
 930         },
 931
 932         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
 933         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
 934         .get_port_pvid = rtl8366_sw_get_port_pvid,
 935         .set_port_pvid = rtl8366_sw_set_port_pvid,
 936         .reset_switch = rtl8366s_sw_reset_switch,
 937 };
 938
 939 static int rtl8366s_switch_init(struct rtl8366_smi *smi)
 940 {
 941         struct switch_dev *dev = &smi->sw_dev;
 942         int err;
 943
 944         dev->name = "RTL8366S";
 945         dev->cpu_port = RTL8366S_PORT_NUM_CPU;
 946         dev->ports = RTL8366S_NUM_PORTS;
 947         dev->vlans = RTL8366S_NUM_VIDS;
 948         dev->ops = &rtl8366_ops;
 949         dev->devname = dev_name(smi->parent);
 950
 951         err = register_switch(dev, NULL);
 952         if (err)
 953                 dev_err(smi->parent, "switch registration failed\n");
 954
 955         return err;
 956 }
 957
 958 static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)
 959 {
 960         unregister_switch(&smi->sw_dev);
 961 }
 962
 963 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
 964 {
 965         struct rtl8366_smi *smi = bus->priv;
 966         u32 val = 0;
 967         int err;
 968
 969         err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
 970         if (err)
 971                 return 0xffff;
 972
 973         return val;
 974 }
 975
 976 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
 977 {
 978         struct rtl8366_smi *smi = bus->priv;
 979         u32 t;
 980         int err;
 981
 982         err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
 983         /* flush write */
 984         (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
 985
 986         return err;
 987 }
 988
 989 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
 990 {
 991         return (bus->read == rtl8366s_mii_read &&
 992                 bus->write == rtl8366s_mii_write);
 993 }
 994
 995 static int rtl8366s_setup(struct rtl8366_smi *smi)
 996 {
 997         int ret;
 998
 999         ret = rtl8366s_reset_chip(smi);
1000         if (ret)
1001                 return ret;
1002
1003         ret = rtl8366s_hw_init(smi);
1004         return ret;
1005 }
1006
1007 static int rtl8366s_detect(struct rtl8366_smi *smi)
1008 {
1009         u32 chip_id = 0;
1010         u32 chip_ver = 0;
1011         int ret;
1012
1013         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1014         if (ret) {
1015                 dev_err(smi->parent, "unable to read chip id\n");
1016                 return ret;
1017         }
1018
1019         switch (chip_id) {
1020         case RTL8366S_CHIP_ID_8366:
1021                 break;
1022         default:
1023                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1024                 return -ENODEV;
1025         }
1026
1027         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1028                                    &chip_ver);
1029         if (ret) {
1030                 dev_err(smi->parent, "unable to read chip version\n");
1031                 return ret;
1032         }
1033
1034         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1035                  chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1036
1037         return 0;
1038 }
1039
1040 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1041         .detect         = rtl8366s_detect,
1042         .setup          = rtl8366s_setup,
1043
1044         .mii_read       = rtl8366s_mii_read,
1045         .mii_write      = rtl8366s_mii_write,
1046
1047         .get_vlan_mc    = rtl8366s_get_vlan_mc,
1048         .set_vlan_mc    = rtl8366s_set_vlan_mc,
1049         .get_vlan_4k    = rtl8366s_get_vlan_4k,
1050         .set_vlan_4k    = rtl8366s_set_vlan_4k,
1051         .get_mc_index   = rtl8366s_get_mc_index,
1052         .set_mc_index   = rtl8366s_set_mc_index,
1053         .get_mib_counter = rtl8366_get_mib_counter,
1054         .is_vlan_valid  = rtl8366s_is_vlan_valid,
1055         .enable_vlan    = rtl8366s_enable_vlan,
1056         .enable_vlan4k  = rtl8366s_enable_vlan4k,
1057         .enable_port    = rtl8366s_enable_port,
1058 };
1059
1060 static int __devinit rtl8366s_probe(struct platform_device *pdev)
1061 {
1062         static int rtl8366_smi_version_printed;
1063         struct rtl8366s_platform_data *pdata;
1064         struct rtl8366_smi *smi;
1065         int err;
1066
1067         if (!rtl8366_smi_version_printed++)
1068                 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1069                        " version " RTL8366S_DRIVER_VER"\n");
1070
1071         pdata = pdev->dev.platform_data;
1072         if (!pdata) {
1073                 dev_err(&pdev->dev, "no platform data specified\n");
1074                 err = -EINVAL;
1075                 goto err_out;
1076         }
1077
1078         smi = rtl8366_smi_alloc(&pdev->dev);
1079         if (!smi) {
1080                 err = -ENOMEM;
1081                 goto err_out;
1082         }
1083
1084         smi->gpio_sda = pdata->gpio_sda;
1085         smi->gpio_sck = pdata->gpio_sck;
1086         smi->ops = &rtl8366s_smi_ops;
1087         smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1088         smi->num_ports = RTL8366S_NUM_PORTS;
1089         smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1090         smi->mib_counters = rtl8366s_mib_counters;
1091         smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1092
1093         err = rtl8366_smi_init(smi);
1094         if (err)
1095                 goto err_free_smi;
1096
1097         platform_set_drvdata(pdev, smi);
1098
1099         err = rtl8366s_switch_init(smi);
1100         if (err)
1101                 goto err_clear_drvdata;
1102
1103         return 0;
1104
1105  err_clear_drvdata:
1106         platform_set_drvdata(pdev, NULL);
1107         rtl8366_smi_cleanup(smi);
1108  err_free_smi:
1109         kfree(smi);
1110  err_out:
1111         return err;
1112 }
1113
1114 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1115 {
1116         if (!rtl8366s_mii_bus_match(phydev->bus))
1117                 return -EINVAL;
1118
1119         return 0;
1120 }
1121
1122 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1123 {
1124         /* phy 4 might be connected to a second mac, allow aneg config */
1125         if (phydev->addr == RTL8366S_PHY_WAN)
1126                 return genphy_config_aneg(phydev);
1127
1128         return 0;
1129 }
1130
1131 static struct phy_driver rtl8366s_phy_driver = {
1132         .phy_id         = 0x001cc960,
1133         .name           = "Realtek RTL8366S",
1134         .phy_id_mask    = 0x1ffffff0,
1135         .features       = PHY_GBIT_FEATURES,
1136         .config_aneg    = rtl8366s_phy_config_aneg,
1137         .config_init    = rtl8366s_phy_config_init,
1138         .read_status    = genphy_read_status,
1139         .driver         = {
1140                 .owner = THIS_MODULE,
1141         },
1142 };
1143
1144 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1145 {
1146         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1147
1148         if (smi) {
1149                 rtl8366s_switch_cleanup(smi);
1150                 platform_set_drvdata(pdev, NULL);
1151                 rtl8366_smi_cleanup(smi);
1152                 kfree(smi);
1153         }
1154
1155         return 0;
1156 }
1157
1158 static struct platform_driver rtl8366s_driver = {
1159         .driver = {
1160                 .name           = RTL8366S_DRIVER_NAME,
1161                 .owner          = THIS_MODULE,
1162         },
1163         .probe          = rtl8366s_probe,
1164         .remove         = __devexit_p(rtl8366s_remove),
1165 };
1166
1167 static int __init rtl8366s_module_init(void)
1168 {
1169         int ret;
1170         ret = platform_driver_register(&rtl8366s_driver);
1171         if (ret)
1172                 return ret;
1173
1174         ret = phy_driver_register(&rtl8366s_phy_driver);
1175         if (ret)
1176                 goto err_platform_unregister;
1177
1178         return 0;
1179
1180  err_platform_unregister:
1181         platform_driver_unregister(&rtl8366s_driver);
1182         return ret;
1183 }
1184 module_init(rtl8366s_module_init);
1185
1186 static void __exit rtl8366s_module_exit(void)
1187 {
1188         phy_driver_unregister(&rtl8366s_phy_driver);
1189         platform_driver_unregister(&rtl8366s_driver);
1190 }
1191 module_exit(rtl8366s_module_exit);
1192
1193 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1194 MODULE_VERSION(RTL8366S_DRIVER_VER);
1195 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1196 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1197 MODULE_LICENSE("GPL v2");
1198 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);