target/linux/generic/files/drivers/net/phy/rtl8366s.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/switch.h>
  19 #include <linux/rtl8366s.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #define RTL8366S_DRIVER_DESC    "Realtek RTL8366S ethernet switch driver"
  24 #define RTL8366S_DRIVER_VER     "0.2.2"
  25
  26 #define RTL8366S_PHY_NO_MAX     4
  27 #define RTL8366S_PHY_PAGE_MAX   7
  28 #define RTL8366S_PHY_ADDR_MAX   31
  29
  30 #define RTL8366S_CHIP_GLOBAL_CTRL_REG           0x0000
  31 #define RTL8366S_CHIP_CTRL_VLAN                 (1 << 13)
  32
  33 /* Switch Global Configuration register */
  34 #define RTL8366S_SGCR                           0x0000
  35 #define RTL8366S_SGCR_EN_BC_STORM_CTRL          BIT(0)
  36 #define RTL8366S_SGCR_MAX_LENGTH(_x)            (_x << 4)
  37 #define RTL8366S_SGCR_MAX_LENGTH_MASK           RTL8366S_SGCR_MAX_LENGTH(0x3)
  38 #define RTL8366S_SGCR_MAX_LENGTH_1522           RTL8366S_SGCR_MAX_LENGTH(0x0)
  39 #define RTL8366S_SGCR_MAX_LENGTH_1536           RTL8366S_SGCR_MAX_LENGTH(0x1)
  40 #define RTL8366S_SGCR_MAX_LENGTH_1552           RTL8366S_SGCR_MAX_LENGTH(0x2)
  41 #define RTL8366S_SGCR_MAX_LENGTH_16000          RTL8366S_SGCR_MAX_LENGTH(0x3)
  42
  43 /* Port Enable Control register */
  44 #define RTL8366S_PECR                           0x0001
  45
  46 /* Switch Security Control registers */
  47 #define RTL8366S_SSCR0                          0x0002
  48 #define RTL8366S_SSCR1                          0x0003
  49 #define RTL8366S_SSCR2                          0x0004
  50 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA          BIT(0)
  51
  52 #define RTL8366S_RESET_CTRL_REG                 0x0100
  53 #define RTL8366S_CHIP_CTRL_RESET_HW             1
  54 #define RTL8366S_CHIP_CTRL_RESET_SW             (1 << 1)
  55
  56 #define RTL8366S_CHIP_VERSION_CTRL_REG          0x0104
  57 #define RTL8366S_CHIP_VERSION_MASK              0xf
  58 #define RTL8366S_CHIP_ID_REG                    0x0105
  59 #define RTL8366S_CHIP_ID_8366                   0x8366
  60
  61 /* PHY registers control */
  62 #define RTL8366S_PHY_ACCESS_CTRL_REG            0x8028
  63 #define RTL8366S_PHY_ACCESS_DATA_REG            0x8029
  64
  65 #define RTL8366S_PHY_CTRL_READ                  1
  66 #define RTL8366S_PHY_CTRL_WRITE                 0
  67
  68 #define RTL8366S_PHY_REG_MASK                   0x1f
  69 #define RTL8366S_PHY_PAGE_OFFSET                5
  70 #define RTL8366S_PHY_PAGE_MASK                  (0x7 << 5)
  71 #define RTL8366S_PHY_NO_OFFSET                  9
  72 #define RTL8366S_PHY_NO_MASK                    (0x1f << 9)
  73
  74 /* LED control registers */
  75 #define RTL8366S_LED_BLINKRATE_REG              0x0420
  76 #define RTL8366S_LED_BLINKRATE_BIT              0
  77 #define RTL8366S_LED_BLINKRATE_MASK             0x0007
  78
  79 #define RTL8366S_LED_CTRL_REG                   0x0421
  80 #define RTL8366S_LED_0_1_CTRL_REG               0x0422
  81 #define RTL8366S_LED_2_3_CTRL_REG               0x0423
  82
  83 #define RTL8366S_MIB_COUNT                      33
  84 #define RTL8366S_GLOBAL_MIB_COUNT               1
  85 #define RTL8366S_MIB_COUNTER_PORT_OFFSET        0x0040
  86 #define RTL8366S_MIB_COUNTER_BASE               0x1000
  87 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2       0x0008
  88 #define RTL8366S_MIB_COUNTER_BASE2              0x1180
  89 #define RTL8366S_MIB_CTRL_REG                   0x11F0
  90 #define RTL8366S_MIB_CTRL_USER_MASK             0x01FF
  91 #define RTL8366S_MIB_CTRL_BUSY_MASK             0x0001
  92 #define RTL8366S_MIB_CTRL_RESET_MASK            0x0002
  93
  94 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK     0x0004
  95 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT        0x0003
  96 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK       0x01FC
  97
  98
  99 #define RTL8366S_PORT_VLAN_CTRL_BASE            0x0058
 100 #define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \
 101                 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
 102 #define RTL8366S_PORT_VLAN_CTRL_MASK            0xf
 103 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)       (4 * ((_p) % 4))
 104
 105
 106 #define RTL8366S_VLAN_TABLE_READ_BASE           0x018B
 107 #define RTL8366S_VLAN_TABLE_WRITE_BASE          0x0185
 108
 109 #define RTL8366S_VLAN_TB_CTRL_REG               0x010F
 110
 111 #define RTL8366S_TABLE_ACCESS_CTRL_REG          0x0180
 112 #define RTL8366S_TABLE_VLAN_READ_CTRL           0x0E01
 113 #define RTL8366S_TABLE_VLAN_WRITE_CTRL          0x0F01
 114
 115 #define RTL8366S_VLAN_MEMCONF_BASE              0x0016
 116
 117
 118 #define RTL8366S_PORT_LINK_STATUS_BASE          0x0060
 119 #define RTL8366S_PORT_STATUS_SPEED_MASK         0x0003
 120 #define RTL8366S_PORT_STATUS_DUPLEX_MASK        0x0004
 121 #define RTL8366S_PORT_STATUS_LINK_MASK          0x0010
 122 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK       0x0020
 123 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK       0x0040
 124 #define RTL8366S_PORT_STATUS_AN_MASK            0x0080
 125
 126
 127 #define RTL8366S_PORT_NUM_CPU           5
 128 #define RTL8366S_NUM_PORTS              6
 129 #define RTL8366S_NUM_VLANS              16
 130 #define RTL8366S_NUM_LEDGROUPS          4
 131 #define RTL8366S_NUM_VIDS               4096
 132 #define RTL8366S_PRIORITYMAX            7
 133 #define RTL8366S_FIDMAX                 7
 134
 135
 136 #define RTL8366S_PORT_1                 (1 << 0) /* In userspace port 0 */
 137 #define RTL8366S_PORT_2                 (1 << 1) /* In userspace port 1 */
 138 #define RTL8366S_PORT_3                 (1 << 2) /* In userspace port 2 */
 139 #define RTL8366S_PORT_4                 (1 << 3) /* In userspace port 3 */
 140
 141 #define RTL8366S_PORT_UNKNOWN           (1 << 4) /* No known connection */
 142 #define RTL8366S_PORT_CPU               (1 << 5) /* CPU port */
 143
 144 #define RTL8366S_PORT_ALL               (RTL8366S_PORT_1 |      \
 145                                          RTL8366S_PORT_2 |      \
 146                                          RTL8366S_PORT_3 |      \
 147                                          RTL8366S_PORT_4 |      \
 148                                          RTL8366S_PORT_UNKNOWN | \
 149                                          RTL8366S_PORT_CPU)
 150
 151 #define RTL8366S_PORT_ALL_BUT_CPU       (RTL8366S_PORT_1 |      \
 152                                          RTL8366S_PORT_2 |      \
 153                                          RTL8366S_PORT_3 |      \
 154                                          RTL8366S_PORT_4 |      \
 155                                          RTL8366S_PORT_UNKNOWN)
 156
 157 #define RTL8366S_PORT_ALL_EXTERNAL      (RTL8366S_PORT_1 |      \
 158                                          RTL8366S_PORT_2 |      \
 159                                          RTL8366S_PORT_3 |      \
 160                                          RTL8366S_PORT_4)
 161
 162 #define RTL8366S_PORT_ALL_INTERNAL      (RTL8366S_PORT_UNKNOWN | \
 163                                          RTL8366S_PORT_CPU)
 164
 165 struct rtl8366s {
 166         struct device           *parent;
 167         struct rtl8366_smi      smi;
 168         struct switch_dev       dev;
 169 };
 170
 171 struct rtl8366s_vlan_mc {
 172         u16     reserved2:1;
 173         u16     priority:3;
 174         u16     vid:12;
 175
 176         u16     reserved1:1;
 177         u16     fid:3;
 178         u16     untag:6;
 179         u16     member:6;
 180 };
 181
 182 struct rtl8366s_vlan_4k {
 183         u16     reserved1:4;
 184         u16     vid:12;
 185
 186         u16     reserved2:1;
 187         u16     fid:3;
 188         u16     untag:6;
 189         u16     member:6;
 190 };
 191
 192 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
 193         { 0,  0, 4, "IfInOctets"                                },
 194         { 0,  4, 4, "EtherStatsOctets"                          },
 195         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 196         { 0, 10, 2, "EtherFragments"                            },
 197         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 198         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 199         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 200         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 201         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 202         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 203         { 0, 24, 2, "EtherOversizeStats"                        },
 204         { 0, 26, 2, "EtherStatsJabbers"                         },
 205         { 0, 28, 2, "IfInUcastPkts"                             },
 206         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 207         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 208         { 0, 34, 2, "EtherStatsDropEvents"                      },
 209         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 210         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 211         { 0, 40, 2, "Dot3InPauseFrames"                         },
 212         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 213         { 0, 44, 4, "IfOutOctets"                               },
 214         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 215         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 216         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 217         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 218         { 0, 56, 2, "EtherStatsCollisions"                      },
 219         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 220         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 221         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 222
 223         /*
 224          * The following counters are accessible at a different
 225          * base address.
 226          */
 227         { 1,  0, 2, "Dot1dTpPortInDiscards"                     },
 228         { 1,  2, 2, "IfOutUcastPkts"                            },
 229         { 1,  4, 2, "IfOutMulticastPkts"                        },
 230         { 1,  6, 2, "IfOutBroadcastPkts"                        },
 231 };
 232
 233 #define REG_WR(_smi, _reg, _val)                                        \
 234         do {                                                            \
 235                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 236                 if (err)                                                \
 237                         return err;                                     \
 238         } while (0)
 239
 240 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 241         do {                                                            \
 242                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 243                 if (err)                                                \
 244                         return err;                                     \
 245         } while (0)
 246
 247 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
 248 {
 249         return container_of(smi, struct rtl8366s, smi);
 250 }
 251
 252 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
 253 {
 254         return container_of(sw, struct rtl8366s, dev);
 255 }
 256
 257 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
 258 {
 259         struct rtl8366s *rtl = sw_to_rtl8366s(sw);
 260         return &rtl->smi;
 261 }
 262
 263 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
 264 {
 265         int timeout = 10;
 266         u32 data;
 267
 268         rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
 269                               RTL8366S_CHIP_CTRL_RESET_HW);
 270         do {
 271                 msleep(1);
 272                 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
 273                         return -EIO;
 274
 275                 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
 276                         break;
 277         } while (--timeout);
 278
 279         if (!timeout) {
 280                 printk("Timeout waiting for the switch to reset\n");
 281                 return -EIO;
 282         }
 283
 284         return 0;
 285 }
 286
 287 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
 288 {
 289         int err;
 290
 291         /* set maximum packet length to 1536 bytes */
 292         REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
 293                 RTL8366S_SGCR_MAX_LENGTH_1536);
 294
 295         /* enable all ports */
 296         REG_WR(smi, RTL8366S_PECR, 0);
 297
 298         /* disable learning for all ports */
 299         REG_WR(smi, RTL8366S_SSCR0, RTL8366S_PORT_ALL);
 300
 301         /* disable auto ageing for all ports */
 302         REG_WR(smi, RTL8366S_SSCR1, RTL8366S_PORT_ALL);
 303
 304         /* don't drop packets whose DA has not been learned */
 305         REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
 306
 307         return 0;
 308 }
 309
 310 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
 311                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 312 {
 313         u32 reg;
 314         int ret;
 315
 316         if (phy_no > RTL8366S_PHY_NO_MAX)
 317                 return -EINVAL;
 318
 319         if (page > RTL8366S_PHY_PAGE_MAX)
 320                 return -EINVAL;
 321
 322         if (addr > RTL8366S_PHY_ADDR_MAX)
 323                 return -EINVAL;
 324
 325         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 326                                     RTL8366S_PHY_CTRL_READ);
 327         if (ret)
 328                 return ret;
 329
 330         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 331               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 332               (addr & RTL8366S_PHY_REG_MASK);
 333
 334         ret = rtl8366_smi_write_reg(smi, reg, 0);
 335         if (ret)
 336                 return ret;
 337
 338         ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
 339         if (ret)
 340                 return ret;
 341
 342         return 0;
 343 }
 344
 345 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
 346                                   u32 phy_no, u32 page, u32 addr, u32 data)
 347 {
 348         u32 reg;
 349         int ret;
 350
 351         if (phy_no > RTL8366S_PHY_NO_MAX)
 352                 return -EINVAL;
 353
 354         if (page > RTL8366S_PHY_PAGE_MAX)
 355                 return -EINVAL;
 356
 357         if (addr > RTL8366S_PHY_ADDR_MAX)
 358                 return -EINVAL;
 359
 360         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 361                                     RTL8366S_PHY_CTRL_WRITE);
 362         if (ret)
 363                 return ret;
 364
 365         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 366               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 367               (addr & RTL8366S_PHY_REG_MASK);
 368
 369         ret = rtl8366_smi_write_reg(smi, reg, data);
 370         if (ret)
 371                 return ret;
 372
 373         return 0;
 374 }
 375
 376 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 377                                    int port, unsigned long long *val)
 378 {
 379         int i;
 380         int err;
 381         u32 addr, data;
 382         u64 mibvalue;
 383
 384         if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
 385                 return -EINVAL;
 386
 387         switch (rtl8366s_mib_counters[counter].base) {
 388         case 0:
 389                 addr = RTL8366S_MIB_COUNTER_BASE +
 390                        RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
 391                 break;
 392
 393         case 1:
 394                 addr = RTL8366S_MIB_COUNTER_BASE2 +
 395                         RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
 396                 break;
 397
 398         default:
 399                 return -EINVAL;
 400         }
 401
 402         addr += rtl8366s_mib_counters[counter].offset;
 403
 404         /*
 405          * Writing access counter address first
 406          * then ASIC will prepare 64bits counter wait for being retrived
 407          */
 408         data = 0; /* writing data will be discard by ASIC */
 409         err = rtl8366_smi_write_reg(smi, addr, data);
 410         if (err)
 411                 return err;
 412
 413         /* read MIB control register */
 414         err =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
 415         if (err)
 416                 return err;
 417
 418         if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
 419                 return -EBUSY;
 420
 421         if (data & RTL8366S_MIB_CTRL_RESET_MASK)
 422                 return -EIO;
 423
 424         mibvalue = 0;
 425         for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
 426                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 427                 if (err)
 428                         return err;
 429
 430                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 431         }
 432
 433         *val = mibvalue;
 434         return 0;
 435 }
 436
 437 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 438                                 struct rtl8366_vlan_4k *vlan4k)
 439 {
 440         struct rtl8366s_vlan_4k vlan4k_priv;
 441         int err;
 442         u32 data;
 443         u16 *tableaddr;
 444
 445         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 446         vlan4k_priv.vid = vid;
 447
 448         if (vid >= RTL8366S_NUM_VIDS)
 449                 return -EINVAL;
 450
 451         tableaddr = (u16 *)&vlan4k_priv;
 452
 453         /* write VID */
 454         data = *tableaddr;
 455         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
 456         if (err)
 457                 return err;
 458
 459         /* write table access control word */
 460         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 461                                     RTL8366S_TABLE_VLAN_READ_CTRL);
 462         if (err)
 463                 return err;
 464
 465         err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
 466         if (err)
 467                 return err;
 468
 469         *tableaddr = data;
 470         tableaddr++;
 471
 472         err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
 473                                    &data);
 474         if (err)
 475                 return err;
 476
 477         *tableaddr = data;
 478
 479         vlan4k->vid = vid;
 480         vlan4k->untag = vlan4k_priv.untag;
 481         vlan4k->member = vlan4k_priv.member;
 482         vlan4k->fid = vlan4k_priv.fid;
 483
 484         return 0;
 485 }
 486
 487 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
 488                                 const struct rtl8366_vlan_4k *vlan4k)
 489 {
 490         struct rtl8366s_vlan_4k vlan4k_priv;
 491         int err;
 492         u32 data;
 493         u16 *tableaddr;
 494
 495         if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
 496             vlan4k->member > RTL8366S_PORT_ALL ||
 497             vlan4k->untag > RTL8366S_PORT_ALL ||
 498             vlan4k->fid > RTL8366S_FIDMAX)
 499                 return -EINVAL;
 500
 501         vlan4k_priv.vid = vlan4k->vid;
 502         vlan4k_priv.untag = vlan4k->untag;
 503         vlan4k_priv.member = vlan4k->member;
 504         vlan4k_priv.fid = vlan4k->fid;
 505
 506         tableaddr = (u16 *)&vlan4k_priv;
 507
 508         data = *tableaddr;
 509
 510         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
 511         if (err)
 512                 return err;
 513
 514         tableaddr++;
 515
 516         data = *tableaddr;
 517
 518         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
 519                                     data);
 520         if (err)
 521                 return err;
 522
 523         /* write table access control word */
 524         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 525                                     RTL8366S_TABLE_VLAN_WRITE_CTRL);
 526
 527         return err;
 528 }
 529
 530 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 531                                 struct rtl8366_vlan_mc *vlanmc)
 532 {
 533         struct rtl8366s_vlan_mc vlanmc_priv;
 534         int err;
 535         u32 addr;
 536         u32 data;
 537         u16 *tableaddr;
 538
 539         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 540
 541         if (index >= RTL8366S_NUM_VLANS)
 542                 return -EINVAL;
 543
 544         tableaddr = (u16 *)&vlanmc_priv;
 545
 546         addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
 547         err = rtl8366_smi_read_reg(smi, addr, &data);
 548         if (err)
 549                 return err;
 550
 551         *tableaddr = data;
 552         tableaddr++;
 553
 554         addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
 555         err = rtl8366_smi_read_reg(smi, addr, &data);
 556         if (err)
 557                 return err;
 558
 559         *tableaddr = data;
 560
 561         vlanmc->vid = vlanmc_priv.vid;
 562         vlanmc->priority = vlanmc_priv.priority;
 563         vlanmc->untag = vlanmc_priv.untag;
 564         vlanmc->member = vlanmc_priv.member;
 565         vlanmc->fid = vlanmc_priv.fid;
 566
 567         return 0;
 568 }
 569
 570 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 571                                 const struct rtl8366_vlan_mc *vlanmc)
 572 {
 573         struct rtl8366s_vlan_mc vlanmc_priv;
 574         int err;
 575         u32 addr;
 576         u32 data;
 577         u16 *tableaddr;
 578
 579         if (index >= RTL8366S_NUM_VLANS ||
 580             vlanmc->vid >= RTL8366S_NUM_VIDS ||
 581             vlanmc->priority > RTL8366S_PRIORITYMAX ||
 582             vlanmc->member > RTL8366S_PORT_ALL ||
 583             vlanmc->untag > RTL8366S_PORT_ALL ||
 584             vlanmc->fid > RTL8366S_FIDMAX)
 585                 return -EINVAL;
 586
 587         vlanmc_priv.vid = vlanmc->vid;
 588         vlanmc_priv.priority = vlanmc->priority;
 589         vlanmc_priv.untag = vlanmc->untag;
 590         vlanmc_priv.member = vlanmc->member;
 591         vlanmc_priv.fid = vlanmc->fid;
 592
 593         addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
 594
 595         tableaddr = (u16 *)&vlanmc_priv;
 596         data = *tableaddr;
 597
 598         err = rtl8366_smi_write_reg(smi, addr, data);
 599         if (err)
 600                 return err;
 601
 602         addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
 603
 604         tableaddr++;
 605         data = *tableaddr;
 606
 607         err = rtl8366_smi_write_reg(smi, addr, data);
 608         if (err)
 609                 return err;
 610
 611         return 0;
 612 }
 613
 614 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 615 {
 616         u32 data;
 617         int err;
 618
 619         if (port >= RTL8366S_NUM_PORTS)
 620                 return -EINVAL;
 621
 622         err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 623                                    &data);
 624         if (err)
 625                 return err;
 626
 627         *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
 628                RTL8366S_PORT_VLAN_CTRL_MASK;
 629
 630         return 0;
 631 }
 632
 633 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 634 {
 635         if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
 636                 return -EINVAL;
 637
 638         return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 639                                 RTL8366S_PORT_VLAN_CTRL_MASK <<
 640                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
 641                                 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
 642                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
 643 }
 644
 645 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
 646 {
 647         return rtl8366_smi_rmwr(smi, RTL8366S_CHIP_GLOBAL_CTRL_REG,
 648                                 RTL8366S_CHIP_CTRL_VLAN,
 649                                 (enable) ? RTL8366S_CHIP_CTRL_VLAN : 0);
 650 }
 651
 652 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
 653 {
 654         return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
 655                                 1, (enable) ? 1 : 0);
 656 }
 657
 658 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
 659                                   const struct switch_attr *attr,
 660                                   struct switch_val *val)
 661 {
 662         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 663         int err = 0;
 664
 665         if (val->value.i == 1)
 666                 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
 667
 668         return err;
 669 }
 670
 671 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
 672                                        const struct switch_attr *attr,
 673                                        struct switch_val *val)
 674 {
 675         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 676         u32 data;
 677
 678         if (attr->ofs == 1) {
 679                 rtl8366_smi_read_reg(smi, RTL8366S_CHIP_GLOBAL_CTRL_REG, &data);
 680
 681                 if (data & RTL8366S_CHIP_CTRL_VLAN)
 682                         val->value.i = 1;
 683                 else
 684                         val->value.i = 0;
 685         } else if (attr->ofs == 2) {
 686                 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
 687
 688                 if (data & 0x0001)
 689                         val->value.i = 1;
 690                 else
 691                         val->value.i = 0;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
 698                                      const struct switch_attr *attr,
 699                                      struct switch_val *val)
 700 {
 701         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 702         u32 data;
 703
 704         rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
 705
 706         val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
 707
 708         return 0;
 709 }
 710
 711 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
 712                                     const struct switch_attr *attr,
 713                                     struct switch_val *val)
 714 {
 715         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 716
 717         if (val->value.i >= 6)
 718                 return -EINVAL;
 719
 720         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
 721                                 RTL8366S_LED_BLINKRATE_MASK,
 722                                 val->value.i);
 723 }
 724
 725 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
 726                                        const struct switch_attr *attr,
 727                                        struct switch_val *val)
 728 {
 729         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 730
 731         if (attr->ofs == 1)
 732                 return rtl8366s_vlan_set_vlan(smi, val->value.i);
 733         else
 734                 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
 735 }
 736
 737 static const char *rtl8366s_speed_str(unsigned speed)
 738 {
 739         switch (speed) {
 740         case 0:
 741                 return "10baseT";
 742         case 1:
 743                 return "100baseT";
 744         case 2:
 745                 return "1000baseT";
 746         }
 747
 748         return "unknown";
 749 }
 750
 751 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
 752                                      const struct switch_attr *attr,
 753                                      struct switch_val *val)
 754 {
 755         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 756         u32 len = 0, data = 0;
 757
 758         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 759                 return -EINVAL;
 760
 761         memset(smi->buf, '\0', sizeof(smi->buf));
 762         rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
 763                              (val->port_vlan / 2), &data);
 764
 765         if (val->port_vlan % 2)
 766                 data = data >> 8;
 767
 768         if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
 769                 len = snprintf(smi->buf, sizeof(smi->buf),
 770                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 771                                 val->port_vlan,
 772                                 rtl8366s_speed_str(data &
 773                                           RTL8366S_PORT_STATUS_SPEED_MASK),
 774                                 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
 775                                         "full" : "half",
 776                                 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
 777                                         "tx-pause ": "",
 778                                 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
 779                                         "rx-pause " : "",
 780                                 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
 781                                         "nway ": "");
 782         } else {
 783                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 784                                 val->port_vlan);
 785         }
 786
 787         val->value.s = smi->buf;
 788         val->len = len;
 789
 790         return 0;
 791 }
 792
 793 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
 794                                      const struct switch_attr *attr,
 795                                      struct switch_val *val)
 796 {
 797         int i;
 798         u32 len = 0;
 799         struct rtl8366_vlan_4k vlan4k;
 800         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 801         char *buf = smi->buf;
 802         int err;
 803
 804         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
 805                 return -EINVAL;
 806
 807         memset(buf, '\0', sizeof(smi->buf));
 808
 809         err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 810         if (err)
 811                 return err;
 812
 813         len += snprintf(buf + len, sizeof(smi->buf) - len,
 814                         "VLAN %d: Ports: '", vlan4k.vid);
 815
 816         for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
 817                 if (!(vlan4k.member & (1 << i)))
 818                         continue;
 819
 820                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
 821                                 (vlan4k.untag & (1 << i)) ? "" : "t");
 822         }
 823
 824         len += snprintf(buf + len, sizeof(smi->buf) - len,
 825                         "', members=%04x, untag=%04x, fid=%u",
 826                         vlan4k.member, vlan4k.untag, vlan4k.fid);
 827
 828         val->value.s = buf;
 829         val->len = len;
 830
 831         return 0;
 832 }
 833
 834 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
 835                                     const struct switch_attr *attr,
 836                                     struct switch_val *val)
 837 {
 838         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 839         u32 data;
 840         u32 mask;
 841         u32 reg;
 842
 843         if (val->port_vlan >= RTL8366S_NUM_PORTS ||
 844             (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
 845                 return -EINVAL;
 846
 847         if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
 848                 reg = RTL8366S_LED_BLINKRATE_REG;
 849                 mask = 0xF << 4;
 850                 data = val->value.i << 4;
 851         } else {
 852                 reg = RTL8366S_LED_CTRL_REG;
 853                 mask = 0xF << (val->port_vlan * 4),
 854                 data = val->value.i << (val->port_vlan * 4);
 855         }
 856
 857         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
 858 }
 859
 860 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
 861                                     const struct switch_attr *attr,
 862                                     struct switch_val *val)
 863 {
 864         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 865         u32 data = 0;
 866
 867         if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
 868                 return -EINVAL;
 869
 870         rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
 871         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 872
 873         return 0;
 874 }
 875
 876 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
 877                                        const struct switch_attr *attr,
 878                                        struct switch_val *val)
 879 {
 880         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 881
 882         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 883                 return -EINVAL;
 884
 885
 886         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
 887                                 0, (1 << (val->port_vlan + 3)));
 888 }
 889
 890 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
 891                                     const struct switch_attr *attr,
 892                                     struct switch_val *val)
 893 {
 894         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 895         int i, len = 0;
 896         unsigned long long counter = 0;
 897         char *buf = smi->buf;
 898
 899         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 900                 return -EINVAL;
 901
 902         len += snprintf(buf + len, sizeof(smi->buf) - len,
 903                         "Port %d MIB counters\n",
 904                         val->port_vlan);
 905
 906         for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
 907                 len += snprintf(buf + len, sizeof(smi->buf) - len,
 908                                 "%-36s: ", rtl8366s_mib_counters[i].name);
 909                 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
 910                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 911                                         "%llu\n", counter);
 912                 else
 913                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 914                                         "%s\n", "error");
 915         }
 916
 917         val->value.s = buf;
 918         val->len = len;
 919         return 0;
 920 }
 921
 922 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
 923                                       struct switch_val *val)
 924 {
 925         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 926         struct switch_port *port;
 927         struct rtl8366_vlan_4k vlan4k;
 928         int i;
 929
 930         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
 931                 return -EINVAL;
 932
 933         rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 934
 935         port = &val->value.ports[0];
 936         val->len = 0;
 937         for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
 938                 if (!(vlan4k.member & BIT(i)))
 939                         continue;
 940
 941                 port->id = i;
 942                 port->flags = (vlan4k.untag & BIT(i)) ?
 943                                         0 : BIT(SWITCH_PORT_FLAG_TAGGED);
 944                 val->len++;
 945                 port++;
 946         }
 947         return 0;
 948 }
 949
 950 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
 951                                       struct switch_val *val)
 952 {
 953         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 954         struct switch_port *port;
 955         u32 member = 0;
 956         u32 untag = 0;
 957         int i;
 958
 959         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
 960                 return -EINVAL;
 961
 962         port = &val->value.ports[0];
 963         for (i = 0; i < val->len; i++, port++) {
 964                 member |= BIT(port->id);
 965
 966                 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
 967                         untag |= BIT(port->id);
 968         }
 969
 970         return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
 971 }
 972
 973 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
 974 {
 975         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 976         return rtl8366_get_pvid(smi, port, val);
 977 }
 978
 979 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
 980 {
 981         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 982         return rtl8366_set_pvid(smi, port, val);
 983 }
 984
 985 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
 986 {
 987         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 988         int err;
 989
 990         err = rtl8366s_reset_chip(smi);
 991         if (err)
 992                 return err;
 993
 994         err = rtl8366s_hw_init(smi);
 995         if (err)
 996                 return err;
 997
 998         return rtl8366_reset_vlan(smi);
 999 }
1000
1001 static struct switch_attr rtl8366s_globals[] = {
1002         {
1003                 .type = SWITCH_TYPE_INT,
1004                 .name = "enable_vlan",
1005                 .description = "Enable VLAN mode",
1006                 .set = rtl8366s_sw_set_vlan_enable,
1007                 .get = rtl8366s_sw_get_vlan_enable,
1008                 .max = 1,
1009                 .ofs = 1
1010         }, {
1011                 .type = SWITCH_TYPE_INT,
1012                 .name = "enable_vlan4k",
1013                 .description = "Enable VLAN 4K mode",
1014                 .set = rtl8366s_sw_set_vlan_enable,
1015                 .get = rtl8366s_sw_get_vlan_enable,
1016                 .max = 1,
1017                 .ofs = 2
1018         }, {
1019                 .type = SWITCH_TYPE_INT,
1020                 .name = "reset_mibs",
1021                 .description = "Reset all MIB counters",
1022                 .set = rtl8366s_sw_reset_mibs,
1023                 .get = NULL,
1024                 .max = 1
1025         }, {
1026                 .type = SWITCH_TYPE_INT,
1027                 .name = "blinkrate",
1028                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1029                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1030                 .set = rtl8366s_sw_set_blinkrate,
1031                 .get = rtl8366s_sw_get_blinkrate,
1032                 .max = 5
1033         },
1034 };
1035
1036 static struct switch_attr rtl8366s_port[] = {
1037         {
1038                 .type = SWITCH_TYPE_STRING,
1039                 .name = "link",
1040                 .description = "Get port link information",
1041                 .max = 1,
1042                 .set = NULL,
1043                 .get = rtl8366s_sw_get_port_link,
1044         }, {
1045                 .type = SWITCH_TYPE_INT,
1046                 .name = "reset_mib",
1047                 .description = "Reset single port MIB counters",
1048                 .max = 1,
1049                 .set = rtl8366s_sw_reset_port_mibs,
1050                 .get = NULL,
1051         }, {
1052                 .type = SWITCH_TYPE_STRING,
1053                 .name = "mib",
1054                 .description = "Get MIB counters for port",
1055                 .max = 33,
1056                 .set = NULL,
1057                 .get = rtl8366s_sw_get_port_mib,
1058         }, {
1059                 .type = SWITCH_TYPE_INT,
1060                 .name = "led",
1061                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1062                 .max = 15,
1063                 .set = rtl8366s_sw_set_port_led,
1064                 .get = rtl8366s_sw_get_port_led,
1065         },
1066 };
1067
1068 static struct switch_attr rtl8366s_vlan[] = {
1069         {
1070                 .type = SWITCH_TYPE_STRING,
1071                 .name = "info",
1072                 .description = "Get vlan information",
1073                 .max = 1,
1074                 .set = NULL,
1075                 .get = rtl8366s_sw_get_vlan_info,
1076         },
1077 };
1078
1079 /* template */
1080 static struct switch_dev rtl8366_switch_dev = {
1081         .name = "RTL8366S",
1082         .cpu_port = RTL8366S_PORT_NUM_CPU,
1083         .ports = RTL8366S_NUM_PORTS,
1084         .vlans = RTL8366S_NUM_VLANS,
1085         .attr_global = {
1086                 .attr = rtl8366s_globals,
1087                 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1088         },
1089         .attr_port = {
1090                 .attr = rtl8366s_port,
1091                 .n_attr = ARRAY_SIZE(rtl8366s_port),
1092         },
1093         .attr_vlan = {
1094                 .attr = rtl8366s_vlan,
1095                 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1096         },
1097
1098         .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1099         .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1100         .get_port_pvid = rtl8366s_sw_get_port_pvid,
1101         .set_port_pvid = rtl8366s_sw_set_port_pvid,
1102         .reset_switch = rtl8366s_sw_reset_switch,
1103 };
1104
1105 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1106 {
1107         struct switch_dev *dev = &rtl->dev;
1108         int err;
1109
1110         memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1111         dev->priv = rtl;
1112         dev->devname = dev_name(rtl->parent);
1113
1114         err = register_switch(dev, NULL);
1115         if (err)
1116                 dev_err(rtl->parent, "switch registration failed\n");
1117
1118         return err;
1119 }
1120
1121 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1122 {
1123         unregister_switch(&rtl->dev);
1124 }
1125
1126 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1127 {
1128         struct rtl8366_smi *smi = bus->priv;
1129         u32 val = 0;
1130         int err;
1131
1132         err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1133         if (err)
1134                 return 0xffff;
1135
1136         return val;
1137 }
1138
1139 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1140 {
1141         struct rtl8366_smi *smi = bus->priv;
1142         u32 t;
1143         int err;
1144
1145         err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1146         /* flush write */
1147         (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1148
1149         return err;
1150 }
1151
1152 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1153 {
1154         return (bus->read == rtl8366s_mii_read &&
1155                 bus->write == rtl8366s_mii_write);
1156 }
1157
1158 static int rtl8366s_setup(struct rtl8366s *rtl)
1159 {
1160         struct rtl8366_smi *smi = &rtl->smi;
1161         int ret;
1162
1163         ret = rtl8366s_reset_chip(smi);
1164         if (ret)
1165                 return ret;
1166
1167         ret = rtl8366s_hw_init(smi);
1168         return ret;
1169 }
1170
1171 static int rtl8366s_detect(struct rtl8366_smi *smi)
1172 {
1173         u32 chip_id = 0;
1174         u32 chip_ver = 0;
1175         int ret;
1176
1177         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1178         if (ret) {
1179                 dev_err(smi->parent, "unable to read chip id\n");
1180                 return ret;
1181         }
1182
1183         switch (chip_id) {
1184         case RTL8366S_CHIP_ID_8366:
1185                 break;
1186         default:
1187                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1188                 return -ENODEV;
1189         }
1190
1191         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1192                                    &chip_ver);
1193         if (ret) {
1194                 dev_err(smi->parent, "unable to read chip version\n");
1195                 return ret;
1196         }
1197
1198         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1199                  chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1200
1201         return 0;
1202 }
1203
1204 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1205         .detect         = rtl8366s_detect,
1206         .mii_read       = rtl8366s_mii_read,
1207         .mii_write      = rtl8366s_mii_write,
1208
1209         .get_vlan_mc    = rtl8366s_get_vlan_mc,
1210         .set_vlan_mc    = rtl8366s_set_vlan_mc,
1211         .get_vlan_4k    = rtl8366s_get_vlan_4k,
1212         .set_vlan_4k    = rtl8366s_set_vlan_4k,
1213         .get_mc_index   = rtl8366s_get_mc_index,
1214         .set_mc_index   = rtl8366s_set_mc_index,
1215         .get_mib_counter = rtl8366_get_mib_counter,
1216 };
1217
1218 static int __init rtl8366s_probe(struct platform_device *pdev)
1219 {
1220         static int rtl8366_smi_version_printed;
1221         struct rtl8366s_platform_data *pdata;
1222         struct rtl8366s *rtl;
1223         struct rtl8366_smi *smi;
1224         int err;
1225
1226         if (!rtl8366_smi_version_printed++)
1227                 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1228                        " version " RTL8366S_DRIVER_VER"\n");
1229
1230         pdata = pdev->dev.platform_data;
1231         if (!pdata) {
1232                 dev_err(&pdev->dev, "no platform data specified\n");
1233                 err = -EINVAL;
1234                 goto err_out;
1235         }
1236
1237         rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1238         if (!rtl) {
1239                 dev_err(&pdev->dev, "no memory for private data\n");
1240                 err = -ENOMEM;
1241                 goto err_out;
1242         }
1243
1244         rtl->parent = &pdev->dev;
1245
1246         smi = &rtl->smi;
1247         smi->parent = &pdev->dev;
1248         smi->gpio_sda = pdata->gpio_sda;
1249         smi->gpio_sck = pdata->gpio_sck;
1250         smi->ops = &rtl8366s_smi_ops;
1251         smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1252         smi->num_ports = RTL8366S_NUM_PORTS;
1253         smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1254         smi->mib_counters = rtl8366s_mib_counters;
1255         smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1256
1257         err = rtl8366_smi_init(smi);
1258         if (err)
1259                 goto err_free_rtl;
1260
1261         platform_set_drvdata(pdev, rtl);
1262
1263         err = rtl8366s_setup(rtl);
1264         if (err)
1265                 goto err_clear_drvdata;
1266
1267         err = rtl8366s_switch_init(rtl);
1268         if (err)
1269                 goto err_clear_drvdata;
1270
1271         return 0;
1272
1273  err_clear_drvdata:
1274         platform_set_drvdata(pdev, NULL);
1275         rtl8366_smi_cleanup(smi);
1276  err_free_rtl:
1277         kfree(rtl);
1278  err_out:
1279         return err;
1280 }
1281
1282 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1283 {
1284         if (!rtl8366s_mii_bus_match(phydev->bus))
1285                 return -EINVAL;
1286
1287         return 0;
1288 }
1289
1290 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1291 {
1292         return 0;
1293 }
1294
1295 static struct phy_driver rtl8366s_phy_driver = {
1296         .phy_id         = 0x001cc960,
1297         .name           = "Realtek RTL8366S",
1298         .phy_id_mask    = 0x1ffffff0,
1299         .features       = PHY_GBIT_FEATURES,
1300         .config_aneg    = rtl8366s_phy_config_aneg,
1301         .config_init    = rtl8366s_phy_config_init,
1302         .read_status    = genphy_read_status,
1303         .driver         = {
1304                 .owner = THIS_MODULE,
1305         },
1306 };
1307
1308 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1309 {
1310         struct rtl8366s *rtl = platform_get_drvdata(pdev);
1311
1312         if (rtl) {
1313                 rtl8366s_switch_cleanup(rtl);
1314                 platform_set_drvdata(pdev, NULL);
1315                 rtl8366_smi_cleanup(&rtl->smi);
1316                 kfree(rtl);
1317         }
1318
1319         return 0;
1320 }
1321
1322 static struct platform_driver rtl8366s_driver = {
1323         .driver = {
1324                 .name           = RTL8366S_DRIVER_NAME,
1325                 .owner          = THIS_MODULE,
1326         },
1327         .probe          = rtl8366s_probe,
1328         .remove         = __devexit_p(rtl8366s_remove),
1329 };
1330
1331 static int __init rtl8366s_module_init(void)
1332 {
1333         int ret;
1334         ret = platform_driver_register(&rtl8366s_driver);
1335         if (ret)
1336                 return ret;
1337
1338         ret = phy_driver_register(&rtl8366s_phy_driver);
1339         if (ret)
1340                 goto err_platform_unregister;
1341
1342         return 0;
1343
1344  err_platform_unregister:
1345         platform_driver_unregister(&rtl8366s_driver);
1346         return ret;
1347 }
1348 module_init(rtl8366s_module_init);
1349
1350 static void __exit rtl8366s_module_exit(void)
1351 {
1352         phy_driver_unregister(&rtl8366s_phy_driver);
1353         platform_driver_unregister(&rtl8366s_driver);
1354 }
1355 module_exit(rtl8366s_module_exit);
1356
1357 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1358 MODULE_VERSION(RTL8366S_DRIVER_VER);
1359 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1360 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1361 MODULE_LICENSE("GPL v2");
1362 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);