target/linux/generic/files/drivers/net/phy/rtl8366rb.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/switch.h>
  19 #include <linux/rtl8366rb.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
  24 #include <linux/debugfs.h>
  25 #endif
  26
  27 #define RTL8366RB_DRIVER_DESC   "Realtek RTL8366RB ethernet switch driver"
  28 #define RTL8366RB_DRIVER_VER    "0.2.2"
  29
  30 #define RTL8366RB_PHY_NO_MAX    4
  31 #define RTL8366RB_PHY_PAGE_MAX  7
  32 #define RTL8366RB_PHY_ADDR_MAX  31
  33
  34 #define RTL8366RB_CHIP_GLOBAL_CTRL_REG          0x0000
  35 #define RTL8366RB_CHIP_CTRL_VLAN                (1 << 13)
  36 #define RTL8366RB_CHIP_CTRL_VLAN_4KTB           (1 << 14)
  37
  38 /* Switch Global Configuration register */
  39 #define RTL8366RB_SGCR                          0x0000
  40 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  41 #define RTL8366RB_SGCR_MAX_LENGTH(_x)           (_x << 4)
  42 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  43 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  44 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  45 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  46 #define RTL8366RB_SGCR_MAX_LENGTH_9216          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  47
  48 /* Port Enable Control register */
  49 #define RTL8366RB_PECR                          0x0001
  50
  51 /* Switch Security Control registers */
  52 #define RTL8366RB_SSCR0                         0x0002
  53 #define RTL8366RB_SSCR1                         0x0003
  54 #define RTL8366RB_SSCR2                         0x0004
  55 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  56
  57 #define RTL8366RB_RESET_CTRL_REG                0x0100
  58 #define RTL8366RB_CHIP_CTRL_RESET_HW            1
  59 #define RTL8366RB_CHIP_CTRL_RESET_SW            (1 << 1)
  60
  61 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
  62 #define RTL8366RB_CHIP_VERSION_MASK             0xf
  63 #define RTL8366RB_CHIP_ID_REG                   0x0509
  64 #define RTL8366RB_CHIP_ID_8366                  0x5937
  65
  66 /* PHY registers control */
  67 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
  68 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
  69
  70 #define RTL8366RB_PHY_CTRL_READ                 1
  71 #define RTL8366RB_PHY_CTRL_WRITE                0
  72
  73 #define RTL8366RB_PHY_REG_MASK                  0x1f
  74 #define RTL8366RB_PHY_PAGE_OFFSET               5
  75 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
  76 #define RTL8366RB_PHY_NO_OFFSET                 9
  77 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
  78
  79 /* LED control registers */
  80 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
  81 #define RTL8366RB_LED_BLINKRATE_BIT             0
  82 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
  83
  84 #define RTL8366RB_LED_CTRL_REG                  0x0431
  85 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
  86 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
  87
  88 #define RTL8366RB_MIB_COUNT                     33
  89 #define RTL8366RB_GLOBAL_MIB_COUNT              1
  90 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
  91 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
  92 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
  93 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
  94 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
  95 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
  96 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
  97 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
  98
  99 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
 100 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
 101                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
 102 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
 103 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
 104
 105
 106 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 107 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 108
 109
 110 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 111 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 112 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 113
 114 #define RTL8366RB_VLAN_MEMCONF_BASE             0x0020
 115
 116
 117 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 118 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 119 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 120 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 121 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 122 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 123 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 124
 125
 126 #define RTL8366RB_PORT_NUM_CPU          5
 127 #define RTL8366RB_NUM_PORTS             6
 128 #define RTL8366RB_NUM_VLANS             16
 129 #define RTL8366RB_NUM_LEDGROUPS         4
 130 #define RTL8366RB_NUM_VIDS              4096
 131 #define RTL8366RB_PRIORITYMAX           7
 132 #define RTL8366RB_FIDMAX                7
 133
 134
 135 #define RTL8366RB_PORT_1                (1 << 0) /* In userspace port 0 */
 136 #define RTL8366RB_PORT_2                (1 << 1) /* In userspace port 1 */
 137 #define RTL8366RB_PORT_3                (1 << 2) /* In userspace port 2 */
 138 #define RTL8366RB_PORT_4                (1 << 3) /* In userspace port 3 */
 139 #define RTL8366RB_PORT_5                (1 << 4) /* In userspace port 4 */
 140
 141 #define RTL8366RB_PORT_CPU              (1 << 5) /* CPU port */
 142
 143 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 144                                          RTL8366RB_PORT_2 |     \
 145                                          RTL8366RB_PORT_3 |     \
 146                                          RTL8366RB_PORT_4 |     \
 147                                          RTL8366RB_PORT_5 |     \
 148                                          RTL8366RB_PORT_CPU)
 149
 150 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 151                                          RTL8366RB_PORT_2 |     \
 152                                          RTL8366RB_PORT_3 |     \
 153                                          RTL8366RB_PORT_4 |     \
 154                                          RTL8366RB_PORT_5)
 155
 156 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 157                                          RTL8366RB_PORT_2 |     \
 158                                          RTL8366RB_PORT_3 |     \
 159                                          RTL8366RB_PORT_4)
 160
 161 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 162
 163 struct rtl8366rb {
 164         struct device           *parent;
 165         struct rtl8366_smi      smi;
 166         struct switch_dev       dev;
 167 };
 168
 169 struct rtl8366rb_vlan_mc {
 170         u16     reserved2:1;
 171         u16     priority:3;
 172         u16     vid:12;
 173         u16     untag:8;
 174         u16     member:8;
 175         u16     stag_mbr:8;
 176         u16     stag_idx:3;
 177         u16     reserved1:2;
 178         u16     fid:3;
 179 };
 180
 181 struct rtl8366rb_vlan_4k {
 182         u16     reserved1:4;
 183         u16     vid:12;
 184         u16     untag:8;
 185         u16     member:8;
 186         u16     reserved2:13;
 187         u16     fid:3;
 188 };
 189
 190 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
 191         { 0,  0, 4, "IfInOctets"                                },
 192         { 0,  4, 4, "EtherStatsOctets"                          },
 193         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 194         { 0, 10, 2, "EtherFragments"                            },
 195         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 196         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 197         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 198         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 199         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 200         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 201         { 0, 24, 2, "EtherOversizeStats"                        },
 202         { 0, 26, 2, "EtherStatsJabbers"                         },
 203         { 0, 28, 2, "IfInUcastPkts"                             },
 204         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 205         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 206         { 0, 34, 2, "EtherStatsDropEvents"                      },
 207         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 208         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 209         { 0, 40, 2, "Dot3InPauseFrames"                         },
 210         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 211         { 0, 44, 4, "IfOutOctets"                               },
 212         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 213         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 214         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 215         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 216         { 0, 56, 2, "EtherStatsCollisions"                      },
 217         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 218         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 219         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 220         { 0, 64, 2, "Dot1dTpPortInDiscards"                     },
 221         { 0, 66, 2, "IfOutUcastPkts"                            },
 222         { 0, 68, 2, "IfOutMulticastPkts"                        },
 223         { 0, 70, 2, "IfOutBroadcastPkts"                        },
 224 };
 225
 226 #define REG_WR(_smi, _reg, _val)                                        \
 227         do {                                                            \
 228                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 229                 if (err)                                                \
 230                         return err;                                     \
 231         } while (0)
 232
 233 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 234         do {                                                            \
 235                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 236                 if (err)                                                \
 237                         return err;                                     \
 238         } while (0)
 239
 240 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
 241 {
 242         return container_of(smi, struct rtl8366rb, smi);
 243 }
 244
 245 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
 246 {
 247         return container_of(sw, struct rtl8366rb, dev);
 248 }
 249
 250 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
 251 {
 252         struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
 253         return &rtl->smi;
 254 }
 255
 256 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
 257 {
 258         int timeout = 10;
 259         u32 data;
 260
 261         rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
 262                               RTL8366RB_CHIP_CTRL_RESET_HW);
 263         do {
 264                 msleep(1);
 265                 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
 266                         return -EIO;
 267
 268                 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
 269                         break;
 270         } while (--timeout);
 271
 272         if (!timeout) {
 273                 printk("Timeout waiting for the switch to reset\n");
 274                 return -EIO;
 275         }
 276
 277         return 0;
 278 }
 279
 280 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
 281 {
 282         int err;
 283
 284         /* set maximum packet length to 1536 bytes */
 285         REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
 286                 RTL8366RB_SGCR_MAX_LENGTH_1536);
 287
 288         /* enable all ports */
 289         REG_WR(smi, RTL8366RB_PECR, 0);
 290
 291         /* disable learning for all ports */
 292         REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
 293
 294         /* disable auto ageing for all ports */
 295         REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
 296
 297         /* don't drop packets whose DA has not been learned */
 298         REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
 299
 300         return 0;
 301 }
 302
 303 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
 304                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 305 {
 306         u32 reg;
 307         int ret;
 308
 309         if (phy_no > RTL8366RB_PHY_NO_MAX)
 310                 return -EINVAL;
 311
 312         if (page > RTL8366RB_PHY_PAGE_MAX)
 313                 return -EINVAL;
 314
 315         if (addr > RTL8366RB_PHY_ADDR_MAX)
 316                 return -EINVAL;
 317
 318         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 319                                     RTL8366RB_PHY_CTRL_READ);
 320         if (ret)
 321                 return ret;
 322
 323         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 324               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 325               (addr & RTL8366RB_PHY_REG_MASK);
 326
 327         ret = rtl8366_smi_write_reg(smi, reg, 0);
 328         if (ret)
 329                 return ret;
 330
 331         ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
 332         if (ret)
 333                 return ret;
 334
 335         return 0;
 336 }
 337
 338 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
 339                                   u32 phy_no, u32 page, u32 addr, u32 data)
 340 {
 341         u32 reg;
 342         int ret;
 343
 344         if (phy_no > RTL8366RB_PHY_NO_MAX)
 345                 return -EINVAL;
 346
 347         if (page > RTL8366RB_PHY_PAGE_MAX)
 348                 return -EINVAL;
 349
 350         if (addr > RTL8366RB_PHY_ADDR_MAX)
 351                 return -EINVAL;
 352
 353         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 354                                     RTL8366RB_PHY_CTRL_WRITE);
 355         if (ret)
 356                 return ret;
 357
 358         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 359               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 360               (addr & RTL8366RB_PHY_REG_MASK);
 361
 362         ret = rtl8366_smi_write_reg(smi, reg, data);
 363         if (ret)
 364                 return ret;
 365
 366         return 0;
 367 }
 368
 369 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 370                                    int port, unsigned long long *val)
 371 {
 372         int i;
 373         int err;
 374         u32 addr, data;
 375         u64 mibvalue;
 376
 377         if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
 378                 return -EINVAL;
 379
 380         addr = RTL8366RB_MIB_COUNTER_BASE +
 381                RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 382                rtl8366rb_mib_counters[counter].offset;
 383
 384         /*
 385          * Writing access counter address first
 386          * then ASIC will prepare 64bits counter wait for being retrived
 387          */
 388         data = 0; /* writing data will be discard by ASIC */
 389         err = rtl8366_smi_write_reg(smi, addr, data);
 390         if (err)
 391                 return err;
 392
 393         /* read MIB control register */
 394         err =  rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
 395         if (err)
 396                 return err;
 397
 398         if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
 399                 return -EBUSY;
 400
 401         if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
 402                 return -EIO;
 403
 404         mibvalue = 0;
 405         for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
 406                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 407                 if (err)
 408                         return err;
 409
 410                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 411         }
 412
 413         *val = mibvalue;
 414         return 0;
 415 }
 416
 417 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 418                                  struct rtl8366_vlan_4k *vlan4k)
 419 {
 420         struct rtl8366rb_vlan_4k vlan4k_priv;
 421         int err;
 422         u32 data;
 423         u16 *tableaddr;
 424
 425         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 426         vlan4k_priv.vid = vid;
 427
 428         if (vid >= RTL8366RB_NUM_VIDS)
 429                 return -EINVAL;
 430
 431         tableaddr = (u16 *)&vlan4k_priv;
 432
 433         /* write VID */
 434         data = *tableaddr;
 435         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
 436         if (err)
 437                 return err;
 438
 439         /* write table access control word */
 440         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 441                                     RTL8366RB_TABLE_VLAN_READ_CTRL);
 442         if (err)
 443                 return err;
 444
 445         err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
 446         if (err)
 447                 return err;
 448
 449         *tableaddr = data;
 450         tableaddr++;
 451
 452         err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
 453                                    &data);
 454         if (err)
 455                 return err;
 456
 457         *tableaddr = data;
 458         tableaddr++;
 459
 460         err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
 461                                    &data);
 462         if (err)
 463                 return err;
 464         *tableaddr = data;
 465
 466         vlan4k->vid = vid;
 467         vlan4k->untag = vlan4k_priv.untag;
 468         vlan4k->member = vlan4k_priv.member;
 469         vlan4k->fid = vlan4k_priv.fid;
 470
 471         return 0;
 472 }
 473
 474 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
 475                                  const struct rtl8366_vlan_4k *vlan4k)
 476 {
 477         struct rtl8366rb_vlan_4k vlan4k_priv;
 478         int err;
 479         u32 data;
 480         u16 *tableaddr;
 481
 482         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
 483             vlan4k->member > RTL8366RB_PORT_ALL ||
 484             vlan4k->untag > RTL8366RB_PORT_ALL ||
 485             vlan4k->fid > RTL8366RB_FIDMAX)
 486                 return -EINVAL;
 487
 488         vlan4k_priv.vid = vlan4k->vid;
 489         vlan4k_priv.untag = vlan4k->untag;
 490         vlan4k_priv.member = vlan4k->member;
 491         vlan4k_priv.fid = vlan4k->fid;
 492
 493         tableaddr = (u16 *)&vlan4k_priv;
 494
 495         data = *tableaddr;
 496
 497         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
 498         if (err)
 499                 return err;
 500
 501         tableaddr++;
 502
 503         data = *tableaddr;
 504
 505         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
 506                                     data);
 507         if (err)
 508                 return err;
 509
 510         tableaddr++;
 511
 512         data = *tableaddr;
 513
 514         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
 515                                     data);
 516         if (err)
 517                 return err;
 518
 519         /* write table access control word */
 520         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 521                                     RTL8366RB_TABLE_VLAN_WRITE_CTRL);
 522
 523         return err;
 524 }
 525
 526 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 527                                  struct rtl8366_vlan_mc *vlanmc)
 528 {
 529         struct rtl8366rb_vlan_mc vlanmc_priv;
 530         int err;
 531         u32 addr;
 532         u32 data;
 533         u16 *tableaddr;
 534
 535         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 536
 537         if (index >= RTL8366RB_NUM_VLANS)
 538                 return -EINVAL;
 539
 540         tableaddr = (u16 *)&vlanmc_priv;
 541
 542         addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
 543         err = rtl8366_smi_read_reg(smi, addr, &data);
 544         if (err)
 545                 return err;
 546
 547         *tableaddr = data;
 548         tableaddr++;
 549
 550         addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
 551         err = rtl8366_smi_read_reg(smi, addr, &data);
 552         if (err)
 553                 return err;
 554
 555         *tableaddr = data;
 556         tableaddr++;
 557
 558         addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
 559         err = rtl8366_smi_read_reg(smi, addr, &data);
 560         if (err)
 561                 return err;
 562
 563         *tableaddr = data;
 564
 565         vlanmc->vid = vlanmc_priv.vid;
 566         vlanmc->priority = vlanmc_priv.priority;
 567         vlanmc->untag = vlanmc_priv.untag;
 568         vlanmc->member = vlanmc_priv.member;
 569         vlanmc->fid = vlanmc_priv.fid;
 570
 571         return 0;
 572 }
 573
 574 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 575                                  const struct rtl8366_vlan_mc *vlanmc)
 576 {
 577         struct rtl8366rb_vlan_mc vlanmc_priv;
 578         int err;
 579         u32 addr;
 580         u32 data;
 581         u16 *tableaddr;
 582
 583         if (index >= RTL8366RB_NUM_VLANS ||
 584             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
 585             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
 586             vlanmc->member > RTL8366RB_PORT_ALL ||
 587             vlanmc->untag > RTL8366RB_PORT_ALL ||
 588             vlanmc->fid > RTL8366RB_FIDMAX)
 589                 return -EINVAL;
 590
 591         vlanmc_priv.vid = vlanmc->vid;
 592         vlanmc_priv.priority = vlanmc->priority;
 593         vlanmc_priv.untag = vlanmc->untag;
 594         vlanmc_priv.member = vlanmc->member;
 595         vlanmc_priv.stag_mbr = 0;
 596         vlanmc_priv.stag_idx = 0;
 597         vlanmc_priv.fid = vlanmc->fid;
 598
 599         addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
 600
 601         tableaddr = (u16 *)&vlanmc_priv;
 602         data = *tableaddr;
 603
 604         err = rtl8366_smi_write_reg(smi, addr, data);
 605         if (err)
 606                 return err;
 607
 608         addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
 609
 610         tableaddr++;
 611         data = *tableaddr;
 612
 613         err = rtl8366_smi_write_reg(smi, addr, data);
 614         if (err)
 615                 return err;
 616
 617         addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
 618
 619         tableaddr++;
 620         data = *tableaddr;
 621
 622         err = rtl8366_smi_write_reg(smi, addr, data);
 623         if (err)
 624                 return err;
 625         return 0;
 626 }
 627
 628 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 629 {
 630         u32 data;
 631         int err;
 632
 633         if (port >= RTL8366RB_NUM_PORTS)
 634                 return -EINVAL;
 635
 636         err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 637                                    &data);
 638         if (err)
 639                 return err;
 640
 641         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
 642                RTL8366RB_PORT_VLAN_CTRL_MASK;
 643
 644         return 0;
 645
 646 }
 647
 648 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 649 {
 650         if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
 651                 return -EINVAL;
 652
 653         return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 654                                 RTL8366RB_PORT_VLAN_CTRL_MASK <<
 655                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
 656                                 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
 657                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
 658 }
 659
 660 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
 661 {
 662         return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
 663                                 RTL8366RB_CHIP_CTRL_VLAN,
 664                                 (enable) ? RTL8366RB_CHIP_CTRL_VLAN : 0);
 665 }
 666
 667 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
 668 {
 669         return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
 670                                 RTL8366RB_CHIP_CTRL_VLAN_4KTB,
 671                                 (enable) ? RTL8366RB_CHIP_CTRL_VLAN_4KTB : 0);
 672 }
 673
 674 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
 675 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
 676                                           char __user *user_buf,
 677                                           size_t count, loff_t *ppos)
 678 {
 679         struct rtl8366_smi *smi = file->private_data;
 680         int i, j, len = 0;
 681         char *buf = smi->buf;
 682
 683         len += snprintf(buf + len, sizeof(smi->buf) - len,
 684                         "%-36s %12s %12s %12s %12s %12s %12s\n",
 685                         "Counter",
 686                         "Port 0", "Port 1", "Port 2",
 687                         "Port 3", "Port 4", "Port 5");
 688
 689         for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
 690                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%-36s ",
 691                                 rtl8366rb_mib_counters[i].name);
 692                 for (j = 0; j < RTL8366RB_NUM_PORTS; ++j) {
 693                         unsigned long long counter = 0;
 694
 695                         if (!rtl8366_get_mib_counter(smi, i, j, &counter))
 696                                 len += snprintf(buf + len,
 697                                                 sizeof(smi->buf) - len,
 698                                                 "%12llu ", counter);
 699                         else
 700                                 len += snprintf(buf + len,
 701                                                 sizeof(smi->buf) - len,
 702                                                 "%12s ", "error");
 703                 }
 704                 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
 705         }
 706
 707         return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 708 }
 709
 710 static const struct file_operations fops_rtl8366rb_mibs = {
 711         .read = rtl8366rb_read_debugfs_mibs,
 712         .open = rtl8366_debugfs_open,
 713         .owner = THIS_MODULE
 714 };
 715
 716 static void rtl8366rb_debugfs_init(struct rtl8366_smi *smi)
 717 {
 718         struct dentry *node;
 719
 720         if (!smi->debugfs_root)
 721                 return;
 722
 723         node = debugfs_create_file("mibs", S_IRUSR, smi->debugfs_root, smi,
 724                                    &fops_rtl8366rb_mibs);
 725         if (!node)
 726                 dev_err(smi->parent, "Creating debugfs file '%s' failed\n",
 727                         "mibs");
 728 }
 729
 730 #else
 731 static inline void rtl8366rb_debugfs_init(struct rtl8366_smi *smi) {}
 732 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
 733
 734 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
 735                                   const struct switch_attr *attr,
 736                                   struct switch_val *val)
 737 {
 738         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 739         int err = 0;
 740
 741         if (val->value.i == 1)
 742                 err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 743                                        RTL8366RB_MIB_CTRL_GLOBAL_RESET);
 744
 745         return err;
 746 }
 747
 748 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
 749                                        const struct switch_attr *attr,
 750                                        struct switch_val *val)
 751 {
 752         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 753         u32 data;
 754
 755         if (attr->ofs == 1) {
 756                 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
 757
 758                 if (data & RTL8366RB_CHIP_CTRL_VLAN)
 759                         val->value.i = 1;
 760                 else
 761                         val->value.i = 0;
 762         } else if (attr->ofs == 2) {
 763                 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
 764
 765                 if (data & RTL8366RB_CHIP_CTRL_VLAN_4KTB)
 766                         val->value.i = 1;
 767                 else
 768                         val->value.i = 0;
 769         }
 770
 771         return 0;
 772 }
 773
 774 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
 775                                      const struct switch_attr *attr,
 776                                      struct switch_val *val)
 777 {
 778         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 779         u32 data;
 780
 781         rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
 782
 783         val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
 784
 785         return 0;
 786 }
 787
 788 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
 789                                     const struct switch_attr *attr,
 790                                     struct switch_val *val)
 791 {
 792         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 793
 794         if (val->value.i >= 6)
 795                 return -EINVAL;
 796
 797         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
 798                                 RTL8366RB_LED_BLINKRATE_MASK,
 799                                 val->value.i);
 800 }
 801
 802 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
 803                                        const struct switch_attr *attr,
 804                                        struct switch_val *val)
 805 {
 806         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 807
 808         if (attr->ofs == 1)
 809                 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
 810         else
 811                 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
 812 }
 813
 814 static const char *rtl8366rb_speed_str(unsigned speed)
 815 {
 816         switch (speed) {
 817         case 0:
 818                 return "10baseT";
 819         case 1:
 820                 return "100baseT";
 821         case 2:
 822                 return "1000baseT";
 823         }
 824
 825         return "unknown";
 826 }
 827
 828 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
 829                                      const struct switch_attr *attr,
 830                                      struct switch_val *val)
 831 {
 832         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 833         u32 len = 0, data = 0;
 834
 835         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 836                 return -EINVAL;
 837
 838         memset(smi->buf, '\0', sizeof(smi->buf));
 839         rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
 840                              (val->port_vlan / 2), &data);
 841
 842         if (val->port_vlan % 2)
 843                 data = data >> 8;
 844
 845         if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
 846                 len = snprintf(smi->buf, sizeof(smi->buf),
 847                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 848                                 val->port_vlan,
 849                                 rtl8366rb_speed_str(data &
 850                                           RTL8366RB_PORT_STATUS_SPEED_MASK),
 851                                 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
 852                                         "full" : "half",
 853                                 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
 854                                         "tx-pause ": "",
 855                                 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
 856                                         "rx-pause " : "",
 857                                 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
 858                                         "nway ": "");
 859         } else {
 860                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 861                                 val->port_vlan);
 862         }
 863
 864         val->value.s = smi->buf;
 865         val->len = len;
 866
 867         return 0;
 868 }
 869
 870 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
 871                                      const struct switch_attr *attr,
 872                                      struct switch_val *val)
 873 {
 874         int i;
 875         u32 len = 0;
 876         struct rtl8366_vlan_4k vlan4k;
 877         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 878         char *buf = smi->buf;
 879         int err;
 880
 881         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
 882                 return -EINVAL;
 883
 884         memset(buf, '\0', sizeof(smi->buf));
 885
 886         err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 887         if (err)
 888                 return err;
 889
 890         len += snprintf(buf + len, sizeof(smi->buf) - len,
 891                         "VLAN %d: Ports: '", vlan4k.vid);
 892
 893         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
 894                 if (!(vlan4k.member & (1 << i)))
 895                         continue;
 896
 897                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
 898                                 (vlan4k.untag & (1 << i)) ? "" : "t");
 899         }
 900
 901         len += snprintf(buf + len, sizeof(smi->buf) - len,
 902                         "', members=%04x, untag=%04x, fid=%u",
 903                         vlan4k.member, vlan4k.untag, vlan4k.fid);
 904
 905         val->value.s = buf;
 906         val->len = len;
 907
 908         return 0;
 909 }
 910
 911 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
 912                                     const struct switch_attr *attr,
 913                                     struct switch_val *val)
 914 {
 915         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 916         u32 data;
 917         u32 mask;
 918         u32 reg;
 919
 920         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 921                 return -EINVAL;
 922
 923         if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
 924                 reg = RTL8366RB_LED_BLINKRATE_REG;
 925                 mask = 0xF << 4;
 926                 data = val->value.i << 4;
 927         } else {
 928                 reg = RTL8366RB_LED_CTRL_REG;
 929                 mask = 0xF << (val->port_vlan * 4),
 930                 data = val->value.i << (val->port_vlan * 4);
 931         }
 932
 933         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
 934 }
 935
 936 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
 937                                     const struct switch_attr *attr,
 938                                     struct switch_val *val)
 939 {
 940         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 941         u32 data = 0;
 942
 943         if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
 944                 return -EINVAL;
 945
 946         rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
 947         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 948
 949         return 0;
 950 }
 951
 952 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
 953                                        const struct switch_attr *attr,
 954                                        struct switch_val *val)
 955 {
 956         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 957
 958         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 959                 return -EINVAL;
 960
 961         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 962                                 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
 963 }
 964
 965 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
 966                                     const struct switch_attr *attr,
 967                                     struct switch_val *val)
 968 {
 969         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 970         int i, len = 0;
 971         unsigned long long counter = 0;
 972         char *buf = smi->buf;
 973
 974         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 975                 return -EINVAL;
 976
 977         len += snprintf(buf + len, sizeof(smi->buf) - len,
 978                         "Port %d MIB counters\n",
 979                         val->port_vlan);
 980
 981         for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
 982                 len += snprintf(buf + len, sizeof(smi->buf) - len,
 983                                 "%-36s: ", rtl8366rb_mib_counters[i].name);
 984                 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
 985                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 986                                         "%llu\n", counter);
 987                 else
 988                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 989                                         "%s\n", "error");
 990         }
 991
 992         val->value.s = buf;
 993         val->len = len;
 994         return 0;
 995 }
 996
 997 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
 998                                       struct switch_val *val)
 999 {
1000         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1001         struct switch_port *port;
1002         struct rtl8366_vlan_4k vlan4k;
1003         int i;
1004
1005         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1006                 return -EINVAL;
1007
1008         rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1009
1010         port = &val->value.ports[0];
1011         val->len = 0;
1012         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1013                 if (!(vlan4k.member & BIT(i)))
1014                         continue;
1015
1016                 port->id = i;
1017                 port->flags = (vlan4k.untag & BIT(i)) ?
1018                                         0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1019                 val->len++;
1020                 port++;
1021         }
1022         return 0;
1023 }
1024
1025 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1026                                       struct switch_val *val)
1027 {
1028         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1029         struct switch_port *port;
1030         u32 member = 0;
1031         u32 untag = 0;
1032         int i;
1033
1034         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1035                 return -EINVAL;
1036
1037         port = &val->value.ports[0];
1038         for (i = 0; i < val->len; i++, port++) {
1039                 member |= BIT(port->id);
1040
1041                 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1042                         untag |= BIT(port->id);
1043         }
1044
1045         return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1046 }
1047
1048 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1049 {
1050         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1051         return rtl8366_get_pvid(smi, port, val);
1052 }
1053
1054 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1055 {
1056         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1057         return rtl8366_set_pvid(smi, port, val);
1058 }
1059
1060 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1061 {
1062         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1063         int err;
1064
1065         err = rtl8366rb_reset_chip(smi);
1066         if (err)
1067                 return err;
1068
1069         err = rtl8366rb_hw_init(smi);
1070         if (err)
1071                 return err;
1072
1073         return rtl8366_reset_vlan(smi);
1074 }
1075
1076 static struct switch_attr rtl8366rb_globals[] = {
1077         {
1078                 .type = SWITCH_TYPE_INT,
1079                 .name = "enable_vlan",
1080                 .description = "Enable VLAN mode",
1081                 .set = rtl8366rb_sw_set_vlan_enable,
1082                 .get = rtl8366rb_sw_get_vlan_enable,
1083                 .max = 1,
1084                 .ofs = 1
1085         }, {
1086                 .type = SWITCH_TYPE_INT,
1087                 .name = "enable_vlan4k",
1088                 .description = "Enable VLAN 4K mode",
1089                 .set = rtl8366rb_sw_set_vlan_enable,
1090                 .get = rtl8366rb_sw_get_vlan_enable,
1091                 .max = 1,
1092                 .ofs = 2
1093         }, {
1094                 .type = SWITCH_TYPE_INT,
1095                 .name = "reset_mibs",
1096                 .description = "Reset all MIB counters",
1097                 .set = rtl8366rb_sw_reset_mibs,
1098                 .get = NULL,
1099                 .max = 1
1100         }, {
1101                 .type = SWITCH_TYPE_INT,
1102                 .name = "blinkrate",
1103                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1104                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1105                 .set = rtl8366rb_sw_set_blinkrate,
1106                 .get = rtl8366rb_sw_get_blinkrate,
1107                 .max = 5
1108         },
1109 };
1110
1111 static struct switch_attr rtl8366rb_port[] = {
1112         {
1113                 .type = SWITCH_TYPE_STRING,
1114                 .name = "link",
1115                 .description = "Get port link information",
1116                 .max = 1,
1117                 .set = NULL,
1118                 .get = rtl8366rb_sw_get_port_link,
1119         }, {
1120                 .type = SWITCH_TYPE_INT,
1121                 .name = "reset_mib",
1122                 .description = "Reset single port MIB counters",
1123                 .max = 1,
1124                 .set = rtl8366rb_sw_reset_port_mibs,
1125                 .get = NULL,
1126         }, {
1127                 .type = SWITCH_TYPE_STRING,
1128                 .name = "mib",
1129                 .description = "Get MIB counters for port",
1130                 .max = 33,
1131                 .set = NULL,
1132                 .get = rtl8366rb_sw_get_port_mib,
1133         }, {
1134                 .type = SWITCH_TYPE_INT,
1135                 .name = "led",
1136                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1137                 .max = 15,
1138                 .set = rtl8366rb_sw_set_port_led,
1139                 .get = rtl8366rb_sw_get_port_led,
1140         },
1141 };
1142
1143 static struct switch_attr rtl8366rb_vlan[] = {
1144         {
1145                 .type = SWITCH_TYPE_STRING,
1146                 .name = "info",
1147                 .description = "Get vlan information",
1148                 .max = 1,
1149                 .set = NULL,
1150                 .get = rtl8366rb_sw_get_vlan_info,
1151         },
1152 };
1153
1154 /* template */
1155 static struct switch_dev rtl8366_switch_dev = {
1156         .name = "RTL8366S",
1157         .cpu_port = RTL8366RB_PORT_NUM_CPU,
1158         .ports = RTL8366RB_NUM_PORTS,
1159         .vlans = RTL8366RB_NUM_VLANS,
1160         .attr_global = {
1161                 .attr = rtl8366rb_globals,
1162                 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1163         },
1164         .attr_port = {
1165                 .attr = rtl8366rb_port,
1166                 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1167         },
1168         .attr_vlan = {
1169                 .attr = rtl8366rb_vlan,
1170                 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1171         },
1172
1173         .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1174         .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1175         .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1176         .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1177         .reset_switch = rtl8366rb_sw_reset_switch,
1178 };
1179
1180 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1181 {
1182         struct switch_dev *dev = &rtl->dev;
1183         int err;
1184
1185         memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1186         dev->priv = rtl;
1187         dev->devname = dev_name(rtl->parent);
1188
1189         err = register_switch(dev, NULL);
1190         if (err)
1191                 dev_err(rtl->parent, "switch registration failed\n");
1192
1193         return err;
1194 }
1195
1196 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1197 {
1198         unregister_switch(&rtl->dev);
1199 }
1200
1201 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1202 {
1203         struct rtl8366_smi *smi = bus->priv;
1204         u32 val = 0;
1205         int err;
1206
1207         err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1208         if (err)
1209                 return 0xffff;
1210
1211         return val;
1212 }
1213
1214 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1215 {
1216         struct rtl8366_smi *smi = bus->priv;
1217         u32 t;
1218         int err;
1219
1220         err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1221         /* flush write */
1222         (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1223
1224         return err;
1225 }
1226
1227 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1228 {
1229         return (bus->read == rtl8366rb_mii_read &&
1230                 bus->write == rtl8366rb_mii_write);
1231 }
1232
1233 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1234 {
1235         struct rtl8366_smi *smi = &rtl->smi;
1236         int ret;
1237
1238         rtl8366rb_debugfs_init(smi);
1239
1240         ret = rtl8366rb_reset_chip(smi);
1241         if (ret)
1242                 return ret;
1243
1244         ret = rtl8366rb_hw_init(smi);
1245         return ret;
1246 }
1247
1248 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1249 {
1250         u32 chip_id = 0;
1251         u32 chip_ver = 0;
1252         int ret;
1253
1254         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1255         if (ret) {
1256                 dev_err(smi->parent, "unable to read chip id\n");
1257                 return ret;
1258         }
1259
1260         switch (chip_id) {
1261         case RTL8366RB_CHIP_ID_8366:
1262                 break;
1263         default:
1264                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1265                 return -ENODEV;
1266         }
1267
1268         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1269                                    &chip_ver);
1270         if (ret) {
1271                 dev_err(smi->parent, "unable to read chip version\n");
1272                 return ret;
1273         }
1274
1275         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1276                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1277
1278         return 0;
1279 }
1280
1281 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1282         .detect         = rtl8366rb_detect,
1283         .mii_read       = rtl8366rb_mii_read,
1284         .mii_write      = rtl8366rb_mii_write,
1285
1286         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
1287         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
1288         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
1289         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
1290         .get_mc_index   = rtl8366rb_get_mc_index,
1291         .set_mc_index   = rtl8366rb_set_mc_index,
1292 };
1293
1294 static int __init rtl8366rb_probe(struct platform_device *pdev)
1295 {
1296         static int rtl8366_smi_version_printed;
1297         struct rtl8366rb_platform_data *pdata;
1298         struct rtl8366rb *rtl;
1299         struct rtl8366_smi *smi;
1300         int err;
1301
1302         if (!rtl8366_smi_version_printed++)
1303                 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1304                        " version " RTL8366RB_DRIVER_VER"\n");
1305
1306         pdata = pdev->dev.platform_data;
1307         if (!pdata) {
1308                 dev_err(&pdev->dev, "no platform data specified\n");
1309                 err = -EINVAL;
1310                 goto err_out;
1311         }
1312
1313         rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1314         if (!rtl) {
1315                 dev_err(&pdev->dev, "no memory for private data\n");
1316                 err = -ENOMEM;
1317                 goto err_out;
1318         }
1319
1320         rtl->parent = &pdev->dev;
1321
1322         smi = &rtl->smi;
1323         smi->parent = &pdev->dev;
1324         smi->gpio_sda = pdata->gpio_sda;
1325         smi->gpio_sck = pdata->gpio_sck;
1326         smi->ops = &rtl8366rb_smi_ops;
1327         smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1328         smi->num_ports = RTL8366RB_NUM_PORTS;
1329         smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1330
1331         err = rtl8366_smi_init(smi);
1332         if (err)
1333                 goto err_free_rtl;
1334
1335         platform_set_drvdata(pdev, rtl);
1336
1337         err = rtl8366rb_setup(rtl);
1338         if (err)
1339                 goto err_clear_drvdata;
1340
1341         err = rtl8366rb_switch_init(rtl);
1342         if (err)
1343                 goto err_clear_drvdata;
1344
1345         return 0;
1346
1347  err_clear_drvdata:
1348         platform_set_drvdata(pdev, NULL);
1349         rtl8366_smi_cleanup(smi);
1350  err_free_rtl:
1351         kfree(rtl);
1352  err_out:
1353         return err;
1354 }
1355
1356 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1357 {
1358         if (!rtl8366rb_mii_bus_match(phydev->bus))
1359                 return -EINVAL;
1360
1361         return 0;
1362 }
1363
1364 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1365 {
1366         return 0;
1367 }
1368
1369 static struct phy_driver rtl8366rb_phy_driver = {
1370         .phy_id         = 0x001cc960,
1371         .name           = "Realtek RTL8366RB",
1372         .phy_id_mask    = 0x1ffffff0,
1373         .features       = PHY_GBIT_FEATURES,
1374         .config_aneg    = rtl8366rb_phy_config_aneg,
1375         .config_init    = rtl8366rb_phy_config_init,
1376         .read_status    = genphy_read_status,
1377         .driver         = {
1378                 .owner = THIS_MODULE,
1379         },
1380 };
1381
1382 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1383 {
1384         struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1385
1386         if (rtl) {
1387                 rtl8366rb_switch_cleanup(rtl);
1388                 platform_set_drvdata(pdev, NULL);
1389                 rtl8366_smi_cleanup(&rtl->smi);
1390                 kfree(rtl);
1391         }
1392
1393         return 0;
1394 }
1395
1396 static struct platform_driver rtl8366rb_driver = {
1397         .driver = {
1398                 .name           = RTL8366RB_DRIVER_NAME,
1399                 .owner          = THIS_MODULE,
1400         },
1401         .probe          = rtl8366rb_probe,
1402         .remove         = __devexit_p(rtl8366rb_remove),
1403 };
1404
1405 static int __init rtl8366rb_module_init(void)
1406 {
1407         int ret;
1408         ret = platform_driver_register(&rtl8366rb_driver);
1409         if (ret)
1410                 return ret;
1411
1412         ret = phy_driver_register(&rtl8366rb_phy_driver);
1413         if (ret)
1414                 goto err_platform_unregister;
1415
1416         return 0;
1417
1418  err_platform_unregister:
1419         platform_driver_unregister(&rtl8366rb_driver);
1420         return ret;
1421 }
1422 module_init(rtl8366rb_module_init);
1423
1424 static void __exit rtl8366rb_module_exit(void)
1425 {
1426         phy_driver_unregister(&rtl8366rb_phy_driver);
1427         platform_driver_unregister(&rtl8366rb_driver);
1428 }
1429 module_exit(rtl8366rb_module_exit);
1430
1431 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1432 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1433 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1434 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1435 MODULE_LICENSE("GPL v2");
1436 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);