target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/version.h>
  37
  38 #include "ar8216.h"
  39
  40 extern const struct ar8xxx_chip ar8327_chip;
  41 extern const struct ar8xxx_chip ar8337_chip;
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 #define MIB_DESC(_s , _o, _n)   \
  46         {                       \
  47                 .size = (_s),   \
  48                 .offset = (_o), \
  49                 .name = (_n),   \
  50         }
  51
  52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  53         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  54         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  55         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  56         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  57         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  58         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  59         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  60         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  61         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  62         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  63         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  64         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  65         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  66         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  67         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  68         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  69         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  70         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  71         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  72         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  73         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  74         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  75         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  76         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  77         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  78         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  79         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  80         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  81         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  82         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  83         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  84         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  85         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  86         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  87         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  88         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  89         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  90 };
  91
  92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
  93         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  94         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  95         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  96         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  97         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  98         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  99         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 100         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 101         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 102         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 103         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 104         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 105         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 106         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 107         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 108         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 109         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 110         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 111         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 112         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 113         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 114         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 115         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 116         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 117         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 118         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 119         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 120         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 121         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 122         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 123         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 124         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 125         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 126         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 127         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 128         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 129         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 130         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 131         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 132 };
 133
 134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 135 static LIST_HEAD(ar8xxx_dev_list);
 136
 137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 138 static int
 139 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 140 {
 141         unsigned int sleep_msecs = 20;
 142         int ret, elapsed, i;
 143
 144         for (elapsed = sleep_msecs; elapsed <= 600;
 145              elapsed += sleep_msecs) {
 146                 msleep(sleep_msecs);
 147                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 148                         ret = mdiobus_read(bus, i, MII_BMCR);
 149                         if (ret < 0)
 150                                 return ret;
 151                         if (ret & BMCR_RESET)
 152                                 break;
 153                         if (i == AR8XXX_NUM_PHYS - 1) {
 154                                 usleep_range(1000, 2000);
 155                                 return 0;
 156                         }
 157                 }
 158         }
 159         return -ETIMEDOUT;
 160 }
 161
 162 static int
 163 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 164 {
 165         int ret;
 166
 167         if (phydev->autoneg != AUTONEG_ENABLE)
 168                 return 0;
 169         /*
 170          * BMCR_ANENABLE might have been cleared
 171          * by phy_init_hw in certain kernel versions
 172          * therefore check for it
 173          */
 174         ret = phy_read(phydev, MII_BMCR);
 175         if (ret < 0)
 176                 return ret;
 177         if (ret & BMCR_ANENABLE)
 178                 return 0;
 179
 180         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 181         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 182         return phy_write(phydev, MII_BMCR, ret);
 183 }
 184
 185 void
 186 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 187 {
 188         int i;
 189         struct mii_bus *bus;
 190
 191         bus = priv->mii_bus;
 192         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 193                 if (priv->chip->phy_fixup)
 194                         priv->chip->phy_fixup(priv, i);
 195
 196                 /* initialize the port itself */
 197                 mdiobus_write(bus, i, MII_ADVERTISE,
 198                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 199                 if (ar8xxx_has_gige(priv))
 200                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 201                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 202         }
 203
 204         ar8xxx_phy_poll_reset(bus);
 205 }
 206
 207 u32
 208 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
 209 {
 210         struct mii_bus *bus = priv->mii_bus;
 211         u16 lo, hi;
 212
 213         lo = bus->read(bus, phy_id, regnum);
 214         hi = bus->read(bus, phy_id, regnum + 1);
 215
 216         return (hi << 16) | lo;
 217 }
 218
 219 void
 220 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
 221 {
 222         struct mii_bus *bus = priv->mii_bus;
 223         u16 lo, hi;
 224
 225         lo = val & 0xffff;
 226         hi = (u16) (val >> 16);
 227
 228         if (priv->chip->mii_lo_first)
 229         {
 230                 bus->write(bus, phy_id, regnum, lo);
 231                 bus->write(bus, phy_id, regnum + 1, hi);
 232         } else {
 233                 bus->write(bus, phy_id, regnum + 1, hi);
 234                 bus->write(bus, phy_id, regnum, lo);
 235         }
 236 }
 237
 238 u32
 239 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
 240 {
 241         struct mii_bus *bus = priv->mii_bus;
 242         u16 r1, r2, page;
 243         u32 val;
 244
 245         split_addr((u32) reg, &r1, &r2, &page);
 246
 247         mutex_lock(&bus->mdio_lock);
 248
 249         bus->write(bus, 0x18, 0, page);
 250         wait_for_page_switch();
 251         val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 252
 253         mutex_unlock(&bus->mdio_lock);
 254
 255         return val;
 256 }
 257
 258 void
 259 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
 260 {
 261         struct mii_bus *bus = priv->mii_bus;
 262         u16 r1, r2, page;
 263
 264         split_addr((u32) reg, &r1, &r2, &page);
 265
 266         mutex_lock(&bus->mdio_lock);
 267
 268         bus->write(bus, 0x18, 0, page);
 269         wait_for_page_switch();
 270         ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
 271
 272         mutex_unlock(&bus->mdio_lock);
 273 }
 274
 275 u32
 276 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 277 {
 278         struct mii_bus *bus = priv->mii_bus;
 279         u16 r1, r2, page;
 280         u32 ret;
 281
 282         split_addr((u32) reg, &r1, &r2, &page);
 283
 284         mutex_lock(&bus->mdio_lock);
 285
 286         bus->write(bus, 0x18, 0, page);
 287         wait_for_page_switch();
 288
 289         ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 290         ret &= ~mask;
 291         ret |= val;
 292         ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
 293
 294         mutex_unlock(&bus->mdio_lock);
 295
 296         return ret;
 297 }
 298
 299 void
 300 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 301                      u16 dbg_addr, u16 dbg_data)
 302 {
 303         struct mii_bus *bus = priv->mii_bus;
 304
 305         mutex_lock(&bus->mdio_lock);
 306         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 307         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 308         mutex_unlock(&bus->mdio_lock);
 309 }
 310
 311 void
 312 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 313 {
 314         struct mii_bus *bus = priv->mii_bus;
 315
 316         mutex_lock(&bus->mdio_lock);
 317         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 318         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 319         mutex_unlock(&bus->mdio_lock);
 320 }
 321
 322 u16
 323 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr)
 324 {
 325         struct mii_bus *bus = priv->mii_bus;
 326         u16 data;
 327
 328         mutex_lock(&bus->mdio_lock);
 329         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 330         data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
 331         mutex_unlock(&bus->mdio_lock);
 332
 333         return data;
 334 }
 335
 336 static int
 337 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 338                 unsigned timeout)
 339 {
 340         int i;
 341
 342         for (i = 0; i < timeout; i++) {
 343                 u32 t;
 344
 345                 t = ar8xxx_read(priv, reg);
 346                 if ((t & mask) == val)
 347                         return 0;
 348
 349                 usleep_range(1000, 2000);
 350         }
 351
 352         return -ETIMEDOUT;
 353 }
 354
 355 static int
 356 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 357 {
 358         unsigned mib_func = priv->chip->mib_func;
 359         int ret;
 360
 361         lockdep_assert_held(&priv->mib_lock);
 362
 363         /* Capture the hardware statistics for all ports */
 364         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 365
 366         /* Wait for the capturing to complete. */
 367         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 368         if (ret)
 369                 goto out;
 370
 371         ret = 0;
 372
 373 out:
 374         return ret;
 375 }
 376
 377 static int
 378 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 379 {
 380         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 381 }
 382
 383 static int
 384 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 385 {
 386         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 387 }
 388
 389 static void
 390 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 391 {
 392         unsigned int base;
 393         u64 *mib_stats;
 394         int i;
 395
 396         WARN_ON(port >= priv->dev.ports);
 397
 398         lockdep_assert_held(&priv->mib_lock);
 399
 400         base = priv->chip->reg_port_stats_start +
 401                priv->chip->reg_port_stats_length * port;
 402
 403         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 404         for (i = 0; i < priv->chip->num_mibs; i++) {
 405                 const struct ar8xxx_mib_desc *mib;
 406                 u64 t;
 407
 408                 mib = &priv->chip->mib_decs[i];
 409                 t = ar8xxx_read(priv, base + mib->offset);
 410                 if (mib->size == 2) {
 411                         u64 hi;
 412
 413                         hi = ar8xxx_read(priv, base + mib->offset + 4);
 414                         t |= hi << 32;
 415                 }
 416
 417                 if (flush)
 418                         mib_stats[i] = 0;
 419                 else
 420                         mib_stats[i] += t;
 421         }
 422 }
 423
 424 static void
 425 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 426                       struct switch_port_link *link)
 427 {
 428         u32 status;
 429         u32 speed;
 430
 431         memset(link, '\0', sizeof(*link));
 432
 433         status = priv->chip->read_port_status(priv, port);
 434
 435         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 436         if (link->aneg) {
 437                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 438         } else {
 439                 link->link = true;
 440
 441                 if (priv->get_port_link) {
 442                         int err;
 443
 444                         err = priv->get_port_link(port);
 445                         if (err >= 0)
 446                                 link->link = !!err;
 447                 }
 448         }
 449
 450         if (!link->link)
 451                 return;
 452
 453         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 454         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 455         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 456
 457         if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
 458                 link->eee = priv->chip->read_port_eee_status(priv, port);
 459
 460         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 461                  AR8216_PORT_STATUS_SPEED_S;
 462
 463         switch (speed) {
 464         case AR8216_PORT_SPEED_10M:
 465                 link->speed = SWITCH_PORT_SPEED_10;
 466                 break;
 467         case AR8216_PORT_SPEED_100M:
 468                 link->speed = SWITCH_PORT_SPEED_100;
 469                 break;
 470         case AR8216_PORT_SPEED_1000M:
 471                 link->speed = SWITCH_PORT_SPEED_1000;
 472                 break;
 473         default:
 474                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 475                 break;
 476         }
 477 }
 478
 479 static struct sk_buff *
 480 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 481 {
 482         struct ar8xxx_priv *priv = dev->phy_ptr;
 483         unsigned char *buf;
 484
 485         if (unlikely(!priv))
 486                 goto error;
 487
 488         if (!priv->vlan)
 489                 goto send;
 490
 491         if (unlikely(skb_headroom(skb) < 2)) {
 492                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 493                         goto error;
 494         }
 495
 496         buf = skb_push(skb, 2);
 497         buf[0] = 0x10;
 498         buf[1] = 0x80;
 499
 500 send:
 501         return skb;
 502
 503 error:
 504         dev_kfree_skb_any(skb);
 505         return NULL;
 506 }
 507
 508 static void
 509 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 510 {
 511         struct ar8xxx_priv *priv;
 512         unsigned char *buf;
 513         int port, vlan;
 514
 515         priv = dev->phy_ptr;
 516         if (!priv)
 517                 return;
 518
 519         /* don't strip the header if vlan mode is disabled */
 520         if (!priv->vlan)
 521                 return;
 522
 523         /* strip header, get vlan id */
 524         buf = skb->data;
 525         skb_pull(skb, 2);
 526
 527         /* check for vlan header presence */
 528         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 529                 return;
 530
 531         port = buf[0] & 0xf;
 532
 533         /* no need to fix up packets coming from a tagged source */
 534         if (priv->vlan_tagged & (1 << port))
 535                 return;
 536
 537         /* lookup port vid from local table, the switch passes an invalid vlan id */
 538         vlan = priv->vlan_id[priv->pvid[port]];
 539
 540         buf[14 + 2] &= 0xf0;
 541         buf[14 + 2] |= vlan >> 8;
 542         buf[15 + 2] = vlan & 0xff;
 543 }
 544
 545 int
 546 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 547 {
 548         int timeout = 20;
 549         u32 t = 0;
 550
 551         while (1) {
 552                 t = ar8xxx_read(priv, reg);
 553                 if ((t & mask) == val)
 554                         return 0;
 555
 556                 if (timeout-- <= 0)
 557                         break;
 558
 559                 udelay(10);
 560         }
 561
 562         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 563                (unsigned int) reg, t, mask, val);
 564         return -ETIMEDOUT;
 565 }
 566
 567 static void
 568 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 569 {
 570         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 571                 return;
 572         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 573                 val &= AR8216_VTUDATA_MEMBER;
 574                 val |= AR8216_VTUDATA_VALID;
 575                 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
 576         }
 577         op |= AR8216_VTU_ACTIVE;
 578         ar8xxx_write(priv, AR8216_REG_VTU, op);
 579 }
 580
 581 static void
 582 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 583 {
 584         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 585 }
 586
 587 static void
 588 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 589 {
 590         u32 op;
 591
 592         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 593         ar8216_vtu_op(priv, op, port_mask);
 594 }
 595
 596 static int
 597 ar8216_atu_flush(struct ar8xxx_priv *priv)
 598 {
 599         int ret;
 600
 601         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 602         if (!ret)
 603                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
 604                                                          AR8216_ATU_ACTIVE);
 605
 606         return ret;
 607 }
 608
 609 static int
 610 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
 611 {
 612         u32 t;
 613         int ret;
 614
 615         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 616         if (!ret) {
 617                 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
 618                 t |= AR8216_ATU_ACTIVE;
 619                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
 620         }
 621
 622         return ret;
 623 }
 624
 625 static u32
 626 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 627 {
 628         return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
 629 }
 630
 631 static void
 632 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 633 {
 634         u32 header;
 635         u32 egress, ingress;
 636         u32 pvid;
 637
 638         if (priv->vlan) {
 639                 pvid = priv->vlan_id[priv->pvid[port]];
 640                 if (priv->vlan_tagged & (1 << port))
 641                         egress = AR8216_OUT_ADD_VLAN;
 642                 else
 643                         egress = AR8216_OUT_STRIP_VLAN;
 644                 ingress = AR8216_IN_SECURE;
 645         } else {
 646                 pvid = port;
 647                 egress = AR8216_OUT_KEEP;
 648                 ingress = AR8216_IN_PORT_ONLY;
 649         }
 650
 651         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 652                 header = AR8216_PORT_CTRL_HEADER;
 653         else
 654                 header = 0;
 655
 656         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 657                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 658                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 659                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 660                    AR8216_PORT_CTRL_LEARN | header |
 661                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 662                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 663
 664         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 665                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 666                    AR8216_PORT_VLAN_DEFAULT_ID,
 667                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 668                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 669                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 670 }
 671
 672 static int
 673 ar8216_hw_init(struct ar8xxx_priv *priv)
 674 {
 675         if (priv->initialized)
 676                 return 0;
 677
 678         ar8xxx_phy_init(priv);
 679
 680         priv->initialized = true;
 681         return 0;
 682 }
 683
 684 static void
 685 ar8216_init_globals(struct ar8xxx_priv *priv)
 686 {
 687         /* standard atheros magic */
 688         ar8xxx_write(priv, 0x38, 0xc000050e);
 689
 690         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 691                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 692 }
 693
 694 static void
 695 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 696 {
 697         /* Enable port learning and tx */
 698         ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
 699                 AR8216_PORT_CTRL_LEARN |
 700                 (4 << AR8216_PORT_CTRL_STATE_S));
 701
 702         ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
 703
 704         if (port == AR8216_PORT_CPU) {
 705                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 706                         AR8216_PORT_STATUS_LINK_UP |
 707                         (ar8xxx_has_gige(priv) ?
 708                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 709                         AR8216_PORT_STATUS_TXMAC |
 710                         AR8216_PORT_STATUS_RXMAC |
 711                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 712                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 713                         AR8216_PORT_STATUS_DUPLEX);
 714         } else {
 715                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 716                         AR8216_PORT_STATUS_LINK_AUTO);
 717         }
 718 }
 719
 720 static void
 721 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
 722 {
 723         int timeout = 20;
 724
 725         while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
 726                 udelay(10);
 727
 728         if (!timeout)
 729                 pr_err("ar8216: timeout waiting for atu to become ready\n");
 730 }
 731
 732 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
 733                                  struct arl_entry *a, u32 *status, enum arl_op op)
 734 {
 735         struct mii_bus *bus = priv->mii_bus;
 736         u16 r2, page;
 737         u16 r1_func0, r1_func1, r1_func2;
 738         u32 t, val0, val1, val2;
 739         int i;
 740
 741         split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
 742         r2 |= 0x10;
 743
 744         r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
 745         r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
 746
 747         switch (op) {
 748         case AR8XXX_ARL_INITIALIZE:
 749                 /* all ATU registers are on the same page
 750                 * therefore set page only once
 751                 */
 752                 bus->write(bus, 0x18, 0, page);
 753                 wait_for_page_switch();
 754
 755                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 756
 757                 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
 758                 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
 759                 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
 760                 break;
 761         case AR8XXX_ARL_GET_NEXT:
 762                 t = ar8xxx_mii_read32(priv, r2, r1_func0);
 763                 t |= AR8216_ATU_ACTIVE;
 764                 ar8xxx_mii_write32(priv, r2, r1_func0, t);
 765                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 766
 767                 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
 768                 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
 769                 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
 770
 771                 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
 772                 if (!*status)
 773                         break;
 774
 775                 i = 0;
 776                 t = AR8216_ATU_PORT0;
 777                 while (!(val2 & t) && ++i < priv->dev.ports)
 778                         t <<= 1;
 779
 780                 a->port = i;
 781                 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
 782                 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
 783                 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
 784                 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
 785                 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
 786                 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
 787                 break;
 788         }
 789 }
 790
 791 static void
 792 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 793 {
 794         u32 egress, ingress;
 795         u32 pvid;
 796
 797         if (priv->vlan) {
 798                 pvid = priv->vlan_id[priv->pvid[port]];
 799                 if (priv->vlan_tagged & (1 << port))
 800                         egress = AR8216_OUT_ADD_VLAN;
 801                 else
 802                         egress = AR8216_OUT_STRIP_VLAN;
 803                 ingress = AR8216_IN_SECURE;
 804         } else {
 805                 pvid = port;
 806                 egress = AR8216_OUT_KEEP;
 807                 ingress = AR8216_IN_PORT_ONLY;
 808         }
 809
 810         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 811                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 812                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 813                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 814                    AR8216_PORT_CTRL_LEARN |
 815                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 816                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 817
 818         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 819                    AR8236_PORT_VLAN_DEFAULT_ID,
 820                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 821
 822         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 823                    AR8236_PORT_VLAN2_VLAN_MODE |
 824                    AR8236_PORT_VLAN2_MEMBER,
 825                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 826                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 827 }
 828
 829 static void
 830 ar8236_init_globals(struct ar8xxx_priv *priv)
 831 {
 832         /* enable jumbo frames */
 833         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 834                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 835
 836         /* enable cpu port to receive arp frames */
 837         ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
 838                    AR8236_ATU_CTRL_RES);
 839
 840         /* enable cpu port to receive multicast and broadcast frames */
 841         ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
 842                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 843
 844         /* Enable MIB counters */
 845         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 846                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 847                    AR8236_MIB_EN);
 848 }
 849
 850 static int
 851 ar8316_hw_init(struct ar8xxx_priv *priv)
 852 {
 853         u32 val, newval;
 854
 855         val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
 856
 857         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 858                 if (priv->port4_phy) {
 859                         /* value taken from Ubiquiti RouterStation Pro */
 860                         newval = 0x81461bea;
 861                         pr_info("ar8316: Using port 4 as PHY\n");
 862                 } else {
 863                         newval = 0x01261be2;
 864                         pr_info("ar8316: Using port 4 as switch port\n");
 865                 }
 866         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 867                 /* value taken from AVM Fritz!Box 7390 sources */
 868                 newval = 0x010e5b71;
 869         } else {
 870                 /* no known value for phy interface */
 871                 pr_err("ar8316: unsupported mii mode: %d.\n",
 872                        priv->phy->interface);
 873                 return -EINVAL;
 874         }
 875
 876         if (val == newval)
 877                 goto out;
 878
 879         ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
 880
 881         if (priv->port4_phy &&
 882             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 883                 /* work around for phy4 rgmii mode */
 884                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 885                 /* rx delay */
 886                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 887                 /* tx delay */
 888                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 889                 msleep(1000);
 890         }
 891
 892         ar8xxx_phy_init(priv);
 893
 894 out:
 895         priv->initialized = true;
 896         return 0;
 897 }
 898
 899 static void
 900 ar8316_init_globals(struct ar8xxx_priv *priv)
 901 {
 902         /* standard atheros magic */
 903         ar8xxx_write(priv, 0x38, 0xc000050e);
 904
 905         /* enable cpu port to receive multicast and broadcast frames */
 906         ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 907
 908         /* enable jumbo frames */
 909         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 910                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 911
 912         /* Enable MIB counters */
 913         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 914                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 915                    AR8236_MIB_EN);
 916 }
 917
 918 int
 919 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 920                    struct switch_val *val)
 921 {
 922         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 923         priv->vlan = !!val->value.i;
 924         return 0;
 925 }
 926
 927 int
 928 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 929                    struct switch_val *val)
 930 {
 931         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 932         val->value.i = priv->vlan;
 933         return 0;
 934 }
 935
 936
 937 int
 938 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
 939 {
 940         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 941
 942         /* make sure no invalid PVIDs get set */
 943
 944         if (vlan >= dev->vlans)
 945                 return -EINVAL;
 946
 947         priv->pvid[port] = vlan;
 948         return 0;
 949 }
 950
 951 int
 952 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
 953 {
 954         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 955         *vlan = priv->pvid[port];
 956         return 0;
 957 }
 958
 959 static int
 960 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
 961                   struct switch_val *val)
 962 {
 963         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 964         priv->vlan_id[val->port_vlan] = val->value.i;
 965         return 0;
 966 }
 967
 968 static int
 969 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
 970                   struct switch_val *val)
 971 {
 972         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 973         val->value.i = priv->vlan_id[val->port_vlan];
 974         return 0;
 975 }
 976
 977 int
 978 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
 979                         struct switch_port_link *link)
 980 {
 981         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 982
 983         ar8216_read_port_link(priv, port, link);
 984         return 0;
 985 }
 986
 987 static int
 988 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
 989 {
 990         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 991         u8 ports = priv->vlan_table[val->port_vlan];
 992         int i;
 993
 994         val->len = 0;
 995         for (i = 0; i < dev->ports; i++) {
 996                 struct switch_port *p;
 997
 998                 if (!(ports & (1 << i)))
 999                         continue;
1000
1001                 p = &val->value.ports[val->len++];
1002                 p->id = i;
1003                 if (priv->vlan_tagged & (1 << i))
1004                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1005                 else
1006                         p->flags = 0;
1007         }
1008         return 0;
1009 }
1010
1011 static int
1012 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1013 {
1014         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1015         u8 *vt = &priv->vlan_table[val->port_vlan];
1016         int i, j;
1017
1018         *vt = 0;
1019         for (i = 0; i < val->len; i++) {
1020                 struct switch_port *p = &val->value.ports[i];
1021
1022                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1023                         priv->vlan_tagged |= (1 << p->id);
1024                 } else {
1025                         priv->vlan_tagged &= ~(1 << p->id);
1026                         priv->pvid[p->id] = val->port_vlan;
1027
1028                         /* make sure that an untagged port does not
1029                          * appear in other vlans */
1030                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1031                                 if (j == val->port_vlan)
1032                                         continue;
1033                                 priv->vlan_table[j] &= ~(1 << p->id);
1034                         }
1035                 }
1036
1037                 *vt |= 1 << p->id;
1038         }
1039         return 0;
1040 }
1041
1042 static void
1043 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1044 {
1045         int port;
1046
1047         /* reset all mirror registers */
1048         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1049                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1050                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1051         for (port = 0; port < AR8216_NUM_PORTS; port++) {
1052                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1053                            AR8216_PORT_CTRL_MIRROR_RX);
1054
1055                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1056                            AR8216_PORT_CTRL_MIRROR_TX);
1057         }
1058
1059         /* now enable mirroring if necessary */
1060         if (priv->source_port >= AR8216_NUM_PORTS ||
1061             priv->monitor_port >= AR8216_NUM_PORTS ||
1062             priv->source_port == priv->monitor_port) {
1063                 return;
1064         }
1065
1066         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1067                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1068                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1069
1070         if (priv->mirror_rx)
1071                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1072                            AR8216_PORT_CTRL_MIRROR_RX);
1073
1074         if (priv->mirror_tx)
1075                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1076                            AR8216_PORT_CTRL_MIRROR_TX);
1077 }
1078
1079 int
1080 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1081 {
1082         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1083         u8 portmask[AR8X16_MAX_PORTS];
1084         int i, j;
1085
1086         mutex_lock(&priv->reg_mutex);
1087         /* flush all vlan translation unit entries */
1088         priv->chip->vtu_flush(priv);
1089
1090         memset(portmask, 0, sizeof(portmask));
1091         if (!priv->init) {
1092                 /* calculate the port destination masks and load vlans
1093                  * into the vlan translation unit */
1094                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1095                         u8 vp = priv->vlan_table[j];
1096
1097                         if (!vp)
1098                                 continue;
1099
1100                         for (i = 0; i < dev->ports; i++) {
1101                                 u8 mask = (1 << i);
1102                                 if (vp & mask)
1103                                         portmask[i] |= vp & ~mask;
1104                         }
1105
1106                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1107                                                  priv->vlan_table[j]);
1108                 }
1109         } else {
1110                 /* vlan disabled:
1111                  * isolate all ports, but connect them to the cpu port */
1112                 for (i = 0; i < dev->ports; i++) {
1113                         if (i == AR8216_PORT_CPU)
1114                                 continue;
1115
1116                         portmask[i] = 1 << AR8216_PORT_CPU;
1117                         portmask[AR8216_PORT_CPU] |= (1 << i);
1118                 }
1119         }
1120
1121         /* update the port destination mask registers and tag settings */
1122         for (i = 0; i < dev->ports; i++) {
1123                 priv->chip->setup_port(priv, i, portmask[i]);
1124         }
1125
1126         priv->chip->set_mirror_regs(priv);
1127
1128         mutex_unlock(&priv->reg_mutex);
1129         return 0;
1130 }
1131
1132 int
1133 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1134 {
1135         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1136         const struct ar8xxx_chip *chip = priv->chip;
1137         int i;
1138
1139         mutex_lock(&priv->reg_mutex);
1140         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1141                 offsetof(struct ar8xxx_priv, vlan));
1142
1143         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1144                 priv->vlan_id[i] = i;
1145
1146         /* Configure all ports */
1147         for (i = 0; i < dev->ports; i++)
1148                 chip->init_port(priv, i);
1149
1150         priv->mirror_rx = false;
1151         priv->mirror_tx = false;
1152         priv->source_port = 0;
1153         priv->monitor_port = 0;
1154
1155         chip->init_globals(priv);
1156
1157         mutex_unlock(&priv->reg_mutex);
1158
1159         return chip->sw_hw_apply(dev);
1160 }
1161
1162 int
1163 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1164                          const struct switch_attr *attr,
1165                          struct switch_val *val)
1166 {
1167         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1168         unsigned int len;
1169         int ret;
1170
1171         if (!ar8xxx_has_mib_counters(priv))
1172                 return -EOPNOTSUPP;
1173
1174         mutex_lock(&priv->mib_lock);
1175
1176         len = priv->dev.ports * priv->chip->num_mibs *
1177               sizeof(*priv->mib_stats);
1178         memset(priv->mib_stats, '\0', len);
1179         ret = ar8xxx_mib_flush(priv);
1180         if (ret)
1181                 goto unlock;
1182
1183         ret = 0;
1184
1185 unlock:
1186         mutex_unlock(&priv->mib_lock);
1187         return ret;
1188 }
1189
1190 int
1191 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1192                                const struct switch_attr *attr,
1193                                struct switch_val *val)
1194 {
1195         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1196
1197         mutex_lock(&priv->reg_mutex);
1198         priv->mirror_rx = !!val->value.i;
1199         priv->chip->set_mirror_regs(priv);
1200         mutex_unlock(&priv->reg_mutex);
1201
1202         return 0;
1203 }
1204
1205 int
1206 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1207                                const struct switch_attr *attr,
1208                                struct switch_val *val)
1209 {
1210         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1211         val->value.i = priv->mirror_rx;
1212         return 0;
1213 }
1214
1215 int
1216 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1217                                const struct switch_attr *attr,
1218                                struct switch_val *val)
1219 {
1220         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1221
1222         mutex_lock(&priv->reg_mutex);
1223         priv->mirror_tx = !!val->value.i;
1224         priv->chip->set_mirror_regs(priv);
1225         mutex_unlock(&priv->reg_mutex);
1226
1227         return 0;
1228 }
1229
1230 int
1231 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1232                                const struct switch_attr *attr,
1233                                struct switch_val *val)
1234 {
1235         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1236         val->value.i = priv->mirror_tx;
1237         return 0;
1238 }
1239
1240 int
1241 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1242                                   const struct switch_attr *attr,
1243                                   struct switch_val *val)
1244 {
1245         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1246
1247         mutex_lock(&priv->reg_mutex);
1248         priv->monitor_port = val->value.i;
1249         priv->chip->set_mirror_regs(priv);
1250         mutex_unlock(&priv->reg_mutex);
1251
1252         return 0;
1253 }
1254
1255 int
1256 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1257                                   const struct switch_attr *attr,
1258                                   struct switch_val *val)
1259 {
1260         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1261         val->value.i = priv->monitor_port;
1262         return 0;
1263 }
1264
1265 int
1266 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1267                                  const struct switch_attr *attr,
1268                                  struct switch_val *val)
1269 {
1270         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1271
1272         mutex_lock(&priv->reg_mutex);
1273         priv->source_port = val->value.i;
1274         priv->chip->set_mirror_regs(priv);
1275         mutex_unlock(&priv->reg_mutex);
1276
1277         return 0;
1278 }
1279
1280 int
1281 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1282                                  const struct switch_attr *attr,
1283                                  struct switch_val *val)
1284 {
1285         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1286         val->value.i = priv->source_port;
1287         return 0;
1288 }
1289
1290 int
1291 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1292                              const struct switch_attr *attr,
1293                              struct switch_val *val)
1294 {
1295         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1296         int port;
1297         int ret;
1298
1299         if (!ar8xxx_has_mib_counters(priv))
1300                 return -EOPNOTSUPP;
1301
1302         port = val->port_vlan;
1303         if (port >= dev->ports)
1304                 return -EINVAL;
1305
1306         mutex_lock(&priv->mib_lock);
1307         ret = ar8xxx_mib_capture(priv);
1308         if (ret)
1309                 goto unlock;
1310
1311         ar8xxx_mib_fetch_port_stat(priv, port, true);
1312
1313         ret = 0;
1314
1315 unlock:
1316         mutex_unlock(&priv->mib_lock);
1317         return ret;
1318 }
1319
1320 int
1321 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1322                        const struct switch_attr *attr,
1323                        struct switch_val *val)
1324 {
1325         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1326         const struct ar8xxx_chip *chip = priv->chip;
1327         u64 *mib_stats;
1328         int port;
1329         int ret;
1330         char *buf = priv->buf;
1331         int i, len = 0;
1332         bool mib_stats_empty = true;
1333
1334         if (!ar8xxx_has_mib_counters(priv))
1335                 return -EOPNOTSUPP;
1336
1337         port = val->port_vlan;
1338         if (port >= dev->ports)
1339                 return -EINVAL;
1340
1341         mutex_lock(&priv->mib_lock);
1342         ret = ar8xxx_mib_capture(priv);
1343         if (ret)
1344                 goto unlock;
1345
1346         ar8xxx_mib_fetch_port_stat(priv, port, false);
1347
1348         len += snprintf(buf + len, sizeof(priv->buf) - len,
1349                         "Port %d MIB counters\n",
1350                         port);
1351
1352         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1353         for (i = 0; i < chip->num_mibs; i++) {
1354                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1355                                 "%-12s: %llu\n",
1356                                 chip->mib_decs[i].name,
1357                                 mib_stats[i]);
1358                 if (mib_stats_empty && mib_stats[i])
1359                         mib_stats_empty = false;
1360         }
1361
1362         if (mib_stats_empty)
1363                 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1364
1365         val->value.s = buf;
1366         val->len = len;
1367
1368         ret = 0;
1369
1370 unlock:
1371         mutex_unlock(&priv->mib_lock);
1372         return ret;
1373 }
1374
1375 int
1376 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1377                         const struct switch_attr *attr,
1378                         struct switch_val *val)
1379 {
1380         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1381         struct mii_bus *bus = priv->mii_bus;
1382         const struct ar8xxx_chip *chip = priv->chip;
1383         char *buf = priv->arl_buf;
1384         int i, j, k, len = 0;
1385         struct arl_entry *a, *a1;
1386         u32 status;
1387
1388         if (!chip->get_arl_entry)
1389                 return -EOPNOTSUPP;
1390
1391         mutex_lock(&priv->reg_mutex);
1392         mutex_lock(&bus->mdio_lock);
1393
1394         chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1395
1396         for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1397                 a = &priv->arl_table[i];
1398                 duplicate:
1399                 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1400
1401                 if (!status)
1402                         break;
1403
1404                 /* avoid duplicates
1405                  * ARL table can include multiple valid entries
1406                  * per MAC, just with differing status codes
1407                  */
1408                 for (j = 0; j < i; ++j) {
1409                         a1 = &priv->arl_table[j];
1410                         if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
1411                                 goto duplicate;
1412                 }
1413         }
1414
1415         mutex_unlock(&bus->mdio_lock);
1416
1417         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1418                         "address resolution table\n");
1419
1420         if (i == AR8XXX_NUM_ARL_RECORDS)
1421                 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1422                                 "Too many entries found, displaying the first %d only!\n",
1423                                 AR8XXX_NUM_ARL_RECORDS);
1424
1425         for (j = 0; j < priv->dev.ports; ++j) {
1426                 for (k = 0; k < i; ++k) {
1427                         a = &priv->arl_table[k];
1428                         if (a->port != j)
1429                                 continue;
1430                         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1431                                         "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1432                                         j,
1433                                         a->mac[5], a->mac[4], a->mac[3],
1434                                         a->mac[2], a->mac[1], a->mac[0]);
1435                 }
1436         }
1437
1438         val->value.s = buf;
1439         val->len = len;
1440
1441         mutex_unlock(&priv->reg_mutex);
1442
1443         return 0;
1444 }
1445
1446 int
1447 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1448                               const struct switch_attr *attr,
1449                               struct switch_val *val)
1450 {
1451         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1452         int ret;
1453
1454         mutex_lock(&priv->reg_mutex);
1455         ret = priv->chip->atu_flush(priv);
1456         mutex_unlock(&priv->reg_mutex);
1457
1458         return ret;
1459 }
1460
1461 int
1462 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1463                                    const struct switch_attr *attr,
1464                                    struct switch_val *val)
1465 {
1466         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1467         int port, ret;
1468
1469         port = val->port_vlan;
1470         if (port >= dev->ports)
1471                 return -EINVAL;
1472
1473         mutex_lock(&priv->reg_mutex);
1474         ret = priv->chip->atu_flush_port(priv, port);
1475         mutex_unlock(&priv->reg_mutex);
1476
1477         return ret;
1478 }
1479
1480 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1481         {
1482                 .type = SWITCH_TYPE_INT,
1483                 .name = "enable_vlan",
1484                 .description = "Enable VLAN mode",
1485                 .set = ar8xxx_sw_set_vlan,
1486                 .get = ar8xxx_sw_get_vlan,
1487                 .max = 1
1488         },
1489         {
1490                 .type = SWITCH_TYPE_NOVAL,
1491                 .name = "reset_mibs",
1492                 .description = "Reset all MIB counters",
1493                 .set = ar8xxx_sw_set_reset_mibs,
1494         },
1495         {
1496                 .type = SWITCH_TYPE_INT,
1497                 .name = "enable_mirror_rx",
1498                 .description = "Enable mirroring of RX packets",
1499                 .set = ar8xxx_sw_set_mirror_rx_enable,
1500                 .get = ar8xxx_sw_get_mirror_rx_enable,
1501                 .max = 1
1502         },
1503         {
1504                 .type = SWITCH_TYPE_INT,
1505                 .name = "enable_mirror_tx",
1506                 .description = "Enable mirroring of TX packets",
1507                 .set = ar8xxx_sw_set_mirror_tx_enable,
1508                 .get = ar8xxx_sw_get_mirror_tx_enable,
1509                 .max = 1
1510         },
1511         {
1512                 .type = SWITCH_TYPE_INT,
1513                 .name = "mirror_monitor_port",
1514                 .description = "Mirror monitor port",
1515                 .set = ar8xxx_sw_set_mirror_monitor_port,
1516                 .get = ar8xxx_sw_get_mirror_monitor_port,
1517                 .max = AR8216_NUM_PORTS - 1
1518         },
1519         {
1520                 .type = SWITCH_TYPE_INT,
1521                 .name = "mirror_source_port",
1522                 .description = "Mirror source port",
1523                 .set = ar8xxx_sw_set_mirror_source_port,
1524                 .get = ar8xxx_sw_get_mirror_source_port,
1525                 .max = AR8216_NUM_PORTS - 1
1526         },
1527         {
1528                 .type = SWITCH_TYPE_STRING,
1529                 .name = "arl_table",
1530                 .description = "Get ARL table",
1531                 .set = NULL,
1532                 .get = ar8xxx_sw_get_arl_table,
1533         },
1534         {
1535                 .type = SWITCH_TYPE_NOVAL,
1536                 .name = "flush_arl_table",
1537                 .description = "Flush ARL table",
1538                 .set = ar8xxx_sw_set_flush_arl_table,
1539         },
1540 };
1541
1542 const struct switch_attr ar8xxx_sw_attr_port[] = {
1543         {
1544                 .type = SWITCH_TYPE_NOVAL,
1545                 .name = "reset_mib",
1546                 .description = "Reset single port MIB counters",
1547                 .set = ar8xxx_sw_set_port_reset_mib,
1548         },
1549         {
1550                 .type = SWITCH_TYPE_STRING,
1551                 .name = "mib",
1552                 .description = "Get port's MIB counters",
1553                 .set = NULL,
1554                 .get = ar8xxx_sw_get_port_mib,
1555         },
1556         {
1557                 .type = SWITCH_TYPE_NOVAL,
1558                 .name = "flush_arl_table",
1559                 .description = "Flush port's ARL table entries",
1560                 .set = ar8xxx_sw_set_flush_port_arl_table,
1561         },
1562 };
1563
1564 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1565         {
1566                 .type = SWITCH_TYPE_INT,
1567                 .name = "vid",
1568                 .description = "VLAN ID (0-4094)",
1569                 .set = ar8xxx_sw_set_vid,
1570                 .get = ar8xxx_sw_get_vid,
1571                 .max = 4094,
1572         },
1573 };
1574
1575 static const struct switch_dev_ops ar8xxx_sw_ops = {
1576         .attr_global = {
1577                 .attr = ar8xxx_sw_attr_globals,
1578                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1579         },
1580         .attr_port = {
1581                 .attr = ar8xxx_sw_attr_port,
1582                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1583         },
1584         .attr_vlan = {
1585                 .attr = ar8xxx_sw_attr_vlan,
1586                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1587         },
1588         .get_port_pvid = ar8xxx_sw_get_pvid,
1589         .set_port_pvid = ar8xxx_sw_set_pvid,
1590         .get_vlan_ports = ar8xxx_sw_get_ports,
1591         .set_vlan_ports = ar8xxx_sw_set_ports,
1592         .apply_config = ar8xxx_sw_hw_apply,
1593         .reset_switch = ar8xxx_sw_reset_switch,
1594         .get_port_link = ar8xxx_sw_get_port_link,
1595 };
1596
1597 static const struct ar8xxx_chip ar8216_chip = {
1598         .caps = AR8XXX_CAP_MIB_COUNTERS,
1599
1600         .reg_port_stats_start = 0x19000,
1601         .reg_port_stats_length = 0xa0,
1602
1603         .name = "Atheros AR8216",
1604         .ports = AR8216_NUM_PORTS,
1605         .vlans = AR8216_NUM_VLANS,
1606         .swops = &ar8xxx_sw_ops,
1607
1608         .hw_init = ar8216_hw_init,
1609         .init_globals = ar8216_init_globals,
1610         .init_port = ar8216_init_port,
1611         .setup_port = ar8216_setup_port,
1612         .read_port_status = ar8216_read_port_status,
1613         .atu_flush = ar8216_atu_flush,
1614         .atu_flush_port = ar8216_atu_flush_port,
1615         .vtu_flush = ar8216_vtu_flush,
1616         .vtu_load_vlan = ar8216_vtu_load_vlan,
1617         .set_mirror_regs = ar8216_set_mirror_regs,
1618         .get_arl_entry = ar8216_get_arl_entry,
1619         .sw_hw_apply = ar8xxx_sw_hw_apply,
1620
1621         .num_mibs = ARRAY_SIZE(ar8216_mibs),
1622         .mib_decs = ar8216_mibs,
1623         .mib_func = AR8216_REG_MIB_FUNC
1624 };
1625
1626 static const struct ar8xxx_chip ar8236_chip = {
1627         .caps = AR8XXX_CAP_MIB_COUNTERS,
1628
1629         .reg_port_stats_start = 0x20000,
1630         .reg_port_stats_length = 0x100,
1631
1632         .name = "Atheros AR8236",
1633         .ports = AR8216_NUM_PORTS,
1634         .vlans = AR8216_NUM_VLANS,
1635         .swops = &ar8xxx_sw_ops,
1636
1637         .hw_init = ar8216_hw_init,
1638         .init_globals = ar8236_init_globals,
1639         .init_port = ar8216_init_port,
1640         .setup_port = ar8236_setup_port,
1641         .read_port_status = ar8216_read_port_status,
1642         .atu_flush = ar8216_atu_flush,
1643         .atu_flush_port = ar8216_atu_flush_port,
1644         .vtu_flush = ar8216_vtu_flush,
1645         .vtu_load_vlan = ar8216_vtu_load_vlan,
1646         .set_mirror_regs = ar8216_set_mirror_regs,
1647         .get_arl_entry = ar8216_get_arl_entry,
1648         .sw_hw_apply = ar8xxx_sw_hw_apply,
1649
1650         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1651         .mib_decs = ar8236_mibs,
1652         .mib_func = AR8216_REG_MIB_FUNC
1653 };
1654
1655 static const struct ar8xxx_chip ar8316_chip = {
1656         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1657
1658         .reg_port_stats_start = 0x20000,
1659         .reg_port_stats_length = 0x100,
1660
1661         .name = "Atheros AR8316",
1662         .ports = AR8216_NUM_PORTS,
1663         .vlans = AR8X16_MAX_VLANS,
1664         .swops = &ar8xxx_sw_ops,
1665
1666         .hw_init = ar8316_hw_init,
1667         .init_globals = ar8316_init_globals,
1668         .init_port = ar8216_init_port,
1669         .setup_port = ar8216_setup_port,
1670         .read_port_status = ar8216_read_port_status,
1671         .atu_flush = ar8216_atu_flush,
1672         .atu_flush_port = ar8216_atu_flush_port,
1673         .vtu_flush = ar8216_vtu_flush,
1674         .vtu_load_vlan = ar8216_vtu_load_vlan,
1675         .set_mirror_regs = ar8216_set_mirror_regs,
1676         .get_arl_entry = ar8216_get_arl_entry,
1677         .sw_hw_apply = ar8xxx_sw_hw_apply,
1678
1679         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1680         .mib_decs = ar8236_mibs,
1681         .mib_func = AR8216_REG_MIB_FUNC
1682 };
1683
1684 static int
1685 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1686 {
1687         u32 val;
1688         u16 id;
1689         int i;
1690
1691         val = ar8xxx_read(priv, AR8216_REG_CTRL);
1692         if (val == ~0)
1693                 return -ENODEV;
1694
1695         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1696         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1697                 u16 t;
1698
1699                 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1700                 if (val == ~0)
1701                         return -ENODEV;
1702
1703                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1704                 if (t != id)
1705                         return -ENODEV;
1706         }
1707
1708         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1709         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1710
1711         switch (priv->chip_ver) {
1712         case AR8XXX_VER_AR8216:
1713                 priv->chip = &ar8216_chip;
1714                 break;
1715         case AR8XXX_VER_AR8236:
1716                 priv->chip = &ar8236_chip;
1717                 break;
1718         case AR8XXX_VER_AR8316:
1719                 priv->chip = &ar8316_chip;
1720                 break;
1721         case AR8XXX_VER_AR8327:
1722                 priv->chip = &ar8327_chip;
1723                 break;
1724         case AR8XXX_VER_AR8337:
1725                 priv->chip = &ar8337_chip;
1726                 break;
1727         default:
1728                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1729                        priv->chip_ver, priv->chip_rev);
1730
1731                 return -ENODEV;
1732         }
1733
1734         return 0;
1735 }
1736
1737 static void
1738 ar8xxx_mib_work_func(struct work_struct *work)
1739 {
1740         struct ar8xxx_priv *priv;
1741         int err;
1742
1743         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1744
1745         mutex_lock(&priv->mib_lock);
1746
1747         err = ar8xxx_mib_capture(priv);
1748         if (err)
1749                 goto next_port;
1750
1751         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1752
1753 next_port:
1754         priv->mib_next_port++;
1755         if (priv->mib_next_port >= priv->dev.ports)
1756                 priv->mib_next_port = 0;
1757
1758         mutex_unlock(&priv->mib_lock);
1759         schedule_delayed_work(&priv->mib_work,
1760                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1761 }
1762
1763 static int
1764 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1765 {
1766         unsigned int len;
1767
1768         if (!ar8xxx_has_mib_counters(priv))
1769                 return 0;
1770
1771         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1772
1773         len = priv->dev.ports * priv->chip->num_mibs *
1774               sizeof(*priv->mib_stats);
1775         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1776
1777         if (!priv->mib_stats)
1778                 return -ENOMEM;
1779
1780         return 0;
1781 }
1782
1783 static void
1784 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1785 {
1786         if (!ar8xxx_has_mib_counters(priv))
1787                 return;
1788
1789         schedule_delayed_work(&priv->mib_work,
1790                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1791 }
1792
1793 static void
1794 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1795 {
1796         if (!ar8xxx_has_mib_counters(priv))
1797                 return;
1798
1799         cancel_delayed_work(&priv->mib_work);
1800 }
1801
1802 static struct ar8xxx_priv *
1803 ar8xxx_create(void)
1804 {
1805         struct ar8xxx_priv *priv;
1806
1807         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1808         if (priv == NULL)
1809                 return NULL;
1810
1811         mutex_init(&priv->reg_mutex);
1812         mutex_init(&priv->mib_lock);
1813         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1814
1815         return priv;
1816 }
1817
1818 static void
1819 ar8xxx_free(struct ar8xxx_priv *priv)
1820 {
1821         if (priv->chip && priv->chip->cleanup)
1822                 priv->chip->cleanup(priv);
1823
1824         kfree(priv->chip_data);
1825         kfree(priv->mib_stats);
1826         kfree(priv);
1827 }
1828
1829 static int
1830 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1831 {
1832         const struct ar8xxx_chip *chip;
1833         struct switch_dev *swdev;
1834         int ret;
1835
1836         ret = ar8xxx_id_chip(priv);
1837         if (ret)
1838                 return ret;
1839
1840         chip = priv->chip;
1841
1842         swdev = &priv->dev;
1843         swdev->cpu_port = AR8216_PORT_CPU;
1844         swdev->name = chip->name;
1845         swdev->vlans = chip->vlans;
1846         swdev->ports = chip->ports;
1847         swdev->ops = chip->swops;
1848
1849         ret = ar8xxx_mib_init(priv);
1850         if (ret)
1851                 return ret;
1852
1853         return 0;
1854 }
1855
1856 static int
1857 ar8xxx_start(struct ar8xxx_priv *priv)
1858 {
1859         int ret;
1860
1861         priv->init = true;
1862
1863         ret = priv->chip->hw_init(priv);
1864         if (ret)
1865                 return ret;
1866
1867         ret = ar8xxx_sw_reset_switch(&priv->dev);
1868         if (ret)
1869                 return ret;
1870
1871         priv->init = false;
1872
1873         ar8xxx_mib_start(priv);
1874
1875         return 0;
1876 }
1877
1878 static int
1879 ar8xxx_phy_config_init(struct phy_device *phydev)
1880 {
1881         struct ar8xxx_priv *priv = phydev->priv;
1882         struct net_device *dev = phydev->attached_dev;
1883         int ret;
1884
1885         if (WARN_ON(!priv))
1886                 return -ENODEV;
1887
1888         if (priv->chip->config_at_probe)
1889                 return ar8xxx_phy_check_aneg(phydev);
1890
1891         priv->phy = phydev;
1892
1893         if (phydev->addr != 0) {
1894                 if (chip_is_ar8316(priv)) {
1895                         /* switch device has been initialized, reinit */
1896                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
1897                         priv->initialized = false;
1898                         priv->port4_phy = true;
1899                         ar8316_hw_init(priv);
1900                         return 0;
1901                 }
1902
1903                 return 0;
1904         }
1905
1906         ret = ar8xxx_start(priv);
1907         if (ret)
1908                 return ret;
1909
1910         /* VID fixup only needed on ar8216 */
1911         if (chip_is_ar8216(priv)) {
1912                 dev->phy_ptr = priv;
1913                 dev->priv_flags |= IFF_NO_IP_ALIGN;
1914                 dev->eth_mangle_rx = ar8216_mangle_rx;
1915                 dev->eth_mangle_tx = ar8216_mangle_tx;
1916         }
1917
1918         return 0;
1919 }
1920
1921 static bool
1922 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
1923 {
1924         bool link_new, changed = false;
1925         u32 status;
1926         int i;
1927
1928         mutex_lock(&priv->reg_mutex);
1929
1930         for (i = 0; i < priv->dev.ports; i++) {
1931                 status = priv->chip->read_port_status(priv, i);
1932                 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
1933                 if (link_new == priv->link_up[i])
1934                         continue;
1935
1936                 priv->link_up[i] = link_new;
1937                 changed = true;
1938                 /* flush ARL entries for this port if it went down*/
1939                 if (!link_new)
1940                         priv->chip->atu_flush_port(priv, i);
1941                 dev_info(&priv->phy->dev, "Port %d is %s\n",
1942                          i, link_new ? "up" : "down");
1943         }
1944
1945         mutex_unlock(&priv->reg_mutex);
1946
1947         return changed;
1948 }
1949
1950 static int
1951 ar8xxx_phy_read_status(struct phy_device *phydev)
1952 {
1953         struct ar8xxx_priv *priv = phydev->priv;
1954         struct switch_port_link link;
1955
1956         /* check for switch port link changes */
1957         if (phydev->state == PHY_CHANGELINK)
1958                 ar8xxx_check_link_states(priv);
1959
1960         if (phydev->addr != 0)
1961                 return genphy_read_status(phydev);
1962
1963         ar8216_read_port_link(priv, phydev->addr, &link);
1964         phydev->link = !!link.link;
1965         if (!phydev->link)
1966                 return 0;
1967
1968         switch (link.speed) {
1969         case SWITCH_PORT_SPEED_10:
1970                 phydev->speed = SPEED_10;
1971                 break;
1972         case SWITCH_PORT_SPEED_100:
1973                 phydev->speed = SPEED_100;
1974                 break;
1975         case SWITCH_PORT_SPEED_1000:
1976                 phydev->speed = SPEED_1000;
1977                 break;
1978         default:
1979                 phydev->speed = 0;
1980         }
1981         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1982
1983         phydev->state = PHY_RUNNING;
1984         netif_carrier_on(phydev->attached_dev);
1985         phydev->adjust_link(phydev->attached_dev);
1986
1987         return 0;
1988 }
1989
1990 static int
1991 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1992 {
1993         if (phydev->addr == 0)
1994                 return 0;
1995
1996         return genphy_config_aneg(phydev);
1997 }
1998
1999 static const u32 ar8xxx_phy_ids[] = {
2000         0x004dd033,
2001         0x004dd034, /* AR8327 */
2002         0x004dd036, /* AR8337 */
2003         0x004dd041,
2004         0x004dd042,
2005         0x004dd043, /* AR8236 */
2006 };
2007
2008 static bool
2009 ar8xxx_phy_match(u32 phy_id)
2010 {
2011         int i;
2012
2013         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2014                 if (phy_id == ar8xxx_phy_ids[i])
2015                         return true;
2016
2017         return false;
2018 }
2019
2020 static bool
2021 ar8xxx_is_possible(struct mii_bus *bus)
2022 {
2023         unsigned i;
2024
2025         for (i = 0; i < 4; i++) {
2026                 u32 phy_id;
2027
2028                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2029                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2030                 if (!ar8xxx_phy_match(phy_id)) {
2031                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2032                                  dev_name(&bus->dev), i, phy_id);
2033                         return false;
2034                 }
2035         }
2036
2037         return true;
2038 }
2039
2040 static int
2041 ar8xxx_phy_probe(struct phy_device *phydev)
2042 {
2043         struct ar8xxx_priv *priv;
2044         struct switch_dev *swdev;
2045         int ret;
2046
2047         /* skip PHYs at unused adresses */
2048         if (phydev->addr != 0 && phydev->addr != 4)
2049                 return -ENODEV;
2050
2051         if (!ar8xxx_is_possible(phydev->bus))
2052                 return -ENODEV;
2053
2054         mutex_lock(&ar8xxx_dev_list_lock);
2055         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2056                 if (priv->mii_bus == phydev->bus)
2057                         goto found;
2058
2059         priv = ar8xxx_create();
2060         if (priv == NULL) {
2061                 ret = -ENOMEM;
2062                 goto unlock;
2063         }
2064
2065         priv->mii_bus = phydev->bus;
2066
2067         ret = ar8xxx_probe_switch(priv);
2068         if (ret)
2069                 goto free_priv;
2070
2071         swdev = &priv->dev;
2072         swdev->alias = dev_name(&priv->mii_bus->dev);
2073         ret = register_switch(swdev, NULL);
2074         if (ret)
2075                 goto free_priv;
2076
2077         pr_info("%s: %s rev. %u switch registered on %s\n",
2078                 swdev->devname, swdev->name, priv->chip_rev,
2079                 dev_name(&priv->mii_bus->dev));
2080
2081 found:
2082         priv->use_count++;
2083
2084         if (phydev->addr == 0) {
2085                 if (ar8xxx_has_gige(priv)) {
2086                         phydev->supported = SUPPORTED_1000baseT_Full;
2087                         phydev->advertising = ADVERTISED_1000baseT_Full;
2088                 } else {
2089                         phydev->supported = SUPPORTED_100baseT_Full;
2090                         phydev->advertising = ADVERTISED_100baseT_Full;
2091                 }
2092
2093                 if (priv->chip->config_at_probe) {
2094                         priv->phy = phydev;
2095
2096                         ret = ar8xxx_start(priv);
2097                         if (ret)
2098                                 goto err_unregister_switch;
2099                 }
2100         } else {
2101                 if (ar8xxx_has_gige(priv)) {
2102                         phydev->supported |= SUPPORTED_1000baseT_Full;
2103                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2104                 }
2105         }
2106
2107         phydev->priv = priv;
2108
2109         list_add(&priv->list, &ar8xxx_dev_list);
2110
2111         mutex_unlock(&ar8xxx_dev_list_lock);
2112
2113         return 0;
2114
2115 err_unregister_switch:
2116         if (--priv->use_count)
2117                 goto unlock;
2118
2119         unregister_switch(&priv->dev);
2120
2121 free_priv:
2122         ar8xxx_free(priv);
2123 unlock:
2124         mutex_unlock(&ar8xxx_dev_list_lock);
2125         return ret;
2126 }
2127
2128 static void
2129 ar8xxx_phy_detach(struct phy_device *phydev)
2130 {
2131         struct net_device *dev = phydev->attached_dev;
2132
2133         if (!dev)
2134                 return;
2135
2136         dev->phy_ptr = NULL;
2137         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2138         dev->eth_mangle_rx = NULL;
2139         dev->eth_mangle_tx = NULL;
2140 }
2141
2142 static void
2143 ar8xxx_phy_remove(struct phy_device *phydev)
2144 {
2145         struct ar8xxx_priv *priv = phydev->priv;
2146
2147         if (WARN_ON(!priv))
2148                 return;
2149
2150         phydev->priv = NULL;
2151         if (--priv->use_count > 0)
2152                 return;
2153
2154         mutex_lock(&ar8xxx_dev_list_lock);
2155         list_del(&priv->list);
2156         mutex_unlock(&ar8xxx_dev_list_lock);
2157
2158         unregister_switch(&priv->dev);
2159         ar8xxx_mib_stop(priv);
2160         ar8xxx_free(priv);
2161 }
2162
2163 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2164 static int
2165 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2166 {
2167         /* we don't need an extra reset */
2168         return 0;
2169 }
2170 #endif
2171
2172 static struct phy_driver ar8xxx_phy_driver = {
2173         .phy_id         = 0x004d0000,
2174         .name           = "Atheros AR8216/AR8236/AR8316",
2175         .phy_id_mask    = 0xffff0000,
2176         .features       = PHY_BASIC_FEATURES,
2177         .probe          = ar8xxx_phy_probe,
2178         .remove         = ar8xxx_phy_remove,
2179         .detach         = ar8xxx_phy_detach,
2180         .config_init    = ar8xxx_phy_config_init,
2181         .config_aneg    = ar8xxx_phy_config_aneg,
2182         .read_status    = ar8xxx_phy_read_status,
2183 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2184         .soft_reset     = ar8xxx_phy_soft_reset,
2185 #endif
2186         .driver         = { .owner = THIS_MODULE },
2187 };
2188
2189 int __init
2190 ar8xxx_init(void)
2191 {
2192         return phy_driver_register(&ar8xxx_phy_driver);
2193 }
2194
2195 void __exit
2196 ar8xxx_exit(void)
2197 {
2198         phy_driver_unregister(&ar8xxx_phy_driver);
2199 }
2200
2201 module_init(ar8xxx_init);
2202 module_exit(ar8xxx_exit);
2203 MODULE_LICENSE("GPL");
2204