target/linux/coldfire/patches/016-Add-nand-driver-support-for-M54418TWR-board.patch

   1 From 6a5c2427d53c24a30f28b8061b2cda4edad37f58 Mon Sep 17 00:00:00 2001
   2 From: Alison Wang <b18965@freescale.com>
   3 Date: Thu, 4 Aug 2011 09:59:43 +0800
   4 Subject: [PATCH 16/52] Add nand driver support for M54418TWR board
   5
   6 Disable hw ECC for erase block aligned pages.
   7
   8 On the erase block, there's always have clean marker for jffs2,
   9 The NFC ECC provide a fake correction on the erase block when
  10 there're clean marker and adjust the bits on the fly when reading back.
  11
  12 Disable the hw ECC on erase block aligned pages is a workaround
  13 for jffs2 on the NAND.
  14
  15 Signed-off-by: Alison Wang <b18965@freescale.com>
  16 ---
  17  arch/m68k/include/asm/fsl_nfc.h |  330 +++++++++++++
  18  drivers/mtd/nand/Kconfig        |    7 +
  19  drivers/mtd/nand/Makefile       |    1 +
  20  drivers/mtd/nand/fsl_nfc.c      |  995 +++++++++++++++++++++++++++++++++++++++
  21  4 files changed, 1333 insertions(+), 0 deletions(-)
  22  create mode 100644 arch/m68k/include/asm/fsl_nfc.h
  23  create mode 100644 drivers/mtd/nand/fsl_nfc.c
  24
  25 --- /dev/null
  26 +++ b/arch/m68k/include/asm/fsl_nfc.h
  27 @@ -0,0 +1,330 @@
  28 +/*
  29 + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  30 + *
  31 + * Author: Shaohui Xie <b21989@freescale.com>
  32 + *
  33 + * Description:
  34 + * MPC5125/M54418TWR Nand driver.
  35 + *
  36 + * This is free software; you can redistribute it and/or modify it
  37 + * under the terms of the GNU General Public License as published by
  38 + * the Free Software Foundation; either version 2 of the License, or
  39 + * (at your option) any later version.
  40 + */
  41 +
  42 +#ifndef MPC5125_NFC_H
  43 +#define MPC5125_NFC_H
  44 +
  45 +
  46 +/* NFC PAD Define */
  47 +#define PAD_NFC_IO                     PAD_FUNC0
  48 +#define PAD_NFC_ALE                    PAD_FUNC0
  49 +#define PAD_NFC_CLE                    PAD_FUNC0
  50 +#define PAD_NFC_WE                     PAD_FUNC0
  51 +#define PAD_NFC_RE                     PAD_FUNC0
  52 +#define PAD_NFC_CE0                    PAD_FUNC0
  53 +#define PAD_NFC_CE1                    PAD_FUNC1
  54 +#define PAD_NFC_CE2                    PAD_FUNC2
  55 +#define PAD_NFC_CE3                    PAD_FUNC2
  56 +#define PAD_NFC_RB0                    PAD_FUNC0
  57 +#define PAD_NFC_RB1                    PAD_FUNC2
  58 +#define PAD_NFC_RB2                    PAD_FUNC2
  59 +#define PAD_NFC_RB3                    PAD_FUNC2
  60 +
  61 +/* NFC Control PAD Define */
  62 +#define BALL_NFC_CE0                   IOCTL_NFC_CE0_B
  63 +#define BALL_NFC_CE1                   IOCTL_SDHC1_CLK
  64 +#define BALL_NFC_CE2                   IOCTL_PSC1_4
  65 +#define BALL_NFC_CE3                   IOCTL_J1850_TX
  66 +#define BALL_NFC_RB0                   IOCTL_NFC_RB
  67 +#define BALL_NFC_RB1                   IOCTL_FEC1_TXD_0
  68 +#define BALL_NFC_RB2                   IOCTL_PSC1_3
  69 +#define BALL_NFC_RB3                   IOCTL_J1850_RX
  70 +#define BALL_NFC_ALE                   IOCTL_EMB_AD19
  71 +#define BALL_NFC_CLE                   IOCTL_EMB_AD18
  72 +#define BALL_NFC_WE                    IOCTL_EMB_AD16
  73 +#define BALL_NFC_RE                    IOCTL_EMB_AD17
  74 +
  75 +/* NFC IO Pad Define */
  76 +#define BALL_NFC_IO0                   IOCTL_EMB_AD00
  77 +#define BALL_NFC_IO1                   IOCTL_EMB_AD01
  78 +#define BALL_NFC_IO2                   IOCTL_EMB_AD02
  79 +#define BALL_NFC_IO3                   IOCTL_EMB_AD03
  80 +#define BALL_NFC_IO4                   IOCTL_EMB_AD04
  81 +#define BALL_NFC_IO5                   IOCTL_EMB_AD05
  82 +#define BALL_NFC_IO6                   IOCTL_EMB_AD06
  83 +#define BALL_NFC_IO7                   IOCTL_EMB_AD07
  84 +
  85 +/* Addresses for NFC MAIN RAM BUFFER areas */
  86 +#define NFC_MAIN_AREA(n)               ((n) *  0x1000)
  87 +
  88 +/* Addresses for NFC SPARE BUFFER areas */
  89 +#define NFC_SPARE_BUFFERS              8
  90 +#define NFC_SPARE_LEN                  0x10
  91 +#define NFC_SPARE_AREA(n)              (0x800 + ((n) * NFC_SPARE_LEN))
  92 +
  93 +#define PAGE_2K                                0x0800
  94 +#define PAGE_64                                0x0040
  95 +
  96 +/* MPC5125 NFC registers */
  97 +/* Typical Flash Commands */
  98 +#define READ_PAGE_CMD_CODE             0x7EE0
  99 +#define PROGRAM_PAGE_CMD_CODE          0x7FC0
 100 +#define ERASE_CMD_CODE                 0x4EC0
 101 +#define READ_ID_CMD_CODE               0x4804
 102 +#define RESET_CMD_CODE                 0x4040
 103 +#define DMA_PROGRAM_PAGE_CMD_CODE      0xFFC8
 104 +#define RANDOM_IN_CMD_CODE             0x7140
 105 +#define RANDOM_OUT_CMD_CODE            0x70E0
 106 +#define STATUS_READ_CMD_CODE           0x4068
 107 +
 108 +#define PAGE_READ_CMD_BYTE1            0x00
 109 +#define PAGE_READ_CMD_BYTE2            0x30
 110 +#define PROGRAM_PAGE_CMD_BYTE1         0x80
 111 +#define PROGRAM_PAGE_CMD_BYTE2         0x10
 112 +#define READ_STATUS_CMD_BYTE           0x70
 113 +#define ERASE_CMD_BYTE1                        0x60
 114 +#define ERASE_CMD_BYTE2                        0xD0
 115 +#define READ_ID_CMD_BYTE               0x90
 116 +#define RESET_CMD_BYTE                 0xFF
 117 +#define RANDOM_OUT_CMD_BYTE1           0x05
 118 +#define RANDOM_OUT_CMD_BYTE2           0xE0
 119 +
 120 +/* NFC ECC mode define */
 121 +#define ECC_BYPASS                     0x0
 122 +#define ECC_8_BYTE                     0x1
 123 +#define ECC_12_BYTE                    0x2
 124 +#define ECC_15_BYTE                    0x3
 125 +#define ECC_23_BYTE                    0x4
 126 +#define ECC_30_BYTE                    0x5
 127 +#define ECC_45_BYTE                    0x6
 128 +#define ECC_60_BYTE                    0x7
 129 +#define ECC_ERROR                      1
 130 +#define ECC_RIGHT                      0
 131 +
 132 +/***************** Module-Relative Register Offsets *************************/
 133 +#define NFC_SRAM_BUFFER                        0x0000
 134 +#define NFC_FLASH_CMD1                 0x3F00
 135 +#define NFC_FLASH_CMD2                 0x3F04
 136 +#define NFC_COL_ADDR                   0x3F08
 137 +#define NFC_ROW_ADDR                   0x3F0c
 138 +#define NFC_FLASH_COMMAND_REPEAT       0x3F10
 139 +#define NFC_ROW_ADDR_INC               0x3F14
 140 +#define NFC_FLASH_STATUS1              0x3F18
 141 +#define NFC_FLASH_STATUS2              0x3F1c
 142 +#define NFC_DMA1_ADDR                  0x3F20
 143 +#define NFC_DMA2_ADDR                  0x3F34
 144 +#define NFC_DMA_CONFIG                 0x3F24
 145 +#define NFC_CACHE_SWAP                 0x3F28
 146 +#define NFC_SECTOR_SIZE                        0x3F2c
 147 +#define NFC_FLASH_CONFIG               0x3F30
 148 +#define NFC_IRQ_STATUS                 0x3F38
 149 +
 150 +/***************** Module-Relative Register Reset Value *********************/
 151 +#define NFC_SRAM_BUFFER_RSTVAL                 0x00000000
 152 +#define NFC_FLASH_CMD1_RSTVAL                  0x30FF0000
 153 +#define NFC_FLASH_CMD2_RSTVAL                  0x007EE000
 154 +#define NFC_COL_ADDR_RSTVAL                    0x00000000
 155 +#define NFC_ROW_ADDR_RSTVAL                    0x11000000
 156 +#define NFC_FLASH_COMMAND_REPEAT_RSTVAL                0x00000000
 157 +#define NFC_ROW_ADDR_INC_RSTVAL                        0x00000001
 158 +#define NFC_FLASH_STATUS1_RSTVAL               0x00000000
 159 +#define NFC_FLASH_STATUS2_RSTVAL               0x00000000
 160 +#define NFC_DMA1_ADDR_RSTVAL                   0x00000000
 161 +#define NFC_DMA2_ADDR_RSTVAL                   0x00000000
 162 +#define NFC_DMA_CONFIG_RSTVAL                  0x00000000
 163 +#define NFC_CACHE_SWAP_RSTVAL                  0x0FFE0FFE
 164 +#define NFC_SECTOR_SIZE_RSTVAL                 0x00000420
 165 +#define NFC_FLASH_CONFIG_RSTVAL                        0x000EA631
 166 +#define NFC_IRQ_STATUS_RSTVAL                  0x04000000
 167 +
 168 +/***************** Module-Relative Register Mask *************************/
 169 +
 170 +/* NFC_FLASH_CMD1 Field */
 171 +#define CMD1_MASK                              0xFFFF0000
 172 +#define CMD1_SHIFT                             0
 173 +#define CMD_BYTE2_MASK                         0xFF000000
 174 +#define CMD_BYTE2_SHIFT                                24
 175 +#define CMD_BYTE3_MASK                         0x00FF0000
 176 +#define CMD_BYTE3_SHIFT                                16
 177 +
 178 +/* NFC_FLASH_CM2 Field */
 179 +#define CMD2_MASK                              0xFFFFFF07
 180 +#define CMD2_SHIFT                             0
 181 +#define CMD_BYTE1_MASK                         0xFF000000
 182 +#define CMD_BYTE1_SHIFT                                24
 183 +#define CMD_CODE_MASK                          0x00FFFF00
 184 +#define CMD_CODE_SHIFT                         8
 185 +#define BUFNO_MASK                             0x00000006
 186 +#define BUFNO_SHIFT                            1
 187 +#define BUSY_MASK                              0x00000001
 188 +#define BUSY_SHIFT                             0
 189 +#define START_MASK                             0x00000001
 190 +#define START_SHIFT                            0
 191 +
 192 +/* NFC_COL_ADDR Field */
 193 +#define COL_ADDR_MASK                          0x0000FFFF
 194 +#define COL_ADDR_SHIFT                         0
 195 +#define COL_ADDR_COL_ADDR2_MASK                        0x0000FF00
 196 +#define COL_ADDR_COL_ADDR2_SHIFT               8
 197 +#define COL_ADDR_COL_ADDR1_MASK                        0x000000FF
 198 +#define COL_ADDR_COL_ADDR1_SHIFT               0
 199 +
 200 +/* NFC_ROW_ADDR Field */
 201 +#define ROW_ADDR_MASK                          0x00FFFFFF
 202 +#define ROW_ADDR_SHIFT                         0
 203 +#define ROW_ADDR_CHIP_SEL_RB_MASK              0xF0000000
 204 +#define ROW_ADDR_CHIP_SEL_RB_SHIFT             28
 205 +#define ROW_ADDR_CHIP_SEL_MASK                 0x0F000000
 206 +#define ROW_ADDR_CHIP_SEL_SHIFT                        24
 207 +#define ROW_ADDR_ROW_ADDR3_MASK                        0x00FF0000
 208 +#define ROW_ADDR_ROW_ADDR3_SHIFT               16
 209 +#define ROW_ADDR_ROW_ADDR2_MASK                        0x0000FF00
 210 +#define ROW_ADDR_ROW_ADDR2_SHIFT               8
 211 +#define ROW_ADDR_ROW_ADDR1_MASK                        0x000000FF
 212 +#define ROW_ADDR_ROW_ADDR1_SHIFT               0
 213 +
 214 +/* NFC_FLASH_COMMAND_REPEAT Field */
 215 +#define COMMAND_REPEAT_MASK                    0x0000FFFF
 216 +#define COMMAND_REPEAT_SHIFT                   0
 217 +#define COMMAND_REPEAT_REPEAT_COUNT_MASK       0x0000FFFF
 218 +#define COMMAND_REPEAT_REPEAT_COUNT_SHIFT      0
 219 +
 220 +/* NFC_ROW_ADDR_INC Field */
 221 +#define ROW_ADDR_INC_MASK                      0x00FFFFFF
 222 +#define ROW_ADDR_INC_SHIFT                     0
 223 +#define ROW_ADDR_INC_ROW_ADDR3_INC_MASK                0x00FF0000
 224 +#define ROW_ADDR_INC_ROW_ADDR3_INC_SHIFT       16
 225 +#define ROW_ADDR_INC_ROW_ADDR2_INC_MASK                0x0000FF00
 226 +#define ROW_ADDR_INC_ROW_ADDR2_INC_SHIFT       8
 227 +#define ROW_ADDR_INC_ROW_ADDR1_INC_MASK                0x000000FF
 228 +#define ROW_ADDR_INC_ROW_ADDR1_INC_SHIFT       0
 229 +
 230 +/* NFC_FLASH_STATUS1 Field */
 231 +#define STATUS1_MASK                           0xFFFFFFFF
 232 +#define STATUS1_SHIFT                          0
 233 +#define STATUS1_ID_BYTE1_MASK                  0xFF000000
 234 +#define STATUS1_ID_BYTE1_SHIFT                 24
 235 +#define STATUS1_ID_BYTE2_MASK                  0x00FF0000
 236 +#define STATUS1_ID_BYTE2_SHIFT                 16
 237 +#define STATUS1_ID_BYTE3_MASK                  0x0000FF00
 238 +#define STATUS1_ID_BYTE3_SHIFT                 8
 239 +#define STATUS1_ID_BYTE4_MASK                  0x000000FF
 240 +#define STATUS1_ID_BYTE4_SHIFT                 0
 241 +
 242 +/* NFC_FLASH_STATUS2 Field */
 243 +#define STATUS2_MASK                           0xFF0000FF
 244 +#define STATUS2_SHIFT                          0
 245 +#define STATUS2_ID_BYTE5_MASK                  0xFF000000
 246 +#define STATUS2_ID_BYTE5_SHIFT                 24
 247 +#define STATUS_BYTE1_MASK                      0x000000FF
 248 +#define STATUS2_STATUS_BYTE1_SHIFT             0
 249 +
 250 +/* NFC_DMA1_ADDR Field */
 251 +#define DMA1_ADDR_MASK                         0xFFFFFFFF
 252 +#define DMA1_ADDR_SHIFT                                0
 253 +#define DMA1_ADDR_DMA1_ADDR_MASK               0xFFFFFFFF
 254 +#define DMA1_ADDR_DMA1_ADDR_SHIFT              0
 255 +
 256 +/* DMA2_ADDR Field */
 257 +#define DMA2_ADDR_MASK                         0xFFFFFFFF
 258 +#define DMA2_ADDR_SHIFT                                0
 259 +#define DMA2_ADDR_DMA2_ADDR_MASK               0xFFFFFFFF
 260 +#define DMA2_ADDR_DMA2_ADDR_SHIFT              0
 261 +
 262 +/* DMA_CONFIG Field */
 263 +#define DMA_CONFIG_MASK                                0xFFFFFFFF
 264 +#define DMA_CONFIG_SHIFT                       0
 265 +#define DMA_CONFIG_DMA1_CNT_MASK               0xFFF00000
 266 +#define DMA_CONFIG_DMA1_CNT_SHIFT              20
 267 +#define DMA_CONFIG_DMA2_CNT_MASK               0x000FE000
 268 +#define DMA_CONFIG_DMA2_CNT_SHIFT              13
 269 +#define DMA_CONFIG_DMA2_OFFSET_MASK            0x00001FC0
 270 +#define DMA_CONFIG_DMA2_OFFSET_SHIFT           2
 271 +#define DMA_CONFIG_DMA1_ACT_MASK               0x00000002
 272 +#define DMA_CONFIG_DMA1_ACT_SHIFT              1
 273 +#define DMA_CONFIG_DMA2_ACT_MASK               0x00000001
 274 +#define DMA_CONFIG_DMA2_ACT_SHIFT              0
 275 +
 276 +/* NFC_CACHE_SWAP Field */
 277 +#define CACHE_SWAP_MASK                                0x0FFE0FFE
 278 +#define CACHE_SWAP_SHIFT                       1
 279 +#define CACHE_SWAP_CACHE_SWAP_ADDR2_MASK       0x0FFE0000
 280 +#define CACHE_SWAP_CACHE_SWAP_ADDR2_SHIFT      17
 281 +#define CACHE_SWAP_CACHE_SWAP_ADDR1_MASK       0x00000FFE
 282 +#define CACHE_SWAP_CACHE_SWAP_ADDR1_SHIFT      1
 283 +
 284 +/* NFC_SECTOR_SIZE Field */
 285 +#define SECTOR_SIZE_MASK                       0x00001FFF
 286 +#define SECTOR_SIZE_SHIFT                      0
 287 +#define SECTOR_SIZE_SECTOR_SIZE_MASK           0x00001FFF
 288 +#define SECTOR_SIZE_SECTOR_SIZE_SHIFT          0
 289 +
 290 +/* NFC_FLASH_CONFIG Field */
 291 +#define CONFIG_MASK                            0xFFFFFFFF
 292 +#define CONFIG_SHIFT                           0
 293 +#define CONFIG_STOP_ON_WERR_MASK               0x80000000
 294 +#define CONFIG_STOP_ON_WERR_SHIFT              31
 295 +#define CONFIG_ECC_SRAM_ADDR_MASK              0x7FC00000
 296 +#define CONFIG_ECC_SRAM_ADDR_SHIFT             22
 297 +#define CONFIG_ECC_SRAM_REQ_MASK               0x00200000
 298 +#define CONFIG_ECC_SRAM_REQ_SHIFT              21
 299 +#define CONFIG_DMA_REQ_MASK                    0x00100000
 300 +#define CONFIG_DMA_REQ_SHIFT                   20
 301 +#define CONFIG_ECC_MODE_MASK                   0x000E0000
 302 +#define CONFIG_ECC_MODE_SHIFT                  17
 303 +#define CONFIG_FAST_FLASH_MASK                 0x00010000
 304 +#define CONFIG_FAST_FLASH_SHIFT                        16
 305 +#define CONFIG_ID_COUNT_MASK                   0x0000E000
 306 +#define CONFIG_ID_COUNT_SHIFT                  13
 307 +#define CONFIG_CMD_TIMEOUT_MASK                        0x00001F00
 308 +#define CONFIG_CMD_TIMEOUT_SHIFT               8
 309 +#define CONFIG_16BIT_MASK                      0x00000080
 310 +#define CONFIG_16BIT_SHIFT                     7
 311 +#define CONFIG_BOOT_MODE_MASK                  0x00000040
 312 +#define CONFIG_BOOT_MODE_SHIFT                 6
 313 +#define CONFIG_ADDR_AUTO_INCR_MASK             0x00000020
 314 +#define CONFIG_ADDR_AUTO_INCR_SHIFT            5
 315 +#define CONFIG_BUFNO_AUTO_INCR_MASK            0x00000010
 316 +#define CONFIG_BUFNO_AUTO_INCR_SHIFT           4
 317 +#define CONFIG_PAGE_CNT_MASK                   0x0000000F
 318 +#define CONFIG_PAGE_CNT_SHIFT                  0
 319 +
 320 +/* NFC_IRQ_STATUS Field */
 321 +#define MASK                                   0xEFFC003F
 322 +#define SHIFT                                  0
 323 +#define WERR_IRQ_MASK                          0x80000000
 324 +#define WERR_IRQ_SHIFT                         31
 325 +#define CMD_DONE_IRQ_MASK                      0x40000000
 326 +#define CMD_DONE_IRQ_SHIFT                     30
 327 +#define IDLE_IRQ_MASK                          0x20000000
 328 +#define IDLE_IRQ_SHIFT                         29
 329 +#define WERR_STATUS_MASK                       0x08000000
 330 +#define WERR_STATUS_SHIFT                      27
 331 +#define FLASH_CMD_BUSY_MASK                    0x04000000
 332 +#define FLASH_CMD_BUSY_SHIFT                   26
 333 +#define RESIDUE_BUSY_MASK                      0x02000000
 334 +#define RESIDUE_BUSY_SHIFT                     25
 335 +#define ECC_BUSY_MASK                          0x01000000
 336 +#define ECC_BUSY_SHIFT                         24
 337 +#define DMA_BUSY_MASK                          0x00800000
 338 +#define DMA_BUSY_SHIFT                         23
 339 +#define WERR_EN_MASK                           0x00400000
 340 +#define WERR_EN_SHIFT                          22
 341 +#define CMD_DONE_EN_MASK                       0x00200000
 342 +#define CMD_DONE_EN_SHIFT                      21
 343 +#define IDLE_EN_MASK                           0x00100000
 344 +#define IDLE_EN_SHIFT                          20
 345 +#define WERR_CLEAR_MASK                                0x00080000
 346 +#define WERR_CLEAR_SHIFT                       19
 347 +#define CMD_DONE_CLEAR_MASK                    0x00040000
 348 +#define CMD_DONE_CLEAR_SHIFT                   18
 349 +#define IDLE_CLEAR_MASK                                0x00020000
 350 +#define IDLE_CLEAR_SHIFT                       17
 351 +#define RESIDUE_BUFF_NO_MASK                   0x00000030
 352 +#define RESIDUE_BUFF_NO_SHIFT                  4
 353 +#define ECC_BUFF_NO_MASK                       0x000000C0
 354 +#define ECC_BUFF_NO_SHIFT                      2
 355 +#define DMA_BUFF_NO_MASK                       0x00000003
 356 +
 357 +#endif /* MPC5125_NFC_H */
 358 --- a/drivers/mtd/nand/Kconfig
 359 +++ b/drivers/mtd/nand/Kconfig
 360 @@ -474,6 +474,13 @@ config MTD_NAND_MPC5121_NFC
 361           This enables the driver for the NAND flash controller on the
 362           MPC5121 SoC.
 363
 364 +config MTD_NAND_FSL_NFC
 365 +       tristate "Support for NAND on Freescale ColdFire NFC"
 366 +       depends on MTD_NAND && M5441X
 367 +       help
 368 +         Enables support for NAND Flash chips wired onto Freescale PowerPC
 369 +         processor localbus with User-Programmable Machine support.
 370 +
 371  config MTD_NAND_MXC
 372         tristate "MXC NAND support"
 373         depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51
 374 --- a/drivers/mtd/nand/Makefile
 375 +++ b/drivers/mtd/nand/Makefile
 376 @@ -38,6 +38,7 @@ obj-$(CONFIG_MTD_NAND_PASEMI)         += pasemi
 377  obj-$(CONFIG_MTD_NAND_ORION)           += orion_nand.o
 378  obj-$(CONFIG_MTD_NAND_FSL_ELBC)                += fsl_elbc_nand.o
 379  obj-$(CONFIG_MTD_NAND_FSL_UPM)         += fsl_upm.o
 380 +obj-$(CONFIG_MTD_NAND_FSL_NFC)         += fsl_nfc.o
 381  obj-$(CONFIG_MTD_NAND_SH_FLCTL)                += sh_flctl.o
 382  obj-$(CONFIG_MTD_NAND_MXC)             += mxc_nand.o
 383  obj-$(CONFIG_MTD_NAND_SOCRATES)                += socrates_nand.o
 384 --- /dev/null
 385 +++ b/drivers/mtd/nand/fsl_nfc.c
 386 @@ -0,0 +1,995 @@
 387 +/*
 388 + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
 389 + *
 390 + * Author: Shaohui Xie <b21989@freescale.com>
 391 + *        Jason Jin <Jason.jin@freescale.com>
 392 + *
 393 + * Description:
 394 + * MPC5125 Nand driver.
 395 + * Jason ported to M54418TWR.
 396 + *
 397 + * Based on original driver mpc5121_nfc.c.
 398 + *
 399 + * This is free software; you can redistribute it and/or modify it
 400 + * under the terms of the GNU General Public License as published by
 401 + * the Free Software Foundation; either version 2 of the License, or
 402 + * (at your option) any later version.
 403 + */
 404 +
 405 +#include <linux/module.h>
 406 +#include <linux/clk.h>
 407 +#include <linux/delay.h>
 408 +#include <linux/init.h>
 409 +#include <linux/interrupt.h>
 410 +#include <linux/io.h>
 411 +#include <linux/mtd/mtd.h>
 412 +#include <linux/mtd/nand.h>
 413 +#include <linux/mtd/partitions.h>
 414 +#include <linux/platform_device.h>
 415 +#include <linux/slab.h>
 416 +#include <asm/fsl_nfc.h>
 417 +#include <asm/mcfsim.h>
 418 +
 419 +#define        DRV_NAME                "fsl_nfc"
 420 +#define        DRV_VERSION             "0.5"
 421 +
 422 +/* Timeouts */
 423 +#define NFC_RESET_TIMEOUT      1000            /* 1 ms */
 424 +#define NFC_TIMEOUT            (HZ)
 425 +
 426 +
 427 +#define ECC_SRAM_ADDR  (0x840 >> 3)
 428 +#define ECC_STATUS_MASK        0x80
 429 +#define ECC_ERR_COUNT  0x3F
 430 +
 431 +#define MIN(x, y)              ((x < y) ? x : y)
 432 +
 433 +#ifdef CONFIG_MTD_NAND_FSL_NFC_SWECC
 434 +static int hardware_ecc;
 435 +#else
 436 +static int hardware_ecc = 1;
 437 +#endif
 438 +
 439 +
 440 +struct fsl_nfc_prv {
 441 +       struct mtd_info         mtd;
 442 +       struct nand_chip        chip;
 443 +       int                     irq;
 444 +       void __iomem            *regs;
 445 +       struct clk              *clk;
 446 +       wait_queue_head_t       irq_waitq;
 447 +       uint                    column;
 448 +       int                     spareonly;
 449 +       int                     page;
 450 +};
 451 +
 452 +static int get_status;
 453 +static int get_id;
 454 +
 455 +static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 456 +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 457 +
 458 +static struct nand_bbt_descr bbt_main_descr = {
 459 +       .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 460 +                  NAND_BBT_2BIT | NAND_BBT_VERSION,
 461 +       .offs = 11,
 462 +       .len = 4,
 463 +       .veroffs = 15,
 464 +       .maxblocks = 4,
 465 +       .pattern = bbt_pattern,
 466 +};
 467 +
 468 +static struct nand_bbt_descr bbt_mirror_descr = {
 469 +       .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 470 +                  NAND_BBT_2BIT | NAND_BBT_VERSION,
 471 +       .offs = 11,
 472 +       .len = 4,
 473 +       .veroffs = 15,
 474 +       .maxblocks = 4,
 475 +       .pattern = mirror_pattern,
 476 +};
 477 +
 478 +
 479 +#ifdef CONFIG_MTD_PARTITIONS
 480 +static const char *fsl_nfc_pprobes[] = { "cmdlinepart", NULL };
 481 +#endif
 482 +#if 0
 483 +static struct nand_ecclayout nand_hw_eccoob_512 = {
 484 +       .eccbytes = 8,
 485 +       .eccpos = {
 486 +               8, 9, 10, 11, 12, 13, 14, 15,
 487 +       },
 488 +       .oobfree = {
 489 +               {0, 5} /* byte 5 is factory bad block marker */
 490 +       },
 491 +};
 492 +#endif
 493 +
 494 +static struct nand_ecclayout fsl_nfc_ecc45 = {
 495 +       .eccbytes = 45,
 496 +       .eccpos = {19, 20, 21, 22, 23,
 497 +                  24, 25, 26, 27, 28, 29, 30, 31,
 498 +                  32, 33, 34, 35, 36, 37, 38, 39,
 499 +                  40, 41, 42, 43, 44, 45, 46, 47,
 500 +                  48, 49, 50, 51, 52, 53, 54, 55,
 501 +                  56, 57, 58, 59, 60, 61, 62, 63},
 502 +       .oobfree = {
 503 +               {.offset = 8,
 504 +                .length = 11} }
 505 +};
 506 +
 507 +
 508 +#if 0
 509 +static struct nand_ecclayout nand_hw_eccoob_2k = {
 510 +       .eccbytes = 32,
 511 +       .eccpos = {
 512 +               /* 8 bytes of ecc for each 512 bytes of data */
 513 +               8, 9, 10, 11, 12, 13, 14, 15,
 514 +               24, 25, 26, 27, 28, 29, 30, 31,
 515 +               40, 41, 42, 43, 44, 45, 46, 47,
 516 +               56, 57, 58, 59, 60, 61, 62, 63,
 517 +       },
 518 +       .oobfree = {
 519 +               {2, 5}, /* bytes 0 and 1 are factory bad block markers */
 520 +               {16, 7},
 521 +               {32, 7},
 522 +               {48, 7},
 523 +       },
 524 +};
 525 +
 526 +
 527 +/* ecc struct for nand 5125 */
 528 +static struct nand_ecclayout nand5125_hw_eccoob_2k = {
 529 +       .eccbytes = 60,
 530 +       .eccpos = {
 531 +               /* 60 bytes of ecc for one page bytes of data */
 532 +               4, 5,
 533 +               6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
 534 +               16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
 535 +               26, 27, 28, 29, 30, 31, 32, 33, 34, 35,
 536 +               36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
 537 +               46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
 538 +               56, 57, 58, 59, 60, 61, 62, 63,
 539 +       },
 540 +       .oobfree = {
 541 +               {2, 2}, /* bytes 0 and 1 are factory bad block markers */
 542 +       },
 543 +};
 544 +#endif
 545 +
 546 +static inline u32 nfc_read(struct mtd_info *mtd, uint reg)
 547 +{
 548 +       struct nand_chip *chip = mtd->priv;
 549 +       struct fsl_nfc_prv *prv = chip->priv;
 550 +
 551 +       return in_be32(prv->regs + reg);
 552 +}
 553 +
 554 +/* Write NFC register */
 555 +static inline void nfc_write(struct mtd_info *mtd, uint reg, u32 val)
 556 +{
 557 +       struct nand_chip *chip = mtd->priv;
 558 +       struct fsl_nfc_prv *prv = chip->priv;
 559 +
 560 +       out_be32(prv->regs + reg, val);
 561 +}
 562 +
 563 +/* Set bits in NFC register */
 564 +static inline void nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
 565 +{
 566 +       nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
 567 +}
 568 +
 569 +/* Clear bits in NFC register */
 570 +static inline void nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
 571 +{
 572 +       nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
 573 +}
 574 +
 575 +static inline void
 576 +nfc_set_field(struct mtd_info *mtd, u32 reg, u32 mask, u32 shift, u32 val)
 577 +{
 578 +       struct nand_chip *chip = mtd->priv;
 579 +       struct fsl_nfc_prv *prv = chip->priv;
 580 +
 581 +       out_be32(prv->regs + reg,
 582 +                       (in_be32(prv->regs + reg) & (~mask))
 583 +                       | val << shift);
 584 +}
 585 +
 586 +static inline int
 587 +nfc_get_field(struct mtd_info *mtd, u32 reg, u32 field_mask)
 588 +{
 589 +       struct nand_chip *chip = mtd->priv;
 590 +       struct fsl_nfc_prv *prv = chip->priv;
 591 +
 592 +       return in_be32(prv->regs + reg) & field_mask;
 593 +}
 594 +
 595 +static inline u8 nfc_check_status(struct mtd_info *mtd)
 596 +{
 597 +       u8 fls_status = 0;
 598 +       fls_status = nfc_get_field(mtd, NFC_FLASH_STATUS2, STATUS_BYTE1_MASK);
 599 +       return fls_status;
 600 +}
 601 +
 602 +/* clear cmd_done and cmd_idle falg for the coming command */
 603 +static void fsl_nfc_clear(struct mtd_info *mtd)
 604 +{
 605 +       nfc_write(mtd, NFC_IRQ_STATUS, 1 << CMD_DONE_CLEAR_SHIFT);
 606 +       nfc_write(mtd, NFC_IRQ_STATUS, 1 << IDLE_CLEAR_SHIFT);
 607 +}
 608 +
 609 +/* Wait for operation complete */
 610 +static void fsl_nfc_done(struct mtd_info *mtd)
 611 +{
 612 +       struct nand_chip *chip = mtd->priv;
 613 +       struct fsl_nfc_prv *prv = chip->priv;
 614 +       int rv;
 615 +
 616 +       nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_MASK);
 617 +
 618 +       nfc_set_field(mtd, NFC_FLASH_CMD2, START_MASK,
 619 +                       START_SHIFT, 1);
 620 +
 621 +       if (!nfc_get_field(mtd, NFC_IRQ_STATUS, IDLE_IRQ_MASK)) {
 622 +               rv = wait_event_timeout(prv->irq_waitq,
 623 +                       nfc_get_field(mtd, NFC_IRQ_STATUS,
 624 +                               IDLE_IRQ_MASK), NFC_TIMEOUT);
 625 +               if (!rv)
 626 +                       printk(KERN_DEBUG DRV_NAME
 627 +                               ": Timeout while waiting for BUSY.\n");
 628 +       }
 629 +       fsl_nfc_clear(mtd);
 630 +}
 631 +
 632 +static inline u8 fsl_nfc_get_id(struct mtd_info *mtd, int col)
 633 +{
 634 +       u32 flash_id1 = 0;
 635 +       u8 *pid;
 636 +
 637 +       flash_id1 = nfc_read(mtd, NFC_FLASH_STATUS1);
 638 +       pid = (u8 *)&flash_id1;
 639 +
 640 +       return *(pid + col);
 641 +}
 642 +
 643 +static inline u8 fsl_nfc_get_status(struct mtd_info *mtd)
 644 +{
 645 +       u32 flash_status = 0;
 646 +       u8 *pstatus;
 647 +
 648 +       flash_status = nfc_read(mtd, NFC_FLASH_STATUS2);
 649 +       pstatus = (u8 *)&flash_status;
 650 +
 651 +       return *(pstatus + 3);
 652 +}
 653 +
 654 +/* Invoke command cycle */
 655 +static inline void
 656 +fsl_nfc_send_cmd(struct mtd_info *mtd, u32 cmd_byte1,
 657 +               u32 cmd_byte2, u32 cmd_code)
 658 +{
 659 +       fsl_nfc_clear(mtd);
 660 +       nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
 661 +                       CMD_BYTE1_SHIFT, cmd_byte1);
 662 +
 663 +       nfc_set_field(mtd, NFC_FLASH_CMD1, CMD_BYTE2_MASK,
 664 +                       CMD_BYTE2_SHIFT, cmd_byte2);
 665 +
 666 +       nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
 667 +                       BUFNO_SHIFT, 0);
 668 +
 669 +       nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK,
 670 +                       CMD_CODE_SHIFT, cmd_code);
 671 +
 672 +       if (cmd_code == RANDOM_OUT_CMD_CODE)
 673 +               nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
 674 +                       BUFNO_SHIFT, 1);
 675 +}
 676 +
 677 +/* Receive ID and status from NAND flash */
 678 +static inline void
 679 +fsl_nfc_send_one_byte(struct mtd_info *mtd, u32 cmd_byte1, u32 cmd_code)
 680 +{
 681 +       fsl_nfc_clear(mtd);
 682 +
 683 +       nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
 684 +                       CMD_BYTE1_SHIFT, cmd_byte1);
 685 +
 686 +       nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
 687 +                       BUFNO_SHIFT, 0);
 688 +
 689 +       nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK,
 690 +                       CMD_CODE_SHIFT, cmd_code);
 691 +}
 692 +
 693 +/* NFC interrupt handler */
 694 +static irqreturn_t
 695 +fsl_nfc_irq(int irq, void *data)
 696 +{
 697 +       struct mtd_info *mtd = data;
 698 +       struct nand_chip *chip = mtd->priv;
 699 +       struct fsl_nfc_prv *prv = chip->priv;
 700 +
 701 +       nfc_clear(mtd, NFC_IRQ_STATUS, IDLE_EN_MASK);
 702 +       wake_up(&prv->irq_waitq);
 703 +
 704 +       return IRQ_HANDLED;
 705 +}
 706 +
 707 +/* Do address cycle(s) */
 708 +static void
 709 +fsl_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
 710 +{
 711 +
 712 +       if (column != -1) {
 713 +               nfc_set_field(mtd, NFC_COL_ADDR,
 714 +                               COL_ADDR_MASK,
 715 +                               COL_ADDR_SHIFT, column);
 716 +       }
 717 +
 718 +       if (page != -1) {
 719 +               nfc_set_field(mtd, NFC_ROW_ADDR,
 720 +                               ROW_ADDR_MASK,
 721 +                               ROW_ADDR_SHIFT, page);
 722 +       }
 723 +
 724 +       /* DMA Disable */
 725 +       nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_MASK);
 726 +
 727 +       /* PAGE_CNT = 1 */
 728 +       nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
 729 +                       CONFIG_PAGE_CNT_SHIFT, 0x1);
 730 +}
 731 +
 732 +/* Control chips select signal on m54418twr board */
 733 +static void
 734 +m54418twr_select_chip(struct mtd_info *mtd, int chip)
 735 +{
 736 +       if (chip < 0) {
 737 +               MCF_GPIO_PAR_FBCTL &= (MCF_GPIO_PAR_FBCTL_ALE_MASK &
 738 +                                  MCF_GPIO_PAR_FBCTL_TA_MASK);
 739 +               MCF_GPIO_PAR_FBCTL |= MCF_GPIO_PAR_FBCTL_ALE_FB_TS |
 740 +                                  MCF_GPIO_PAR_FBCTL_TA_TA;
 741 +
 742 +               MCF_GPIO_PAR_BE =
 743 +                   MCF_GPIO_PAR_BE_BE3_BE3 | MCF_GPIO_PAR_BE_BE2_BE2 |
 744 +                   MCF_GPIO_PAR_BE_BE1_BE1 | MCF_GPIO_PAR_BE_BE0_BE0;
 745 +
 746 +               MCF_GPIO_PAR_CS &= ~MCF_GPIO_PAR_CS_CS1_NFC_CE;
 747 +               MCF_GPIO_PAR_CS |= MCF_GPIO_PAR_CS_CS0_CS0;
 748 +               return;
 749 +       }
 750 +
 751 +       MCF_GPIO_PAR_FBCTL &= (MCF_GPIO_PAR_FBCTL_ALE_MASK &
 752 +                       MCF_GPIO_PAR_FBCTL_TA_MASK);
 753 +       MCF_GPIO_PAR_FBCTL |= MCF_GPIO_PAR_FBCTL_ALE_FB_ALE |
 754 +                       MCF_GPIO_PAR_FBCTL_TA_NFC_RB;
 755 +       MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_BE3_FB_A1 |
 756 +               MCF_GPIO_PAR_BE_BE2_FB_A0 |
 757 +               MCF_GPIO_PAR_BE_BE1_BE1 | MCF_GPIO_PAR_BE_BE0_BE0;
 758 +
 759 +       MCF_GPIO_PAR_CS &= (MCF_GPIO_PAR_BE_BE3_MASK &
 760 +               MCF_GPIO_PAR_BE_BE2_MASK);
 761 +       MCF_GPIO_PAR_CS |= MCF_GPIO_PAR_CS_CS1_NFC_CE;
 762 +       return;
 763 +}
 764 +
 765 +/* Read NAND Ready/Busy signal */
 766 +static int
 767 +fsl_nfc_dev_ready(struct mtd_info *mtd)
 768 +{
 769 +       /*
 770 +        * NFC handles ready/busy signal internally. Therefore, this function
 771 +        * always returns status as ready.
 772 +        */
 773 +       return 1;
 774 +}
 775 +
 776 +/* Write command to NAND flash */
 777 +static void
 778 +fsl_nfc_command(struct mtd_info *mtd, unsigned command,
 779 +                                       int column, int page)
 780 +{
 781 +       struct nand_chip *chip = mtd->priv;
 782 +       struct fsl_nfc_prv *prv = chip->priv;
 783 +
 784 +       prv->column = (column >= 0) ? column : 0;
 785 +       prv->spareonly = 0;
 786 +       get_id = 0;
 787 +       get_status = 0;
 788 +
 789 +       if (page != -1)
 790 +               prv->page = page;
 791 +
 792 +       nfc_set_field(mtd, NFC_FLASH_CONFIG,
 793 +               CONFIG_ECC_MODE_MASK,
 794 +               CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
 795 +
 796 +       if (!(page%0x40)) {
 797 +                       nfc_set_field(mtd, NFC_FLASH_CONFIG,
 798 +                               CONFIG_ECC_MODE_MASK,
 799 +                               CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
 800 +       }
 801 +
 802 +       switch (command) {
 803 +       case NAND_CMD_PAGEPROG:
 804 +               if (!(prv->page%0x40))
 805 +                       nfc_set_field(mtd, NFC_FLASH_CONFIG,
 806 +                               CONFIG_ECC_MODE_MASK,
 807 +                               CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
 808 +
 809 +               fsl_nfc_send_cmd(mtd,
 810 +                               PROGRAM_PAGE_CMD_BYTE1,
 811 +                               PROGRAM_PAGE_CMD_BYTE2,
 812 +                               PROGRAM_PAGE_CMD_CODE);
 813 +               break;
 814 +       /*
 815 +        * NFC does not support sub-page reads and writes,
 816 +        * so emulate them using full page transfers.
 817 +        */
 818 +       case NAND_CMD_READ0:
 819 +               column = 0;
 820 +               goto read0;
 821 +               break;
 822 +
 823 +       case NAND_CMD_READ1:
 824 +               prv->column += 256;
 825 +               command = NAND_CMD_READ0;
 826 +               column = 0;
 827 +               goto read0;
 828 +               break;
 829 +
 830 +       case NAND_CMD_READOOB:
 831 +               prv->spareonly = 1;
 832 +               command = NAND_CMD_READ0;
 833 +               column = 0;
 834 +read0:
 835 +               fsl_nfc_send_cmd(mtd,
 836 +                               PAGE_READ_CMD_BYTE1,
 837 +                               PAGE_READ_CMD_BYTE2,
 838 +                               READ_PAGE_CMD_CODE);
 839 +               break;
 840 +
 841 +       case NAND_CMD_SEQIN:
 842 +               fsl_nfc_command(mtd, NAND_CMD_READ0, column, page);
 843 +               column = 0;
 844 +               break;
 845 +
 846 +       case NAND_CMD_ERASE1:
 847 +               fsl_nfc_send_cmd(mtd,
 848 +                               ERASE_CMD_BYTE1,
 849 +                               ERASE_CMD_BYTE2,
 850 +                               ERASE_CMD_CODE);
 851 +               break;
 852 +       case NAND_CMD_ERASE2:
 853 +               return;
 854 +       case NAND_CMD_READID:
 855 +               get_id = 1;
 856 +               fsl_nfc_send_one_byte(mtd, command, READ_ID_CMD_CODE);
 857 +               break;
 858 +       case NAND_CMD_STATUS:
 859 +               get_status = 1;
 860 +               fsl_nfc_send_one_byte(mtd, command, STATUS_READ_CMD_CODE);
 861 +               break;
 862 +       case NAND_CMD_RNDOUT:
 863 +               fsl_nfc_send_cmd(mtd,
 864 +                               RANDOM_OUT_CMD_BYTE1,
 865 +                               RANDOM_OUT_CMD_BYTE2,
 866 +                               RANDOM_OUT_CMD_CODE);
 867 +               break;
 868 +       case NAND_CMD_RESET:
 869 +               fsl_nfc_send_one_byte(mtd, command, RESET_CMD_CODE);
 870 +               break;
 871 +       default:
 872 +               return;
 873 +       }
 874 +
 875 +       fsl_nfc_addr_cycle(mtd, column, page);
 876 +
 877 +       fsl_nfc_done(mtd);
 878 +}
 879 +
 880 +/* Copy data from/to NFC spare buffers. */
 881 +static void
 882 +fsl_nfc_copy_spare(struct mtd_info *mtd, uint offset,
 883 +                       u8 *buffer, uint size, int wr)
 884 +{
 885 +       struct nand_chip *nand = mtd->priv;
 886 +       struct fsl_nfc_prv *prv = nand->priv;
 887 +       uint o, s, sbsize, blksize;
 888 +
 889 +       /*
 890 +        * NAND spare area is available through NFC spare buffers.
 891 +        * The NFC divides spare area into (page_size / 512) chunks.
 892 +        * Each chunk is placed into separate spare memory area, using
 893 +        * first (spare_size / num_of_chunks) bytes of the buffer.
 894 +        *
 895 +        * For NAND device in which the spare area is not divided fully
 896 +        * by the number of chunks, number of used bytes in each spare
 897 +        * buffer is rounded down to the nearest even number of bytes,
 898 +        * and all remaining bytes are added to the last used spare area.
 899 +        *
 900 +        * For more information read section 26.6.10 of MPC5121e
 901 +        * Microcontroller Reference Manual, Rev. 3.
 902 +        */
 903 +
 904 +       /* Calculate number of valid bytes in each spare buffer */
 905 +/*     sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;*/
 906 +       sbsize = (mtd->oobsize / (mtd->writesize / 2048)) & ~1;
 907 +
 908 +
 909 +       while (size) {
 910 +               /* Calculate spare buffer number */
 911 +               s = offset / sbsize;
 912 +               if (s > NFC_SPARE_BUFFERS - 1)
 913 +                       s = NFC_SPARE_BUFFERS - 1;
 914 +
 915 +               /*
 916 +                * Calculate offset to requested data block in selected spare
 917 +                * buffer and its size.
 918 +                */
 919 +               o = offset - (s * sbsize);
 920 +               blksize = min(sbsize - o, size);
 921 +
 922 +               if (wr)
 923 +                       memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
 924 +                                                       buffer, blksize);
 925 +               else {
 926 +                       memcpy_fromio(buffer,
 927 +                               prv->regs + NFC_SPARE_AREA(s) + o, blksize);
 928 +               }
 929 +
 930 +               buffer += blksize;
 931 +               offset += blksize;
 932 +               size -= blksize;
 933 +       };
 934 +}
 935 +
 936 +/* Copy data from/to NFC main and spare buffers */
 937 +static void
 938 +fsl_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len, int wr)
 939 +{
 940 +       struct nand_chip *chip = mtd->priv;
 941 +       struct fsl_nfc_prv *prv = chip->priv;
 942 +       uint c = prv->column;
 943 +       uint l;
 944 +
 945 +       /* Handle spare area access */
 946 +       if (prv->spareonly || c >= mtd->writesize) {
 947 +               /* Calculate offset from beginning of spare area */
 948 +               if (c >= mtd->writesize)
 949 +                       c -= mtd->writesize;
 950 +
 951 +               prv->column += len;
 952 +               fsl_nfc_copy_spare(mtd, c, buf, len, wr);
 953 +               return;
 954 +       }
 955 +
 956 +       /*
 957 +        * Handle main area access - limit copy length to prevent
 958 +        * crossing main/spare boundary.
 959 +        */
 960 +       l = min((uint)len, mtd->writesize - c);
 961 +       prv->column += l;
 962 +
 963 +       if (wr)
 964 +               memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
 965 +       else {
 966 +               if (get_status) {
 967 +                       get_status = 0;
 968 +                       *buf = fsl_nfc_get_status(mtd);
 969 +               } else if (l == 1 && c <= 3 && get_id) {
 970 +                       *buf = fsl_nfc_get_id(mtd, c);
 971 +               } else
 972 +                       memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
 973 +       }
 974 +
 975 +       /* Handle crossing main/spare boundary */
 976 +       if (l != len) {
 977 +               buf += l;
 978 +               len -= l;
 979 +               fsl_nfc_buf_copy(mtd, buf, len, wr);
 980 +       }
 981 +}
 982 +
 983 +/* Read data from NFC buffers */
 984 +static void
 985 +fsl_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 986 +{
 987 +       fsl_nfc_buf_copy(mtd, buf, len, 0);
 988 +}
 989 +
 990 +/* Write data to NFC buffers */
 991 +static void
 992 +fsl_nfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 993 +{
 994 +       fsl_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
 995 +}
 996 +
 997 +/* Compare buffer with NAND flash */
 998 +static int
 999 +fsl_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
1000 +{
1001 +       u_char tmp[256];
1002 +       uint bsize;
1003 +
1004 +       while (len) {
1005 +               bsize = min(len, 256);
1006 +               fsl_nfc_read_buf(mtd, tmp, bsize);
1007 +
1008 +               if (memcmp(buf, tmp, bsize))
1009 +                       return 1;
1010 +
1011 +               buf += bsize;
1012 +               len -= bsize;
1013 +       }
1014 +
1015 +       return 0;
1016 +}
1017 +
1018 +/* Read byte from NFC buffers */
1019 +static u8
1020 +fsl_nfc_read_byte(struct mtd_info *mtd)
1021 +{
1022 +       u8 tmp;
1023 +       fsl_nfc_read_buf(mtd, &tmp, sizeof(tmp));
1024 +       return tmp;
1025 +}
1026 +
1027 +/* Read word from NFC buffers */
1028 +static u16
1029 +fsl_nfc_read_word(struct mtd_info *mtd)
1030 +{
1031 +       u16 tmp;
1032 +       fsl_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
1033 +       return tmp;
1034 +}
1035 +
1036 +#if 0
1037 +static void fsl_nfc_check_ecc_status(struct mtd_info *mtd)
1038 +{
1039 +       struct nand_chip *chip = mtd->priv;
1040 +       struct fsl_nfc_prv *prv = chip->priv;
1041 +       u8 ecc_status, ecc_count;
1042 +
1043 +       ecc_status = *(u8 *)(prv->regs + ECC_SRAM_ADDR * 8 + 7);
1044 +       ecc_count = ecc_status & ECC_ERR_COUNT;
1045 +       if (ecc_status & ECC_STATUS_MASK) {
1046 +               /*mtd->ecc_stats.failed++;*/
1047 +               printk("ECC failed to correct all errors!\n");
1048 +       } else if (ecc_count) {
1049 +               /*mtd->ecc_stats.corrected += ecc_count;*/
1050 +               printk(KERN_INFO"ECC corrected %d errors\n", ecc_count);
1051 +       }
1052 +
1053 +}
1054 +#endif
1055 +
1056 +static void
1057 +copy_from_to_spare(struct mtd_info *mtd, void *pbuf, int len, int wr)
1058 +{
1059 +       struct nand_chip *chip = mtd->priv;
1060 +       struct fsl_nfc_prv *prv = chip->priv;
1061 +       int i, copy_count, copy_size;
1062 +
1063 +/*     copy_count = mtd->writesize / 512;*/
1064 +       copy_count = mtd->writesize / 2048;
1065 +       /*
1066 +        * Each spare area has 16 bytes for 512, 2K and normal 4K nand.
1067 +        * For 4K nand with large 218 byte spare size, the size is 26 bytes for
1068 +        * the first 7 buffers and 36 for the last.
1069 +        */
1070 +/*     copy_size = mtd->oobsize == 218 ? 26 : 16;*/
1071 +       copy_size = 64;
1072 +
1073 +       /*
1074 +        * Each spare area has 16 bytes for 512, 2K and normal 4K nand.
1075 +        * For 4K nand with large 218 byte spare size, the size is 26
1076 +        * bytes for the first 7 buffers and 36 for the last.
1077 +        */
1078 +       for (i = 0; i < copy_count - 1 && len > 0; i++) {
1079 +               if (wr)
1080 +                       memcpy_toio(prv->regs + NFC_SPARE_AREA(i),
1081 +                                       pbuf, MIN(len, copy_size));
1082 +               else
1083 +                       memcpy_fromio(pbuf, prv->regs + NFC_SPARE_AREA(i),
1084 +                                       MIN(len, copy_size));
1085 +               pbuf += copy_size;
1086 +               len -= copy_size;
1087 +       }
1088 +       if (len > 0) {
1089 +               if (wr)
1090 +                       memcpy_toio(prv->regs + NFC_SPARE_AREA(i),
1091 +                               pbuf, len);
1092 +               else
1093 +                       memcpy_fromio(pbuf,
1094 +                               prv->regs + NFC_SPARE_AREA(i), len);
1095 +       }
1096 +}
1097 +
1098 +
1099 +static int fsl_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1100 +                               int page, int sndcmd)
1101 +{
1102 +       fsl_nfc_command(mtd, NAND_CMD_READ0, 0, page);
1103 +
1104 +       copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 0);
1105 +       return 0;
1106 +}
1107 +
1108 +static int fsl_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1109 +                                       int page)
1110 +{
1111 +       fsl_nfc_command(mtd, NAND_CMD_READ0, 0, page);
1112 +       /* copy the oob data */
1113 +       copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 1);
1114 +       fsl_nfc_command(mtd, NAND_CMD_PAGEPROG, 0, page);
1115 +       return 0;
1116 +}
1117 +
1118 +static int fsl_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1119 +                                       uint8_t *buf, int page)
1120 +{
1121 +       struct fsl_nfc_prv *prv = chip->priv;
1122 +       /*fsl_nfc_check_ecc_status(mtd);*/
1123 +
1124 +       memcpy_fromio((void *)buf, prv->regs + NFC_MAIN_AREA(0),
1125 +                       mtd->writesize);
1126 +       copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 0);
1127 +       return 0;
1128 +}
1129 +
1130 +static void fsl_nfc_write_page(struct mtd_info *mtd,
1131 +               struct nand_chip *chip, const uint8_t *buf)
1132 +{
1133 +       struct fsl_nfc_prv *prv = chip->priv;
1134 +       memcpy_toio(prv->regs + NFC_MAIN_AREA(0), buf, mtd->writesize);
1135 +       copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 1);
1136 +}
1137 +
1138 +static void fsl_nfc_enable_hwecc(struct mtd_info *mtd, int mode)
1139 +{
1140 +       return;
1141 +}
1142 +
1143 +/* Free driver resources */
1144 +static void
1145 +fsl_nfc_free(struct  platform_device *dev, struct mtd_info *mtd)
1146 +{
1147 +       struct nand_chip *chip = mtd->priv;
1148 +       struct fsl_nfc_prv *prv = chip->priv;
1149 +
1150 +       kfree(prv);
1151 +}
1152 +
1153 +static int __devinit
1154 +fsl_nfc_probe(struct platform_device *pdev)
1155 +{
1156 +       struct fsl_nfc_prv *prv;
1157 +       struct resource *res;
1158 +       struct mtd_info *mtd;
1159 +#ifdef CONFIG_MTD_PARTITIONS
1160 +       struct mtd_partition *parts;
1161 +#endif
1162 +       struct nand_chip *chip;
1163 +       unsigned long regs_paddr, regs_size;
1164 +       int retval = 0;
1165 +
1166 +       prv = kzalloc(sizeof(*prv), GFP_KERNEL);
1167 +       if (!prv) {
1168 +               printk(KERN_ERR DRV_NAME ": Memory exhausted!\n");
1169 +               return -ENOMEM;
1170 +       }
1171 +       mtd = &prv->mtd;
1172 +       chip = &prv->chip;
1173 +
1174 +       mtd->priv = chip;
1175 +       chip->priv = prv;
1176 +
1177 +       prv->irq = platform_get_irq(pdev, 0);
1178 +       if (prv->irq <= 0) {
1179 +               printk(KERN_ERR DRV_NAME ": Error mapping IRQ!\n");
1180 +               return -EINVAL;
1181 +       }
1182 +
1183 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1184 +       if (res == NULL) {
1185 +               printk(KERN_ERR "%s platform_get_resource MEM  failed %x\n",
1186 +                       __func__, (unsigned int)res);
1187 +               retval = -ENOMEM;
1188 +               goto error;
1189 +       }
1190 +       regs_paddr = res->start;
1191 +       regs_size = res->end - res->start + 1;
1192 +
1193 +#if 0
1194 +       if (!request_mem_region(regs_paddr, regs_size, DRV_NAME)) {
1195 +               printk(KERN_ERR DRV_NAME ": Error requesting memory region!\n");
1196 +               return -EBUSY;
1197 +       }
1198 +
1199 +       prv->regs = ioremap(regs_paddr, regs_size);
1200 +#endif
1201 +       prv->regs = (void __iomem *)regs_paddr;
1202 +       if (!prv->regs) {
1203 +               printk(KERN_ERR DRV_NAME ": Error mapping memory region!\n");
1204 +               return -ENOMEM;
1205 +       }
1206 +
1207 +       mtd->name = "NAND";
1208 +       mtd->writesize = 2048;
1209 +       mtd->oobsize = 64;
1210 +
1211 +       chip->dev_ready = fsl_nfc_dev_ready;
1212 +       chip->cmdfunc = fsl_nfc_command;
1213 +       chip->read_byte = fsl_nfc_read_byte;
1214 +       chip->read_word = fsl_nfc_read_word;
1215 +       chip->read_buf = fsl_nfc_read_buf;
1216 +       chip->write_buf = fsl_nfc_write_buf;
1217 +       chip->verify_buf = fsl_nfc_verify_buf;
1218 +       chip->options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT |
1219 +                               NAND_BUSWIDTH_16 | NAND_CACHEPRG;
1220 +
1221 +       chip->select_chip = m54418twr_select_chip;
1222 +
1223 +       if (hardware_ecc) {
1224 +               chip->ecc.read_page = fsl_nfc_read_page;
1225 +               chip->ecc.write_page = fsl_nfc_write_page;
1226 +               chip->ecc.read_oob = fsl_nfc_read_oob;
1227 +               chip->ecc.write_oob = fsl_nfc_write_oob;
1228 +               chip->ecc.layout = &fsl_nfc_ecc45;
1229 +
1230 +               /* propagate ecc.layout to mtd_info */
1231 +               mtd->ecclayout = chip->ecc.layout;
1232 +               chip->ecc.calculate = NULL;
1233 +               chip->ecc.hwctl = fsl_nfc_enable_hwecc;
1234 +               chip->ecc.correct = NULL;
1235 +               chip->ecc.mode = NAND_ECC_HW;
1236 +               /* RS-ECC is applied for both MAIN+SPARE not MAIN alone */
1237 +               chip->ecc.steps = 1;
1238 +               chip->ecc.bytes = 45;
1239 +               chip->ecc.size = 0x800;
1240 +
1241 +               /* set ECC mode = ECC_45_BYTE */
1242 +               nfc_set_field(mtd, NFC_FLASH_CONFIG,
1243 +                               CONFIG_ECC_MODE_MASK,
1244 +                               CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
1245 +               /* set ECC_STATUS write position */
1246 +               nfc_set_field(mtd, NFC_FLASH_CONFIG,
1247 +                               CONFIG_ECC_SRAM_ADDR_MASK,
1248 +                               CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR);
1249 +               /* enable ECC_STATUS results write */
1250 +               nfc_set_field(mtd, NFC_FLASH_CONFIG,
1251 +                               CONFIG_ECC_SRAM_REQ_MASK,
1252 +                               CONFIG_ECC_SRAM_REQ_SHIFT, 1);
1253 +       } else {
1254 +               chip->ecc.mode = NAND_ECC_SOFT;
1255 +               /* set ECC BY_PASS */
1256 +               nfc_set_field(mtd, NFC_FLASH_CONFIG,
1257 +                               CONFIG_ECC_MODE_MASK,
1258 +                               CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
1259 +       }
1260 +       chip->bbt_td = &bbt_main_descr;
1261 +       chip->bbt_md = &bbt_mirror_descr;
1262 +       bbt_main_descr.pattern = bbt_pattern;
1263 +       bbt_mirror_descr.pattern = mirror_pattern;
1264 +
1265 +       init_waitqueue_head(&prv->irq_waitq);
1266 +       retval = request_irq(prv->irq, fsl_nfc_irq, IRQF_DISABLED,
1267 +                       DRV_NAME, mtd);
1268 +       if (retval) {
1269 +               printk(KERN_ERR DRV_NAME ": Error requesting IRQ!\n");
1270 +               goto error;
1271 +       }
1272 +
1273 +       /* SET SECTOR SIZE */
1274 +       nfc_write(mtd, NFC_SECTOR_SIZE, PAGE_2K | PAGE_64);
1275 +
1276 +       nfc_set_field(mtd, NFC_FLASH_CONFIG,
1277 +                       CONFIG_ADDR_AUTO_INCR_MASK,
1278 +                       CONFIG_ADDR_AUTO_INCR_SHIFT, 0);
1279 +
1280 +       nfc_set_field(mtd, NFC_FLASH_CONFIG,
1281 +                       CONFIG_BUFNO_AUTO_INCR_MASK,
1282 +                       CONFIG_BUFNO_AUTO_INCR_SHIFT, 0);
1283 +       /* SET FAST_FLASH = 1 */
1284 +#if 0
1285 +       nfc_set_field(mtd, NFC_FLASH_CONFIG,
1286 +                       CONFIG_FAST_FLASH_MASK,
1287 +                       CONFIG_FAST_FLASH_SHIFT, 1);
1288 +#endif
1289 +
1290 +       nfc_set_field(mtd, NFC_FLASH_CONFIG,
1291 +                       CONFIG_16BIT_MASK,
1292 +                       CONFIG_16BIT_SHIFT, 1);
1293 +
1294 +
1295 +       /* Detect NAND chips */
1296 +       if (nand_scan(mtd, 1)) {
1297 +               printk(KERN_ERR DRV_NAME ": NAND Flash not found !\n");
1298 +               free_irq(prv->irq, mtd);
1299 +               retval = -ENXIO;
1300 +               goto error;
1301 +       }
1302 +
1303 +       platform_set_drvdata(pdev, mtd);
1304 +
1305 +       /* Register device in MTD */
1306 +#ifdef CONFIG_MTD_PARTITIONS
1307 +       retval = parse_mtd_partitions(mtd, fsl_nfc_pprobes, &parts, 0);
1308 +       if (retval < 0) {
1309 +               printk(KERN_ERR DRV_NAME ": Error parsing MTD partitions!\n");
1310 +               free_irq(prv->irq, mtd);
1311 +               retval = -EINVAL;
1312 +               goto error;
1313 +       }
1314 +
1315 +       printk(KERN_DEBUG "parse partition: partnr = %d\n", retval);
1316 +
1317 +       if (retval > 0)
1318 +               retval = add_mtd_partitions(mtd, parts, retval);
1319 +       else
1320 +#endif
1321 +               retval = add_mtd_device(mtd);
1322 +
1323 +       if (retval) {
1324 +               printk(KERN_ERR DRV_NAME ": Error adding MTD device!\n");
1325 +               free_irq(prv->irq, mtd);
1326 +               goto error;
1327 +       }
1328 +
1329 +       return 0;
1330 +error:
1331 +       fsl_nfc_free(pdev, mtd);
1332 +       return retval;
1333 +}
1334 +
1335 +static int __exit
1336 +fsl_nfc_remove(struct platform_device *pdev)
1337 +{
1338 +       struct mtd_info *mtd = platform_get_drvdata(pdev);
1339 +       struct nand_chip *chip = mtd->priv;
1340 +       struct fsl_nfc_prv *prv = chip->priv;
1341 +
1342 +       nand_release(mtd);
1343 +       free_irq(prv->irq, mtd);
1344 +       fsl_nfc_free(pdev, mtd);
1345 +
1346 +       return 0;
1347 +}
1348 +
1349 +static struct platform_driver fsl_nfc_driver = {
1350 +       .probe          = fsl_nfc_probe,
1351 +       .remove         = __exit_p(fsl_nfc_remove),
1352 +       .suspend        = NULL,
1353 +       .resume         = NULL,
1354 +       .driver         = {
1355 +               .name   = DRV_NAME,
1356 +               .owner  = THIS_MODULE,
1357 +       },
1358 +};
1359 +
1360 +static int __init fsl_nfc_init(void)
1361 +{
1362 +       pr_info("FSL NFC MTD nand Driver %s\n", DRV_VERSION);
1363 +       if (platform_driver_register(&fsl_nfc_driver) != 0) {
1364 +               printk(KERN_ERR DRV_NAME ": Driver register failed!\n");
1365 +               return -ENODEV;
1366 +       }
1367 +       return 0;
1368 +}
1369 +
1370 +static void __exit fsl_nfc_cleanup(void)
1371 +{
1372 +       platform_driver_unregister(&fsl_nfc_driver);
1373 +}
1374 +
1375 +module_init(fsl_nfc_init);
1376 +module_exit(fsl_nfc_cleanup);
1377 +
1378 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1379 +MODULE_DESCRIPTION("FSL NFC NAND MTD driver");
1380 +MODULE_LICENSE("GPL");
1381 +MODULE_VERSION(DRV_VERSION);