target/linux/cns3xxx/patches-3.8/040-fiq_support.patch

   1 --- a/arch/arm/Kconfig
   2 +++ b/arch/arm/Kconfig
   3 @@ -368,6 +368,7 @@ config ARCH_CNS3XXX
   4         select CLKDEV_LOOKUP
   5         select CPU_CACHE_FORCE_MULTI
   6         select HAVE_SMP
   7 +       select FIQ
   8         help
   9           Support for Cavium Networks CNS3XXX platform.
  10
  11 --- a/arch/arm/kernel/fiq.c
  12 +++ b/arch/arm/kernel/fiq.c
  13 @@ -49,6 +49,8 @@
  14
  15  static unsigned long no_fiq_insn;
  16
  17 +unsigned int fiq_number[2] = {0, 0};
  18 +
  19  /* Default reacquire function
  20   * - we always relinquish FIQ control
  21   * - we always reacquire FIQ control
  22 @@ -70,9 +72,12 @@ static struct fiq_handler *current_fiq =
  23
  24  int show_fiq_list(struct seq_file *p, int prec)
  25  {
  26 -       if (current_fiq != &default_owner)
  27 -               seq_printf(p, "%*s:              %s\n", prec, "FIQ",
  28 -                       current_fiq->name);
  29 +       if (current_fiq != &default_owner) {
  30 +               seq_printf(p, "%*s: ", prec, "FIQ");
  31 +               seq_printf(p, "%10u ", fiq_number[0]);
  32 +               seq_printf(p, "%10u ", fiq_number[1]);
  33 +               seq_printf(p, "      %s\n", current_fiq->name);
  34 +       }
  35
  36         return 0;
  37  }
  38 --- a/arch/arm/mach-cns3xxx/Makefile
  39 +++ b/arch/arm/mach-cns3xxx/Makefile
  40 @@ -1,5 +1,5 @@
  41  obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o devices.o
  42  obj-$(CONFIG_PCI)                      += pcie.o
  43  obj-$(CONFIG_MACH_CNS3420VB)           += cns3420vb.o
  44 -obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o
  45 +obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o cns3xxx_fiq.o
  46  obj-$(CONFIG_HOTPLUG_CPU)              += hotplug.o
  47 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
  48 +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
  49 @@ -294,6 +294,7 @@
  50  #define MISC_PCIE_INT_MASK(x)                  MISC_MEM_MAP(0x978 + (x) * 0x100)
  51  #define MISC_PCIE_INT_STATUS(x)                        MISC_MEM_MAP(0x97C + (x) * 0x100)
  52
  53 +#define MISC_FIQ_CPU(x)                                MISC_MEM_MAP(0xA58 - (x) * 0x4)
  54  /*
  55   * Power management and clock control
  56   */
  57 --- a/arch/arm/mach-cns3xxx/include/mach/irqs.h
  58 +++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h
  59 @@ -14,6 +14,7 @@
  60  #define IRQ_LOCALTIMER         29
  61  #define IRQ_LOCALWDOG          30
  62  #define IRQ_TC11MP_GIC_START   32
  63 +#define FIQ_START 0
  64
  65  #include <mach/cns3xxx.h>
  66
  67 --- a/arch/arm/mm/Kconfig
  68 +++ b/arch/arm/mm/Kconfig
  69 @@ -773,7 +773,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
  70
  71  config DMA_CACHE_RWFO
  72         bool "Enable read/write for ownership DMA cache maintenance"
  73 -       depends on CPU_V6K && SMP
  74 +       depends on CPU_V6K && SMP && !ARCH_CNS3XXX
  75         default y
  76         help
  77           The Snoop Control Unit on ARM11MPCore does not detect the