target/linux/cns3xxx/patches-3.1/100-laguna_support.patch

   1 --- /dev/null
   2 +++ b/arch/arm/mach-cns3xxx/laguna.c
   3 @@ -0,0 +1,761 @@
   4 +/*
   5 + * Gateworks Corporation Laguna Platform
   6 + *
   7 + * Copyright 2000 Deep Blue Solutions Ltd
   8 + * Copyright 2008 ARM Limited
   9 + * Copyright 2008 Cavium Networks
  10 + *               Scott Shu
  11 + * Copyright 2010 MontaVista Software, LLC.
  12 + *               Anton Vorontsov <avorontsov@mvista.com>
  13 + * Copyright 2011 Gateworks Corporation
  14 + *               Chris Lang <clang@gateworks.com>
  15 + *
  16 + * This file is free software; you can redistribute it and/or modify
  17 + * it under the terms of the GNU General Public License, Version 2, as
  18 + * published by the Free Software Foundation.
  19 + */
  20 +
  21 +#include <linux/init.h>
  22 +#include <linux/kernel.h>
  23 +#include <linux/compiler.h>
  24 +#include <linux/io.h>
  25 +#include <linux/dma-mapping.h>
  26 +#include <linux/serial_core.h>
  27 +#include <linux/serial_8250.h>
  28 +#include <linux/platform_device.h>
  29 +#include <linux/mtd/mtd.h>
  30 +#include <linux/mtd/physmap.h>
  31 +#include <linux/mtd/partitions.h>
  32 +#include <linux/leds.h>
  33 +#include <linux/i2c.h>
  34 +#include <linux/i2c/at24.h>
  35 +#include <linux/i2c/pca953x.h>
  36 +#include <linux/spi/spi.h>
  37 +#include <linux/spi/flash.h>
  38 +#include <linux/if_ether.h>
  39 +#include <asm/setup.h>
  40 +#include <asm/mach-types.h>
  41 +#include <asm/mach/arch.h>
  42 +#include <asm/mach/map.h>
  43 +#include <asm/mach/time.h>
  44 +#include <mach/cns3xxx.h>
  45 +#include <mach/irqs.h>
  46 +#include <mach/platform.h>
  47 +#include <mach/pm.h>
  48 +#include "core.h"
  49 +#include "devices.h"
  50 +
  51 +// Config 1 Bitmap
  52 +#define ETH0_LOAD           BIT(0)
  53 +#define ETH1_LOAD           BIT(1)
  54 +#define ETH2_LOAD           BIT(2)
  55 +#define SATA0_LOAD          BIT(3)
  56 +#define SATA1_LOAD          BIT(4)
  57 +#define PCM_LOAD            BIT(5)
  58 +#define I2S_LOAD            BIT(6)
  59 +#define SPI0_LOAD           BIT(7)
  60 +#define SPI1_LOAD           BIT(8)
  61 +#define PCIE0_LOAD          BIT(9)
  62 +#define PCIE1_LOAD          BIT(10)
  63 +#define USB0_LOAD           BIT(11)
  64 +#define USB1_LOAD           BIT(12)
  65 +#define USB1_ROUTE          BIT(13)
  66 +#define SD_LOAD             BIT(14)
  67 +#define UART0_LOAD          BIT(15)
  68 +#define UART1_LOAD          BIT(16)
  69 +#define UART2_LOAD          BIT(17)
  70 +#define MPCI0_LOAD          BIT(18)
  71 +#define MPCI1_LOAD          BIT(19)
  72 +#define MPCI2_LOAD          BIT(20)
  73 +#define MPCI3_LOAD          BIT(21)
  74 +#define FP_BUT_LOAD         BIT(22)
  75 +#define FP_BUT_HEADER_LOAD  BIT(23)
  76 +#define FP_LED_LOAD         BIT(24)
  77 +#define FP_LED_HEADER_LOAD  BIT(25)
  78 +#define FP_TAMPER_LOAD      BIT(26)
  79 +#define HEADER_33V_LOAD     BIT(27)
  80 +#define SATA_POWER_LOAD     BIT(28)
  81 +#define FP_POWER_LOAD       BIT(29)
  82 +#define GPIO_HEADER_LOAD    BIT(30)
  83 +#define GSP_BAT_LOAD        BIT(31)
  84 +
  85 +// Config 2 Bitmap
  86 +#define FAN_LOAD            BIT(0)
  87 +#define SPI_FLASH_LOAD      BIT(1)
  88 +#define NOR_FLASH_LOAD      BIT(2)
  89 +#define GPS_LOAD            BIT(3)
  90 +#define SUPPLY_5V_LOAD      BIT(6)
  91 +#define SUPPLY_33V_LOAD     BIT(7)
  92 +
  93 +struct laguna_board_info {
  94 +       char model[16];
  95 +       u32 config_bitmap;
  96 +       u32 config2_bitmap;
  97 +       u8 nor_flash_size;
  98 +       u8 spi_flash_size;
  99 +};
 100 +
 101 +static struct laguna_board_info laguna_info __initdata;
 102 +
 103 +/*
 104 + * NOR Flash
 105 + */
 106 +static struct mtd_partition laguna_nor_partitions[] = {
 107 +       {
 108 +               .name           = "uboot",
 109 +               .size           = SZ_256K,
 110 +               .offset         = 0,
 111 +               .mask_flags     = MTD_WRITEABLE,
 112 +       }, {
 113 +               .name           = "params",
 114 +               .size           = SZ_128K,
 115 +               .offset         = SZ_256K,
 116 +       }, {
 117 +               .name           = "kernel",
 118 +               .size           = SZ_2M,
 119 +               .offset         = SZ_256K + SZ_128K,
 120 +       }, {
 121 +               .name           = "rootfs",
 122 +               .size           = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
 123 +               .offset         = SZ_256K + SZ_128K + SZ_2M,
 124 +       },
 125 +};
 126 +
 127 +static struct physmap_flash_data laguna_nor_pdata = {
 128 +       .width = 2,
 129 +       .parts = laguna_nor_partitions,
 130 +       .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
 131 +};
 132 +
 133 +static struct resource laguna_nor_res = {
 134 +       .start = CNS3XXX_FLASH_BASE,
 135 +       .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
 136 +       .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 137 +};
 138 +
 139 +static struct platform_device laguna_nor_pdev = {
 140 +       .name = "physmap-flash",
 141 +       .id = 0,
 142 +       .resource = &laguna_nor_res,
 143 +       .num_resources = 1,
 144 +       .dev = {
 145 +               .platform_data = &laguna_nor_pdata,
 146 +       },
 147 +};
 148 +
 149 +/*
 150 + * SPI
 151 + */
 152 +static struct mtd_partition laguna_spi_partitions[] = {
 153 +       {
 154 +               .name           = "uboot",
 155 +               .size           = SZ_256K,
 156 +               .offset         = 0,
 157 +               .mask_flags     = MTD_WRITEABLE,
 158 +       }, {
 159 +               .name           = "params",
 160 +               .size           = SZ_256K,
 161 +               .offset         = SZ_256K,
 162 +       }, {
 163 +               .name           = "kernel",
 164 +               .size           = SZ_1M + SZ_512K,
 165 +               .offset         = SZ_512K,
 166 +       }, {
 167 +               .name           = "rootfs",
 168 +               .size           = SZ_16M - SZ_2M,
 169 +               .offset         = SZ_2M,
 170 +       },
 171 +};
 172 +
 173 +static struct flash_platform_data laguna_spi_pdata = {
 174 +       .parts = laguna_spi_partitions,
 175 +       .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
 176 +};
 177 +
 178 +static struct spi_board_info __initdata laguna_spi_devices[] = {
 179 +       {
 180 +               .modalias = "m25p80",
 181 +               .platform_data = &laguna_spi_pdata,
 182 +               .max_speed_hz = 50000000,
 183 +               .bus_num = 1,
 184 +               .chip_select = 0,
 185 +       },
 186 +};
 187 +
 188 +static struct platform_device laguna_spi_controller = {
 189 +       .name = "cns3xxx_spi",
 190 +};
 191 +
 192 +/*
 193 + * LED's
 194 + */
 195 +static struct gpio_led laguna_gpio_leds[] = {
 196 +       {
 197 +               .name = "user1", /* Green Led */
 198 +               .gpio = 115,
 199 +               .active_low = 1,
 200 +       },{
 201 +               .name = "user2", /* Red Led */
 202 +               .gpio = 114,
 203 +               .active_low = 1,
 204 +       },{
 205 +               .name = "pwr1", /* Green Led */
 206 +               .gpio = 116,
 207 +               .active_low = 1,
 208 +       },{
 209 +               .name = "pwr2", /* Yellow Led */
 210 +               .gpio = 117,
 211 +               .active_low = 1,
 212 +       },{
 213 +               .name = "txd1", /* Green Led */
 214 +               .gpio = 118,
 215 +               .active_low = 1,
 216 +       },{
 217 +               .name = "txd2", /* Yellow Led */
 218 +               .gpio = 119,
 219 +               .active_low = 1,
 220 +       },{
 221 +               .name = "rxd1", /* Green Led */
 222 +               .gpio = 120,
 223 +               .active_low = 1,
 224 +       },{
 225 +               .name = "rxd2", /* Yellow Led */
 226 +               .gpio = 121,
 227 +               .active_low = 1,
 228 +       },{
 229 +               .name = "ser1", /* Green Led */
 230 +               .gpio = 122,
 231 +               .active_low = 1,
 232 +       },{
 233 +               .name = "ser2", /* Yellow Led */
 234 +               .gpio = 123,
 235 +               .active_low = 1,
 236 +       },{
 237 +               .name = "enet1", /* Green Led */
 238 +               .gpio = 124,
 239 +               .active_low = 1,
 240 +       },{
 241 +               .name = "enet2", /* Yellow Led */
 242 +               .gpio = 125,
 243 +               .active_low = 1,
 244 +       },{
 245 +               .name = "sig1_1", /* Green Led */
 246 +               .gpio = 126,
 247 +               .active_low = 1,
 248 +       },{
 249 +               .name = "sig1_2", /* Yellow Led */
 250 +               .gpio = 127,
 251 +               .active_low = 1,
 252 +       },{
 253 +               .name = "sig2_1", /* Green Led */
 254 +               .gpio = 128,
 255 +               .active_low = 1,
 256 +       },{
 257 +               .name = "sig2_2", /* Yellow Led */
 258 +               .gpio = 129,
 259 +               .active_low = 1,
 260 +       },{
 261 +               .name = "sig3_1", /* Green Led */
 262 +               .gpio = 130,
 263 +               .active_low = 1,
 264 +       },{
 265 +               .name = "sig3_2", /* Yellow Led */
 266 +               .gpio = 131,
 267 +               .active_low = 1,
 268 +       },{
 269 +               .name = "net1", /*Green Led */
 270 +               .gpio = 109,
 271 +               .active_low = 1,
 272 +       },{
 273 +               .name = "net2", /* Red Led */
 274 +               .gpio = 110,
 275 +               .active_low = 1,
 276 +       },{
 277 +               .name = "mod1", /* Green Led */
 278 +               .gpio = 111,
 279 +               .active_low = 1,
 280 +       },{
 281 +               .name = "mod2", /* Red Led */
 282 +               .gpio = 112,
 283 +               .active_low = 1,
 284 +       },
 285 +};
 286 +
 287 +static struct gpio_led_platform_data laguna_gpio_leds_data = {
 288 +       .num_leds = 22,
 289 +       .leds = laguna_gpio_leds,
 290 +};
 291 +
 292 +static struct platform_device laguna_gpio_leds_device = {
 293 +       .name = "leds-gpio",
 294 +       .id = -1,
 295 +       .dev.platform_data = &laguna_gpio_leds_data,
 296 +};
 297 +
 298 +/*
 299 + * Ethernet
 300 + */
 301 +static struct cns3xxx_plat_info laguna_net_data = {
 302 +       .ports = 0,
 303 +       .phy = {
 304 +               0,
 305 +               1,
 306 +               2,
 307 +       },
 308 +};
 309 +
 310 +static struct platform_device laguna_net_device = {
 311 +       .name = "cns3xxx_eth",
 312 +       .id = 0,
 313 +       .dev.platform_data = &laguna_net_data,
 314 +};
 315 +
 316 +/*
 317 + * UART
 318 + */
 319 +static void __init laguna_early_serial_setup(void)
 320 +{
 321 +#ifdef CONFIG_SERIAL_8250_CONSOLE
 322 +       static struct uart_port laguna_serial_port = {
 323 +               .membase        = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
 324 +               .mapbase        = CNS3XXX_UART0_BASE,
 325 +               .irq            = IRQ_CNS3XXX_UART0,
 326 +               .iotype         = UPIO_MEM,
 327 +               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
 328 +               .regshift       = 2,
 329 +               .uartclk        = 24000000,
 330 +               .line           = 0,
 331 +               .type           = PORT_16550A,
 332 +               .fifosize       = 16,
 333 +       };
 334 +
 335 +       early_serial_setup(&laguna_serial_port);
 336 +#endif
 337 +}
 338 +
 339 +static struct resource laguna_uart_resources[] = {
 340 +       {
 341 +               .start = CNS3XXX_UART0_BASE,
 342 +               .end   = CNS3XXX_UART0_BASE + SZ_4K - 1,
 343 +               .flags    = IORESOURCE_MEM
 344 +       },{
 345 +               .start = CNS3XXX_UART2_BASE,
 346 +               .end   = CNS3XXX_UART2_BASE + SZ_4K - 1,
 347 +               .flags    = IORESOURCE_MEM
 348 +       },{
 349 +               .start = CNS3XXX_UART2_BASE,
 350 +               .end   = CNS3XXX_UART2_BASE + SZ_4K - 1,
 351 +               .flags    = IORESOURCE_MEM
 352 +       },
 353 +};
 354 +
 355 +static struct plat_serial8250_port laguna_uart_data[] = {
 356 +       {
 357 +               .membase        = (char*) (CNS3XXX_UART0_BASE_VIRT),
 358 +               .mapbase        = (CNS3XXX_UART0_BASE),
 359 +               .irq            = IRQ_CNS3XXX_UART0,
 360 +               .iotype         = UPIO_MEM,
 361 +               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
 362 +               .regshift       = 2,
 363 +               .uartclk        = 24000000,
 364 +               .type           = PORT_16550A,
 365 +       },{
 366 +               .membase        = (char*) (CNS3XXX_UART1_BASE_VIRT),
 367 +               .mapbase        = (CNS3XXX_UART1_BASE),
 368 +               .irq            = IRQ_CNS3XXX_UART1,
 369 +               .iotype         = UPIO_MEM,
 370 +               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
 371 +               .regshift       = 2,
 372 +               .uartclk        = 24000000,
 373 +               .type           = PORT_16550A,
 374 +       },{
 375 +               .membase        = (char*) (CNS3XXX_UART2_BASE_VIRT),
 376 +               .mapbase        = (CNS3XXX_UART2_BASE),
 377 +               .irq            = IRQ_CNS3XXX_UART2,
 378 +               .iotype         = UPIO_MEM,
 379 +               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
 380 +               .regshift       = 2,
 381 +               .uartclk        = 24000000,
 382 +               .type           = PORT_16550A,
 383 +       },
 384 +};
 385 +
 386 +static struct platform_device laguna_uart = {
 387 +       .name     = "serial8250",
 388 +       .id     = PLAT8250_DEV_PLATFORM,
 389 +       .dev.platform_data  = laguna_uart_data,
 390 +       .num_resources    = 3,
 391 +       .resource   = laguna_uart_resources
 392 +};
 393 +
 394 +/*
 395 + * USB
 396 + */
 397 +static struct resource cns3xxx_usb_ehci_resources[] = {
 398 +       [0] = {
 399 +               .start = CNS3XXX_USB_BASE,
 400 +               .end   = CNS3XXX_USB_BASE + SZ_16M - 1,
 401 +               .flags = IORESOURCE_MEM,
 402 +       },
 403 +       [1] = {
 404 +               .start = IRQ_CNS3XXX_USB_EHCI,
 405 +               .flags = IORESOURCE_IRQ,
 406 +       },
 407 +};
 408 +
 409 +static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
 410 +
 411 +static struct platform_device cns3xxx_usb_ehci_device = {
 412 +       .name          = "cns3xxx-ehci",
 413 +       .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
 414 +       .resource      = cns3xxx_usb_ehci_resources,
 415 +       .dev           = {
 416 +               .dma_mask          = &cns3xxx_usb_ehci_dma_mask,
 417 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 418 +       },
 419 +};
 420 +
 421 +static struct resource cns3xxx_usb_ohci_resources[] = {
 422 +       [0] = {
 423 +               .start = CNS3XXX_USB_OHCI_BASE,
 424 +               .end   = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
 425 +               .flags = IORESOURCE_MEM,
 426 +       },
 427 +       [1] = {
 428 +               .start = IRQ_CNS3XXX_USB_OHCI,
 429 +               .flags = IORESOURCE_IRQ,
 430 +       },
 431 +};
 432 +
 433 +static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
 434 +
 435 +static struct platform_device cns3xxx_usb_ohci_device = {
 436 +       .name          = "cns3xxx-ohci",
 437 +       .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
 438 +       .resource      = cns3xxx_usb_ohci_resources,
 439 +       .dev           = {
 440 +               .dma_mask          = &cns3xxx_usb_ohci_dma_mask,
 441 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 442 +       },
 443 +};
 444 +
 445 +static struct resource cns3xxx_usb_otg_resources[] = {
 446 +       [0] = {
 447 +               .start = CNS3XXX_USBOTG_BASE,
 448 +               .end   = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
 449 +               .flags = IORESOURCE_MEM,
 450 +       },
 451 +       [1] = {
 452 +               .start = IRQ_CNS3XXX_USB_OTG,
 453 +               .flags = IORESOURCE_IRQ,
 454 +       },
 455 +};
 456 +
 457 +static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
 458 +
 459 +static struct platform_device cns3xxx_usb_otg_device = {
 460 +       .name          = "dwc_otg",
 461 +       .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
 462 +       .resource      = cns3xxx_usb_otg_resources,
 463 +       .dev           = {
 464 +               .dma_mask          = &cns3xxx_usb_otg_dma_mask,
 465 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 466 +       },
 467 +};
 468 +
 469 +/*
 470 + * I2C
 471 + */
 472 +static struct resource laguna_i2c_resource[] = {
 473 +       {
 474 +               .start    = CNS3XXX_SSP_BASE + 0x20,
 475 +               .end      = 0x7100003f,
 476 +               .flags    = IORESOURCE_MEM,
 477 +       },{
 478 +               .start    = IRQ_CNS3XXX_I2C,
 479 +               .flags    = IORESOURCE_IRQ,
 480 +       },
 481 +};
 482 +
 483 +static struct platform_device laguna_i2c_controller = {
 484 +       .name   = "cns3xxx-i2c",
 485 +       .num_resources  = 2,
 486 +       .resource = laguna_i2c_resource,
 487 +};
 488 +
 489 +static struct memory_accessor *at24_mem_acc;
 490 +
 491 +static void at24_setup(struct memory_accessor *mem_acc, void *context)
 492 +{
 493 +       char buf[8];
 494 +
 495 +       at24_mem_acc = mem_acc;
 496 +
 497 +       /* Read MAC addresses */
 498 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
 499 +               memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
 500 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
 501 +               memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
 502 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
 503 +               memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
 504 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
 505 +               memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
 506 +
 507 +       /* Read out Model Information */
 508 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
 509 +               memcpy(&laguna_info.model, buf, 16);
 510 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
 511 +               memcpy(&laguna_info.nor_flash_size, buf, 1);
 512 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
 513 +               memcpy(&laguna_info.spi_flash_size, buf, 1);
 514 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
 515 +               memcpy(&laguna_info.config_bitmap, buf, 4);
 516 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
 517 +               memcpy(&laguna_info.config2_bitmap, buf, 4);
 518 +};
 519 +
 520 +static struct at24_platform_data laguna_eeprom_info = {
 521 +       .byte_len = 1024,
 522 +       .page_size = 16,
 523 +       .flags = AT24_FLAG_READONLY,
 524 +       .setup = at24_setup,
 525 +};
 526 +
 527 +static struct pca953x_platform_data laguna_pca_data = {
 528 +       .gpio_base = 100,
 529 +       .irq_base = -1,
 530 +};
 531 +
 532 +static struct pca953x_platform_data laguna_pca2_data = {
 533 +       .gpio_base = 116,
 534 +       .irq_base = -1,
 535 +};
 536 +
 537 +static struct i2c_board_info __initdata laguna_i2c_devices[] = {
 538 +       {
 539 +               I2C_BOARD_INFO("pca9555", 0x23),
 540 +               .platform_data = &laguna_pca_data,
 541 +       },{
 542 +               I2C_BOARD_INFO("pca9555", 0x27),
 543 +               .platform_data = &laguna_pca2_data,
 544 +       },{
 545 +               I2C_BOARD_INFO("gsp", 0x29),
 546 +       },{
 547 +               I2C_BOARD_INFO ("24c08",0x50),
 548 +               .platform_data = &laguna_eeprom_info,
 549 +       },{
 550 +               I2C_BOARD_INFO("ds1672", 0x68),
 551 +       },
 552 +};
 553 +
 554 +/*
 555 + * Watchdog
 556 + */
 557 +
 558 +static struct resource laguna_watchdog_resources[] = {
 559 +       [0] = {
 560 +               .start  = CNS3XXX_TC11MP_TWD_BASE,
 561 +               .end    = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
 562 +               .flags  = IORESOURCE_MEM,
 563 +       },
 564 +       [1] = {
 565 +               .start  = IRQ_LOCALWDOG,
 566 +               .end    = IRQ_LOCALWDOG,
 567 +               .flags  = IORESOURCE_IRQ,
 568 +       }
 569 +};
 570 +
 571 +static struct platform_device laguna_watchdog = {
 572 +       .name           = "mpcore_wdt",
 573 +       .id             = -1,
 574 +       .num_resources  = ARRAY_SIZE(laguna_watchdog_resources),
 575 +       .resource       = laguna_watchdog_resources,
 576 +};
 577 +
 578 +/*
 579 + * Initialization
 580 + */
 581 +
 582 +static void __init laguna_init(void)
 583 +{
 584 +       cns3xxx_l2x0_init();
 585 +
 586 +       platform_device_register(&laguna_watchdog);
 587 +
 588 +       platform_device_register(&laguna_i2c_controller);
 589 +
 590 +       i2c_register_board_info(0, laguna_i2c_devices,
 591 +                       ARRAY_SIZE(laguna_i2c_devices));
 592 +
 593 +       pm_power_off = cns3xxx_power_off;
 594 +}
 595 +
 596 +static struct map_desc laguna_io_desc[] __initdata = {
 597 +       {
 598 +               .virtual        = CNS3XXX_UART0_BASE_VIRT,
 599 +               .pfn            = __phys_to_pfn(CNS3XXX_UART0_BASE),
 600 +               .length         = SZ_4K,
 601 +               .type           = MT_DEVICE,
 602 +       },{
 603 +               .virtual        = CNS3XXX_UART1_BASE_VIRT,
 604 +               .pfn            = __phys_to_pfn(CNS3XXX_UART1_BASE),
 605 +               .length         = SZ_4K,
 606 +               .type           = MT_DEVICE,
 607 +       },{
 608 +               .virtual        = CNS3XXX_UART2_BASE_VIRT,
 609 +               .pfn            = __phys_to_pfn(CNS3XXX_UART2_BASE),
 610 +               .length         = SZ_4K,
 611 +               .type           = MT_DEVICE,
 612 +       },
 613 +};
 614 +
 615 +static void __init laguna_map_io(void)
 616 +{
 617 +       cns3xxx_map_io();
 618 +       iotable_init(laguna_io_desc, ARRAY_SIZE(laguna_io_desc));
 619 +       laguna_early_serial_setup();
 620 +}
 621 +
 622 +static int __init laguna_model_setup(void)
 623 +{
 624 +       u32 __iomem *mem;
 625 +       u32 reg;
 626 +       u8 pcie_bitmap = 0;
 627 +
 628 +       printk("Running on Gateworks Laguna %s\n", laguna_info.model);
 629 +
 630 +       if (strncmp(laguna_info.model, "GW", 2) == 0) {
 631 +               if (laguna_info.config_bitmap & ETH0_LOAD)
 632 +                       laguna_net_data.ports |= BIT(0);
 633 +               if (laguna_info.config_bitmap & ETH1_LOAD)
 634 +                       laguna_net_data.ports |= BIT(1);
 635 +               if (laguna_info.config_bitmap & ETH2_LOAD)
 636 +                       laguna_net_data.ports |= BIT(2);
 637 +               if (laguna_net_data.ports)
 638 +                       platform_device_register(&laguna_net_device);
 639 +
 640 +               if ((laguna_info.config_bitmap & SATA0_LOAD) ||
 641 +                   (laguna_info.config_bitmap & SATA1_LOAD))
 642 +                       cns3xxx_ahci_init();
 643 +
 644 +               if (laguna_info.config_bitmap & (PCIE0_LOAD))
 645 +                       pcie_bitmap |= 0x1;
 646 +
 647 +               if (laguna_info.config_bitmap & (PCIE1_LOAD))
 648 +                       pcie_bitmap |= 0x2;
 649 +
 650 +               cns3xxx_pcie_init(pcie_bitmap);
 651 +
 652 +               if (laguna_info.config_bitmap & (USB0_LOAD)) {
 653 +                       cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
 654 +
 655 +                       /* DRVVBUS pins share with GPIOA */
 656 +                       mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
 657 +                       reg = __raw_readl(mem);
 658 +                       reg |= 0x8;
 659 +                       __raw_writel(reg, mem);
 660 +
 661 +                       /* Enable OTG */
 662 +                       mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
 663 +                       reg = __raw_readl(mem);
 664 +                       reg &= ~(1 << 10);
 665 +                       __raw_writel(reg, mem);
 666 +
 667 +                       platform_device_register(&cns3xxx_usb_otg_device);
 668 +               }
 669 +
 670 +               if (laguna_info.config_bitmap & (USB1_LOAD)) {
 671 +                       platform_device_register(&cns3xxx_usb_ehci_device);
 672 +                       platform_device_register(&cns3xxx_usb_ohci_device);
 673 +               }
 674 +
 675 +               if (laguna_info.config_bitmap & (SD_LOAD))
 676 +                       cns3xxx_sdhci_init();
 677 +
 678 +               if (laguna_info.config_bitmap & (UART0_LOAD))
 679 +                       laguna_uart.num_resources = 1;
 680 +               if (laguna_info.config_bitmap & (UART1_LOAD))
 681 +                       laguna_uart.num_resources = 2;
 682 +               if (laguna_info.config_bitmap & (UART2_LOAD))
 683 +                       laguna_uart.num_resources = 3;
 684 +               platform_device_register(&laguna_uart);
 685 +
 686 +               if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
 687 +                       switch (laguna_info.nor_flash_size) {
 688 +                               case 1:
 689 +                                       laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
 690 +                                       laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
 691 +                               break;
 692 +                               case 2:
 693 +                                       laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
 694 +                                       laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
 695 +                               break;
 696 +                               case 3:
 697 +                                       laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
 698 +                                       laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
 699 +                               break;
 700 +                               case 4:
 701 +                                       laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
 702 +                                       laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
 703 +                               break;
 704 +                               case 5:
 705 +                                       laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
 706 +                                       laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
 707 +                               break;
 708 +                       }
 709 +                       platform_device_register(&laguna_nor_pdev);
 710 +               }
 711 +
 712 +               if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
 713 +                       switch (laguna_info.spi_flash_size) {
 714 +                               case 1:
 715 +                                       laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
 716 +                               break;
 717 +                               case 2:
 718 +                                       laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
 719 +                               break;
 720 +                               case 3:
 721 +                                       laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
 722 +                               break;
 723 +                               case 4:
 724 +                                       laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
 725 +                               break;
 726 +                               case 5:
 727 +                                       laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
 728 +                               break;
 729 +                       }
 730 +                       spi_register_board_info(laguna_spi_devices, ARRAY_SIZE(laguna_spi_devices));
 731 +               }
 732 +
 733 +               if ((laguna_info.config_bitmap & SPI0_LOAD) ||
 734 +                   (laguna_info.config_bitmap & SPI1_LOAD))
 735 +                       platform_device_register(&laguna_spi_controller);
 736 +
 737 +               /*
 738 +                * Do any model specific setup not known by the bitmap by matching
 739 +                *  the first 6 characters of the model name
 740 +                */
 741 +
 742 +               if (strncmp(laguna_info.model, "GW2388", 6) == 0) {
 743 +                       laguna_gpio_leds_data.num_leds = 2;
 744 +               } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
 745 +                       laguna_gpio_leds[0].gpio = 107;
 746 +                       laguna_gpio_leds[1].gpio = 106;
 747 +                       laguna_gpio_leds_data.num_leds = 2;
 748 +               }
 749 +               platform_device_register(&laguna_gpio_leds_device);
 750 +       } else {
 751 +               // Do some defaults here, not sure what yet
 752 +       }
 753 +       return 0;
 754 +}
 755 +
 756 +late_initcall(laguna_model_setup);
 757 +
 758 +MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
 759 +       .boot_params    = 0x00000100,
 760 +       .map_io         = laguna_map_io,
 761 +       .init_irq       = cns3xxx_init_irq,
 762 +       .timer          = &cns3xxx_timer,
 763 +       .init_machine   = laguna_init,
 764 +MACHINE_END
 765 --- a/arch/arm/mach-cns3xxx/Kconfig
 766 +++ b/arch/arm/mach-cns3xxx/Kconfig
 767 @@ -11,4 +11,14 @@ config MACH_CNS3420VB
 768           This is a platform with an on-board ARM11 MPCore and has support
 769           for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
 770
 771 +config MACH_GW2388
 772 +       bool "Support for Gateworks Laguna Platform"
 773 +       select HAVE_ARM_SCU if SMP
 774 +       select MIGHT_HAVE_PCI
 775 +       help
 776 +         Include support for the Gateworks Laguna Platform
 777 +
 778 +         This is a platform with an on-board ARM11 MPCore and has support
 779 +         for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
 780 +
 781  endmenu
 782 --- a/arch/arm/mach-cns3xxx/core.c
 783 +++ b/arch/arm/mach-cns3xxx/core.c
 784 @@ -16,6 +16,7 @@
 785  #include <asm/mach/time.h>
 786  #include <asm/mach/irq.h>
 787  #include <asm/hardware/gic.h>
 788 +#include <asm/smp_twd.h>
 789  #include <asm/hardware/cache-l2x0.h>
 790  #include <mach/cns3xxx.h>
 791  #include "core.h"
 792 @@ -61,11 +62,24 @@ static struct map_desc cns3xxx_io_desc[]
 793                 .pfn            = __phys_to_pfn(CNS3XXX_PM_BASE),
 794                 .length         = SZ_4K,
 795                 .type           = MT_DEVICE,
 796 +       }, {
 797 +               .virtual        = CNS3XXX_SWITCH_BASE_VIRT,
 798 +               .pfn            = __phys_to_pfn(CNS3XXX_SWITCH_BASE),
 799 +               .length         = SZ_4K,
 800 +               .type           = MT_DEVICE,
 801 +       }, {
 802 +               .virtual        = CNS3XXX_SSP_BASE_VIRT,
 803 +               .pfn            = __phys_to_pfn(CNS3XXX_SSP_BASE),
 804 +               .length         = SZ_4K,
 805 +               .type           = MT_DEVICE,
 806         },
 807  };
 808
 809  void __init cns3xxx_map_io(void)
 810  {
 811 +#ifdef CONFIG_LOCAL_TIMERS
 812 +       twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
 813 +#endif
 814         iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
 815  }
 816
 817 --- a/arch/arm/Kconfig
 818 +++ b/arch/arm/Kconfig
 819 @@ -329,6 +329,7 @@ config ARCH_CLPS711X
 820  config ARCH_CNS3XXX
 821         bool "Cavium Networks CNS3XXX family"
 822         select CPU_V6K
 823 +       select ARCH_WANT_OPTIONAL_GPIOLIB
 824         select GENERIC_CLOCKEVENTS
 825         select ARM_GIC
 826         select MIGHT_HAVE_PCI
 827 --- /dev/null
 828 +++ b/arch/arm/mach-cns3xxx/include/mach/gpio.h
 829 @@ -0,0 +1,98 @@
 830 +/*
 831 + * arch/arm/mach-cns3xxx/include/mach/gpio.h
 832 + *
 833 + * CNS3xxx GPIO wrappers for arch-neutral GPIO calls
 834 + *
 835 + * Copyright 2011 Gateworks Corporation
 836 + *               Chris Lang <clang@gateworks.com>
 837 + *
 838 + * Based on IXP implementation by Milan Svoboda <msvoboda@ra.rockwell.com>
 839 + * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
 840 + *
 841 + * This program is free software; you can redistribute it and/or modify
 842 + * it under the terms of the GNU General Public License as published by
 843 + * the Free Software Foundation; either version 2 of the License, or
 844 + * (at your option) any later version.
 845 + *
 846 + * This program is distributed in the hope that it will be useful,
 847 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 848 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 849 + * GNU General Public License for more details.
 850 + *
 851 + * You should have received a copy of the GNU General Public License
 852 + * along with this program; if not, write to the Free Software
 853 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 854 + *
 855 + */
 856 +
 857 +#ifndef __ASM_ARCH_CNS3XXX_GPIO_H
 858 +#define __ASM_ARCH_CNS3XXX_GPIO_H
 859 +
 860 +#include <linux/kernel.h>
 861 +#include <linux/io.h>
 862 +#include <mach/platform.h>
 863 +#include <asm-generic/gpio.h>                  /* cansleep wrappers */
 864 +
 865 +#define NR_BUILTIN_GPIO 64
 866 +
 867 +#define CNS3XXX_GPIO_IN    0x0
 868 +#define CNS3XXX_GPIO_OUT   0x1
 869 +
 870 +#define CNS3XXX_GPIO_LO   0
 871 +#define CNS3XXX_GPIO_HI   1
 872 +
 873 +#define CNS3XXX_GPIO_OUTPUT         0x00
 874 +#define CNS3XXX_GPIO_INPUT          0x04
 875 +#define CNS3XXX_GPIO_DIR            0x08
 876 +#define CNS3XXX_GPIO_SET            0x10
 877 +#define CNS3XXX_GPIO_CLEAR          0x14
 878 +
 879 +static inline void gpio_line_get(u8 line, int *value)
 880 +{
 881 +       if (line < 32)
 882 +               *value = ((__raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> line) & 0x1);
 883 +       else
 884 +               *value = ((__raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> (line - 32)) & 0x1);
 885 +}
 886 +
 887 +static inline void gpio_line_set(u8 line, int value)
 888 +{
 889 +       if (line < 32) {
 890 +               if (value)
 891 +                       __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_SET);
 892 +               else
 893 +                       __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
 894 +       } else {
 895 +               if (value)
 896 +                       __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_SET);
 897 +               else
 898 +                       __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
 899 +       }
 900 +}
 901 +
 902 +static inline int gpio_get_value(unsigned gpio)
 903 +{
 904 +       if (gpio < NR_BUILTIN_GPIO)
 905 +       {
 906 +               int value;
 907 +               gpio_line_get(gpio, &value);
 908 +               return value;
 909 +       }
 910 +       else
 911 +               return __gpio_get_value(gpio);
 912 +}
 913 +
 914 +static inline void gpio_set_value(unsigned gpio, int value)
 915 +{
 916 +       if (gpio < NR_BUILTIN_GPIO)
 917 +               gpio_line_set(gpio, value);
 918 +       else
 919 +               __gpio_set_value(gpio, value);
 920 +}
 921 +
 922 +#define gpio_cansleep __gpio_cansleep
 923 +
 924 +extern int gpio_to_irq(int gpio);
 925 +extern int irq_to_gpio(int gpio);
 926 +
 927 +#endif
 928 --- a/arch/arm/mach-cns3xxx/Makefile
 929 +++ b/arch/arm/mach-cns3xxx/Makefile
 930 @@ -1,6 +1,7 @@
 931  obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o devices.o
 932  obj-$(CONFIG_PCI)                      += pcie.o
 933  obj-$(CONFIG_MACH_CNS3420VB)           += cns3420vb.o
 934 +obj-$(CONFIG_MACH_GW2388)              += laguna.o
 935  obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o
 936  obj-$(CONFIG_HOTPLUG_CPU)              += hotplug.o
 937  obj-$(CONFIG_LOCAL_TIMERS)             += localtimer.o
 938 --- a/arch/arm/mach-cns3xxx/pcie.c
 939 +++ b/arch/arm/mach-cns3xxx/pcie.c
 940 @@ -365,7 +365,7 @@ static int cns3xxx_pcie_abort_handler(un
 941         return 0;
 942  }
 943
 944 -static int __init cns3xxx_pcie_init(void)
 945 +int cns3xxx_pcie_init(u8 bitmap)
 946  {
 947         int i;
 948
 949 @@ -376,6 +376,9 @@ static int __init cns3xxx_pcie_init(void
 950                         "imprecise external abort");
 951
 952         for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
 953 +               if (!(bitmap & (1 << i)))
 954 +                       continue;
 955 +
 956                 iotable_init(cns3xxx_pcie[i].cfg_bases,
 957                              ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
 958                 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
 959 @@ -387,4 +390,3 @@ static int __init cns3xxx_pcie_init(void
 960
 961         return 0;
 962  }
 963 -device_initcall(cns3xxx_pcie_init);
 964 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
 965 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
 966 @@ -31,6 +31,7 @@
 967  #include <asm/mach/time.h>
 968  #include <mach/cns3xxx.h>
 969  #include <mach/irqs.h>
 970 +#include <mach/platform.h>
 971  #include "core.h"
 972  #include "devices.h"
 973
 974 @@ -198,6 +199,8 @@ static void __init cns3420_init(void)
 975         cns3xxx_ahci_init();
 976         cns3xxx_sdhci_init();
 977
 978 +       cns3xxx_pcie_init(0x3);
 979 +
 980         pm_power_off = cns3xxx_power_off;
 981  }
 982
 983 --- a/arch/arm/mach-cns3xxx/include/mach/platform.h
 984 +++ b/arch/arm/mach-cns3xxx/include/mach/platform.h
 985 @@ -22,5 +22,7 @@ struct cns3xxx_plat_info {
 986         u32 phy[3];
 987  };
 988
 989 +extern int cns3xxx_pcie_init(u8 bitmap);
 990 +
 991  #endif /* __ASM_ARCH_PLATFORM_H */
 992  #endif