1 --- a/arch/arm/mach-cns3xxx/Makefile
2 +++ b/arch/arm/mach-cns3xxx/Makefile
4 obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
5 obj-$(CONFIG_PCI) += pcie.o
6 obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
7 +obj-$(CONFIG_SMP) += platsmp.o headsmp.o
8 +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
9 +obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
11 +++ b/arch/arm/mach-cns3xxx/headsmp.S
14 + * linux/arch/arm/mach-cns3xxx/headsmp.S
16 + * Cloned from linux/arch/arm/plat-versatile/headsmp.S
18 + * Copyright (c) 2003 ARM Limited
19 + * All Rights Reserved
21 + * This program is free software; you can redistribute it and/or modify
22 + * it under the terms of the GNU General Public License version 2 as
23 + * published by the Free Software Foundation.
25 +#include <linux/linkage.h>
26 +#include <linux/init.h>
31 + * CNS3XXX specific entry point for secondary CPUs. This provides
32 + * a "holding pen" into which all secondary cores are held until we're
33 + * ready for them to initialise.
35 +ENTRY(cns3xxx_secondary_startup)
36 + mrc p15, 0, r0, c0, c0, 5
47 + * we've been released from the holding pen: secondary_stack
48 + * should now contain the SVC stack for this core
56 +++ b/arch/arm/mach-cns3xxx/hotplug.c
58 +/* linux arch/arm/mach-cns3xxx/hotplug.c
60 + * Cloned from linux/arch/arm/mach-realview/hotplug.c
62 + * Copyright (C) 2002 ARM Ltd.
63 + * All Rights Reserved
65 + * This program is free software; you can redistribute it and/or modify
66 + * it under the terms of the GNU General Public License version 2 as
67 + * published by the Free Software Foundation.
70 +#include <linux/kernel.h>
71 +#include <linux/errno.h>
72 +#include <linux/smp.h>
74 +#include <asm/cacheflush.h>
76 +extern volatile int pen_release;
78 +static inline void cpu_enter_lowpower(void)
84 + " mcr p15, 0, %1, c7, c5, 0\n"
85 + " mcr p15, 0, %1, c7, c10, 4\n"
87 + * Turn off coherency
89 + " mrc p15, 0, %0, c1, c0, 1\n"
91 + " mcr p15, 0, %0, c1, c0, 1\n"
92 + " mrc p15, 0, %0, c1, c0, 0\n"
94 + " mcr p15, 0, %0, c1, c0, 0\n"
96 + : "r" (0), "Ir" (CR_C), "Ir" (0x40)
100 +static inline void cpu_leave_lowpower(void)
105 + "mrc p15, 0, %0, c1, c0, 0\n"
106 + " orr %0, %0, %1\n"
107 + " mcr p15, 0, %0, c1, c0, 0\n"
108 + " mrc p15, 0, %0, c1, c0, 1\n"
109 + " orr %0, %0, %2\n"
110 + " mcr p15, 0, %0, c1, c0, 1\n"
112 + : "Ir" (CR_C), "Ir" (0x40)
116 +static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
119 + * there is no power-control hardware on this platform, so all
120 + * we can do is put the core into WFI; this is safe as the calling
121 + * code will have already disabled interrupts
127 + asm(".word 0xe320f003\n"
132 + if (pen_release == cpu) {
134 + * OK, proper wakeup, we're done
140 + * Getting here, means that we have come out of WFI without
141 + * having been woken up - this shouldn't happen
143 + * Just note it happening - when we're woken, we can report
150 +int platform_cpu_kill(unsigned int cpu)
156 + * platform-specific code to shutdown a CPU
158 + * Called with IRQs disabled
160 +void platform_cpu_die(unsigned int cpu)
165 + * we're ready for shutdown now, so do it
167 + cpu_enter_lowpower();
168 + platform_do_lowpower(cpu, &spurious);
171 + * bring this CPU back into the world of cache
172 + * coherency, and then restore interrupts
174 + cpu_leave_lowpower();
177 + pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
180 +int platform_cpu_disable(unsigned int cpu)
183 + * we don't allow CPU 0 to be shutdown (it is still too special
184 + * e.g. clock tick interrupts)
186 + return cpu == 0 ? -EPERM : 0;
189 +++ b/arch/arm/mach-cns3xxx/localtimer.c
191 +/* linux/arch/arm/mach-cns3xxx/localtimer.c
193 + * Cloned from linux/arch/arm/mach-realview/localtimer.c
195 + * Copyright (C) 2002 ARM Ltd.
196 + * All Rights Reserved
198 + * This program is free software; you can redistribute it and/or modify
199 + * it under the terms of the GNU General Public License version 2 as
200 + * published by the Free Software Foundation.
203 +#include <linux/clockchips.h>
205 +#include <asm/irq.h>
206 +#include <asm/localtimer.h>
209 + * Setup the local clock events for a CPU.
211 +int __cpuinit local_timer_setup(struct clock_event_device *evt)
213 + evt->irq = IRQ_LOCALTIMER;
214 + twd_timer_setup(evt);
218 +++ b/arch/arm/mach-cns3xxx/platsmp.c
220 +/* linux/arch/arm/mach-cns3xxx/platsmp.c
222 + * Copyright 2011 Gateworks Corporation
223 + * Chris Lang <clang@gateworks.com>
224 + * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
226 + * Copyright (C) 2002 ARM Ltd.
227 + * All Rights Reserved
229 + * This program is free software; you can redistribute it and/or modify
230 + * it under the terms of the GNU General Public License version 2 as
231 + * published by the Free Software Foundation.
234 +#include <linux/init.h>
235 +#include <linux/errno.h>
236 +#include <linux/delay.h>
237 +#include <linux/device.h>
238 +#include <linux/jiffies.h>
239 +#include <linux/smp.h>
240 +#include <linux/io.h>
242 +#include <asm/cacheflush.h>
243 +#include <asm/hardware/gic.h>
244 +#include <asm/smp_scu.h>
245 +#include <asm/unified.h>
247 +#include <mach/hardware.h>
248 +#include <mach/cns3xxx.h>
250 +extern void cns3xxx_secondary_startup(void);
253 + * control for which core is the next to come out of the secondary
254 + * boot "holding pen"
257 +volatile int __cpuinitdata pen_release = -1;
260 + * Write pen_release in a way that is guaranteed to be visible to all
261 + * observers, irrespective of whether they're taking part in coherency
262 + * or not. This is necessary for the hotplug code to work reliably.
264 +static void write_pen_release(int val)
268 + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
269 + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
272 +static void __iomem *scu_base_addr(void)
274 + return (void __iomem *)(CNS3XXX_TC11MP_SCU_BASE_VIRT);
277 +static DEFINE_SPINLOCK(boot_lock);
279 +void __cpuinit platform_secondary_init(unsigned int cpu)
282 + * if any interrupts are already enabled for the primary
283 + * core (e.g. timer irq), then they will not have been enabled
286 + gic_secondary_init(0);
289 + * let the primary processor know we're out of the
290 + * pen, then head off into the C entry point
292 + write_pen_release(-1);
295 + * Synchronise with the boot thread.
297 + spin_lock(&boot_lock);
298 + spin_unlock(&boot_lock);
301 +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
303 + unsigned long timeout;
306 + * Set synchronisation state between this boot processor
307 + * and the secondary one
309 + spin_lock(&boot_lock);
312 + * The secondary processor is waiting to be released from
313 + * the holding pen - release it, then wait for it to flag
314 + * that it has been released by resetting pen_release.
316 + * Note that "pen_release" is the hardware CPU ID, whereas
317 + * "cpu" is Linux's internal ID.
319 + write_pen_release(cpu);
322 + * Send the secondary CPU a soft interrupt, thereby causing
323 + * the boot monitor to read the system wide flags register,
324 + * and branch to the address found there.
326 + gic_raise_softirq(cpumask_of(cpu), 1);
328 + timeout = jiffies + (1 * HZ);
329 + while (time_before(jiffies, timeout)) {
331 + if (pen_release == -1)
338 + * now the secondary core is starting up let it run its
339 + * calibrations, then wait for it to finish
341 + spin_unlock(&boot_lock);
343 + return pen_release != -1 ? -ENOSYS : 0;
347 + * Initialise the CPU possible map early - this describes the CPUs
348 + * which may be present or become present in the system.
351 +void __init smp_init_cpus(void)
353 + void __iomem *scu_base = scu_base_addr();
354 + unsigned int i, ncores;
356 + ncores = scu_base ? scu_get_core_count(scu_base) : 1;
359 + if (ncores > NR_CPUS) {
360 + printk(KERN_WARNING
361 + "cns3xxx: no. of cores (%d) greater than configured "
362 + "maximum of %d - clipping\n",
367 + for (i = 0; i < ncores; i++)
368 + set_cpu_possible(i, true);
370 + set_smp_cross_call(gic_raise_softirq);
373 +void __init platform_smp_prepare_cpus(unsigned int max_cpus)
378 + * Initialise the present map, which describes the set of CPUs
379 + * actually populated at the present time.
381 + for (i = 0; i < max_cpus; i++)
382 + set_cpu_present(i, true);
384 + scu_enable(scu_base_addr());
387 + * Write the address of secondary startup into the
388 + * system-wide flags register. The boot monitor waits
389 + * until it receives a soft interrupt, and then the
390 + * secondary CPU branches to this address.
392 + __raw_writel(virt_to_phys(cns3xxx_secondary_startup),
393 + (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
395 --- a/arch/arm/Kconfig
396 +++ b/arch/arm/Kconfig
397 @@ -1312,7 +1312,7 @@ config SMP
398 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
399 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
400 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
401 - ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
402 + ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_CNS3XXX
403 select USE_GENERIC_SMP_HELPERS
404 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP