target/linux/brcm63xx/patches-3.9/048-bcm63xx_enet-add-support-Broadcom-BCM6345-Ethernet.patch

   1 From fb7e08ec47f7168b8f4f72d8e3b5bcf625e1089e Mon Sep 17 00:00:00 2001
   2 From: Florian Fainelli <florian@openwrt.org>
   3 Date: Wed, 12 Jun 2013 18:53:05 +0000
   4 Subject: [PATCH] bcm63xx_enet: add support Broadcom BCM6345 Ethernet
   5
   6 This patch adds support for the Broadcom BCM6345 SoC Ethernet. BCM6345
   7 has a slightly different and older DMA engine which requires the
   8 following modifications:
   9
  10 - the width of the DMA channels on BCM6345 is 64 bytes vs 16 bytes,
  11   which means that the helpers enet_dma{c,s} need to account for this
  12   channel width and we can no longer use macros
  13
  14 - BCM6345 DMA engine does not have any internal SRAM for transfering
  15   buffers
  16
  17 - BCM6345 buffer allocation and flow control is not per-channel but
  18   global (done in RSET_ENETDMA)
  19
  20 - the DMA engine bits are right-shifted by 3 compared to other DMA
  21   generations
  22
  23 - the DMA enable/interrupt masks are a little different (we need to
  24   enabled more bits for 6345)
  25
  26 - some register have the same meaning but are offsetted in the ENET_DMAC
  27   space so a lookup table is required to return the proper offset
  28
  29 The MAC itself is identical and requires no modifications to work.
  30
  31 Signed-off-by: Florian Fainelli <florian@openwrt.org>
  32 Acked-by: Ralf Baechle <ralf@linux-mips.org>
  33 ---
  34  arch/mips/bcm63xx/dev-enet.c                       |   65 ++++++-
  35  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h   |    3 +-
  36  .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h    |   94 +++++++++
  37  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h  |   43 ++++-
  38  drivers/net/ethernet/broadcom/bcm63xx_enet.c       |  200 ++++++++++++--------
  39  drivers/net/ethernet/broadcom/bcm63xx_enet.h       |   15 ++
  40  6 files changed, 329 insertions(+), 91 deletions(-)
  41
  42 --- a/arch/mips/bcm63xx/dev-enet.c
  43 +++ b/arch/mips/bcm63xx/dev-enet.c
  44 @@ -9,10 +9,44 @@
  45  #include <linux/init.h>
  46  #include <linux/kernel.h>
  47  #include <linux/platform_device.h>
  48 +#include <linux/export.h>
  49  #include <bcm63xx_dev_enet.h>
  50  #include <bcm63xx_io.h>
  51  #include <bcm63xx_regs.h>
  52
  53 +#ifdef BCMCPU_RUNTIME_DETECT
  54 +static const unsigned long bcm6348_regs_enetdmac[] = {
  55 +       [ENETDMAC_CHANCFG]      = ENETDMAC_CHANCFG_REG,
  56 +       [ENETDMAC_IR]           = ENETDMAC_IR_REG,
  57 +       [ENETDMAC_IRMASK]       = ENETDMAC_IRMASK_REG,
  58 +       [ENETDMAC_MAXBURST]     = ENETDMAC_MAXBURST_REG,
  59 +};
  60 +
  61 +static const unsigned long bcm6345_regs_enetdmac[] = {
  62 +       [ENETDMAC_CHANCFG]      = ENETDMA_6345_CHANCFG_REG,
  63 +       [ENETDMAC_IR]           = ENETDMA_6345_IR_REG,
  64 +       [ENETDMAC_IRMASK]       = ENETDMA_6345_IRMASK_REG,
  65 +       [ENETDMAC_MAXBURST]     = ENETDMA_6345_MAXBURST_REG,
  66 +       [ENETDMAC_BUFALLOC]     = ENETDMA_6345_BUFALLOC_REG,
  67 +       [ENETDMAC_RSTART]       = ENETDMA_6345_RSTART_REG,
  68 +       [ENETDMAC_FC]           = ENETDMA_6345_FC_REG,
  69 +       [ENETDMAC_LEN]          = ENETDMA_6345_LEN_REG,
  70 +};
  71 +
  72 +const unsigned long *bcm63xx_regs_enetdmac;
  73 +EXPORT_SYMBOL(bcm63xx_regs_enetdmac);
  74 +
  75 +static __init void bcm63xx_enetdmac_regs_init(void)
  76 +{
  77 +       if (BCMCPU_IS_6345())
  78 +               bcm63xx_regs_enetdmac = bcm6345_regs_enetdmac;
  79 +       else
  80 +               bcm63xx_regs_enetdmac = bcm6348_regs_enetdmac;
  81 +}
  82 +#else
  83 +static __init void bcm63xx_enetdmac_regs_init(void) { }
  84 +#endif
  85 +
  86  static struct resource shared_res[] = {
  87         {
  88                 .start          = -1, /* filled at runtime */
  89 @@ -137,12 +171,19 @@ static int __init register_shared(void)
  90         if (shared_device_registered)
  91                 return 0;
  92
  93 +       bcm63xx_enetdmac_regs_init();
  94 +
  95         shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
  96         shared_res[0].end = shared_res[0].start;
  97 -       shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
  98 +       if (BCMCPU_IS_6345())
  99 +               shared_res[0].end += (RSET_6345_ENETDMA_SIZE) - 1;
 100 +       else
 101 +               shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
 102
 103         if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
 104                 chan_count = 32;
 105 +       else if (BCMCPU_IS_6345())
 106 +               chan_count = 8;
 107         else
 108                 chan_count = 16;
 109
 110 @@ -172,7 +213,7 @@ int __init bcm63xx_enet_register(int uni
 111         if (unit > 1)
 112                 return -ENODEV;
 113
 114 -       if (unit == 1 && BCMCPU_IS_6338())
 115 +       if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
 116                 return -ENODEV;
 117
 118         ret = register_shared();
 119 @@ -213,6 +254,21 @@ int __init bcm63xx_enet_register(int uni
 120                 dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
 121         }
 122
 123 +       dpd->dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
 124 +       dpd->dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
 125 +       if (BCMCPU_IS_6345()) {
 126 +               dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_CHAINING_MASK;
 127 +               dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_WRAP_EN_MASK;
 128 +               dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_FLOWC_EN_MASK;
 129 +               dpd->dma_chan_int_mask |= ENETDMA_IR_BUFDONE_MASK;
 130 +               dpd->dma_chan_int_mask |= ENETDMA_IR_NOTOWNER_MASK;
 131 +               dpd->dma_chan_width = ENETDMA_6345_CHAN_WIDTH;
 132 +               dpd->dma_desc_shift = ENETDMA_6345_DESC_SHIFT;
 133 +       } else {
 134 +               dpd->dma_has_sram = true;
 135 +               dpd->dma_chan_width = ENETDMA_CHAN_WIDTH;
 136 +       }
 137 +
 138         ret = platform_device_register(pdev);
 139         if (ret)
 140                 return ret;
 141 @@ -246,6 +302,11 @@ bcm63xx_enetsw_register(const struct bcm
 142         else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
 143                 enetsw_pd.num_ports = ENETSW_PORTS_6368;
 144
 145 +       enetsw_pd.dma_has_sram = true;
 146 +       enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
 147 +       enetsw_pd.dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
 148 +       enetsw_pd.dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
 149 +
 150         ret = platform_device_register(&bcm63xx_enetsw_device);
 151         if (ret)
 152                 return ret;
 153 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 154 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 155 @@ -188,6 +188,7 @@ enum bcm63xx_regs_set {
 156  #define BCM_6368_RSET_SPI_SIZE         1804
 157  #define RSET_ENET_SIZE                 2048
 158  #define RSET_ENETDMA_SIZE              256
 159 +#define RSET_6345_ENETDMA_SIZE         64
 160  #define RSET_ENETDMAC_SIZE(chans)      (16 * (chans))
 161  #define RSET_ENETDMAS_SIZE(chans)      (16 * (chans))
 162  #define RSET_ENETSW_SIZE               65536
 163 @@ -363,7 +364,7 @@ enum bcm63xx_regs_set {
 164  #define BCM_6345_USBDMA_BASE           (0xfffe2800)
 165  #define BCM_6345_ENET0_BASE            (0xfffe1800)
 166  #define BCM_6345_ENETDMA_BASE          (0xfffe2800)
 167 -#define BCM_6345_ENETDMAC_BASE         (0xfffe2900)
 168 +#define BCM_6345_ENETDMAC_BASE         (0xfffe2840)
 169  #define BCM_6345_ENETDMAS_BASE         (0xfffe2a00)
 170  #define BCM_6345_ENETSW_BASE           (0xdeadbeef)
 171  #define BCM_6345_PCMCIA_BASE           (0xfffe2028)
 172 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
 173 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
 174 @@ -4,6 +4,8 @@
 175  #include <linux/if_ether.h>
 176  #include <linux/init.h>
 177
 178 +#include <bcm63xx_regs.h>
 179 +
 180  /*
 181   * on board ethernet platform data
 182   */
 183 @@ -37,6 +39,21 @@ struct bcm63xx_enet_platform_data {
 184                                           int phy_id, int reg),
 185                           void (*mii_write)(struct net_device *dev,
 186                                             int phy_id, int reg, int val));
 187 +
 188 +       /* DMA channel enable mask */
 189 +       u32 dma_chan_en_mask;
 190 +
 191 +       /* DMA channel interrupt mask */
 192 +       u32 dma_chan_int_mask;
 193 +
 194 +       /* DMA engine has internal SRAM */
 195 +       bool dma_has_sram;
 196 +
 197 +       /* DMA channel register width */
 198 +       unsigned int dma_chan_width;
 199 +
 200 +       /* DMA descriptor shift */
 201 +       unsigned int dma_desc_shift;
 202  };
 203
 204  /*
 205 @@ -63,6 +80,18 @@ struct bcm63xx_enetsw_platform_data {
 206         char mac_addr[ETH_ALEN];
 207         int num_ports;
 208         struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
 209 +
 210 +       /* DMA channel enable mask */
 211 +       u32 dma_chan_en_mask;
 212 +
 213 +       /* DMA channel interrupt mask */
 214 +       u32 dma_chan_int_mask;
 215 +
 216 +       /* DMA channel register width */
 217 +       unsigned int dma_chan_width;
 218 +
 219 +       /* DMA engine has internal SRAM */
 220 +       bool dma_has_sram;
 221  };
 222
 223  int __init bcm63xx_enet_register(int unit,
 224 @@ -70,4 +99,69 @@ int __init bcm63xx_enet_register(int uni
 225
 226  int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
 227
 228 +enum bcm63xx_regs_enetdmac {
 229 +       ENETDMAC_CHANCFG,
 230 +       ENETDMAC_IR,
 231 +       ENETDMAC_IRMASK,
 232 +       ENETDMAC_MAXBURST,
 233 +       ENETDMAC_BUFALLOC,
 234 +       ENETDMAC_RSTART,
 235 +       ENETDMAC_FC,
 236 +       ENETDMAC_LEN,
 237 +};
 238 +
 239 +static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
 240 +{
 241 +#ifdef BCMCPU_RUNTIME_DETECT
 242 +       extern const unsigned long *bcm63xx_regs_enetdmac;
 243 +
 244 +       return bcm63xx_regs_enetdmac[reg];
 245 +#else
 246 +#ifdef CONFIG_BCM63XX_CPU_6345
 247 +       switch (reg) {
 248 +       case ENETDMAC_CHANCFG:
 249 +               return ENETDMA_6345_CHANCFG_REG;
 250 +       case ENETDMAC_IR:
 251 +               return ENETDMA_6345_IR_REG;
 252 +       case ENETDMAC_IRMASK:
 253 +               return ENETDMA_6345_IRMASK_REG;
 254 +       case ENETDMAC_MAXBURST:
 255 +               return ENETDMA_6345_MAXBURST_REG;
 256 +       case ENETDMAC_BUFALLOC:
 257 +               return ENETDMA_6345_BUFALLOC_REG;
 258 +       case ENETDMAC_RSTART:
 259 +               return ENETDMA_6345_RSTART_REG;
 260 +       case ENETDMAC_FC:
 261 +               return ENETDMA_6345_FC_REG;
 262 +       case ENETDMAC_LEN:
 263 +               return ENETDMA_6345_LEN_REG;
 264 +       }
 265 +#endif
 266 +#if defined(CONFIG_BCM63XX_CPU_6328) || \
 267 +       defined(CONFIG_BCM63XX_CPU_6338) || \
 268 +       defined(CONFIG_BCM63XX_CPU_6348) || \
 269 +       defined(CONFIG_BCM63XX_CPU_6358) || \
 270 +       defined(CONFIG_BCM63XX_CPU_6362) || \
 271 +       defined(CONFIG_BCM63XX_CPU_6368)
 272 +       switch (reg) {
 273 +       case ENETDMAC_CHANCFG:
 274 +               return ENETDMAC_CHANCFG_REG;
 275 +       case ENETDMAC_IR:
 276 +               return ENETDMAC_IR_REG;
 277 +       case ENETDMAC_IRMASK:
 278 +               return ENETDMAC_IRMASK_REG;
 279 +       case ENETDMAC_MAXBURST:
 280 +               return ENETDMAC_MAXBURST_REG;
 281 +       case ENETDMAC_BUFALLOC:
 282 +       case ENETDMAC_RSTART:
 283 +       case ENETDMAC_FC:
 284 +       case ENETDMAC_LEN:
 285 +               return 0;
 286 +       }
 287 +#endif
 288 +#endif
 289 +       return 0;
 290 +}
 291 +
 292 +
 293  #endif /* ! BCM63XX_DEV_ENET_H_ */
 294 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 295 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 296 @@ -770,6 +770,8 @@
 297  /*************************************************************************
 298   * _REG relative to RSET_ENETDMA
 299   *************************************************************************/
 300 +#define ENETDMA_CHAN_WIDTH             0x10
 301 +#define ENETDMA_6345_CHAN_WIDTH                0x40
 302
 303  /* Controller Configuration Register */
 304  #define ENETDMA_CFG_REG                        (0x0)
 305 @@ -825,31 +827,56 @@
 306  /* State Ram Word 4 */
 307  #define ENETDMA_SRAM4_REG(x)           (0x20c + (x) * 0x10)
 308
 309 +/* Broadcom 6345 ENET DMA definitions */
 310 +#define ENETDMA_6345_CHANCFG_REG       (0x00)
 311 +
 312 +#define ENETDMA_6345_MAXBURST_REG      (0x40)
 313 +
 314 +#define ENETDMA_6345_RSTART_REG                (0x08)
 315 +
 316 +#define ENETDMA_6345_LEN_REG           (0x0C)
 317 +
 318 +#define ENETDMA_6345_IR_REG            (0x14)
 319 +
 320 +#define ENETDMA_6345_IRMASK_REG                (0x18)
 321 +
 322 +#define ENETDMA_6345_FC_REG            (0x1C)
 323 +
 324 +#define ENETDMA_6345_BUFALLOC_REG      (0x20)
 325 +
 326 +/* Shift down for EOP, SOP and WRAP bits */
 327 +#define ENETDMA_6345_DESC_SHIFT                (3)
 328
 329  /*************************************************************************
 330   * _REG relative to RSET_ENETDMAC
 331   *************************************************************************/
 332
 333  /* Channel Configuration register */
 334 -#define ENETDMAC_CHANCFG_REG(x)                ((x) * 0x10)
 335 +#define ENETDMAC_CHANCFG_REG           (0x0)
 336  #define ENETDMAC_CHANCFG_EN_SHIFT      0
 337  #define ENETDMAC_CHANCFG_EN_MASK       (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 338  #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
 339  #define ENETDMAC_CHANCFG_PKTHALT_MASK  (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
 340  #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
 341  #define ENETDMAC_CHANCFG_BUFHALT_MASK  (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
 342 +#define ENETDMAC_CHANCFG_CHAINING_SHIFT        2
 343 +#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
 344 +#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
 345 +#define ENETDMAC_CHANCFG_WRAP_EN_MASK  (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
 346 +#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT        4
 347 +#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
 348
 349  /* Interrupt Control/Status register */
 350 -#define ENETDMAC_IR_REG(x)             (0x4 + (x) * 0x10)
 351 +#define ENETDMAC_IR_REG                        (0x4)
 352  #define ENETDMAC_IR_BUFDONE_MASK       (1 << 0)
 353  #define ENETDMAC_IR_PKTDONE_MASK       (1 << 1)
 354  #define ENETDMAC_IR_NOTOWNER_MASK      (1 << 2)
 355
 356  /* Interrupt Mask register */
 357 -#define ENETDMAC_IRMASK_REG(x)         (0x8 + (x) * 0x10)
 358 +#define ENETDMAC_IRMASK_REG            (0x8)
 359
 360  /* Maximum Burst Length */
 361 -#define ENETDMAC_MAXBURST_REG(x)       (0xc + (x) * 0x10)
 362 +#define ENETDMAC_MAXBURST_REG          (0xc)
 363
 364
 365  /*************************************************************************
 366 @@ -857,16 +884,16 @@
 367   *************************************************************************/
 368
 369  /* Ring Start Address register */
 370 -#define ENETDMAS_RSTART_REG(x)         ((x) * 0x10)
 371 +#define ENETDMAS_RSTART_REG            (0x0)
 372
 373  /* State Ram Word 2 */
 374 -#define ENETDMAS_SRAM2_REG(x)          (0x4 + (x) * 0x10)
 375 +#define ENETDMAS_SRAM2_REG             (0x4)
 376
 377  /* State Ram Word 3 */
 378 -#define ENETDMAS_SRAM3_REG(x)          (0x8 + (x) * 0x10)
 379 +#define ENETDMAS_SRAM3_REG             (0x8)
 380
 381  /* State Ram Word 4 */
 382 -#define ENETDMAS_SRAM4_REG(x)          (0xc + (x) * 0x10)
 383 +#define ENETDMAS_SRAM4_REG             (0xc)
 384
 385
 386  /*************************************************************************
 387 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
 388 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
 389 @@ -107,26 +107,28 @@ static inline void enet_dma_writel(struc
 390         bcm_writel(val, bcm_enet_shared_base[0] + off);
 391  }
 392
 393 -static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
 394 +static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 395  {
 396 -       return bcm_readl(bcm_enet_shared_base[1] + off);
 397 +       return bcm_readl(bcm_enet_shared_base[1] +
 398 +               bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 399  }
 400
 401  static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 402 -                                      u32 val, u32 off)
 403 +                                      u32 val, u32 off, int chan)
 404  {
 405 -       bcm_writel(val, bcm_enet_shared_base[1] + off);
 406 +       bcm_writel(val, bcm_enet_shared_base[1] +
 407 +               bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 408  }
 409
 410 -static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
 411 +static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 412  {
 413 -       return bcm_readl(bcm_enet_shared_base[2] + off);
 414 +       return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 415  }
 416
 417  static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 418 -                                      u32 val, u32 off)
 419 +                                      u32 val, u32 off, int chan)
 420  {
 421 -       bcm_writel(val, bcm_enet_shared_base[2] + off);
 422 +       bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 423  }
 424
 425  /*
 426 @@ -262,7 +264,7 @@ static int bcm_enet_refill_rx(struct net
 427                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 428                 len_stat |= DMADESC_OWNER_MASK;
 429                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 430 -                       len_stat |= DMADESC_WRAP_MASK;
 431 +                       len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 432                         priv->rx_dirty_desc = 0;
 433                 } else {
 434                         priv->rx_dirty_desc++;
 435 @@ -273,7 +275,10 @@ static int bcm_enet_refill_rx(struct net
 436                 priv->rx_desc_count++;
 437
 438                 /* tell dma engine we allocated one buffer */
 439 -               enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 440 +               if (priv->dma_has_sram)
 441 +                       enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 442 +               else
 443 +                       enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 444         }
 445
 446         /* If rx ring is still empty, set a timer to try allocating
 447 @@ -349,7 +354,8 @@ static int bcm_enet_receive_queue(struct
 448
 449                 /* if the packet does not have start of packet _and_
 450                  * end of packet flag set, then just recycle it */
 451 -               if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 452 +               if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 453 +                       (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 454                         dev->stats.rx_dropped++;
 455                         continue;
 456                 }
 457 @@ -410,8 +416,8 @@ static int bcm_enet_receive_queue(struct
 458                 bcm_enet_refill_rx(dev);
 459
 460                 /* kick rx dma */
 461 -               enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 462 -                                ENETDMAC_CHANCFG_REG(priv->rx_chan));
 463 +               enet_dmac_writel(priv, priv->dma_chan_en_mask,
 464 +                                        ENETDMAC_CHANCFG, priv->rx_chan);
 465         }
 466
 467         return processed;
 468 @@ -486,10 +492,10 @@ static int bcm_enet_poll(struct napi_str
 469         dev = priv->net_dev;
 470
 471         /* ack interrupts */
 472 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 473 -                        ENETDMAC_IR_REG(priv->rx_chan));
 474 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 475 -                        ENETDMAC_IR_REG(priv->tx_chan));
 476 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 477 +                        ENETDMAC_IR, priv->rx_chan);
 478 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 479 +                        ENETDMAC_IR, priv->tx_chan);
 480
 481         /* reclaim sent skb */
 482         tx_work_done = bcm_enet_tx_reclaim(dev, 0);
 483 @@ -508,10 +514,10 @@ static int bcm_enet_poll(struct napi_str
 484         napi_complete(napi);
 485
 486         /* restore rx/tx interrupt */
 487 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 488 -                        ENETDMAC_IRMASK_REG(priv->rx_chan));
 489 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 490 -                        ENETDMAC_IRMASK_REG(priv->tx_chan));
 491 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 492 +                        ENETDMAC_IRMASK, priv->rx_chan);
 493 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 494 +                        ENETDMAC_IRMASK, priv->tx_chan);
 495
 496         return rx_work_done;
 497  }
 498 @@ -554,8 +560,8 @@ static irqreturn_t bcm_enet_isr_dma(int
 499         priv = netdev_priv(dev);
 500
 501         /* mask rx/tx interrupts */
 502 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 503 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 504 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 505 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 506
 507         napi_schedule(&priv->napi);
 508
 509 @@ -616,14 +622,14 @@ static int bcm_enet_start_xmit(struct sk
 510                                        DMA_TO_DEVICE);
 511
 512         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 513 -       len_stat |= DMADESC_ESOP_MASK |
 514 +       len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 515                 DMADESC_APPEND_CRC |
 516                 DMADESC_OWNER_MASK;
 517
 518         priv->tx_curr_desc++;
 519         if (priv->tx_curr_desc == priv->tx_ring_size) {
 520                 priv->tx_curr_desc = 0;
 521 -               len_stat |= DMADESC_WRAP_MASK;
 522 +               len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 523         }
 524         priv->tx_desc_count--;
 525
 526 @@ -634,8 +640,8 @@ static int bcm_enet_start_xmit(struct sk
 527         wmb();
 528
 529         /* kick tx dma */
 530 -       enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 531 -                        ENETDMAC_CHANCFG_REG(priv->tx_chan));
 532 +       enet_dmac_writel(priv, priv->dma_chan_en_mask,
 533 +                                ENETDMAC_CHANCFG, priv->tx_chan);
 534
 535         /* stop queue if no more desc available */
 536         if (!priv->tx_desc_count)
 537 @@ -763,6 +769,9 @@ static void bcm_enet_set_flow(struct bcm
 538                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 539         enet_writel(priv, val, ENET_RXCFG_REG);
 540
 541 +       if (!priv->dma_has_sram)
 542 +               return;
 543 +
 544         /* tx flow control (pause frame generation) */
 545         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 546         if (tx_en)
 547 @@ -910,8 +919,8 @@ static int bcm_enet_open(struct net_devi
 548
 549         /* mask all interrupts and request them */
 550         enet_writel(priv, 0, ENET_IRMASK_REG);
 551 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 552 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 553 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 554 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 555
 556         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 557         if (ret)
 558 @@ -988,8 +997,12 @@ static int bcm_enet_open(struct net_devi
 559         priv->rx_curr_desc = 0;
 560
 561         /* initialize flow control buffer allocation */
 562 -       enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 563 -                       ENETDMA_BUFALLOC_REG(priv->rx_chan));
 564 +       if (priv->dma_has_sram)
 565 +               enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 566 +                               ENETDMA_BUFALLOC_REG(priv->rx_chan));
 567 +       else
 568 +               enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 569 +                               ENETDMAC_BUFALLOC, priv->rx_chan);
 570
 571         if (bcm_enet_refill_rx(dev)) {
 572                 dev_err(kdev, "cannot allocate rx skb queue\n");
 573 @@ -998,18 +1011,30 @@ static int bcm_enet_open(struct net_devi
 574         }
 575
 576         /* write rx & tx ring addresses */
 577 -       enet_dmas_writel(priv, priv->rx_desc_dma,
 578 -                        ENETDMAS_RSTART_REG(priv->rx_chan));
 579 -       enet_dmas_writel(priv, priv->tx_desc_dma,
 580 -                        ENETDMAS_RSTART_REG(priv->tx_chan));
 581 +       if (priv->dma_has_sram) {
 582 +               enet_dmas_writel(priv, priv->rx_desc_dma,
 583 +                                ENETDMAS_RSTART_REG, priv->rx_chan);
 584 +               enet_dmas_writel(priv, priv->tx_desc_dma,
 585 +                        ENETDMAS_RSTART_REG, priv->tx_chan);
 586 +       } else {
 587 +               enet_dmac_writel(priv, priv->rx_desc_dma,
 588 +                               ENETDMAC_RSTART, priv->rx_chan);
 589 +               enet_dmac_writel(priv, priv->tx_desc_dma,
 590 +                               ENETDMAC_RSTART, priv->tx_chan);
 591 +       }
 592
 593         /* clear remaining state ram for rx & tx channel */
 594 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
 595 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
 596 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
 597 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
 598 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
 599 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
 600 +       if (priv->dma_has_sram) {
 601 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
 602 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
 603 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
 604 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
 605 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
 606 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
 607 +       } else {
 608 +               enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
 609 +               enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
 610 +       }
 611
 612         /* set max rx/tx length */
 613         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
 614 @@ -1017,18 +1042,24 @@ static int bcm_enet_open(struct net_devi
 615
 616         /* set dma maximum burst len */
 617         enet_dmac_writel(priv, priv->dma_maxburst,
 618 -                        ENETDMAC_MAXBURST_REG(priv->rx_chan));
 619 +                        ENETDMAC_MAXBURST, priv->rx_chan);
 620         enet_dmac_writel(priv, priv->dma_maxburst,
 621 -                        ENETDMAC_MAXBURST_REG(priv->tx_chan));
 622 +                        ENETDMAC_MAXBURST, priv->tx_chan);
 623
 624         /* set correct transmit fifo watermark */
 625         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
 626
 627         /* set flow control low/high threshold to 1/3 / 2/3 */
 628 -       val = priv->rx_ring_size / 3;
 629 -       enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
 630 -       val = (priv->rx_ring_size * 2) / 3;
 631 -       enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
 632 +       if (priv->dma_has_sram) {
 633 +               val = priv->rx_ring_size / 3;
 634 +               enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
 635 +               val = (priv->rx_ring_size * 2) / 3;
 636 +               enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
 637 +       } else {
 638 +               enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
 639 +               enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
 640 +               enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
 641 +       }
 642
 643         /* all set, enable mac and interrupts, start dma engine and
 644          * kick rx dma channel */
 645 @@ -1037,26 +1068,26 @@ static int bcm_enet_open(struct net_devi
 646         val |= ENET_CTL_ENABLE_MASK;
 647         enet_writel(priv, val, ENET_CTL_REG);
 648         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
 649 -       enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 650 -                        ENETDMAC_CHANCFG_REG(priv->rx_chan));
 651 +       enet_dmac_writel(priv, priv->dma_chan_en_mask,
 652 +                        ENETDMAC_CHANCFG, priv->rx_chan);
 653
 654         /* watch "mib counters about to overflow" interrupt */
 655         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 656         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
 657
 658         /* watch "packet transferred" interrupt in rx and tx */
 659 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 660 -                        ENETDMAC_IR_REG(priv->rx_chan));
 661 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 662 -                        ENETDMAC_IR_REG(priv->tx_chan));
 663 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 664 +                        ENETDMAC_IR, priv->rx_chan);
 665 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 666 +                        ENETDMAC_IR, priv->tx_chan);
 667
 668         /* make sure we enable napi before rx interrupt  */
 669         napi_enable(&priv->napi);
 670
 671 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 672 -                        ENETDMAC_IRMASK_REG(priv->rx_chan));
 673 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 674 -                        ENETDMAC_IRMASK_REG(priv->tx_chan));
 675 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 676 +                        ENETDMAC_IRMASK, priv->rx_chan);
 677 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 678 +                        ENETDMAC_IRMASK, priv->tx_chan);
 679
 680         if (priv->has_phy)
 681                 phy_start(priv->phydev);
 682 @@ -1136,13 +1167,13 @@ static void bcm_enet_disable_dma(struct
 683  {
 684         int limit;
 685
 686 -       enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
 687 +       enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
 688
 689         limit = 1000;
 690         do {
 691                 u32 val;
 692
 693 -               val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
 694 +               val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
 695                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
 696                         break;
 697                 udelay(1);
 698 @@ -1169,8 +1200,8 @@ static int bcm_enet_stop(struct net_devi
 699
 700         /* mask all interrupts */
 701         enet_writel(priv, 0, ENET_IRMASK_REG);
 702 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 703 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 704 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 705 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 706
 707         /* make sure no mib update is scheduled */
 708         cancel_work_sync(&priv->mib_update_task);
 709 @@ -1784,6 +1815,11 @@ static int bcm_enet_probe(struct platfor
 710                 priv->pause_tx = pd->pause_tx;
 711                 priv->force_duplex_full = pd->force_duplex_full;
 712                 priv->force_speed_100 = pd->force_speed_100;
 713 +               priv->dma_chan_en_mask = pd->dma_chan_en_mask;
 714 +               priv->dma_chan_int_mask = pd->dma_chan_int_mask;
 715 +               priv->dma_chan_width = pd->dma_chan_width;
 716 +               priv->dma_has_sram = pd->dma_has_sram;
 717 +               priv->dma_desc_shift = pd->dma_desc_shift;
 718         }
 719
 720         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
 721 @@ -2121,8 +2157,8 @@ static int bcm_enetsw_open(struct net_de
 722         kdev = &priv->pdev->dev;
 723
 724         /* mask all interrupts and request them */
 725 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 726 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 727 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 728 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 729
 730         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
 731                           IRQF_DISABLED, dev->name, dev);
 732 @@ -2234,23 +2270,23 @@ static int bcm_enetsw_open(struct net_de
 733
 734         /* write rx & tx ring addresses */
 735         enet_dmas_writel(priv, priv->rx_desc_dma,
 736 -                        ENETDMAS_RSTART_REG(priv->rx_chan));
 737 +                        ENETDMAS_RSTART_REG, priv->rx_chan);
 738         enet_dmas_writel(priv, priv->tx_desc_dma,
 739 -                        ENETDMAS_RSTART_REG(priv->tx_chan));
 740 +                        ENETDMAS_RSTART_REG, priv->tx_chan);
 741
 742         /* clear remaining state ram for rx & tx channel */
 743 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
 744 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
 745 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
 746 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
 747 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
 748 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
 749 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
 750 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
 751 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
 752 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
 753 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
 754 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
 755
 756         /* set dma maximum burst len */
 757         enet_dmac_writel(priv, priv->dma_maxburst,
 758 -                        ENETDMAC_MAXBURST_REG(priv->rx_chan));
 759 +                        ENETDMAC_MAXBURST, priv->rx_chan);
 760         enet_dmac_writel(priv, priv->dma_maxburst,
 761 -                        ENETDMAC_MAXBURST_REG(priv->tx_chan));
 762 +                        ENETDMAC_MAXBURST, priv->tx_chan);
 763
 764         /* set flow control low/high threshold to 1/3 / 2/3 */
 765         val = priv->rx_ring_size / 3;
 766 @@ -2264,21 +2300,21 @@ static int bcm_enetsw_open(struct net_de
 767         wmb();
 768         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
 769         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 770 -                        ENETDMAC_CHANCFG_REG(priv->rx_chan));
 771 +                        ENETDMAC_CHANCFG, priv->rx_chan);
 772
 773         /* watch "packet transferred" interrupt in rx and tx */
 774         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 775 -                        ENETDMAC_IR_REG(priv->rx_chan));
 776 +                        ENETDMAC_IR, priv->rx_chan);
 777         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 778 -                        ENETDMAC_IR_REG(priv->tx_chan));
 779 +                        ENETDMAC_IR, priv->tx_chan);
 780
 781         /* make sure we enable napi before rx interrupt  */
 782         napi_enable(&priv->napi);
 783
 784         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 785 -                        ENETDMAC_IRMASK_REG(priv->rx_chan));
 786 +                        ENETDMAC_IRMASK, priv->rx_chan);
 787         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 788 -                        ENETDMAC_IRMASK_REG(priv->tx_chan));
 789 +                        ENETDMAC_IRMASK, priv->tx_chan);
 790
 791         netif_carrier_on(dev);
 792         netif_start_queue(dev);
 793 @@ -2380,8 +2416,8 @@ static int bcm_enetsw_stop(struct net_de
 794         del_timer_sync(&priv->rx_timeout);
 795
 796         /* mask all interrupts */
 797 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 798 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 799 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 800 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 801
 802         /* disable dma & mac */
 803         bcm_enet_disable_dma(priv, priv->tx_chan);
 804 @@ -2715,6 +2751,10 @@ static int bcm_enetsw_probe(struct platf
 805                 memcpy(priv->used_ports, pd->used_ports,
 806                        sizeof(pd->used_ports));
 807                 priv->num_ports = pd->num_ports;
 808 +               priv->dma_has_sram = pd->dma_has_sram;
 809 +               priv->dma_chan_en_mask = pd->dma_chan_en_mask;
 810 +               priv->dma_chan_int_mask = pd->dma_chan_int_mask;
 811 +               priv->dma_chan_width = pd->dma_chan_width;
 812         }
 813
 814         ret = compute_hw_mtu(priv, dev->mtu);
 815 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
 816 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
 817 @@ -339,6 +339,21 @@ struct bcm_enet_priv {
 818         /* used to poll switch port state */
 819         struct timer_list swphy_poll;
 820         spinlock_t enetsw_mdio_lock;
 821 +
 822 +       /* dma channel enable mask */
 823 +       u32 dma_chan_en_mask;
 824 +
 825 +       /* dma channel interrupt mask */
 826 +       u32 dma_chan_int_mask;
 827 +
 828 +       /* DMA engine has internal SRAM */
 829 +       bool dma_has_sram;
 830 +
 831 +       /* dma channel width */
 832 +       unsigned int dma_chan_width;
 833 +
 834 +       /* dma descriptor shift value */
 835 +       unsigned int dma_desc_shift;
 836  };
 837
 838