target/linux/brcm63xx/patches-3.3/008-MIPS-BCM63XX-define-internal-registers-offsets-of-th.patch

   1 From 81f9e7d6aa1dde65483387ba9e9823ef44f90435 Mon Sep 17 00:00:00 2001
   2 From: Florian Fainelli <florian@openwrt.org>
   3 Date: Wed, 25 Jan 2012 17:40:03 +0100
   4 Subject: [PATCH 10/63] MIPS: BCM63XX: define internal registers offsets of the SPI controller
   5
   6 BCM6338, BCM6348, BCM6358 and BCM6368 basically use the same SPI controller
   7 though the internal registers are shuffled, which still allows a common
   8 driver to drive that IP block.
   9
  10 Signed-off-by: Florian Fainelli <florian@openwrt.org>
  11 ---
  12  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  119 +++++++++++++++++++++
  13  1 files changed, 119 insertions(+), 0 deletions(-)
  14
  15 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  16 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  17 @@ -973,4 +973,123 @@
  18  #define M2M_SRCID_REG(x)               ((x) * 0x40 + 0x14)
  19  #define M2M_DSTID_REG(x)               ((x) * 0x40 + 0x18)
  20
  21 +/*************************************************************************
  22 + * _REG relative to RSET_SPI
  23 + *************************************************************************/
  24 +
  25 +/* BCM 6338 SPI core */
  26 +#define SPI_6338_CMD                   0x00    /* 16-bits register */
  27 +#define SPI_6338_INT_STATUS            0x02
  28 +#define SPI_6338_INT_MASK_ST           0x03
  29 +#define SPI_6338_INT_MASK              0x04
  30 +#define SPI_6338_ST                    0x05
  31 +#define SPI_6338_CLK_CFG               0x06
  32 +#define SPI_6338_FILL_BYTE             0x07
  33 +#define SPI_6338_MSG_TAIL              0x09
  34 +#define SPI_6338_RX_TAIL               0x0b
  35 +#define SPI_6338_MSG_CTL               0x40
  36 +#define SPI_6338_MSG_DATA              0x41
  37 +#define SPI_6338_MSG_DATA_SIZE         0x3f
  38 +#define SPI_6338_RX_DATA               0x80
  39 +#define SPI_6338_RX_DATA_SIZE          0x3f
  40 +
  41 +/* BCM 6348 SPI core */
  42 +#define SPI_6348_CMD                   0x00    /* 16-bits register */
  43 +#define SPI_6348_INT_STATUS            0x02
  44 +#define SPI_6348_INT_MASK_ST           0x03
  45 +#define SPI_6348_INT_MASK              0x04
  46 +#define SPI_6348_ST                    0x05
  47 +#define SPI_6348_CLK_CFG               0x06
  48 +#define SPI_6348_FILL_BYTE             0x07
  49 +#define SPI_6348_MSG_TAIL              0x09
  50 +#define SPI_6348_RX_TAIL               0x0b
  51 +#define SPI_6348_MSG_CTL               0x40
  52 +#define SPI_6348_MSG_DATA              0x41
  53 +#define SPI_6348_MSG_DATA_SIZE         0x3f
  54 +#define SPI_6348_RX_DATA               0x80
  55 +#define SPI_6348_RX_DATA_SIZE          0x3f
  56 +
  57 +/* BCM 6358 SPI core */
  58 +#define SPI_6358_MSG_CTL               0x00    /* 16-bits register */
  59 +#define SPI_6358_MSG_DATA              0x02
  60 +#define SPI_6358_MSG_DATA_SIZE         0x21e
  61 +#define SPI_6358_RX_DATA               0x400
  62 +#define SPI_6358_RX_DATA_SIZE          0x220
  63 +#define SPI_6358_CMD                   0x700   /* 16-bits register */
  64 +#define SPI_6358_INT_STATUS            0x702
  65 +#define SPI_6358_INT_MASK_ST           0x703
  66 +#define SPI_6358_INT_MASK              0x704
  67 +#define SPI_6358_ST                    0x705
  68 +#define SPI_6358_CLK_CFG               0x706
  69 +#define SPI_6358_FILL_BYTE             0x707
  70 +#define SPI_6358_MSG_TAIL              0x709
  71 +#define SPI_6358_RX_TAIL               0x70B
  72 +
  73 +/* BCM 6358 SPI core */
  74 +#define SPI_6368_MSG_CTL               0x00    /* 16-bits register */
  75 +#define SPI_6368_MSG_DATA              0x02
  76 +#define SPI_6368_MSG_DATA_SIZE         0x21e
  77 +#define SPI_6368_RX_DATA               0x400
  78 +#define SPI_6368_RX_DATA_SIZE          0x220
  79 +#define SPI_6368_CMD                   0x700   /* 16-bits register */
  80 +#define SPI_6368_INT_STATUS            0x702
  81 +#define SPI_6368_INT_MASK_ST           0x703
  82 +#define SPI_6368_INT_MASK              0x704
  83 +#define SPI_6368_ST                    0x705
  84 +#define SPI_6368_CLK_CFG               0x706
  85 +#define SPI_6368_FILL_BYTE             0x707
  86 +#define SPI_6368_MSG_TAIL              0x709
  87 +#define SPI_6368_RX_TAIL               0x70B
  88 +
  89 +/* Shared SPI definitions */
  90 +
  91 +/* Message configuration */
  92 +#define SPI_FD_RW                      0x00
  93 +#define SPI_HD_W                       0x01
  94 +#define SPI_HD_R                       0x02
  95 +#define SPI_BYTE_CNT_SHIFT             0
  96 +#define SPI_MSG_TYPE_SHIFT             14
  97 +
  98 +/* Command */
  99 +#define SPI_CMD_NOOP                   0x00
 100 +#define SPI_CMD_SOFT_RESET             0x01
 101 +#define SPI_CMD_HARD_RESET             0x02
 102 +#define SPI_CMD_START_IMMEDIATE                0x03
 103 +#define SPI_CMD_COMMAND_SHIFT          0
 104 +#define SPI_CMD_COMMAND_MASK           0x000f
 105 +#define SPI_CMD_DEVICE_ID_SHIFT                4
 106 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
 107 +#define SPI_CMD_ONE_BYTE_SHIFT         11
 108 +#define SPI_CMD_ONE_WIRE_SHIFT         12
 109 +#define SPI_DEV_ID_0                   0
 110 +#define SPI_DEV_ID_1                   1
 111 +#define SPI_DEV_ID_2                   2
 112 +#define SPI_DEV_ID_3                   3
 113 +
 114 +/* Interrupt mask */
 115 +#define SPI_INTR_CMD_DONE              0x01
 116 +#define SPI_INTR_RX_OVERFLOW           0x02
 117 +#define SPI_INTR_TX_UNDERFLOW          0x04
 118 +#define SPI_INTR_TX_OVERFLOW           0x08
 119 +#define SPI_INTR_RX_UNDERFLOW          0x10
 120 +#define SPI_INTR_CLEAR_ALL             0x1f
 121 +
 122 +/* Status */
 123 +#define SPI_RX_EMPTY                   0x02
 124 +#define SPI_CMD_BUSY                   0x04
 125 +#define SPI_SERIAL_BUSY                        0x08
 126 +
 127 +/* Clock configuration */
 128 +#define SPI_CLK_20MHZ                  0x00
 129 +#define SPI_CLK_0_391MHZ               0x01
 130 +#define SPI_CLK_0_781MHZ               0x02 /* default */
 131 +#define SPI_CLK_1_563MHZ               0x03
 132 +#define SPI_CLK_3_125MHZ               0x04
 133 +#define SPI_CLK_6_250MHZ               0x05
 134 +#define SPI_CLK_12_50MHZ               0x06
 135 +#define SPI_CLK_MASK                   0x07
 136 +#define SPI_SSOFFTIME_MASK             0x38
 137 +#define SPI_SSOFFTIME_SHIFT            3
 138 +#define SPI_BYTE_SWAP                  0x80
 139 +
 140  #endif /* BCM63XX_REGS_H_ */