target/linux/brcm63xx/patches-3.18/321-irqchip-add-support-for-bcm6345-style-external-inter.patch

   1 From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sun, 30 Nov 2014 14:54:27 +0100
   4 Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external
   5  interrupt controller
   6
   7 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
   8 ---
   9  .../interrupt-controller/brcm,bcm6345-ext-intc.txt |   29 ++
  10  drivers/irqchip/Kconfig                            |    4 +
  11  drivers/irqchip/Makefile                           |    1 +
  12  drivers/irqchip/irq-bcm6345-ext.c                  |  287 ++++++++++++++++++++
  13  include/linux/irqchip/irq-bcm6345-ext.h            |   14 +
  14  5 files changed, 335 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
  16  create mode 100644 drivers/irqchip/irq-bcm6345-ext.c
  17  create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h
  18
  19 --- /dev/null
  20 +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
  21 @@ -0,0 +1,29 @@
  22 +Broadcom BCM6345-style external interrupt controller
  23 +
  24 +Required properties:
  25 +
  26 +- compatible: Should be "brcm,bcm6345-l2-intc".
  27 +- reg: Specifies the base physical addresses and size of the registers.
  28 +- interrupt-controller: identifies the node as an interrupt controller.
  29 +- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
  30 +  source, Should be 2.
  31 +- interrupt-parent: Specifies the phandle to the parent interrupt controller
  32 +  this one is cascaded from.
  33 +- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
  34 +  node, valid values depend on the type of parent interrupt controller.
  35 +
  36 +Optional properties:
  37 +
  38 +- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the
  39 +  register. Defaults to 4.
  40 +
  41 +Example:
  42 +
  43 +ext_intc: interrupt-controller@10000018 {
  44 +       compatible = "brcm,bcm6345-l2-intc";
  45 +       interrupt-parent = <&periph_intc>;
  46 +       #interrupt-cells = <2>;
  47 +       reg = <0x10000018 0x4>;
  48 +       interrupt-controller;
  49 +       interrupts = <24>, <25>, <26>, <27>;
  50 +};
  51 --- a/drivers/irqchip/Kconfig
  52 +++ b/drivers/irqchip/Kconfig
  53 @@ -54,6 +54,10 @@ config BRCMSTB_L2_IRQ
  54         select GENERIC_IRQ_CHIP
  55         select IRQ_DOMAIN
  56
  57 +config BCM6345_EXT_IRQ
  58 +       bool
  59 +       select IRQ_DOMAIN
  60 +
  61  config BCM6345_PERIPH_IRQ
  62         bool
  63         select IRQ_DOMAIN
  64 --- a/drivers/irqchip/Makefile
  65 +++ b/drivers/irqchip/Makefile
  66 @@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_MMP)                  += irq-mmp.o
  67  obj-$(CONFIG_ARCH_MVEBU)               += irq-armada-370-xp.o
  68  obj-$(CONFIG_ARCH_MXS)                 += irq-mxs.o
  69  obj-$(CONFIG_ARCH_S3C24XX)             += irq-s3c24xx.o
  70 +obj-$(CONFIG_BCM6345_EXT_IRQ)          += irq-bcm6345-ext.o
  71  obj-$(CONFIG_BCM6345_PERIPH_IRQ)       += irq-bcm6345-periph.o
  72  obj-$(CONFIG_DW_APB_ICTL)              += irq-dw-apb-ictl.o
  73  obj-$(CONFIG_METAG)                    += irq-metag-ext.o
  74 --- /dev/null
  75 +++ b/drivers/irqchip/irq-bcm6345-ext.c
  76 @@ -0,0 +1,287 @@
  77 +/*
  78 + * This file is subject to the terms and conditions of the GNU General Public
  79 + * License.  See the file "COPYING" in the main directory of this archive
  80 + * for more details.
  81 + *
  82 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
  83 + */
  84 +
  85 +#include <linux/ioport.h>
  86 +#include <linux/irq.h>
  87 +#include <linux/irqchip/chained_irq.h>
  88 +#include <linux/irqchip/irq-bcm6345-ext.h>
  89 +#include <linux/kernel.h>
  90 +#include <linux/of.h>
  91 +#include <linux/of_irq.h>
  92 +#include <linux/of_address.h>
  93 +#include <linux/slab.h>
  94 +#include <linux/spinlock.h>
  95 +
  96 +#include "irqchip.h"
  97 +
  98 +#ifdef CONFIG_BCM63XX
  99 +#include <asm/mach-bcm63xx/bcm63xx_irq.h>
 100 +
 101 +#define VIRQ_BASE              IRQ_EXTERNAL_BASE
 102 +#else
 103 +#define VIRQ_BASE              0
 104 +#endif
 105 +
 106 +#define MAX_IRQS               4
 107 +
 108 +#define EXTIRQ_CFG_SENSE       0
 109 +#define EXTIRQ_CFG_STAT                1
 110 +#define EXTIRQ_CFG_CLEAR       2
 111 +#define EXTIRQ_CFG_MASK                3
 112 +#define EXTIRQ_CFG_BOTHEDGE    4
 113 +#define EXTIRQ_CFG_LEVELSENSE  5
 114 +
 115 +struct intc_data {
 116 +       struct irq_chip chip;
 117 +       struct irq_domain *domain;
 118 +       raw_spinlock_t lock;
 119 +
 120 +       int parent_irq[MAX_IRQS];
 121 +       void __iomem *reg;
 122 +       int shift;
 123 +};
 124 +
 125 +static void bcm6345_ext_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
 126 +{
 127 +       struct intc_data *data = irq_desc_get_handler_data(desc);
 128 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 129 +       unsigned int idx;
 130 +
 131 +       chained_irq_enter(chip, desc);
 132 +
 133 +       for (idx = 0; idx < MAX_IRQS; idx++) {
 134 +               if (data->parent_irq[idx] != irq)
 135 +                       continue;
 136 +
 137 +               generic_handle_irq(irq_find_mapping(data->domain, idx));
 138 +       }
 139 +
 140 +       chained_irq_exit(chip, desc);
 141 +}
 142 +
 143 +static void bcm6345_ext_intc_irq_ack(struct irq_data *data)
 144 +{
 145 +       struct intc_data *priv = data->domain->host_data;
 146 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 147 +       u32 reg;
 148 +
 149 +       raw_spin_lock(&priv->lock);
 150 +       reg = __raw_readl(priv->reg);
 151 +       reg |= hwirq << (EXTIRQ_CFG_CLEAR * priv->shift);
 152 +       __raw_writel(reg, priv->reg);
 153 +       raw_spin_unlock(&priv->lock);
 154 +}
 155 +
 156 +static void bcm6345_ext_intc_irq_mask(struct irq_data *data)
 157 +{
 158 +       struct intc_data *priv = data->domain->host_data;
 159 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 160 +       u32 reg;
 161 +
 162 +       raw_spin_lock(&priv->lock);
 163 +       reg = __raw_readl(priv->reg);
 164 +       reg &= ~(hwirq << (EXTIRQ_CFG_MASK * priv->shift));
 165 +       __raw_writel(reg, priv->reg);
 166 +       raw_spin_unlock(&priv->lock);
 167 +}
 168 +
 169 +static void bcm6345_ext_intc_irq_unmask(struct irq_data *data)
 170 +{
 171 +       struct intc_data *priv = data->domain->host_data;
 172 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 173 +       u32 reg;
 174 +
 175 +       raw_spin_lock(&priv->lock);
 176 +       reg = __raw_readl(priv->reg);
 177 +       reg |= hwirq << (EXTIRQ_CFG_MASK * priv->shift);
 178 +       __raw_writel(reg, priv->reg);
 179 +       raw_spin_unlock(&priv->lock);
 180 +}
 181 +
 182 +static int bcm6345_ext_intc_set_type(struct irq_data *data,
 183 +                                    unsigned int flow_type)
 184 +{
 185 +       struct intc_data *priv = data->domain->host_data;
 186 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 187 +       bool levelsense = 0, sense = 0, bothedge = 0;
 188 +       u32 reg;
 189 +
 190 +       flow_type &= IRQ_TYPE_SENSE_MASK;
 191 +
 192 +       if (flow_type == IRQ_TYPE_NONE)
 193 +               flow_type = IRQ_TYPE_LEVEL_LOW;
 194 +
 195 +       switch (flow_type) {
 196 +       case IRQ_TYPE_EDGE_BOTH:
 197 +               bothedge = 1;
 198 +               break;
 199 +
 200 +       case IRQ_TYPE_EDGE_RISING:
 201 +               break;
 202 +
 203 +       case IRQ_TYPE_EDGE_FALLING:
 204 +               sense = 1;
 205 +               break;
 206 +
 207 +       case IRQ_TYPE_LEVEL_HIGH:
 208 +               levelsense = 1;
 209 +               sense = 1;
 210 +               break;
 211 +
 212 +       case IRQ_TYPE_LEVEL_LOW:
 213 +               levelsense = 1;
 214 +               break;
 215 +
 216 +       default:
 217 +               pr_err("bogus flow type combination given!\n");
 218 +               return -EINVAL;
 219 +       }
 220 +
 221 +       raw_spin_lock(&priv->lock);
 222 +       reg = __raw_readl(priv->reg);
 223 +
 224 +       if (levelsense)
 225 +               reg |= hwirq << (EXTIRQ_CFG_LEVELSENSE * priv->shift);
 226 +       else
 227 +               reg &= ~(hwirq << (EXTIRQ_CFG_LEVELSENSE * priv->shift));
 228 +       if (sense)
 229 +               reg |= hwirq << (EXTIRQ_CFG_SENSE * priv->shift);
 230 +       else
 231 +               reg &= ~(hwirq << (EXTIRQ_CFG_SENSE * priv->shift));
 232 +       if (bothedge)
 233 +               reg |= hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift);
 234 +       else
 235 +               reg &= ~(hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift));
 236 +
 237 +       __raw_writel(reg, priv->reg);
 238 +       raw_spin_unlock(&priv->lock);
 239 +
 240 +       irqd_set_trigger_type(data, flow_type);
 241 +       if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 242 +               __irq_set_handler_locked(data->irq, handle_level_irq);
 243 +       else
 244 +               __irq_set_handler_locked(data->irq, handle_edge_irq);
 245 +
 246 +       return 0;
 247 +}
 248 +
 249 +static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq,
 250 +                               irq_hw_number_t hw)
 251 +{
 252 +       struct intc_data *priv = d->host_data;
 253 +
 254 +       irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
 255 +
 256 +       return 0;
 257 +}
 258 +
 259 +static const struct irq_domain_ops bcm6345_ext_domain_ops = {
 260 +       .xlate = irq_domain_xlate_twocell,
 261 +       .map = bcm6345_ext_intc_map,
 262 +};
 263 +
 264 +static int __init __bcm6345_ext_intc_init(struct device_node *node,
 265 +                                         int num_irqs, int *irqs,
 266 +                                         void __iomem *reg, int shift)
 267 +{
 268 +       struct intc_data *data;
 269 +       unsigned int i;
 270 +       int start = VIRQ_BASE;
 271 +
 272 +       data = kzalloc(sizeof(*data), GFP_KERNEL);
 273 +       if (!data)
 274 +               return -ENOMEM;
 275 +
 276 +       raw_spin_lock_init(&data->lock);
 277 +
 278 +       for (i = 0; i < num_irqs; i++) {
 279 +               data->parent_irq[i] = irqs[i];
 280 +
 281 +               irq_set_handler_data(irqs[i], data);
 282 +               irq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle);
 283 +       }
 284 +
 285 +       data->reg = reg;
 286 +
 287 +       data->chip.name = "bcm6345-ext-intc";
 288 +       data->chip.irq_ack = bcm6345_ext_intc_irq_ack;
 289 +       data->chip.irq_mask = bcm6345_ext_intc_irq_mask;
 290 +       data->chip.irq_unmask = bcm6345_ext_intc_irq_unmask;
 291 +       data->chip.irq_set_type = bcm6345_ext_intc_set_type;
 292 +
 293 +       /*
 294 +        * If we have less than 4 irqs, this is the second controller on
 295 +        * bcm63xx. So increase the VIRQ start to not overlap with the first
 296 +        * one, but only do so if we actually use a non-zero start.
 297 +        *
 298 +        * This can be removed when bcm63xx has no legacy users anymore.
 299 +        */
 300 +       if (start && num_irqs < 4)
 301 +               start += 4;
 302 +
 303 +       data->domain = irq_domain_add_simple(node, num_irqs, start,
 304 +                                            &bcm6345_ext_domain_ops, data);
 305 +       if (!data->domain) {
 306 +               kfree(data);
 307 +               return -ENOMEM;
 308 +       }
 309 +
 310 +       return 0;
 311 +}
 312 +
 313 +void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg,
 314 +                                 int shift)
 315 +{
 316 +       __bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift);
 317 +}
 318 +
 319 +#ifdef CONFIG_OF
 320 +static int __init bcm6345_ext_intc_of_init(struct device_node *node,
 321 +                                          struct device_node *parent)
 322 +{
 323 +       int num_irqs, ret = -EINVAL;
 324 +       unsigned i;
 325 +       void __iomem *base;
 326 +       int irqs[MAX_IRQS] = { 0 };
 327 +       u32 shift;
 328 +
 329 +       num_irqs = of_irq_count(node);
 330 +
 331 +       if (!num_irqs || num_irqs > MAX_IRQS)
 332 +               return -EINVAL;
 333 +
 334 +       if (of_property_read_u32(node, "brcm,field-width", &shift))
 335 +               shift = 4;
 336 +
 337 +       for (i = 0; i < num_irqs; i++) {
 338 +               irqs[i] = irq_of_parse_and_map(node, i);
 339 +               if (!irqs[i]) {
 340 +                       ret = -ENOMEM;
 341 +                       goto out_unmap;
 342 +               }
 343 +       }
 344 +
 345 +       base = of_iomap(node, 0);
 346 +       if (!base)
 347 +               goto out_unmap;
 348 +
 349 +       ret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift);
 350 +       if (!ret)
 351 +               return 0;
 352 +out_unmap:
 353 +       iounmap(base);
 354 +
 355 +       for (i = 0; i < num_irqs; i++)
 356 +               irq_dispose_mapping(irqs[i]);
 357 +
 358 +       return ret;
 359 +}
 360 +
 361 +IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc",
 362 +               bcm6345_ext_intc_of_init);
 363 +#endif
 364 --- /dev/null
 365 +++ b/include/linux/irqchip/irq-bcm6345-ext.h
 366 @@ -0,0 +1,14 @@
 367 +/*
 368 + * This file is subject to the terms and conditions of the GNU General Public
 369 + * License.  See the file "COPYING" in the main directory of this archive
 370 + * for more details.
 371 + *
 372 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
 373 + */
 374 +
 375 +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
 376 +#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
 377 +
 378 +void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift);
 379 +
 380 +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */