ar71xx: add user-space support for GL.iNet v1
[openwrt.git] / target / linux / brcm63xx / patches-3.14 / 319-MIPS-BCM63XX-move-bcm63xx_init_irq-down.patch
1 From 6e79c6dd02aa56e37eb071797f0eb5e3fb588cba Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sun, 15 Dec 2013 20:52:53 +0100
4 Subject: [PATCH 02/10] MIPS: BCM63XX: move bcm63xx_init_irq down
5
6 Allows up to drop the prototypes from the top.
7
8 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
9 ---
10  arch/mips/bcm63xx/irq.c | 190 +++++++++++++++++++++++-------------------------
11  1 file changed, 92 insertions(+), 98 deletions(-)
12
13 --- a/arch/mips/bcm63xx/irq.c
14 +++ b/arch/mips/bcm63xx/irq.c
15 @@ -19,13 +19,6 @@
16  #include <bcm63xx_io.h>
17  #include <bcm63xx_irq.h>
18  
19 -static void __dispatch_internal_32(void) __maybe_unused;
20 -static void __dispatch_internal_64(void) __maybe_unused;
21 -static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
22 -static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
23 -static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
24 -static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
25 -
26  static u32 irq_stat_addr, irq_mask_addr;
27  static void (*dispatch_internal)(void);
28  static int is_ext_irq_cascaded;
29 @@ -35,97 +28,6 @@ static unsigned int ext_irq_cfg_reg1, ex
30  static void (*internal_irq_mask)(unsigned int irq);
31  static void (*internal_irq_unmask)(unsigned int irq);
32  
33 -static void bcm63xx_init_irq(void)
34 -{
35 -       int irq_bits;
36 -
37 -       irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
38 -       irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
39 -
40 -       switch (bcm63xx_get_cpu_id()) {
41 -       case BCM3368_CPU_ID:
42 -               irq_stat_addr += PERF_IRQSTAT_3368_REG;
43 -               irq_mask_addr += PERF_IRQMASK_3368_REG;
44 -               irq_bits = 32;
45 -               ext_irq_count = 4;
46 -               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
47 -               break;
48 -       case BCM6328_CPU_ID:
49 -               irq_stat_addr += PERF_IRQSTAT_6328_REG;
50 -               irq_mask_addr += PERF_IRQMASK_6328_REG;
51 -               irq_bits = 64;
52 -               ext_irq_count = 4;
53 -               is_ext_irq_cascaded = 1;
54 -               ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
55 -               ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
56 -               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
57 -               break;
58 -       case BCM6338_CPU_ID:
59 -               irq_stat_addr += PERF_IRQSTAT_6338_REG;
60 -               irq_mask_addr += PERF_IRQMASK_6338_REG;
61 -               irq_bits = 32;
62 -               ext_irq_count = 4;
63 -               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
64 -               break;
65 -       case BCM6345_CPU_ID:
66 -               irq_stat_addr += PERF_IRQSTAT_6345_REG;
67 -               irq_mask_addr += PERF_IRQMASK_6345_REG;
68 -               irq_bits = 32;
69 -               ext_irq_count = 4;
70 -               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
71 -               break;
72 -       case BCM6348_CPU_ID:
73 -               irq_stat_addr += PERF_IRQSTAT_6348_REG;
74 -               irq_mask_addr += PERF_IRQMASK_6348_REG;
75 -               irq_bits = 32;
76 -               ext_irq_count = 4;
77 -               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
78 -               break;
79 -       case BCM6358_CPU_ID:
80 -               irq_stat_addr += PERF_IRQSTAT_6358_REG;
81 -               irq_mask_addr += PERF_IRQMASK_6358_REG;
82 -               irq_bits = 32;
83 -               ext_irq_count = 4;
84 -               is_ext_irq_cascaded = 1;
85 -               ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
86 -               ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
87 -               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
88 -               break;
89 -       case BCM6362_CPU_ID:
90 -               irq_stat_addr += PERF_IRQSTAT_6362_REG;
91 -               irq_mask_addr += PERF_IRQMASK_6362_REG;
92 -               irq_bits = 64;
93 -               ext_irq_count = 4;
94 -               is_ext_irq_cascaded = 1;
95 -               ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
96 -               ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
97 -               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
98 -               break;
99 -       case BCM6368_CPU_ID:
100 -               irq_stat_addr += PERF_IRQSTAT_6368_REG;
101 -               irq_mask_addr += PERF_IRQMASK_6368_REG;
102 -               irq_bits = 64;
103 -               ext_irq_count = 6;
104 -               is_ext_irq_cascaded = 1;
105 -               ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
106 -               ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
107 -               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
108 -               ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
109 -               break;
110 -       default:
111 -               BUG();
112 -       }
113 -
114 -       if (irq_bits == 32) {
115 -               dispatch_internal = __dispatch_internal_32;
116 -               internal_irq_mask = __internal_irq_mask_32;
117 -               internal_irq_unmask = __internal_irq_unmask_32;
118 -       } else {
119 -               dispatch_internal = __dispatch_internal_64;
120 -               internal_irq_mask = __internal_irq_mask_64;
121 -               internal_irq_unmask = __internal_irq_unmask_64;
122 -       }
123 -}
124  
125  static inline u32 get_ext_irq_perf_reg(int irq)
126  {
127 @@ -451,6 +353,98 @@ static struct irqaction cpu_ext_cascade_
128         .flags          = IRQF_NO_THREAD,
129  };
130  
131 +static void bcm63xx_init_irq(void)
132 +{
133 +       int irq_bits;
134 +
135 +       irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
136 +       irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
137 +
138 +       switch (bcm63xx_get_cpu_id()) {
139 +       case BCM3368_CPU_ID:
140 +               irq_stat_addr += PERF_IRQSTAT_3368_REG;
141 +               irq_mask_addr += PERF_IRQMASK_3368_REG;
142 +               irq_bits = 32;
143 +               ext_irq_count = 4;
144 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
145 +               break;
146 +       case BCM6328_CPU_ID:
147 +               irq_stat_addr += PERF_IRQSTAT_6328_REG;
148 +               irq_mask_addr += PERF_IRQMASK_6328_REG;
149 +               irq_bits = 64;
150 +               ext_irq_count = 4;
151 +               is_ext_irq_cascaded = 1;
152 +               ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
153 +               ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
154 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
155 +               break;
156 +       case BCM6338_CPU_ID:
157 +               irq_stat_addr += PERF_IRQSTAT_6338_REG;
158 +               irq_mask_addr += PERF_IRQMASK_6338_REG;
159 +               irq_bits = 32;
160 +               ext_irq_count = 4;
161 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
162 +               break;
163 +       case BCM6345_CPU_ID:
164 +               irq_stat_addr += PERF_IRQSTAT_6345_REG;
165 +               irq_mask_addr += PERF_IRQMASK_6345_REG;
166 +               irq_bits = 32;
167 +               ext_irq_count = 4;
168 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
169 +               break;
170 +       case BCM6348_CPU_ID:
171 +               irq_stat_addr += PERF_IRQSTAT_6348_REG;
172 +               irq_mask_addr += PERF_IRQMASK_6348_REG;
173 +               irq_bits = 32;
174 +               ext_irq_count = 4;
175 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
176 +               break;
177 +       case BCM6358_CPU_ID:
178 +               irq_stat_addr += PERF_IRQSTAT_6358_REG;
179 +               irq_mask_addr += PERF_IRQMASK_6358_REG;
180 +               irq_bits = 32;
181 +               ext_irq_count = 4;
182 +               is_ext_irq_cascaded = 1;
183 +               ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
184 +               ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
185 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
186 +               break;
187 +       case BCM6362_CPU_ID:
188 +               irq_stat_addr += PERF_IRQSTAT_6362_REG;
189 +               irq_mask_addr += PERF_IRQMASK_6362_REG;
190 +               irq_bits = 64;
191 +               ext_irq_count = 4;
192 +               is_ext_irq_cascaded = 1;
193 +               ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
194 +               ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
195 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
196 +               break;
197 +       case BCM6368_CPU_ID:
198 +               irq_stat_addr += PERF_IRQSTAT_6368_REG;
199 +               irq_mask_addr += PERF_IRQMASK_6368_REG;
200 +               irq_bits = 64;
201 +               ext_irq_count = 6;
202 +               is_ext_irq_cascaded = 1;
203 +               ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
204 +               ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
205 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
206 +               ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
207 +               break;
208 +       default:
209 +               BUG();
210 +       }
211 +
212 +       if (irq_bits == 32) {
213 +               dispatch_internal = __dispatch_internal_32;
214 +               internal_irq_mask = __internal_irq_mask_32;
215 +               internal_irq_unmask = __internal_irq_unmask_32;
216 +       } else {
217 +               dispatch_internal = __dispatch_internal_64;
218 +               internal_irq_mask = __internal_irq_mask_64;
219 +               internal_irq_unmask = __internal_irq_unmask_64;
220 +       }
221 +}
222 +
223  void __init arch_init_irq(void)
224  {
225         int i;