target/linux/brcm63xx/patches-3.10/044-MIPS-BCM63XX-Enable-second-core-SMP-on-BCM6328-if-av.patch

   1 From 41fa6dec9df9b4e55ac522c899270a72e51a9b4b Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sat, 9 Jul 2011 12:15:06 -0700
   4 Subject: [PATCH V2 2/2] MIPS: BCM63XX: Enable second core SMP on BCM6328 if
   5  available
   6
   7 BCM6328 has a OTP which tells us if the second core is available.
   8
   9 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  10 ---
  11  arch/mips/bcm63xx/prom.c                          |    6 +++++-
  12  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    2 ++
  13  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    7 +++++++
  14  3 files changed, 14 insertions(+), 1 deletion(-)
  15
  16 --- a/arch/mips/bcm63xx/prom.c
  17 +++ b/arch/mips/bcm63xx/prom.c
  18 @@ -69,7 +69,11 @@ void __init prom_init(void)
  19                  * for now.
  20                  */
  21                 if (BCMCPU_IS_6328()) {
  22 -                       bmips_smp_enabled = 0;
  23 +                       reg = bcm_readl(BCM_6328_OTP_BASE +
  24 +                                       OTP_USER_BITS_6328_REG(3));
  25 +
  26 +                       if (reg & OTP_6328_REG3_TP1_DISABLED)
  27 +                               bmips_smp_enabled = 0;
  28                 } else if (BCMCPU_IS_6358()) {
  29                         bmips_smp_enabled = 0;
  30                 }
  31 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  32 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  33 @@ -296,6 +296,8 @@ enum bcm63xx_regs_set {
  34  #define BCM_6328_PCMDMAS_BASE          (0xdeadbeef)
  35  #define BCM_6328_RNG_BASE              (0xdeadbeef)
  36  #define BCM_6328_MISC_BASE             (0xb0001800)
  37 +#define BCM_6328_OTP_BASE              (0xb0000600)
  38 +
  39  /*
  40   * 6338 register sets base address
  41   */
  42 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  43 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  44 @@ -1477,4 +1477,11 @@
  45
  46  #define PCIE_DEVICE_OFFSET             0x8000
  47
  48 +/*************************************************************************
  49 + * _REG relative to RSET_OTP
  50 + *************************************************************************/
  51 +
  52 +#define OTP_USER_BITS_6328_REG(i)      (0x20 + (i) * 4)
  53 +#define   OTP_6328_REG3_TP1_DISABLED   BIT(9)
  54 +
  55  #endif /* BCM63XX_REGS_H_ */