target/linux/brcm63xx/patches-3.10/036-MIPS-BCM63XX-add-support-for-BCM3368-Cable-Modem.patch

   1 From 31c761c9c1fa91bf4ed83d75dcbc4e426ea2b670 Mon Sep 17 00:00:00 2001
   2 From: Florian Fainelli <florian@openwrt.org>
   3 Date: Tue, 18 Jun 2013 16:55:40 +0000
   4 Subject: [PATCH 2/6] MIPS: BCM63XX: add support for BCM3368 Cable Modem
   5
   6 The Broadcom BCM3368 Cable Modem SoC is extremely similar to the
   7 existing BCM63xx DSL SoCs, in particular BCM6358, therefore little effort
   8 in the existing code base is required to get it supported. This patch adds
   9 support for the following on-chip peripherals:
  10
  11 - two UARTS
  12 - GPIO
  13 - Ethernet
  14 - SPI
  15 - PCI
  16 - NOR Flash
  17
  18 The most noticeable difference with 3368 is that it has its peripheral
  19 register at 0xfff8_0000 we check that separately in ioremap.h. Since
  20 3368 is identical to 6358 for its clock and reset bits, we use them
  21 verbatim.
  22
  23 Signed-off-by: Florian Fainelli <florian@openwrt.org>
  24 Cc: linux-mips@linux-mips.org
  25 Cc: cernekee@gmail.com
  26 Cc: jogo@openwrt.org
  27 Patchwork: https://patchwork.linux-mips.org/patch/5499/
  28 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  29 ---
  30  arch/mips/bcm63xx/Kconfig                         |    4 +
  31  arch/mips/bcm63xx/clk.c                           |   18 ++--
  32  arch/mips/bcm63xx/cpu.c                           |   28 +++++-
  33  arch/mips/bcm63xx/dev-flash.c                     |    1 +
  34  arch/mips/bcm63xx/dev-spi.c                       |    6 +-
  35  arch/mips/bcm63xx/dev-uart.c                      |    3 +-
  36  arch/mips/bcm63xx/irq.c                           |   19 ++++
  37  arch/mips/bcm63xx/prom.c                          |    4 +-
  38  arch/mips/bcm63xx/reset.c                         |   29 +++++-
  39  arch/mips/bcm63xx/setup.c                         |    3 +
  40  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |  110 +++++++++++++++++++++
  41  arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |    1 +
  42  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   45 ++++++++-
  43  arch/mips/include/asm/mach-bcm63xx/ioremap.h      |    4 +
  44  arch/mips/pci/pci-bcm63xx.c                       |    3 +-
  45  15 files changed, 259 insertions(+), 19 deletions(-)
  46
  47 --- a/arch/mips/bcm63xx/Kconfig
  48 +++ b/arch/mips/bcm63xx/Kconfig
  49 @@ -1,6 +1,10 @@
  50  menu "CPU support"
  51         depends on BCM63XX
  52
  53 +config BCM63XX_CPU_3368
  54 +       bool "support 3368 CPU"
  55 +       select HW_HAS_PCI
  56 +
  57  config BCM63XX_CPU_6328
  58         bool "support 6328 CPU"
  59         select HW_HAS_PCI
  60 --- a/arch/mips/bcm63xx/clk.c
  61 +++ b/arch/mips/bcm63xx/clk.c
  62 @@ -84,7 +84,7 @@ static void enetx_set(struct clk *clk, i
  63         else
  64                 clk_disable_unlocked(&clk_enet_misc);
  65
  66 -       if (BCMCPU_IS_6358()) {
  67 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
  68                 u32 mask;
  69
  70                 if (clk->id == 0)
  71 @@ -110,9 +110,8 @@ static struct clk clk_enet1 = {
  72   */
  73  static void ephy_set(struct clk *clk, int enable)
  74  {
  75 -       if (!BCMCPU_IS_6358())
  76 -               return;
  77 -       bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
  78 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
  79 +               bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
  80  }
  81
  82
  83 @@ -155,9 +154,10 @@ static struct clk clk_enetsw = {
  84   */
  85  static void pcm_set(struct clk *clk, int enable)
  86  {
  87 -       if (!BCMCPU_IS_6358())
  88 -               return;
  89 -       bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
  90 +       if (BCMCPU_IS_3368())
  91 +               bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
  92 +       if (BCMCPU_IS_6358())
  93 +               bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
  94  }
  95
  96  static struct clk clk_pcm = {
  97 @@ -211,7 +211,7 @@ static void spi_set(struct clk *clk, int
  98                 mask = CKCTL_6338_SPI_EN;
  99         else if (BCMCPU_IS_6348())
 100                 mask = CKCTL_6348_SPI_EN;
 101 -       else if (BCMCPU_IS_6358())
 102 +       else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
 103                 mask = CKCTL_6358_SPI_EN;
 104         else if (BCMCPU_IS_6362())
 105                 mask = CKCTL_6362_SPI_EN;
 106 @@ -338,7 +338,7 @@ struct clk *clk_get(struct device *dev,
 107                 return &clk_xtm;
 108         if (!strcmp(id, "periph"))
 109                 return &clk_periph;
 110 -       if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
 111 +       if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
 112                 return &clk_pcm;
 113         if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
 114                 return &clk_ipsec;
 115 --- a/arch/mips/bcm63xx/cpu.c
 116 +++ b/arch/mips/bcm63xx/cpu.c
 117 @@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev;
 118  static unsigned int bcm63xx_cpu_freq;
 119  static unsigned int bcm63xx_memory_size;
 120
 121 +static const unsigned long bcm3368_regs_base[] = {
 122 +       __GEN_CPU_REGS_TABLE(3368)
 123 +};
 124 +
 125 +static const int bcm3368_irqs[] = {
 126 +       __GEN_CPU_IRQ_TABLE(3368)
 127 +};
 128 +
 129  static const unsigned long bcm6328_regs_base[] = {
 130         __GEN_CPU_REGS_TABLE(6328)
 131  };
 132 @@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(voi
 133  static unsigned int detect_cpu_clock(void)
 134  {
 135         switch (bcm63xx_get_cpu_id()) {
 136 +       case BCM3368_CPU_ID:
 137 +               return 300000000;
 138 +
 139         case BCM6328_CPU_ID:
 140         {
 141                 unsigned int tmp, mips_pll_fcvo;
 142 @@ -266,7 +277,7 @@ static unsigned int detect_memory_size(v
 143                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 144         }
 145
 146 -       if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
 147 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
 148                 val = bcm_memc_readl(MEMC_CFG_REG);
 149                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 150                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
 151 @@ -302,10 +313,17 @@ void __init bcm63xx_cpu_init(void)
 152                 chipid_reg = BCM_6345_PERF_BASE;
 153                 break;
 154         case CPU_BMIPS4350:
 155 -               if ((read_c0_prid() & 0xf0) == 0x10)
 156 +               switch ((read_c0_prid() & 0xff)) {
 157 +               case 0x04:
 158 +                       chipid_reg = BCM_3368_PERF_BASE;
 159 +                       break;
 160 +               case 0x10:
 161                         chipid_reg = BCM_6345_PERF_BASE;
 162 -               else
 163 +                       break;
 164 +               default:
 165                         chipid_reg = BCM_6368_PERF_BASE;
 166 +                       break;
 167 +               }
 168                 break;
 169         }
 170
 171 @@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void)
 172         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 173
 174         switch (bcm63xx_cpu_id) {
 175 +       case BCM3368_CPU_ID:
 176 +               bcm63xx_regs_base = bcm3368_regs_base;
 177 +               bcm63xx_irqs = bcm3368_irqs;
 178 +               break;
 179         case BCM6328_CPU_ID:
 180                 bcm63xx_regs_base = bcm6328_regs_base;
 181                 bcm63xx_irqs = bcm6328_irqs;
 182 --- a/arch/mips/bcm63xx/dev-flash.c
 183 +++ b/arch/mips/bcm63xx/dev-flash.c
 184 @@ -71,6 +71,7 @@ static int __init bcm63xx_detect_flash_t
 185         case BCM6348_CPU_ID:
 186                 /* no way to auto detect so assume parallel */
 187                 return BCM63XX_FLASH_TYPE_PARALLEL;
 188 +       case BCM3368_CPU_ID:
 189         case BCM6358_CPU_ID:
 190                 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
 191                 if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
 192 --- a/arch/mips/bcm63xx/dev-spi.c
 193 +++ b/arch/mips/bcm63xx/dev-spi.c
 194 @@ -37,7 +37,8 @@ static __init void bcm63xx_spi_regs_init
 195  {
 196         if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
 197                 bcm63xx_regs_spi = bcm6348_regs_spi;
 198 -       if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
 199 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358() ||
 200 +               BCMCPU_IS_6362() || BCMCPU_IS_6368())
 201                 bcm63xx_regs_spi = bcm6358_regs_spi;
 202  }
 203  #else
 204 @@ -87,7 +88,8 @@ int __init bcm63xx_spi_register(void)
 205                 spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
 206         }
 207
 208 -       if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
 209 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
 210 +               BCMCPU_IS_6368()) {
 211                 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
 212                 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
 213                 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
 214 --- a/arch/mips/bcm63xx/dev-uart.c
 215 +++ b/arch/mips/bcm63xx/dev-uart.c
 216 @@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigne
 217         if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
 218                 return -ENODEV;
 219
 220 -       if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
 221 +       if (id == 1 && (!BCMCPU_IS_3368() && !BCMCPU_IS_6358() &&
 222 +               !BCMCPU_IS_6368()))
 223                 return -ENODEV;
 224
 225         if (id == 0) {
 226 --- a/arch/mips/bcm63xx/irq.c
 227 +++ b/arch/mips/bcm63xx/irq.c
 228 @@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(uns
 229  static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
 230
 231  #ifndef BCMCPU_RUNTIME_DETECT
 232 +#ifdef CONFIG_BCM63XX_CPU_3368
 233 +#define irq_stat_reg           PERF_IRQSTAT_3368_REG
 234 +#define irq_mask_reg           PERF_IRQMASK_3368_REG
 235 +#define irq_bits               32
 236 +#define is_ext_irq_cascaded    0
 237 +#define ext_irq_start          0
 238 +#define ext_irq_end            0
 239 +#define ext_irq_count          4
 240 +#define ext_irq_cfg_reg1       PERF_EXTIRQ_CFG_REG_3368
 241 +#define ext_irq_cfg_reg2       0
 242 +#endif
 243  #ifdef CONFIG_BCM63XX_CPU_6328
 244  #define irq_stat_reg           PERF_IRQSTAT_6328_REG
 245  #define irq_mask_reg           PERF_IRQMASK_6328_REG
 246 @@ -140,6 +151,13 @@ static void bcm63xx_init_irq(void)
 247         irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
 248
 249         switch (bcm63xx_get_cpu_id()) {
 250 +       case BCM3368_CPU_ID:
 251 +               irq_stat_addr += PERF_IRQSTAT_3368_REG;
 252 +               irq_mask_addr += PERF_IRQMASK_3368_REG;
 253 +               irq_bits = 32;
 254 +               ext_irq_count = 4;
 255 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
 256 +               break;
 257         case BCM6328_CPU_ID:
 258                 irq_stat_addr += PERF_IRQSTAT_6328_REG;
 259                 irq_mask_addr += PERF_IRQMASK_6328_REG;
 260 @@ -479,6 +497,7 @@ static int bcm63xx_external_irq_set_type
 261                         reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
 262                 break;
 263
 264 +       case BCM3368_CPU_ID:
 265         case BCM6328_CPU_ID:
 266         case BCM6338_CPU_ID:
 267         case BCM6345_CPU_ID:
 268 --- a/arch/mips/bcm63xx/prom.c
 269 +++ b/arch/mips/bcm63xx/prom.c
 270 @@ -26,7 +26,9 @@ void __init prom_init(void)
 271         bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
 272
 273         /* disable all hardware blocks clock for now */
 274 -       if (BCMCPU_IS_6328())
 275 +       if (BCMCPU_IS_3368())
 276 +               mask = CKCTL_3368_ALL_SAFE_EN;
 277 +       else if (BCMCPU_IS_6328())
 278                 mask = CKCTL_6328_ALL_SAFE_EN;
 279         else if (BCMCPU_IS_6338())
 280                 mask = CKCTL_6338_ALL_SAFE_EN;
 281 --- a/arch/mips/bcm63xx/reset.c
 282 +++ b/arch/mips/bcm63xx/reset.c
 283 @@ -30,6 +30,19 @@
 284         [BCM63XX_RESET_PCIE]            = BCM## __cpu ##_RESET_PCIE,    \
 285         [BCM63XX_RESET_PCIE_EXT]        = BCM## __cpu ##_RESET_PCIE_EXT,
 286
 287 +#define BCM3368_RESET_SPI      SOFTRESET_3368_SPI_MASK
 288 +#define BCM3368_RESET_ENET     SOFTRESET_3368_ENET_MASK
 289 +#define BCM3368_RESET_USBH     0
 290 +#define BCM3368_RESET_USBD     SOFTRESET_3368_USBS_MASK
 291 +#define BCM3368_RESET_DSL      0
 292 +#define BCM3368_RESET_SAR      0
 293 +#define BCM3368_RESET_EPHY     SOFTRESET_3368_EPHY_MASK
 294 +#define BCM3368_RESET_ENETSW   0
 295 +#define BCM3368_RESET_PCM      SOFTRESET_3368_PCM_MASK
 296 +#define BCM3368_RESET_MPI      SOFTRESET_3368_MPI_MASK
 297 +#define BCM3368_RESET_PCIE     0
 298 +#define BCM3368_RESET_PCIE_EXT 0
 299 +
 300  #define BCM6328_RESET_SPI      SOFTRESET_6328_SPI_MASK
 301  #define BCM6328_RESET_ENET     0
 302  #define BCM6328_RESET_USBH     SOFTRESET_6328_USBH_MASK
 303 @@ -117,6 +130,10 @@
 304  /*
 305   * core reset bits
 306   */
 307 +static const u32 bcm3368_reset_bits[] = {
 308 +       __GEN_RESET_BITS_TABLE(3368)
 309 +};
 310 +
 311  static const u32 bcm6328_reset_bits[] = {
 312         __GEN_RESET_BITS_TABLE(6328)
 313  };
 314 @@ -146,7 +163,10 @@ static int reset_reg;
 315
 316  static int __init bcm63xx_reset_bits_init(void)
 317  {
 318 -       if (BCMCPU_IS_6328()) {
 319 +       if (BCMCPU_IS_3368()) {
 320 +               reset_reg = PERF_SOFTRESET_6358_REG;
 321 +               bcm63xx_reset_bits = bcm3368_reset_bits;
 322 +       } else if (BCMCPU_IS_6328()) {
 323                 reset_reg = PERF_SOFTRESET_6328_REG;
 324                 bcm63xx_reset_bits = bcm6328_reset_bits;
 325         } else if (BCMCPU_IS_6338()) {
 326 @@ -170,6 +190,13 @@ static int __init bcm63xx_reset_bits_ini
 327  }
 328  #else
 329
 330 +#ifdef CONFIG_BCM63XX_CPU_3368
 331 +static const u32 bcm63xx_reset_bits[] = {
 332 +       __GEN_RESET_BITS_TABLE(3368)
 333 +};
 334 +#define reset_reg PERF_SOFTRESET_6358_REG
 335 +#endif
 336 +
 337  #ifdef CONFIG_BCM63XX_CPU_6328
 338  static const u32 bcm63xx_reset_bits[] = {
 339         __GEN_RESET_BITS_TABLE(6328)
 340 --- a/arch/mips/bcm63xx/setup.c
 341 +++ b/arch/mips/bcm63xx/setup.c
 342 @@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
 343
 344         /* mask and clear all external irq */
 345         switch (bcm63xx_get_cpu_id()) {
 346 +       case BCM3368_CPU_ID:
 347 +               perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
 348 +               break;
 349         case BCM6328_CPU_ID:
 350                 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
 351                 break;
 352 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 353 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 354 @@ -9,6 +9,7 @@
 355   * compile time if only one CPU support is enabled (idea stolen from
 356   * arm mach-types)
 357   */
 358 +#define BCM3368_CPU_ID         0x3368
 359  #define BCM6328_CPU_ID         0x6328
 360  #define BCM6338_CPU_ID         0x6338
 361  #define BCM6345_CPU_ID         0x6345
 362 @@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
 363  u8 bcm63xx_get_cpu_rev(void);
 364  unsigned int bcm63xx_get_cpu_freq(void);
 365
 366 +#ifdef CONFIG_BCM63XX_CPU_3368
 367 +# ifdef bcm63xx_get_cpu_id
 368 +#  undef bcm63xx_get_cpu_id
 369 +#  define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
 370 +#  define BCMCPU_RUNTIME_DETECT
 371 +# else
 372 +#  define bcm63xx_get_cpu_id() BCM3368_CPU_ID
 373 +# endif
 374 +# define BCMCPU_IS_3368()      (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
 375 +#else
 376 +# define BCMCPU_IS_3368()      (0)
 377 +#endif
 378 +
 379  #ifdef CONFIG_BCM63XX_CPU_6328
 380  # ifdef bcm63xx_get_cpu_id
 381  #  undef bcm63xx_get_cpu_id
 382 @@ -191,6 +205,53 @@ enum bcm63xx_regs_set {
 383  #define RSET_RNG_SIZE                  20
 384
 385  /*
 386 + * 3368 register sets base address
 387 + */
 388 +#define BCM_3368_DSL_LMEM_BASE         (0xdeadbeef)
 389 +#define BCM_3368_PERF_BASE             (0xfff8c000)
 390 +#define BCM_3368_TIMER_BASE            (0xfff8c040)
 391 +#define BCM_3368_WDT_BASE              (0xfff8c080)
 392 +#define BCM_3368_UART0_BASE            (0xfff8c100)
 393 +#define BCM_3368_UART1_BASE            (0xfff8c120)
 394 +#define BCM_3368_GPIO_BASE             (0xfff8c080)
 395 +#define BCM_3368_SPI_BASE              (0xfff8c800)
 396 +#define BCM_3368_HSSPI_BASE            (0xdeadbeef)
 397 +#define BCM_3368_UDC0_BASE             (0xdeadbeef)
 398 +#define BCM_3368_USBDMA_BASE           (0xdeadbeef)
 399 +#define BCM_3368_OHCI0_BASE            (0xdeadbeef)
 400 +#define BCM_3368_OHCI_PRIV_BASE                (0xdeadbeef)
 401 +#define BCM_3368_USBH_PRIV_BASE                (0xdeadbeef)
 402 +#define BCM_3368_USBD_BASE             (0xdeadbeef)
 403 +#define BCM_3368_MPI_BASE              (0xfff80000)
 404 +#define BCM_3368_PCMCIA_BASE           (0xfff80054)
 405 +#define BCM_3368_PCIE_BASE             (0xdeadbeef)
 406 +#define BCM_3368_SDRAM_REGS_BASE       (0xdeadbeef)
 407 +#define BCM_3368_DSL_BASE              (0xdeadbeef)
 408 +#define BCM_3368_UBUS_BASE             (0xdeadbeef)
 409 +#define BCM_3368_ENET0_BASE            (0xfff98000)
 410 +#define BCM_3368_ENET1_BASE            (0xfff98800)
 411 +#define BCM_3368_ENETDMA_BASE          (0xfff99800)
 412 +#define BCM_3368_ENETDMAC_BASE         (0xfff99900)
 413 +#define BCM_3368_ENETDMAS_BASE         (0xfff99a00)
 414 +#define BCM_3368_ENETSW_BASE           (0xdeadbeef)
 415 +#define BCM_3368_EHCI0_BASE            (0xdeadbeef)
 416 +#define BCM_3368_SDRAM_BASE            (0xdeadbeef)
 417 +#define BCM_3368_MEMC_BASE             (0xfff84000)
 418 +#define BCM_3368_DDR_BASE              (0xdeadbeef)
 419 +#define BCM_3368_M2M_BASE              (0xdeadbeef)
 420 +#define BCM_3368_ATM_BASE              (0xdeadbeef)
 421 +#define BCM_3368_XTM_BASE              (0xdeadbeef)
 422 +#define BCM_3368_XTMDMA_BASE           (0xdeadbeef)
 423 +#define BCM_3368_XTMDMAC_BASE          (0xdeadbeef)
 424 +#define BCM_3368_XTMDMAS_BASE          (0xdeadbeef)
 425 +#define BCM_3368_PCM_BASE              (0xfff9c200)
 426 +#define BCM_3368_PCMDMA_BASE           (0xdeadbeef)
 427 +#define BCM_3368_PCMDMAC_BASE          (0xdeadbeef)
 428 +#define BCM_3368_PCMDMAS_BASE          (0xdeadbeef)
 429 +#define BCM_3368_RNG_BASE              (0xdeadbeef)
 430 +#define BCM_3368_MISC_BASE             (0xdeadbeef)
 431 +
 432 +/*
 433   * 6328 register sets base address
 434   */
 435  #define BCM_6328_DSL_LMEM_BASE         (0xdeadbeef)
 436 @@ -620,6 +681,9 @@ static inline unsigned long bcm63xx_regs
 437  #ifdef BCMCPU_RUNTIME_DETECT
 438         return bcm63xx_regs_base[set];
 439  #else
 440 +#ifdef CONFIG_BCM63XX_CPU_3368
 441 +       __GEN_RSET(3368)
 442 +#endif
 443  #ifdef CONFIG_BCM63XX_CPU_6328
 444         __GEN_RSET(6328)
 445  #endif
 446 @@ -687,6 +751,52 @@ enum bcm63xx_irq {
 447  };
 448
 449  /*
 450 + * 3368 irqs
 451 + */
 452 +#define BCM_3368_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 453 +#define BCM_3368_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 454 +#define BCM_3368_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 455 +#define BCM_3368_UART1_IRQ             (IRQ_INTERNAL_BASE + 3)
 456 +#define BCM_3368_DSL_IRQ               0
 457 +#define BCM_3368_UDC0_IRQ              0
 458 +#define BCM_3368_OHCI0_IRQ             0
 459 +#define BCM_3368_ENET0_IRQ             (IRQ_INTERNAL_BASE + 8)
 460 +#define BCM_3368_ENET1_IRQ             (IRQ_INTERNAL_BASE + 6)
 461 +#define BCM_3368_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 9)
 462 +#define BCM_3368_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 15)
 463 +#define BCM_3368_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 16)
 464 +#define BCM_3368_HSSPI_IRQ             0
 465 +#define BCM_3368_EHCI0_IRQ             0
 466 +#define BCM_3368_USBD_IRQ              0
 467 +#define BCM_3368_USBD_RXDMA0_IRQ       0
 468 +#define BCM_3368_USBD_TXDMA0_IRQ       0
 469 +#define BCM_3368_USBD_RXDMA1_IRQ       0
 470 +#define BCM_3368_USBD_TXDMA1_IRQ       0
 471 +#define BCM_3368_USBD_RXDMA2_IRQ       0
 472 +#define BCM_3368_USBD_TXDMA2_IRQ       0
 473 +#define BCM_3368_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
 474 +#define BCM_3368_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
 475 +#define BCM_3368_PCI_IRQ               (IRQ_INTERNAL_BASE + 31)
 476 +#define BCM_3368_PCMCIA_IRQ            0
 477 +#define BCM_3368_ATM_IRQ               0
 478 +#define BCM_3368_ENETSW_RXDMA0_IRQ     0
 479 +#define BCM_3368_ENETSW_RXDMA1_IRQ     0
 480 +#define BCM_3368_ENETSW_RXDMA2_IRQ     0
 481 +#define BCM_3368_ENETSW_RXDMA3_IRQ     0
 482 +#define BCM_3368_ENETSW_TXDMA0_IRQ     0
 483 +#define BCM_3368_ENETSW_TXDMA1_IRQ     0
 484 +#define BCM_3368_ENETSW_TXDMA2_IRQ     0
 485 +#define BCM_3368_ENETSW_TXDMA3_IRQ     0
 486 +#define BCM_3368_XTM_IRQ               0
 487 +#define BCM_3368_XTM_DMA0_IRQ          0
 488 +
 489 +#define BCM_3368_EXT_IRQ0              (IRQ_INTERNAL_BASE + 25)
 490 +#define BCM_3368_EXT_IRQ1              (IRQ_INTERNAL_BASE + 26)
 491 +#define BCM_3368_EXT_IRQ2              (IRQ_INTERNAL_BASE + 27)
 492 +#define BCM_3368_EXT_IRQ3              (IRQ_INTERNAL_BASE + 28)
 493 +
 494 +
 495 +/*
 496   * 6328 irqs
 497   */
 498  #define BCM_6328_HIGH_IRQ_BASE         (IRQ_INTERNAL_BASE + 32)
 499 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
 500 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
 501 @@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio
 502         switch (bcm63xx_get_cpu_id()) {
 503         case BCM6328_CPU_ID:
 504                 return 32;
 505 +       case BCM3368_CPU_ID:
 506         case BCM6358_CPU_ID:
 507                 return 40;
 508         case BCM6338_CPU_ID:
 509 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 510 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 511 @@ -15,6 +15,39 @@
 512  /* Clock Control register */
 513  #define PERF_CKCTL_REG                 0x4
 514
 515 +#define CKCTL_3368_MAC_EN              (1 << 3)
 516 +#define CKCTL_3368_TC_EN               (1 << 5)
 517 +#define CKCTL_3368_US_TOP_EN           (1 << 6)
 518 +#define CKCTL_3368_DS_TOP_EN           (1 << 7)
 519 +#define CKCTL_3368_APM_EN              (1 << 8)
 520 +#define CKCTL_3368_SPI_EN              (1 << 9)
 521 +#define CKCTL_3368_USBS_EN             (1 << 10)
 522 +#define CKCTL_3368_BMU_EN              (1 << 11)
 523 +#define CKCTL_3368_PCM_EN              (1 << 12)
 524 +#define CKCTL_3368_NTP_EN              (1 << 13)
 525 +#define CKCTL_3368_ACP_B_EN            (1 << 14)
 526 +#define CKCTL_3368_ACP_A_EN            (1 << 15)
 527 +#define CKCTL_3368_EMUSB_EN            (1 << 17)
 528 +#define CKCTL_3368_ENET0_EN            (1 << 18)
 529 +#define CKCTL_3368_ENET1_EN            (1 << 19)
 530 +#define CKCTL_3368_USBU_EN             (1 << 20)
 531 +#define CKCTL_3368_EPHY_EN             (1 << 21)
 532 +
 533 +#define CKCTL_3368_ALL_SAFE_EN         (CKCTL_3368_MAC_EN | \
 534 +                                        CKCTL_3368_TC_EN | \
 535 +                                        CKCTL_3368_US_TOP_EN | \
 536 +                                        CKCTL_3368_DS_TOP_EN | \
 537 +                                        CKCTL_3368_APM_EN | \
 538 +                                        CKCTL_3368_SPI_EN | \
 539 +                                        CKCTL_3368_USBS_EN | \
 540 +                                        CKCTL_3368_BMU_EN | \
 541 +                                        CKCTL_3368_PCM_EN | \
 542 +                                        CKCTL_3368_NTP_EN | \
 543 +                                        CKCTL_3368_ACP_B_EN | \
 544 +                                        CKCTL_3368_ACP_A_EN | \
 545 +                                        CKCTL_3368_EMUSB_EN | \
 546 +                                        CKCTL_3368_USBU_EN)
 547 +
 548  #define CKCTL_6328_PHYMIPS_EN          (1 << 0)
 549  #define CKCTL_6328_ADSL_QPROC_EN       (1 << 1)
 550  #define CKCTL_6328_ADSL_AFE_EN         (1 << 2)
 551 @@ -181,6 +214,7 @@
 552  #define SYS_PLL_SOFT_RESET             0x1
 553
 554  /* Interrupt Mask register */
 555 +#define PERF_IRQMASK_3368_REG          0xc
 556  #define PERF_IRQMASK_6328_REG          0x20
 557  #define PERF_IRQMASK_6338_REG          0xc
 558  #define PERF_IRQMASK_6345_REG          0xc
 559 @@ -190,6 +224,7 @@
 560  #define PERF_IRQMASK_6368_REG          0x20
 561
 562  /* Interrupt Status register */
 563 +#define PERF_IRQSTAT_3368_REG          0x10
 564  #define PERF_IRQSTAT_6328_REG          0x28
 565  #define PERF_IRQSTAT_6338_REG          0x10
 566  #define PERF_IRQSTAT_6345_REG          0x10
 567 @@ -199,6 +234,7 @@
 568  #define PERF_IRQSTAT_6368_REG          0x28
 569
 570  /* External Interrupt Configuration register */
 571 +#define PERF_EXTIRQ_CFG_REG_3368       0x14
 572  #define PERF_EXTIRQ_CFG_REG_6328       0x18
 573  #define PERF_EXTIRQ_CFG_REG_6338       0x14
 574  #define PERF_EXTIRQ_CFG_REG_6345       0x14
 575 @@ -236,6 +272,13 @@
 576  #define PERF_SOFTRESET_6362_REG                0x10
 577  #define PERF_SOFTRESET_6368_REG                0x10
 578
 579 +#define SOFTRESET_3368_SPI_MASK                (1 << 0)
 580 +#define SOFTRESET_3368_ENET_MASK       (1 << 2)
 581 +#define SOFTRESET_3368_MPI_MASK                (1 << 3)
 582 +#define SOFTRESET_3368_EPHY_MASK       (1 << 6)
 583 +#define SOFTRESET_3368_USBS_MASK       (1 << 11)
 584 +#define SOFTRESET_3368_PCM_MASK                (1 << 13)
 585 +
 586  #define SOFTRESET_6328_SPI_MASK                (1 << 0)
 587  #define SOFTRESET_6328_EPHY_MASK       (1 << 1)
 588  #define SOFTRESET_6328_SAR_MASK                (1 << 2)
 589 @@ -1293,7 +1336,7 @@
 590  #define SPI_6348_RX_DATA               0x80
 591  #define SPI_6348_RX_DATA_SIZE          0x3f
 592
 593 -/* BCM 6358/6262/6368 SPI core */
 594 +/* BCM 3368/6358/6262/6368 SPI core */
 595  #define SPI_6358_MSG_CTL               0x00    /* 16-bits register */
 596  #define SPI_6358_MSG_CTL_WIDTH         16
 597  #define SPI_6358_MSG_DATA              0x02
 598 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
 599 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
 600 @@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(
 601  static inline int is_bcm63xx_internal_registers(phys_t offset)
 602  {
 603         switch (bcm63xx_get_cpu_id()) {
 604 +       case BCM3368_CPU_ID:
 605 +               if (offset >= 0xfff80000)
 606 +                       return 1;
 607 +               break;
 608         case BCM6338_CPU_ID:
 609         case BCM6345_CPU_ID:
 610         case BCM6348_CPU_ID:
 611 --- a/arch/mips/pci/pci-bcm63xx.c
 612 +++ b/arch/mips/pci/pci-bcm63xx.c
 613 @@ -266,7 +266,7 @@ static int __init bcm63xx_register_pci(v
 614         /* setup PCI to local bus access, used by PCI device to target
 615          * local RAM while bus mastering */
 616         bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
 617 -       if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
 618 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
 619                 val = MPI_SP0_REMAP_ENABLE_MASK;
 620         else
 621                 val = 0;
 622 @@ -338,6 +338,7 @@ static int __init bcm63xx_pci_init(void)
 623         case BCM6328_CPU_ID:
 624         case BCM6362_CPU_ID:
 625                 return bcm63xx_register_pcie();
 626 +       case BCM3368_CPU_ID:
 627         case BCM6348_CPU_ID:
 628         case BCM6358_CPU_ID:
 629         case BCM6368_CPU_ID: