target/linux/brcm47xx-2.6/patches/100-board_support.patch

   1 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
   2 --- linux.old/arch/mips/bcm947xx/cfe_env.c      1970-01-01 01:00:00.000000000 +0100
   3 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c      2007-01-03 02:26:02.000000000 +0100
   4 @@ -0,0 +1,232 @@
   5 +/*
   6 + * CFE environment varialble access
   7 + *
   8 + * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
   9 + *
  10 + * This program is free software; you can redistribute  it and/or modify it
  11 + * under  the terms of  the GNU General  Public License as published by the
  12 + * Free Software Foundation;  either version 2 of the  License, or (at your
  13 + * option) any later version.
  14 + *
  15 + * Copyright 2001-2003, Broadcom Corporation
  16 + *
  17 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
  18 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
  19 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  20 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  21 + */
  22 +
  23 +#include <linux/init.h>
  24 +#include <linux/module.h>
  25 +#include <linux/kernel.h>
  26 +#include <linux/string.h>
  27 +#include <asm/io.h>
  28 +#include <asm/uaccess.h>
  29 +
  30 +#define NVRAM_SIZE       (0x1ff0)
  31 +static char _nvdata[NVRAM_SIZE] __initdata;
  32 +static char _valuestr[256] __initdata;
  33 +
  34 +/*
  35 + * TLV types.  These codes are used in the "type-length-value"
  36 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
  37 + *
  38 + * The layout of the flash/nvram is as follows:
  39 + *
  40 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
  41 + *
  42 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
  43 + * The "length" field marks the length of the data section, not
  44 + * including the type and length fields.
  45 + *
  46 + * Environment variables are stored as follows:
  47 + *
  48 + * <type_env> <length> <flags> <name> = <value>
  49 + *
  50 + * If bit 0 (low bit) is set, the length is an 8-bit value.
  51 + * If bit 0 (low bit) is clear, the length is a 16-bit value
  52 + *
  53 + * Bit 7 set indicates "user" TLVs.  In this case, bit 0 still
  54 + * indicates the size of the length field.
  55 + *
  56 + * Flags are from the constants below:
  57 + *
  58 + */
  59 +#define ENV_LENGTH_16BITS      0x00    /* for low bit */
  60 +#define ENV_LENGTH_8BITS       0x01
  61 +
  62 +#define ENV_TYPE_USER          0x80
  63 +
  64 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
  65 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
  66 +
  67 +/*
  68 + * The actual TLV types we support
  69 + */
  70 +
  71 +#define ENV_TLV_TYPE_END       0x00
  72 +#define ENV_TLV_TYPE_ENV       ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
  73 +
  74 +/*
  75 + * Environment variable flags
  76 + */
  77 +
  78 +#define ENV_FLG_NORMAL         0x00    /* normal read/write */
  79 +#define ENV_FLG_BUILTIN                0x01    /* builtin - not stored in flash */
  80 +#define ENV_FLG_READONLY       0x02    /* read-only - cannot be changed */
  81 +
  82 +#define ENV_FLG_MASK           0xFF    /* mask of attributes we keep */
  83 +#define ENV_FLG_ADMIN          0x100   /* lets us internally override permissions */
  84 +
  85 +
  86 +/*  *********************************************************************
  87 +    *  _nvram_read(buffer,offset,length)
  88 +    *
  89 +    *  Read data from the NVRAM device
  90 +    *
  91 +    *  Input parameters:
  92 +    *             buffer - destination buffer
  93 +    *             offset - offset of data to read
  94 +    *             length - number of bytes to read
  95 +    *
  96 +    *  Return value:
  97 +    *             number of bytes read, or <0 if error occured
  98 +    ********************************************************************* */
  99 +static int
 100 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
 101 +{
 102 +    int i;
 103 +    if (offset > NVRAM_SIZE)
 104 +       return -1;
 105 +
 106 +    for ( i = 0; i < length; i++) {
 107 +       buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
 108 +    }
 109 +    return length;
 110 +}
 111 +
 112 +
 113 +static char*
 114 +_strnchr(const char *dest,int c,size_t cnt)
 115 +{
 116 +       while (*dest && (cnt > 0)) {
 117 +       if (*dest == c) return (char *) dest;
 118 +       dest++;
 119 +       cnt--;
 120 +       }
 121 +       return NULL;
 122 +}
 123 +
 124 +
 125 +
 126 +/*
 127 + * Core support API: Externally visible.
 128 + */
 129 +
 130 +/*
 131 + * Get the value of an NVRAM variable
 132 + * @param      name    name of variable to get
 133 + * @return     value of variable or NULL if undefined
 134 + */
 135 +
 136 +char*
 137 +cfe_env_get(unsigned char *nv_buf, char* name)
 138 +{
 139 +    int size;
 140 +    unsigned char *buffer;
 141 +    unsigned char *ptr;
 142 +    unsigned char *envval;
 143 +    unsigned int reclen;
 144 +    unsigned int rectype;
 145 +    int offset;
 146 +    int flg;
 147 +
 148 +    size = NVRAM_SIZE;
 149 +    buffer = &_nvdata[0];
 150 +
 151 +    ptr = buffer;
 152 +    offset = 0;
 153 +
 154 +    /* Read the record type and length */
 155 +    if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
 156 +       goto error;
 157 +    }
 158 +
 159 +    while ((*ptr != ENV_TLV_TYPE_END)  && (size > 1)) {
 160 +
 161 +       /* Adjust pointer for TLV type */
 162 +       rectype = *(ptr);
 163 +       offset++;
 164 +       size--;
 165 +
 166 +       /*
 167 +        * Read the length.  It can be either 1 or 2 bytes
 168 +        * depending on the code
 169 +        */
 170 +       if (rectype & ENV_LENGTH_8BITS) {
 171 +           /* Read the record type and length - 8 bits */
 172 +           if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
 173 +               goto error;
 174 +           }
 175 +           reclen = *(ptr);
 176 +           size--;
 177 +           offset++;
 178 +       }
 179 +       else {
 180 +           /* Read the record type and length - 16 bits, MSB first */
 181 +           if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
 182 +               goto error;
 183 +           }
 184 +           reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
 185 +           size -= 2;
 186 +           offset += 2;
 187 +       }
 188 +
 189 +       if (reclen > size)
 190 +           break;      /* should not happen, bad NVRAM */
 191 +
 192 +       switch (rectype) {
 193 +           case ENV_TLV_TYPE_ENV:
 194 +               /* Read the TLV data */
 195 +               if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
 196 +                   goto error;
 197 +               flg = *ptr++;
 198 +               envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
 199 +               if (envval) {
 200 +                   *envval++ = '\0';
 201 +                   memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
 202 +                   _valuestr[(reclen-1)-(envval-ptr)] = '\0';
 203 +#if 0
 204 +                   printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
 205 +#endif
 206 +                   if(!strcmp(ptr, name)){
 207 +                       return _valuestr;
 208 +                   }
 209 +                   if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
 210 +                       return _valuestr;
 211 +               }
 212 +               break;
 213 +
 214 +           default:
 215 +               /* Unknown TLV type, skip it. */
 216 +               break;
 217 +           }
 218 +
 219 +       /*
 220 +        * Advance to next TLV
 221 +        */
 222 +
 223 +       size -= (int)reclen;
 224 +       offset += reclen;
 225 +
 226 +       /* Read the next record type */
 227 +       ptr = buffer;
 228 +       if (_nvram_read(nv_buf, ptr,offset,1) != 1)
 229 +           goto error;
 230 +       }
 231 +
 232 +error:
 233 +    return NULL;
 234 +
 235 +}
 236 +
 237 diff -urN linux.old/arch/mips/bcm947xx/include/nvram.h linux.dev/arch/mips/bcm947xx/include/nvram.h
 238 --- linux.old/arch/mips/bcm947xx/include/nvram.h        1970-01-01 01:00:00.000000000 +0100
 239 +++ linux.dev/arch/mips/bcm947xx/include/nvram.h        2007-01-03 02:26:02.000000000 +0100
 240 @@ -0,0 +1,37 @@
 241 +/*
 242 + *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
 243 + *
 244 + *  This program is free software; you can redistribute  it and/or modify it
 245 + *  under  the terms of  the GNU General  Public License as published by the
 246 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 247 + *  option) any later version.
 248 + */
 249 +
 250 +#ifndef __NVRAM_H
 251 +#define __NVRAM_H
 252 +
 253 +struct nvram_header {
 254 +       u32 magic;
 255 +       u32 len;
 256 +       u32 crc_ver_init;       /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
 257 +       u32 config_refresh;     /* 0:15 sdram_config, 16:31 sdram_refresh */
 258 +       u32 config_ncdl;        /* ncdl values for memc */
 259 +};
 260 +
 261 +struct nvram_tuple {
 262 +       char *name;
 263 +       char *value;
 264 +       struct nvram_tuple *next;
 265 +};
 266 +
 267 +#define NVRAM_HEADER           0x48534C46      /* 'FLSH' */
 268 +#define NVRAM_VERSION          1
 269 +#define NVRAM_HEADER_SIZE      20
 270 +#define NVRAM_SPACE            0x8000
 271 +
 272 +#define NVRAM_MAX_VALUE_LEN 255
 273 +#define NVRAM_MAX_PARAM_LEN 64
 274 +
 275 +char *nvram_get(const char *name);
 276 +
 277 +#endif
 278 diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
 279 --- linux.old/arch/mips/bcm947xx/irq.c  1970-01-01 01:00:00.000000000 +0100
 280 +++ linux.dev/arch/mips/bcm947xx/irq.c  2007-01-03 02:26:02.000000000 +0100
 281 @@ -0,0 +1,63 @@
 282 +/*
 283 + *  Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
 284 + *
 285 + *  This program is free software; you can redistribute  it and/or modify it
 286 + *  under  the terms of  the GNU General  Public License as published by the
 287 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 288 + *  option) any later version.
 289 + *
 290 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 291 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 292 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 293 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 294 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 295 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 296 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 297 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 298 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 299 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 300 + *
 301 + *  You should have received a copy of the  GNU General Public License along
 302 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 303 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 304 + */
 305 +
 306 +#include <linux/errno.h>
 307 +#include <linux/init.h>
 308 +#include <linux/interrupt.h>
 309 +#include <linux/irq.h>
 310 +#include <linux/module.h>
 311 +#include <linux/smp.h>
 312 +#include <linux/types.h>
 313 +
 314 +#include <asm/cpu.h>
 315 +#include <asm/io.h>
 316 +#include <asm/irq.h>
 317 +#include <asm/irq_cpu.h>
 318 +
 319 +void plat_irq_dispatch(void)
 320 +{
 321 +       u32 cause;
 322 +
 323 +       cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
 324 +
 325 +       clear_c0_status(cause);
 326 +
 327 +       if (cause & CAUSEF_IP7)
 328 +               do_IRQ(7);
 329 +       if (cause & CAUSEF_IP2)
 330 +               do_IRQ(2);
 331 +       if (cause & CAUSEF_IP3)
 332 +               do_IRQ(3);
 333 +       if (cause & CAUSEF_IP4)
 334 +               do_IRQ(4);
 335 +       if (cause & CAUSEF_IP5)
 336 +               do_IRQ(5);
 337 +       if (cause & CAUSEF_IP6)
 338 +               do_IRQ(6);
 339 +}
 340 +
 341 +void __init arch_init_irq(void)
 342 +{
 343 +       mips_cpu_irq_init(0);
 344 +}
 345 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
 346 --- linux.old/arch/mips/bcm947xx/Makefile       1970-01-01 01:00:00.000000000 +0100
 347 +++ linux.dev/arch/mips/bcm947xx/Makefile       2007-01-03 02:26:02.000000000 +0100
 348 @@ -0,0 +1,8 @@
 349 +#
 350 +# Makefile for the BCM47xx specific kernel interface routines
 351 +# under Linux.
 352 +#
 353 +
 354 +obj-y := irq.o prom.o setup.o time.o
 355 +obj-y += nvram.o cfe_env.o
 356 +#obj-y += pci.o
 357 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
 358 --- linux.old/arch/mips/bcm947xx/nvram.c        1970-01-01 01:00:00.000000000 +0100
 359 +++ linux.dev/arch/mips/bcm947xx/nvram.c        2007-01-03 02:26:02.000000000 +0100
 360 @@ -0,0 +1,131 @@
 361 +/*
 362 + * BCM947xx nvram variable access
 363 + *
 364 + * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
 365 + *
 366 + * This program is free software; you can redistribute  it and/or modify it
 367 + * under  the terms of  the GNU General  Public License as published by the
 368 + * Free Software Foundation;  either version 2 of the  License, or (at your
 369 + * option) any later version.
 370 + *
 371 + *
 372 + * Copyright 2005, Broadcom Corporation
 373 + *
 374 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
 375 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
 376 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
 377 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
 378 + *
 379 + */
 380 +
 381 +#include <linux/init.h>
 382 +#include <linux/module.h>
 383 +#include <linux/ssb.h>
 384 +#include <linux/kernel.h>
 385 +#include <linux/string.h>
 386 +#include <linux/interrupt.h>
 387 +#include <linux/spinlock.h>
 388 +#include <linux/slab.h>
 389 +#include <asm/byteorder.h>
 390 +#include <asm/bootinfo.h>
 391 +#include <asm/addrspace.h>
 392 +#include <asm/io.h>
 393 +#include <asm/uaccess.h>
 394 +
 395 +#include <nvram.h>
 396 +
 397 +#define MB * 1048576
 398 +extern struct ssb_bus ssb;
 399 +
 400 +static char nvram_buf[NVRAM_SPACE];
 401 +static int cfe_env;
 402 +extern char *cfe_env_get(char *nv_buf, const char *name);
 403 +
 404 +/* Probe for NVRAM header */
 405 +static void __init early_nvram_init(void)
 406 +{
 407 +       struct ssb_mipscore *mcore = &ssb.mipscore;
 408 +       struct nvram_header *header;
 409 +       int i;
 410 +       u32 base, lim, off;
 411 +       u32 *src, *dst;
 412 +
 413 +       base = mcore->flash_window;
 414 +       lim = mcore->flash_window_size;
 415 +       cfe_env = 0;
 416 +
 417 +
 418 +       /* XXX: hack for supporting the CFE environment stuff on WGT634U */
 419 +       if (lim >= 8 MB) {
 420 +               src = (u32 *) KSEG1ADDR(base + 8 MB - 0x2000);
 421 +               dst = (u32 *) nvram_buf;
 422 +
 423 +               if ((*src & 0xff00ff) == 0x000001) {
 424 +                       printk("early_nvram_init: WGT634U NVRAM found.\n");
 425 +
 426 +                       for (i = 0; i < 0x1ff0; i++) {
 427 +                               if (*src == 0xFFFFFFFF)
 428 +                                       break;
 429 +                               *dst++ = *src++;
 430 +                       }
 431 +                       cfe_env = 1;
 432 +                       return;
 433 +               }
 434 +       }
 435 +
 436 +       off = 0x20000;
 437 +       while (off <= lim) {
 438 +               /* Windowed flash access */
 439 +               header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
 440 +               if (header->magic == NVRAM_HEADER)
 441 +                       goto found;
 442 +               off <<= 1;
 443 +       }
 444 +
 445 +       /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
 446 +       header = (struct nvram_header *) KSEG1ADDR(base + 4096);
 447 +       if (header->magic == NVRAM_HEADER)
 448 +               goto found;
 449 +
 450 +       header = (struct nvram_header *) KSEG1ADDR(base + 1024);
 451 +       if (header->magic == NVRAM_HEADER)
 452 +               goto found;
 453 +
 454 +       return;
 455 +
 456 +found:
 457 +       src = (u32 *) header;
 458 +       dst = (u32 *) nvram_buf;
 459 +       for (i = 0; i < sizeof(struct nvram_header); i += 4)
 460 +               *dst++ = *src++;
 461 +       for (; i < header->len && i < NVRAM_SPACE; i += 4)
 462 +               *dst++ = le32_to_cpu(*src++);
 463 +}
 464 +
 465 +char *nvram_get(const char *name)
 466 +{
 467 +       char *var, *value, *end, *eq;
 468 +
 469 +       if (!name)
 470 +               return NULL;
 471 +
 472 +       if (!nvram_buf[0])
 473 +               early_nvram_init();
 474 +
 475 +       if (cfe_env)
 476 +               return cfe_env_get(nvram_buf, name);
 477 +
 478 +       /* Look for name=value and return value */
 479 +       var = &nvram_buf[sizeof(struct nvram_header)];
 480 +       end = nvram_buf + sizeof(nvram_buf) - 2;
 481 +       end[0] = end[1] = '\0';
 482 +       for (; *var; var = value + strlen(value) + 1) {
 483 +               if (!(eq = strchr(var, '=')))
 484 +                       break;
 485 +               value = eq + 1;
 486 +               if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
 487 +                       return value;
 488 +       }
 489 +
 490 +       return NULL;
 491 +}
 492 diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
 493 --- linux.old/arch/mips/bcm947xx/pci.c  1970-01-01 01:00:00.000000000 +0100
 494 +++ linux.dev/arch/mips/bcm947xx/pci.c  2007-01-03 02:26:02.000000000 +0100
 495 @@ -0,0 +1,227 @@
 496 +#include <linux/kernel.h>
 497 +#include <linux/init.h>
 498 +#include <linux/pci.h>
 499 +#include <linux/types.h>
 500 +
 501 +#include <asm/cpu.h>
 502 +#include <asm/io.h>
 503 +
 504 +#include <typedefs.h>
 505 +#include <osl.h>
 506 +#include <sbutils.h>
 507 +#include <sbmips.h>
 508 +#include <sbconfig.h>
 509 +#include <sbpci.h>
 510 +#include <bcmdevs.h>
 511 +#include <pcicfg.h>
 512 +
 513 +extern sb_t *sbh;
 514 +extern spinlock_t sbh_lock;
 515 +
 516 +
 517 +static int
 518 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 519 +                               int reg, int size, u32 *val)
 520 +{
 521 +       int ret;
 522 +       unsigned long flags;
 523 +
 524 +       spin_lock_irqsave(&sbh_lock, flags);
 525 +       ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
 526 +       spin_unlock_irqrestore(&sbh_lock, flags);
 527 +
 528 +       return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 529 +}
 530 +
 531 +static int
 532 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 533 +                               int reg, int size, u32 val)
 534 +{
 535 +       int ret;
 536 +       unsigned long flags;
 537 +
 538 +       spin_lock_irqsave(&sbh_lock, flags);
 539 +       ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
 540 +       spin_unlock_irqrestore(&sbh_lock, flags);
 541 +
 542 +       return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 543 +}
 544 +
 545 +
 546 +static struct pci_ops sb_pci_ops = {
 547 +       .read   = sb_pci_read_config,
 548 +       .write  = sb_pci_write_config,
 549 +};
 550 +
 551 +static struct resource sb_pci_mem_resource = {
 552 +       .name   = "SB PCI Memory resources",
 553 +       .start  = SB_ENUM_BASE,
 554 +       .end    = SB_ENUM_LIM - 1,
 555 +       .flags  = IORESOURCE_MEM,
 556 +};
 557 +
 558 +static struct resource sb_pci_io_resource = {
 559 +       .name   = "SB PCI I/O resources",
 560 +       .start  = 0x000,
 561 +       .end    = 0x0FF,
 562 +       .flags  = IORESOURCE_IO,
 563 +};
 564 +
 565 +static struct pci_controller bcm47xx_sb_pci_controller = {
 566 +       .pci_ops        = &sb_pci_ops,
 567 +       .mem_resource   = &sb_pci_mem_resource,
 568 +       .io_resource    = &sb_pci_io_resource,
 569 +};
 570 +
 571 +static struct resource ext_pci_mem_resource = {
 572 +       .name   = "Ext PCI Memory resources",
 573 +       .start  = 0x40000000,
 574 +       .end    = 0x7fffffff,
 575 +       .flags  = IORESOURCE_MEM,
 576 +};
 577 +
 578 +static struct resource ext_pci_io_resource = {
 579 +       .name   = "Ext PCI I/O resources",
 580 +       .start  = 0x100,
 581 +       .end    = 0x7FF,
 582 +       .flags  = IORESOURCE_IO,
 583 +};
 584 +
 585 +static struct pci_controller bcm47xx_ext_pci_controller = {
 586 +       .pci_ops        = &sb_pci_ops,
 587 +       .io_resource    = &ext_pci_io_resource,
 588 +       .mem_resource   = &ext_pci_mem_resource,
 589 +       .mem_offset             = 0x24000000,
 590 +};
 591 +
 592 +void bcm47xx_pci_init(void)
 593 +{
 594 +       unsigned long flags;
 595 +
 596 +       spin_lock_irqsave(&sbh_lock, flags);
 597 +       sbpci_init(sbh);
 598 +       spin_unlock_irqrestore(&sbh_lock, flags);
 599 +
 600 +       set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
 601 +
 602 +       register_pci_controller(&bcm47xx_sb_pci_controller);
 603 +       register_pci_controller(&bcm47xx_ext_pci_controller);
 604 +}
 605 +
 606 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 607 +{
 608 +       unsigned long flags;
 609 +       u8 irq;
 610 +       uint idx;
 611 +
 612 +       /* external: use the irq of the pci core */
 613 +       if (dev->bus->number >= 1) {
 614 +               spin_lock_irqsave(&sbh_lock, flags);
 615 +               idx = sb_coreidx(sbh);
 616 +               sb_setcore(sbh, SB_PCI, 0);
 617 +               irq = sb_irq(sbh);
 618 +               sb_setcoreidx(sbh, idx);
 619 +               spin_unlock_irqrestore(&sbh_lock, flags);
 620 +
 621 +               return irq + 2;
 622 +       }
 623 +
 624 +       /* internal */
 625 +       pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 626 +       return irq + 2;
 627 +}
 628 +
 629 +u32 pci_iobase = 0x100;
 630 +u32 pci_membase = SB_PCI_DMA;
 631 +
 632 +static void bcm47xx_fixup_device(struct pci_dev *d)
 633 +{
 634 +       struct resource *res;
 635 +       int pos, size;
 636 +       u32 *base;
 637 +
 638 +       if (d->bus->number == 0)
 639 +               return;
 640 +
 641 +       printk("PCI: Fixing up device %s\n", pci_name(d));
 642 +
 643 +       /* Fix up resource bases */
 644 +       for (pos = 0; pos < 6; pos++) {
 645 +               res = &d->resource[pos];
 646 +               base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
 647 +               if (res->end) {
 648 +                       size = res->end - res->start + 1;
 649 +                       if (*base & (size - 1))
 650 +                               *base = (*base + size) & ~(size - 1);
 651 +                       res->start = *base;
 652 +                       res->end = res->start + size - 1;
 653 +                       *base += size;
 654 +                       pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
 655 +               }
 656 +               /* Fix up PCI bridge BAR0 only */
 657 +               if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0)
 658 +                       break;
 659 +       }
 660 +       /* Fix up interrupt lines */
 661 +       if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
 662 +               d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
 663 +       pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 664 +}
 665 +
 666 +
 667 +static void bcm47xx_fixup_bridge(struct pci_dev *dev)
 668 +{
 669 +       if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
 670 +               return;
 671 +
 672 +       printk("PCI: fixing up bridge\n");
 673 +
 674 +       /* Enable PCI bridge bus mastering and memory space */
 675 +       pci_set_master(dev);
 676 +       pcibios_enable_device(dev, ~0);
 677 +
 678 +       /* Enable PCI bridge BAR1 prefetch and burst */
 679 +       pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
 680 +}
 681 +
 682 +/* Do platform specific device initialization at pci_enable_device() time */
 683 +int pcibios_plat_dev_init(struct pci_dev *dev)
 684 +{
 685 +       uint coreidx;
 686 +       unsigned long flags;
 687 +
 688 +       bcm47xx_fixup_device(dev);
 689 +
 690 +       /* These cores come out of reset enabled */
 691 +       if ((dev->bus->number != 0) ||
 692 +               (dev->device == SB_MIPS) ||
 693 +               (dev->device == SB_MIPS33) ||
 694 +               (dev->device == SB_EXTIF) ||
 695 +               (dev->device == SB_CC))
 696 +               return 0;
 697 +
 698 +       /* Do a core reset */
 699 +       spin_lock_irqsave(&sbh_lock, flags);
 700 +       coreidx = sb_coreidx(sbh);
 701 +       if (sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)) && (sb_coreid(sbh) == SB_USB)) {
 702 +               /*
 703 +                * The USB core requires a special bit to be set during core
 704 +                * reset to enable host (OHCI) mode. Resetting the SB core in
 705 +                * pcibios_enable_device() is a hack for compatibility with
 706 +                * vanilla usb-ohci so that it does not have to know about
 707 +                * SB. A driver that wants to use the USB core in device mode
 708 +                * should know about SB and should reset the bit back to 0
 709 +                * after calling pcibios_enable_device().
 710 +                */
 711 +               sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
 712 +               sb_core_reset(sbh, 1 << 29);
 713 +       } else {
 714 +               sb_core_reset(sbh, 0);
 715 +       }
 716 +       sb_setcoreidx(sbh, coreidx);
 717 +       spin_unlock_irqrestore(&sbh_lock, flags);
 718 +
 719 +       return 0;
 720 +}
 721 +
 722 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge);
 723 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
 724 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
 725 +++ linux.dev/arch/mips/bcm947xx/prom.c 2007-01-03 02:26:02.000000000 +0100
 726 @@ -0,0 +1,59 @@
 727 +/*
 728 + *  Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
 729 + *
 730 + *  This program is free software; you can redistribute  it and/or modify it
 731 + *  under  the terms of  the GNU General  Public License as published by the
 732 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 733 + *  option) any later version.
 734 + *
 735 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 736 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 737 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 738 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 739 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 740 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 741 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 742 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 743 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 744 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 745 + *
 746 + *  You should have received a copy of the  GNU General Public License along
 747 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 748 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 749 + */
 750 +
 751 +#include <linux/init.h>
 752 +#include <linux/mm.h>
 753 +#include <linux/sched.h>
 754 +#include <linux/bootmem.h>
 755 +
 756 +#include <asm/addrspace.h>
 757 +#include <asm/bootinfo.h>
 758 +#include <asm/pmon.h>
 759 +
 760 +const char *get_system_type(void)
 761 +{
 762 +       return "Broadcom BCM47xx";
 763 +}
 764 +
 765 +void __init prom_init(void)
 766 +{
 767 +       unsigned long mem;
 768 +
 769 +        mips_machgroup = MACH_GROUP_BRCM;
 770 +        mips_machtype = MACH_BCM47XX;
 771 +
 772 +       /* Figure out memory size by finding aliases */
 773 +       for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
 774 +               if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
 775 +                   *(unsigned long *)(prom_init))
 776 +                       break;
 777 +       }
 778 +
 779 +       add_memory_region(0, mem, BOOT_MEM_RAM);
 780 +}
 781 +
 782 +unsigned long __init prom_free_prom_memory(void)
 783 +{
 784 +       return 0;
 785 +}
 786 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
 787 --- linux.old/arch/mips/bcm947xx/setup.c        1970-01-01 01:00:00.000000000 +0100
 788 +++ linux.dev/arch/mips/bcm947xx/setup.c        2007-01-03 02:26:02.000000000 +0100
 789 @@ -0,0 +1,161 @@
 790 +/*
 791 + *  Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
 792 + *  Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
 793 + *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
 794 + *  Copyright (C) 2006 Michael Buesch
 795 + *
 796 + *  This program is free software; you can redistribute  it and/or modify it
 797 + *  under  the terms of  the GNU General  Public License as published by the
 798 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 799 + *  option) any later version.
 800 + *
 801 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 802 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 803 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 804 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 805 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 806 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 807 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 808 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 809 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 810 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 811 + *
 812 + *  You should have received a copy of the  GNU General Public License along
 813 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 814 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 815 + */
 816 +
 817 +#include <linux/init.h>
 818 +#include <linux/types.h>
 819 +#include <linux/tty.h>
 820 +#include <linux/serial.h>
 821 +#include <linux/serial_core.h>
 822 +#include <linux/serial_reg.h>
 823 +#include <asm/bootinfo.h>
 824 +#include <asm/time.h>
 825 +#include <asm/reboot.h>
 826 +#include <asm/cfe.h>
 827 +#include <linux/pm.h>
 828 +#include <linux/ssb.h>
 829 +
 830 +#include <nvram.h>
 831 +
 832 +extern void bcm47xx_pci_init(void);
 833 +extern void bcm47xx_time_init(void);
 834 +
 835 +struct ssb_bus ssb;
 836 +
 837 +static void bcm47xx_machine_restart(char *command)
 838 +{
 839 +       printk(KERN_ALERT "Please stand by while rebooting the system...\n");
 840 +       local_irq_disable();
 841 +       /* CFE has a reboot callback, but that does not work.
 842 +        * Oopses with: Reserved instruction in kernel code.
 843 +        */
 844 +
 845 +       /* Set the watchdog timer to reset immediately */
 846 +//TODO sb_watchdog(sbh, 1);
 847 +       while (1)
 848 +               cpu_relax();
 849 +}
 850 +
 851 +static void bcm47xx_machine_halt(void)
 852 +{
 853 +       /* Disable interrupts and watchdog and spin forever */
 854 +       local_irq_disable();
 855 +//TODO sb_watchdog(sbh, 0);
 856 +       while (1)
 857 +               cpu_relax();
 858 +}
 859 +
 860 +static void e_aton(char *str, char *dest)
 861 +{
 862 +       int i = 0;
 863 +
 864 +       if (str == NULL) {
 865 +               memset(dest, 0, 6);
 866 +               return;
 867 +       }
 868 +
 869 +       for (;;) {
 870 +               dest[i++] = (char) simple_strtoul(str, NULL, 16);
 871 +               str += 2;
 872 +               if (!*str++ || i == 6)
 873 +                       break;
 874 +       }
 875 +}
 876 +
 877 +static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
 878 +{
 879 +       // TODO
 880 +}
 881 +
 882 +static void bcm47xx_fill_sprom_nvram(struct ssb_sprom *sprom)
 883 +{
 884 +       char *s;
 885 +
 886 +       memset(sprom, 0, sizeof(struct ssb_sprom));
 887 +
 888 +       sprom->revision = 3;
 889 +       if ((s = nvram_get("et0macaddr")))
 890 +               e_aton(s, sprom->r1.et0mac);
 891 +       if ((s = nvram_get("et1macaddr")))
 892 +               e_aton(s, sprom->r1.et1mac);
 893 +       if ((s = nvram_get("et0phyaddr")))
 894 +               sprom->r1.et0phyaddr = simple_strtoul(s, NULL, 10);
 895 +       if ((s = nvram_get("et1phyaddr")))
 896 +               sprom->r1.et1phyaddr = simple_strtoul(s, NULL, 10);
 897 +}
 898 +
 899 +void __init plat_mem_setup(void)
 900 +{
 901 +       int i, err;
 902 +       char *s;
 903 +       struct ssb_mipscore *mcore;
 904 +
 905 +       err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_fill_sprom);
 906 +       if (err) {
 907 +               const char *msg = "Failed to initialize SSB bus (err %d)\n";
 908 +               cfe_printk(msg, err); /* Make sure the message gets out of the box. */
 909 +               panic(msg, err);
 910 +       }
 911 +       mcore = &ssb.mipscore;
 912 +
 913 +       /* FIXME: the nvram init depends on the ssb being fully initializes,
 914 +        * can't use the fill_sprom callback yet! */
 915 +       bcm47xx_fill_sprom_nvram(&ssb.sprom);
 916 +
 917 +       s = nvram_get("kernel_args");
 918 +       if (s && !strncmp(s, "console=ttyS1", 13) && (mcore->nr_serial_ports >= 2)) {
 919 +               struct ssb_serial_port port;
 920 +
 921 +               /* swap serial ports */
 922 +               memcpy(&port, &mcore->serial_ports[0], sizeof(port));
 923 +               memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
 924 +               memcpy(&mcore->serial_ports[1], &port, sizeof(port));
 925 +       }
 926 +
 927 +       for (i = 0; i < mcore->nr_serial_ports; i++) {
 928 +               struct ssb_serial_port *port = &(mcore->serial_ports[i]);
 929 +               struct uart_port s;
 930 +
 931 +               memset(&s, 0, sizeof(s));
 932 +               s.line = i;
 933 +               s.membase = port->regs;
 934 +               s.irq = port->irq + 2;//FIXME?
 935 +               s.uartclk = port->baud_base;
 936 +               s.flags = ASYNC_BOOT_AUTOCONF;
 937 +               s.iotype = SERIAL_IO_MEM;
 938 +               s.regshift = port->reg_shift;
 939 +
 940 +               early_serial_setup(&s);
 941 +       }
 942 +       cfe_printk("Serial init done.\n");
 943 +
 944 +       _machine_restart = bcm47xx_machine_restart;
 945 +       _machine_halt = bcm47xx_machine_halt;
 946 +       pm_power_off = bcm47xx_machine_halt;
 947 +
 948 +       board_time_init = bcm47xx_time_init;//FIXME move into ssb
 949 +}
 950 +
 951 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
 952 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
 953 +++ linux.dev/arch/mips/bcm947xx/time.c 2007-01-03 02:26:02.000000000 +0100
 954 @@ -0,0 +1,62 @@
 955 +/*
 956 + *  Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
 957 + *
 958 + *  This program is free software; you can redistribute  it and/or modify it
 959 + *  under  the terms of  the GNU General  Public License as published by the
 960 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 961 + *  option) any later version.
 962 + *
 963 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 964 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 965 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 966 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 967 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 968 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 969 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 970 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 971 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 972 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 973 + *
 974 + *  You should have received a copy of the  GNU General Public License along
 975 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 976 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 977 + */
 978 +
 979 +#include <linux/init.h>
 980 +#include <linux/kernel.h>
 981 +#include <linux/sched.h>
 982 +#include <linux/serial_reg.h>
 983 +#include <linux/interrupt.h>
 984 +#include <linux/ssb.h>
 985 +#include <asm/addrspace.h>
 986 +#include <asm/io.h>
 987 +#include <asm/time.h>
 988 +
 989 +extern struct ssb_bus ssb;
 990 +
 991 +void __init
 992 +bcm47xx_time_init(void)
 993 +{
 994 +       unsigned long hz;
 995 +
 996 +       /*
 997 +        * Use deterministic values for initial counter interrupt
 998 +        * so that calibrate delay avoids encountering a counter wrap.
 999 +        */
1000 +       write_c0_count(0);
1001 +       write_c0_compare(0xffff);
1002 +
1003 +       hz = ssb_clockspeed(&ssb);
1004 +       if (!hz)
1005 +               hz = 100000000;
1006 +
1007 +       /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
1008 +       mips_hpt_frequency = hz;
1009 +}
1010 +
1011 +void __init
1012 +plat_timer_setup(struct irqaction *irq)
1013 +{
1014 +       /* Enable the timer interrupt */
1015 +       setup_irq(7, irq);
1016 +}
1017 diff -urN linux.old/arch/mips/cfe/cfe.c linux.dev/arch/mips/cfe/cfe.c
1018 --- linux.old/arch/mips/cfe/cfe.c       1970-01-01 01:00:00.000000000 +0100
1019 +++ linux.dev/arch/mips/cfe/cfe.c       2007-01-03 02:26:02.000000000 +0100
1020 @@ -0,0 +1,533 @@
1021 +/*
1022 + * Broadcom Common Firmware Environment (CFE) support
1023 + *
1024 + * Copyright 2000, 2001, 2002
1025 + * Broadcom Corporation. All rights reserved.
1026 + *
1027 + * Copyright (C) 2006 Michael Buesch
1028 + *
1029 + * Original Authors:  Mitch Lichtenberg, Chris Demetriou
1030 + *
1031 + * This software is furnished under license and may be used and copied only
1032 + * in accordance with the following terms and conditions.  Subject to these
1033 + * conditions, you may download, copy, install, use, modify and distribute
1034 + * modified or unmodified copies of this software in source and/or binary
1035 + * form. No title or ownership is transferred hereby.
1036 + *
1037 + * 1) Any source code used, modified or distributed must reproduce and
1038 + *    retain this copyright notice and list of conditions as they appear in
1039 + *    the source file.
1040 + *
1041 + * 2) No right is granted to use any trade name, trademark, or logo of
1042 + *    Broadcom Corporation.  The "Broadcom Corporation" name may not be
1043 + *    used to endorse or promote products derived from this software
1044 + *    without the prior written permission of Broadcom Corporation.
1045 + *
1046 + * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
1047 + *    WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
1048 + *    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
1049 + *    NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
1050 + *    FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
1051 + *    LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1052 + *    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1053 + *    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
1054 + *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
1055 + *    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
1056 + *    OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1057 + */
1058 +
1059 +#include <linux/init.h>
1060 +#include <linux/string.h>
1061 +#include <linux/errno.h>
1062 +#include <linux/spinlock.h>
1063 +#include <asm/cfe.h>
1064 +
1065 +#include "cfe_private.h"
1066 +
1067 +
1068 +static cfe_uint_t cfe_handle;
1069 +static int (*cfe_trampoline)(long handle, long iocb);
1070 +
1071 +
1072 +#include <linux/kernel.h>
1073 +
1074 +void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
1075 +                     unsigned long fwarg2, unsigned long fwarg3)
1076 +{
1077 +       if (fwarg3 == 0x80300000) {
1078 +               /* WRT54G workaround */
1079 +               fwarg3 = CFE_EPTSEAL;
1080 +               fwarg2 = 0xBFC00500;
1081 +       }
1082 +       if (fwarg3 != CFE_EPTSEAL) {
1083 +               /* We are not booted from CFE */
1084 +               return;
1085 +       }
1086 +       if (fwarg1 == 0) {
1087 +               /* We are on the boot CPU */
1088 +               cfe_handle = (cfe_uint_t)fwarg0;
1089 +               cfe_trampoline = CFE_TO_PTR(fwarg2);
1090 +       }
1091 +}
1092 +
1093 +int cfe_vprintk(const char *fmt, va_list args)
1094 +{
1095 +       static char buffer[1024];
1096 +       static DEFINE_SPINLOCK(lock);
1097 +       static const char pfx[] = "CFE-console: ";
1098 +       static const size_t pfx_len = sizeof(pfx) - 1;
1099 +       unsigned long flags;
1100 +       int len, cnt, pos;
1101 +       int handle;
1102 +       int res;
1103 +
1104 +       if (!cfe_present())
1105 +               return -ENODEV;
1106 +
1107 +       spin_lock_irqsave(&lock, flags);
1108 +       handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
1109 +       if (CFE_ISERR(handle)) {
1110 +               len = -EIO;
1111 +               goto out;
1112 +       }
1113 +       strcpy(buffer, pfx);
1114 +       len = vscnprintf(buffer + pfx_len,
1115 +                        sizeof(buffer) - pfx_len - 2,
1116 +                        fmt, args);
1117 +       len += pfx_len;
1118 +       /* The CFE console requires CR-LF line-ends.
1119 +        * Add a CR, if we only terminate lines with a LF.
1120 +        * This does only fix CR-LF at the end of the string.
1121 +        * So for multiple lines, use multiple cfe_vprintk calls.
1122 +        */
1123 +       if (len > 1 &&
1124 +           buffer[len - 1] == '\n' && buffer[len - 2] != '\r') {
1125 +               buffer[len - 1] = '\r';
1126 +               buffer[len] = '\n';
1127 +               len += 1;
1128 +       }
1129 +       cnt = len;
1130 +       pos = 0;
1131 +       while (cnt > 0) {
1132 +               res = cfe_write(handle, buffer + pos, len - pos);
1133 +               if (CFE_ISERR(res)) {
1134 +                       len = -EIO;
1135 +                       goto out;
1136 +               }
1137 +               cnt -= res;
1138 +               pos += res;
1139 +       }
1140 +out:
1141 +       spin_unlock_irqrestore(&lock, flags);
1142 +
1143 +       return len;
1144 +}
1145 +
1146 +int cfe_printk(const char *fmt, ...)
1147 +{
1148 +       va_list args;
1149 +       int res;
1150 +
1151 +       va_start(args, fmt);
1152 +       res = cfe_vprintk(fmt, args);
1153 +       va_end(args);
1154 +
1155 +       return res;
1156 +}
1157 +
1158 +static int cfe_iocb_dispatch(struct cfe_iocb *iocb)
1159 +{
1160 +       if (!cfe_present())
1161 +               return CFE_ERR_UNSUPPORTED;
1162 +       return cfe_trampoline((long)cfe_handle, (long)iocb);
1163 +}
1164 +
1165 +int cfe_present(void)
1166 +{
1167 +       return (cfe_trampoline != NULL);
1168 +}
1169 +
1170 +int cfe_close(int handle)
1171 +{
1172 +       struct cfe_iocb iocb;
1173 +       int err;
1174 +
1175 +       memset(&iocb, 0, sizeof(iocb));
1176 +       iocb.fcode = CFE_CMD_DEV_CLOSE;
1177 +       iocb.handle = handle;
1178 +
1179 +       err = cfe_iocb_dispatch(&iocb);
1180 +
1181 +       return (CFE_ISERR(err)) ? err : iocb.status;
1182 +}
1183 +
1184 +int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1)
1185 +{
1186 +       struct cfe_iocb iocb;
1187 +       int err;
1188 +
1189 +       memset(&iocb, 0, sizeof(iocb));
1190 +       iocb.fcode = CFE_CMD_FW_CPUCTL;
1191 +       iocb.psize = sizeof(struct cfe_iocb_cpuctl);
1192 +       iocb.cpuctl.number = cpu;
1193 +       iocb.cpuctl.command = CFE_CPU_CMD_START;
1194 +       iocb.cpuctl.gp = gp;
1195 +       iocb.cpuctl.sp = sp;
1196 +       iocb.cpuctl.a1 = a1;
1197 +       iocb.cpuctl.start_addr = (long)fn;
1198 +
1199 +       err = cfe_iocb_dispatch(&iocb);
1200 +
1201 +       return (CFE_ISERR(err)) ? err : iocb.status;
1202 +}
1203 +
1204 +int cfe_cpu_stop(int cpu)
1205 +{
1206 +       struct cfe_iocb iocb;
1207 +       int err;
1208 +
1209 +       memset(&iocb, 0, sizeof(iocb));
1210 +       iocb.fcode = CFE_CMD_FW_CPUCTL;
1211 +       iocb.psize = sizeof(struct cfe_iocb_cpuctl);
1212 +       iocb.cpuctl.number = cpu;
1213 +       iocb.cpuctl.command = CFE_CPU_CMD_STOP;
1214 +
1215 +       err = cfe_iocb_dispatch(&iocb);
1216 +
1217 +       return (CFE_ISERR(err)) ? err : iocb.status;
1218 +}
1219 +
1220 +int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
1221 +{
1222 +       struct cfe_iocb iocb;
1223 +       int err;
1224 +
1225 +       memset(&iocb, 0, sizeof(iocb));
1226 +       iocb.fcode = CFE_CMD_ENV_ENUM;
1227 +       iocb.psize = sizeof(struct cfe_iocb_envbuf);
1228 +       iocb.envbuf.index = idx;
1229 +       iocb.envbuf.name = PTR_TO_CFE(name);
1230 +       iocb.envbuf.name_len = namelen;
1231 +       iocb.envbuf.val = PTR_TO_CFE(val);
1232 +       iocb.envbuf.val_len = vallen;
1233 +
1234 +       err = cfe_iocb_dispatch(&iocb);
1235 +
1236 +       return (CFE_ISERR(err)) ? err : iocb.status;
1237 +}
1238 +
1239 +int cfe_enumdev(int idx, char *name, int namelen)
1240 +{
1241 +       struct cfe_iocb iocb;
1242 +       int err;
1243 +
1244 +       memset(&iocb, 0, sizeof(iocb));
1245 +
1246 +       iocb.fcode = CFE_CMD_DEV_ENUM;
1247 +       iocb.psize = sizeof(struct cfe_iocb_envbuf);
1248 +       iocb.envbuf.index = idx;
1249 +       iocb.envbuf.name = PTR_TO_CFE(name);
1250 +       iocb.envbuf.name_len = namelen;
1251 +
1252 +       err = cfe_iocb_dispatch(&iocb);
1253 +
1254 +       return (CFE_ISERR(err)) ? err : iocb.status;
1255 +}
1256 +
1257 +int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
1258 +               u64 *type)
1259 +{
1260 +       struct cfe_iocb iocb;
1261 +       int err;
1262 +
1263 +       memset(&iocb, 0, sizeof(iocb));
1264 +
1265 +       iocb.fcode = CFE_CMD_FW_MEMENUM;
1266 +       iocb.flags = flags;
1267 +       iocb.psize = sizeof(struct cfe_iocb_meminfo);
1268 +       iocb.meminfo.index = idx;
1269 +
1270 +       err = cfe_iocb_dispatch(&iocb);
1271 +       if (CFE_ISERR(err))
1272 +               return err;
1273 +       if (!CFE_ISERR(iocb.status)) {
1274 +               *start = iocb.meminfo.addr;
1275 +               *length = iocb.meminfo.size;
1276 +               *type = iocb.meminfo.type;
1277 +       }
1278 +
1279 +       return iocb.status;
1280 +}
1281 +
1282 +int cfe_exit(int warm, int status)
1283 +{
1284 +       struct cfe_iocb iocb;
1285 +       int err;
1286 +
1287 +printk("CFE REBOOT\n");
1288 +       memset(&iocb, 0, sizeof(iocb));
1289 +       iocb.fcode = CFE_CMD_FW_RESTART;
1290 +       if (warm)
1291 +               iocb.flags = CFE_FLG_WARMSTART;
1292 +       iocb.psize = sizeof(struct cfe_iocb_exitstat);
1293 +       iocb.exitstat.status = status;
1294 +
1295 +printk("CALL\n");
1296 +       err = cfe_iocb_dispatch(&iocb);
1297 +printk("DONE\n");
1298 +
1299 +       return (CFE_ISERR(err)) ? err : iocb.status;
1300 +}
1301 +
1302 +int cfe_flushcache(int flags)
1303 +{
1304 +       struct cfe_iocb iocb;
1305 +       int err;
1306 +
1307 +       memset(&iocb, 0, sizeof(iocb));
1308 +       iocb.fcode = CFE_CMD_FW_FLUSHCACHE;
1309 +       iocb.flags = flags;
1310 +
1311 +       err = cfe_iocb_dispatch(&iocb);
1312 +
1313 +       return (CFE_ISERR(err)) ? err : iocb.status;
1314 +}
1315 +
1316 +int cfe_getdevinfo(char *name)
1317 +{
1318 +       struct cfe_iocb iocb;
1319 +       int err;
1320 +
1321 +       memset(&iocb, 0, sizeof(iocb));
1322 +       iocb.fcode = CFE_CMD_DEV_GETINFO;
1323 +       iocb.psize = sizeof(struct cfe_iocb_buf);
1324 +       iocb.buffer.ptr = PTR_TO_CFE(name);
1325 +       iocb.buffer.length = strlen(name);
1326 +
1327 +       err = cfe_iocb_dispatch(&iocb);
1328 +       if (CFE_ISERR(err))
1329 +               return err;
1330 +       if (CFE_ISERR(iocb.status))
1331 +               return iocb.status;
1332 +
1333 +       return iocb.buffer.devflags;
1334 +}
1335 +
1336 +int cfe_getenv(char *name, char *dest, int destlen)
1337 +{
1338 +       struct cfe_iocb iocb;
1339 +       int err;
1340 +
1341 +       dest[0] = '\0';
1342 +       memset(&iocb, 0, sizeof(iocb));
1343 +       iocb.fcode = CFE_CMD_ENV_GET;
1344 +       iocb.psize = sizeof(struct cfe_iocb_envbuf);
1345 +       iocb.envbuf.name = PTR_TO_CFE(name);
1346 +       iocb.envbuf.name_len = strlen(name);
1347 +       iocb.envbuf.val = PTR_TO_CFE(dest);
1348 +       iocb.envbuf.val_len = destlen;
1349 +
1350 +       err = cfe_iocb_dispatch(&iocb);
1351 +
1352 +       return (CFE_ISERR(err)) ? err : iocb.status;
1353 +}
1354 +
1355 +int cfe_getfwinfo(struct cfe_fwinfo *info)
1356 +{
1357 +       struct cfe_iocb iocb;
1358 +       int err;
1359 +
1360 +       memset(&iocb, 0, sizeof(iocb));
1361 +       iocb.fcode = CFE_CMD_FW_GETINFO;
1362 +       iocb.psize = sizeof(struct cfe_iocb_fwinfo);
1363 +
1364 +       err = cfe_iocb_dispatch(&iocb);
1365 +       if (CFE_ISERR(err))
1366 +               return err;
1367 +       if (CFE_ISERR(iocb.status))
1368 +               return err;
1369 +
1370 +       info->version = iocb.fwinfo.version;
1371 +       info->totalmem = iocb.fwinfo.totalmem;
1372 +       info->flags = iocb.fwinfo.flags;
1373 +       info->boardid = iocb.fwinfo.boardid;
1374 +       info->bootarea_va = iocb.fwinfo.bootarea_va;
1375 +       info->bootarea_pa = iocb.fwinfo.bootarea_pa;
1376 +       info->bootarea_size = iocb.fwinfo.bootarea_size;
1377 +
1378 +       return iocb.status;
1379 +}
1380 +
1381 +int cfe_getstdhandle(int handletype)
1382 +{
1383 +       struct cfe_iocb iocb;
1384 +       int err;
1385 +
1386 +       memset(&iocb, 0, sizeof(iocb));
1387 +       iocb.fcode = CFE_CMD_DEV_GETHANDLE;
1388 +       iocb.flags = handletype;
1389 +
1390 +       err = cfe_iocb_dispatch(&iocb);
1391 +       if (CFE_ISERR(err))
1392 +               return err;
1393 +       if (CFE_ISERR(iocb.status))
1394 +               return iocb.status;
1395 +
1396 +       return iocb.handle;
1397 +}
1398 +
1399 +int cfe_getticks(s64 *ticks)
1400 +{
1401 +       struct cfe_iocb iocb;
1402 +       int err;
1403 +
1404 +       memset(&iocb, 0, sizeof(iocb));
1405 +       iocb.fcode = CFE_CMD_FW_GETTIME;
1406 +       iocb.psize = sizeof(struct cfe_iocb_time);
1407 +
1408 +       err = cfe_iocb_dispatch(&iocb);
1409 +       if (CFE_ISERR(err))
1410 +               return err;
1411 +       if (!CFE_ISERR(iocb.status))
1412 +               *ticks = iocb.time.ticks;
1413 +
1414 +       return iocb.status;
1415 +}
1416 +
1417 +int cfe_inpstat(int handle)
1418 +{
1419 +       struct cfe_iocb iocb;
1420 +       int err;
1421 +
1422 +       memset(&iocb, 0, sizeof(iocb));
1423 +       iocb.fcode = CFE_CMD_DEV_INPSTAT;
1424 +       iocb.handle = handle;
1425 +       iocb.psize = sizeof(struct cfe_iocb_inpstat);
1426 +
1427 +       err = cfe_iocb_dispatch(&iocb);
1428 +       if (CFE_ISERR(err))
1429 +               return err;
1430 +       if (CFE_ISERR(iocb.status))
1431 +               return iocb.status;
1432 +
1433 +       return iocb.inpstat.status;
1434 +}
1435 +
1436 +int cfe_ioctl(int handle, unsigned int ioctlnum,
1437 +             unsigned char *buffer, int length,
1438 +             int *retlen, u64 offset)
1439 +{
1440 +       struct cfe_iocb iocb;
1441 +       int err;
1442 +
1443 +       memset(&iocb, 0, sizeof(iocb));
1444 +       iocb.fcode = CFE_CMD_DEV_IOCTL;
1445 +       iocb.handle = handle;
1446 +       iocb.psize = sizeof(struct cfe_iocb_buf);
1447 +       iocb.buffer.offset = offset;
1448 +       iocb.buffer.ioctlcmd = ioctlnum;
1449 +       iocb.buffer.ptr = PTR_TO_CFE(buffer);
1450 +       iocb.buffer.length = length;
1451 +
1452 +       err = cfe_iocb_dispatch(&iocb);
1453 +       if (CFE_ISERR(err))
1454 +               return err;
1455 +       if (CFE_ISERR(iocb.status))
1456 +               return iocb.status;
1457 +       if (retlen)
1458 +               *retlen = iocb.buffer.retlen;
1459 +
1460 +       return iocb.status;
1461 +}
1462 +
1463 +int cfe_open(char *name)
1464 +{
1465 +       struct cfe_iocb iocb;
1466 +       int err;
1467 +
1468 +       memset(&iocb, 0, sizeof(iocb));
1469 +       iocb.fcode = CFE_CMD_DEV_OPEN;
1470 +       iocb.psize = sizeof(struct cfe_iocb_buf);
1471 +       iocb.buffer.ptr = PTR_TO_CFE(name);
1472 +       iocb.buffer.length = strlen(name);
1473 +
1474 +       err = cfe_iocb_dispatch(&iocb);
1475 +       if (CFE_ISERR(err))
1476 +               return err;
1477 +       if (CFE_ISERR(iocb.status))
1478 +               return iocb.status;
1479 +
1480 +       return iocb.handle;
1481 +}
1482 +
1483 +int cfe_read(int handle, unsigned char *buffer, int length)
1484 +{
1485 +       return cfe_readblk(handle, 0, buffer, length);
1486 +}
1487 +
1488 +int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length)
1489 +{
1490 +       struct cfe_iocb iocb;
1491 +       int err;
1492 +
1493 +       memset(&iocb, 0, sizeof(iocb));
1494 +       iocb.fcode = CFE_CMD_DEV_READ;
1495 +       iocb.handle = handle;
1496 +       iocb.psize = sizeof(struct cfe_iocb_buf);
1497 +       iocb.buffer.offset = offset;
1498 +       iocb.buffer.ptr = PTR_TO_CFE(buffer);
1499 +       iocb.buffer.length = length;
1500 +
1501 +       err = cfe_iocb_dispatch(&iocb);
1502 +       if (CFE_ISERR(err))
1503 +               return err;
1504 +       if (CFE_ISERR(iocb.status))
1505 +               return iocb.status;
1506 +
1507 +       return iocb.buffer.retlen;
1508 +}
1509 +
1510 +int cfe_setenv(char *name, char *val)
1511 +{
1512 +       struct cfe_iocb iocb;
1513 +       int err;
1514 +
1515 +       memset(&iocb, 0, sizeof(iocb));
1516 +       iocb.fcode = CFE_CMD_ENV_SET;
1517 +       iocb.psize = sizeof(struct cfe_iocb_envbuf);
1518 +       iocb.envbuf.name = PTR_TO_CFE(name);
1519 +       iocb.envbuf.name_len = strlen(name);
1520 +       iocb.envbuf.val = PTR_TO_CFE(val);
1521 +       iocb.envbuf.val_len = strlen(val);
1522 +
1523 +       err = cfe_iocb_dispatch(&iocb);
1524 +
1525 +       return (CFE_ISERR(err)) ? err : iocb.status;
1526 +}
1527 +
1528 +int cfe_write(int handle, unsigned char *buffer, int length)
1529 +{
1530 +       return cfe_writeblk(handle, 0, buffer, length);
1531 +}
1532 +
1533 +int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length)
1534 +{
1535 +       struct cfe_iocb iocb;
1536 +       int err;
1537 +
1538 +       memset(&iocb, 0, sizeof(iocb));
1539 +       iocb.fcode = CFE_CMD_DEV_WRITE;
1540 +       iocb.handle = handle;
1541 +       iocb.psize = sizeof(struct cfe_iocb_buf);
1542 +       iocb.buffer.offset = offset;
1543 +       iocb.buffer.ptr = PTR_TO_CFE(buffer);
1544 +       iocb.buffer.length = length;
1545 +
1546 +       err = cfe_iocb_dispatch(&iocb);
1547 +       if (CFE_ISERR(err))
1548 +               return err;
1549 +       if (CFE_ISERR(iocb.status))
1550 +               return iocb.status;
1551 +
1552 +       return iocb.buffer.retlen;
1553 +}
1554 diff -urN linux.old/arch/mips/cfe/cfe_private.h linux.dev/arch/mips/cfe/cfe_private.h
1555 --- linux.old/arch/mips/cfe/cfe_private.h       1970-01-01 01:00:00.000000000 +0100
1556 +++ linux.dev/arch/mips/cfe/cfe_private.h       2007-01-03 02:26:02.000000000 +0100
1557 @@ -0,0 +1,176 @@
1558 +/*
1559 + * Broadcom Common Firmware Environment (CFE) support
1560 + *
1561 + * Copyright 2000, 2001, 2002
1562 + * Broadcom Corporation. All rights reserved.
1563 + *
1564 + * Copyright (C) 2006 Michael Buesch
1565 + *
1566 + * Original Authors:  Mitch Lichtenberg, Chris Demetriou
1567 + *
1568 + * This software is furnished under license and may be used and copied only
1569 + * in accordance with the following terms and conditions.  Subject to these
1570 + * conditions, you may download, copy, install, use, modify and distribute
1571 + * modified or unmodified copies of this software in source and/or binary
1572 + * form. No title or ownership is transferred hereby.
1573 + *
1574 + * 1) Any source code used, modified or distributed must reproduce and
1575 + *    retain this copyright notice and list of conditions as they appear in
1576 + *    the source file.
1577 + *
1578 + * 2) No right is granted to use any trade name, trademark, or logo of
1579 + *    Broadcom Corporation.  The "Broadcom Corporation" name may not be
1580 + *    used to endorse or promote products derived from this software
1581 + *    without the prior written permission of Broadcom Corporation.
1582 + *
1583 + * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
1584 + *    WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
1585 + *    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
1586 + *    NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
1587 + *    FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
1588 + *    LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1589 + *    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1590 + *    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
1591 + *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
1592 + *    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
1593 + *    OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1594 + */
1595 +
1596 +#ifndef LINUX_CFE_PRIVATE_H_
1597 +#define LINUX_CFE_PRIVATE_H_
1598 +
1599 +#ifndef __ASSEMBLY__
1600 +
1601 +/* Seal indicating CFE's presence, passed to the kernel. */
1602 +#define CFE_EPTSEAL            0x43464531
1603 +
1604 +#define CFE_CMD_FW_GETINFO     0
1605 +#define CFE_CMD_FW_RESTART     1
1606 +#define CFE_CMD_FW_BOOT                2
1607 +#define CFE_CMD_FW_CPUCTL      3
1608 +#define CFE_CMD_FW_GETTIME      4
1609 +#define CFE_CMD_FW_MEMENUM     5
1610 +#define CFE_CMD_FW_FLUSHCACHE  6
1611 +
1612 +#define CFE_CMD_DEV_GETHANDLE  9
1613 +#define CFE_CMD_DEV_ENUM       10
1614 +#define CFE_CMD_DEV_OPEN       11
1615 +#define CFE_CMD_DEV_INPSTAT    12
1616 +#define CFE_CMD_DEV_READ       13
1617 +#define CFE_CMD_DEV_WRITE      14
1618 +#define CFE_CMD_DEV_IOCTL      15
1619 +#define CFE_CMD_DEV_CLOSE      16
1620 +#define CFE_CMD_DEV_GETINFO    17
1621 +
1622 +#define CFE_CMD_ENV_ENUM       20
1623 +#define CFE_CMD_ENV_GET                22
1624 +#define CFE_CMD_ENV_SET                23
1625 +#define CFE_CMD_ENV_DEL                24
1626 +
1627 +#define CFE_CMD_MAX            32
1628 +
1629 +#define CFE_CMD_VENDOR_USE     0x8000  /* codes above this are for customer use */
1630 +
1631 +typedef u64 cfe_uint_t;
1632 +typedef s64 cfe_int_t;
1633 +typedef s64 cfe_ptr_t;
1634 +
1635 +/* Cast a pointer from native to CFE-API pointer and back */
1636 +#define CFE_TO_PTR(p)          ((void *)(unsigned long)(p))
1637 +#define PTR_TO_CFE(p)          ((cfe_ptr_t)(unsigned long)(p))
1638 +
1639 +struct cfe_iocb_buf {
1640 +       cfe_uint_t      offset;         /* offset on device (bytes) */
1641 +       cfe_ptr_t       ptr;            /* pointer to a buffer */
1642 +       cfe_uint_t      length;         /* length of this buffer */
1643 +       cfe_uint_t      retlen;         /* returned length (for read ops) */
1644 +       union {
1645 +               cfe_uint_t      ioctlcmd;       /* IOCTL command (used only for IOCTLs) */
1646 +               cfe_uint_t      devflags;       /* Returned device info flags */
1647 +       };
1648 +};
1649 +
1650 +struct cfe_iocb_inpstat {
1651 +       cfe_uint_t      status;         /* 1 means input available */
1652 +};
1653 +
1654 +struct cfe_iocb_envbuf {
1655 +       cfe_int_t       index;          /* 0-based enumeration index */
1656 +       cfe_ptr_t       name;           /* name string buffer */
1657 +       cfe_int_t       name_len;       /* size of name buffer */
1658 +       cfe_ptr_t       val;            /* value string buffer */
1659 +       cfe_int_t       val_len;        /* size of value string buffer */
1660 +};
1661 +
1662 +struct cfe_iocb_cpuctl {
1663 +       cfe_uint_t      number;         /* cpu number to control */
1664 +       cfe_uint_t      command;        /* command to issue to CPU */
1665 +       cfe_uint_t      start_addr;     /* CPU start address */
1666 +       cfe_uint_t      gp;             /* starting GP value */
1667 +       cfe_uint_t      sp;             /* starting SP value */
1668 +       cfe_uint_t      a1;             /* starting A1 value */
1669 +};
1670 +
1671 +struct cfe_iocb_time {
1672 +       cfe_int_t       ticks;          /* current time in ticks */
1673 +};
1674 +
1675 +struct cfe_iocb_exitstat {
1676 +       cfe_int_t       status;
1677 +};
1678 +
1679 +struct cfe_iocb_meminfo {
1680 +       cfe_int_t       index;          /* 0-based enumeration index */
1681 +       cfe_int_t       type;           /* type of memory block */
1682 +       cfe_uint_t      addr;           /* physical start address */
1683 +       cfe_uint_t      size;           /* block size */
1684 +};
1685 +
1686 +struct cfe_iocb_fwinfo {
1687 +       cfe_int_t       version;        /* major, minor, eco version */
1688 +       cfe_int_t       totalmem;       /* total installed mem */
1689 +       cfe_int_t       flags;          /* various flags */
1690 +       cfe_int_t       boardid;        /* board ID */
1691 +       cfe_int_t       bootarea_va;    /* VA of boot area */
1692 +       cfe_int_t       bootarea_pa;    /* PA of boot area */
1693 +       cfe_int_t       bootarea_size;  /* size of boot area */
1694 +       cfe_int_t       reserved1;
1695 +       cfe_int_t       reserved2;
1696 +       cfe_int_t       reserved3;
1697 +};
1698 +
1699 +/* CFE I/O Control Block */
1700 +struct cfe_iocb {
1701 +       cfe_uint_t      fcode;          /* IOCB function code */
1702 +       cfe_int_t       status;         /* return status */
1703 +       cfe_int_t       handle;         /* file/device handle */
1704 +       cfe_uint_t      flags;          /* flags for this IOCB */
1705 +       cfe_uint_t      psize;          /* size of parameter list */
1706 +       union {
1707 +               struct cfe_iocb_buf             buffer;         /* buffer parameters */
1708 +               struct cfe_iocb_inpstat         inpstat;        /* input status parameters */
1709 +               struct cfe_iocb_envbuf          envbuf;         /* environment function parameters */
1710 +               struct cfe_iocb_cpuctl          cpuctl;         /* CPU control parameters */
1711 +               struct cfe_iocb_time            time;           /* timer parameters */
1712 +               struct cfe_iocb_meminfo         meminfo;        /* memory arena info parameters */
1713 +               struct cfe_iocb_fwinfo          fwinfo;         /* firmware information */
1714 +               struct cfe_iocb_exitstat        exitstat;       /* Exit Status */
1715 +       };
1716 +};
1717 +
1718 +
1719 +#include <linux/init.h>
1720 +
1721 +void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
1722 +                     unsigned long fwarg2, unsigned long fwarg3);
1723 +
1724 +#else /* __ASSEMBLY__ */
1725 +
1726 +       .macro  cfe_early_init
1727 +#ifdef CONFIG_CFE
1728 +               jal     cfe_setup
1729 +#endif
1730 +       .endm
1731 +
1732 +#endif /* __ASSEMBLY__ */
1733 +#endif /* LINUX_CFE_PRIVATE_H_ */
1734 diff -urN linux.old/arch/mips/cfe/Makefile linux.dev/arch/mips/cfe/Makefile
1735 --- linux.old/arch/mips/cfe/Makefile    1970-01-01 01:00:00.000000000 +0100
1736 +++ linux.dev/arch/mips/cfe/Makefile    2007-01-03 02:26:02.000000000 +0100
1737 @@ -0,0 +1,5 @@
1738 +#
1739 +# Makefile for the Broadcom Common Firmware Environment support
1740 +#
1741 +
1742 +obj-y += cfe.o
1743 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
1744 --- linux.old/arch/mips/Kconfig 2006-12-11 20:32:53.000000000 +0100
1745 +++ linux.dev/arch/mips/Kconfig 2007-01-03 02:26:02.000000000 +0100
1746 @@ -4,6 +4,10 @@
1747         # Horrible source of confusion.  Die, die, die ...
1748         select EMBEDDED
1749
1750 +config CFE
1751 +       bool
1752 +       # Common Firmware Environment
1753 +
1754  mainmenu "Linux/MIPS Kernel Configuration"
1755
1756  menu "Machine selection"
1757 @@ -222,6 +226,22 @@
1758          Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
1759          Olivetti M700-10 workstations.
1760
1761 +config BCM947XX
1762 +       bool "Support for BCM947xx based boards"
1763 +       select DMA_NONCOHERENT
1764 +       select HW_HAS_PCI
1765 +       select IRQ_CPU
1766 +       select SYS_HAS_CPU_MIPS32_R1
1767 +       select SYS_SUPPORTS_32BIT_KERNEL
1768 +       select SYS_SUPPORTS_LITTLE_ENDIAN
1769 +       select MIPS_CPU_SCACHE
1770 +       select SSB
1771 +       select SSB_DRIVER_MIPS
1772 +       select SSB_DRIVER_EXTIF
1773 +       select CFE
1774 +       help
1775 +        Support for BCM947xx based boards
1776 +
1777  config LASAT
1778         bool "LASAT Networks platforms"
1779         select DMA_NONCOHERENT
1780 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
1781 --- linux.old/arch/mips/kernel/cpu-probe.c      2006-12-11 20:32:53.000000000 +0100
1782 +++ linux.dev/arch/mips/kernel/cpu-probe.c      2007-01-03 02:26:02.000000000 +0100
1783 @@ -723,6 +723,28 @@
1784  }
1785
1786
1787 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
1788 +{
1789 +       decode_config1(c);
1790 +       switch (c->processor_id & 0xff00) {
1791 +               case PRID_IMP_BCM3302:
1792 +                       c->cputype = CPU_BCM3302;
1793 +                       c->isa_level = MIPS_CPU_ISA_M32R1;
1794 +                       c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1795 +                                       MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
1796 +               break;
1797 +               case PRID_IMP_BCM4710:
1798 +                       c->cputype = CPU_BCM4710;
1799 +                       c->isa_level = MIPS_CPU_ISA_M32R1;
1800 +                       c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1801 +                                       MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
1802 +               break;
1803 +       default:
1804 +               c->cputype = CPU_UNKNOWN;
1805 +               break;
1806 +       }
1807 +}
1808 +
1809  __init void cpu_probe(void)
1810  {
1811         struct cpuinfo_mips *c = &current_cpu_data;
1812 @@ -745,6 +767,9 @@
1813         case PRID_COMP_SIBYTE:
1814                 cpu_probe_sibyte(c);
1815                 break;
1816 +       case PRID_COMP_BROADCOM:
1817 +               cpu_probe_broadcom(c);
1818 +               break;
1819         case PRID_COMP_SANDCRAFT:
1820                 cpu_probe_sandcraft(c);
1821                 break;
1822 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
1823 --- linux.old/arch/mips/kernel/proc.c   2006-12-11 20:32:53.000000000 +0100
1824 +++ linux.dev/arch/mips/kernel/proc.c   2007-01-03 02:26:02.000000000 +0100
1825 @@ -83,6 +83,8 @@
1826         [CPU_VR4181]    = "NEC VR4181",
1827         [CPU_VR4181A]   = "NEC VR4181A",
1828         [CPU_SR71000]   = "Sandcraft SR71000",
1829 +       [CPU_BCM3302]   = "Broadcom BCM3302",
1830 +       [CPU_BCM4710]   = "Broadcom BCM4710",
1831         [CPU_PR4450]    = "Philips PR4450",
1832  };
1833
1834 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
1835 --- linux.old/arch/mips/Makefile        2007-01-03 02:25:09.000000000 +0100
1836 +++ linux.dev/arch/mips/Makefile        2007-01-03 02:26:02.000000000 +0100
1837 @@ -571,6 +571,18 @@
1838  load-$(CONFIG_SIBYTE_BIGSUR)   := 0xffffffff80100000
1839
1840  #
1841 +# Broadcom BCM47XX boards
1842 +#
1843 +core-$(CONFIG_BCM947XX)                += arch/mips/bcm947xx/
1844 +cflags-$(CONFIG_BCM947XX)      += -Iarch/mips/bcm947xx/include -Iinclude/asm-mips/mach-bcm947xx
1845 +load-$(CONFIG_BCM947XX)                := 0xffffffff80001000
1846 +
1847 +#
1848 +# Common Firmware Environment
1849 +#
1850 +core-$(CONFIG_CFE)             += arch/mips/cfe/
1851 +
1852 +#
1853  # SNI RM200 PCI
1854  #
1855  core-$(CONFIG_SNI_RM200_PCI)   += arch/mips/sni/
1856 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
1857 --- linux.old/arch/mips/mm/tlbex.c      2006-12-11 20:32:53.000000000 +0100
1858 +++ linux.dev/arch/mips/mm/tlbex.c      2007-01-03 02:26:02.000000000 +0100
1859 @@ -880,6 +880,8 @@
1860         case CPU_4KSC:
1861         case CPU_20KC:
1862         case CPU_25KF:
1863 +       case CPU_BCM3302:
1864 +       case CPU_BCM4710:
1865                 tlbw(p);
1866                 break;
1867
1868 diff -urN linux.old/drivers/Kconfig linux.dev/drivers/Kconfig
1869 --- linux.old/drivers/Kconfig   2006-12-11 20:32:53.000000000 +0100
1870 +++ linux.dev/drivers/Kconfig   2007-01-03 02:26:02.000000000 +0100
1871 @@ -56,6 +56,8 @@
1872
1873  source "drivers/hwmon/Kconfig"
1874
1875 +source "drivers/ssb/Kconfig"
1876 +
1877  source "drivers/mfd/Kconfig"
1878
1879  source "drivers/media/Kconfig"
1880 diff -urN linux.old/drivers/Makefile linux.dev/drivers/Makefile
1881 --- linux.old/drivers/Makefile  2006-12-11 20:32:53.000000000 +0100
1882 +++ linux.dev/drivers/Makefile  2007-01-03 02:26:02.000000000 +0100
1883 @@ -77,3 +77,4 @@
1884  obj-$(CONFIG_SUPERH)           += sh/
1885  obj-$(CONFIG_GENERIC_TIME)     += clocksource/
1886  obj-$(CONFIG_DMA_ENGINE)       += dma/
1887 +obj-$(CONFIG_SSB)              += ssb/
1888 diff -urN linux.old/drivers/ssb/core.c linux.dev/drivers/ssb/core.c
1889 --- linux.old/drivers/ssb/core.c        1970-01-01 01:00:00.000000000 +0100
1890 +++ linux.dev/drivers/ssb/core.c        2007-01-03 02:29:17.000000000 +0100
1891 @@ -0,0 +1,677 @@
1892 +#include "ssb_private.h"
1893 +
1894 +#include <linux/delay.h>
1895 +#include <linux/pci.h>
1896 +#include <linux/ssb.h>
1897 +#include <linux/ssb_regs.h>
1898 +
1899 +
1900 +MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
1901 +MODULE_LICENSE("GPL");
1902 +
1903 +
1904 +static LIST_HEAD(attach_queue);
1905 +static LIST_HEAD(buses);
1906 +static int nr_buses;
1907 +static DEFINE_MUTEX(buses_mutex);
1908 +
1909 +#define ssb_buses_lock() do {                  \
1910 +       if (!is_early_boot())                   \
1911 +               mutex_lock(&buses_mutex);       \
1912 +                       } while (0)
1913 +
1914 +#define ssb_buses_unlock() do {                        \
1915 +       if (!is_early_boot())                   \
1916 +               mutex_unlock(&buses_mutex);     \
1917 +                       } while (0)
1918 +
1919 +
1920 +static struct ssb_device * ssb_device_get(struct ssb_device *dev)
1921 +{
1922 +       if (dev)
1923 +               get_device(&dev->dev);
1924 +       return dev;
1925 +}
1926 +
1927 +static void ssb_device_put(struct ssb_device *dev)
1928 +{
1929 +       if (dev)
1930 +               put_device(&dev->dev);
1931 +}
1932 +
1933 +static int ssb_device_resume(struct device *dev)
1934 +{
1935 +       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1936 +       struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
1937 +       int err = 0;
1938 +
1939 +       if (ssb_drv && ssb_drv->resume)
1940 +               err = ssb_drv->resume(ssb_dev);
1941 +
1942 +       return err;
1943 +}
1944 +
1945 +static int ssb_device_suspend(struct device *dev, pm_message_t state)
1946 +{
1947 +       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1948 +       struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
1949 +       int err = 0;
1950 +
1951 +       if (ssb_drv && ssb_drv->suspend)
1952 +               err = ssb_drv->suspend(ssb_dev, state);
1953 +
1954 +       return err;
1955 +}
1956 +
1957 +static void ssb_device_shutdown(struct device *dev)
1958 +{
1959 +       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1960 +       struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
1961 +
1962 +       if (ssb_drv && ssb_drv->shutdown)
1963 +               ssb_drv->shutdown(ssb_dev);
1964 +}
1965 +
1966 +static int ssb_device_remove(struct device *dev)
1967 +{
1968 +       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1969 +       struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
1970 +
1971 +       if (ssb_drv && ssb_drv->remove)
1972 +               ssb_drv->remove(ssb_dev);
1973 +       ssb_device_put(ssb_dev);
1974 +
1975 +       return 0;
1976 +}
1977 +
1978 +static int ssb_device_probe(struct device *dev)
1979 +{
1980 +       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1981 +       struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
1982 +       int err = 0;
1983 +
1984 +       ssb_device_get(ssb_dev);
1985 +       if (ssb_drv && ssb_drv->probe)
1986 +               err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
1987 +       if (err)
1988 +               ssb_device_put(ssb_dev);
1989 +
1990 +       return err;
1991 +}
1992 +
1993 +static int ssb_match_devid(const struct ssb_device_id *tabid,
1994 +                          const struct ssb_device_id *devid)
1995 +{
1996 +       if ((tabid->vendor != devid->vendor) &&
1997 +           tabid->vendor != SSB_ANY_VENDOR)
1998 +               return 0;
1999 +       if ((tabid->coreid != devid->coreid) &&
2000 +           tabid->coreid != SSB_ANY_ID)
2001 +               return 0;
2002 +       if ((tabid->revision != devid->revision) &&
2003 +           tabid->revision != SSB_ANY_REV)
2004 +               return 0;
2005 +       return 1;
2006 +}
2007 +
2008 +static int ssb_bus_match(struct device *dev, struct device_driver *drv)
2009 +{
2010 +       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
2011 +       struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
2012 +       const struct ssb_device_id *id;
2013 +
2014 +       for (id = ssb_drv->id_table;
2015 +            id->vendor || id->coreid || id->revision;
2016 +            id++) {
2017 +               if (ssb_match_devid(id, &ssb_dev->id))
2018 +                       return 1; /* found */
2019 +       }
2020 +
2021 +       return 0;
2022 +}
2023 +
2024 +struct bus_type ssb_bustype = {
2025 +       .name           = NULL, /* Intentionally NULL to indicate early boot */
2026 +       .match          = ssb_bus_match,
2027 +       .probe          = ssb_device_probe,
2028 +       .remove         = ssb_device_remove,
2029 +       .shutdown       = ssb_device_shutdown,
2030 +       .suspend        = ssb_device_suspend,
2031 +       .resume         = ssb_device_resume,
2032 +};
2033 +
2034 +#define is_early_boot()                (ssb_bustype.name == NULL)
2035 +
2036 +void ssb_bus_unregister(struct ssb_bus *bus)
2037 +{
2038 +       struct ssb_device *dev;
2039 +       int i;
2040 +
2041 +       ssb_buses_lock();
2042 +       for (i = bus->nr_devices - 1; i >= 0; i--) {
2043 +               dev = &(bus->devices[i]);
2044 +               device_unregister(&dev->dev);
2045 +       }
2046 +       list_del(&bus->list);
2047 +       ssb_buses_unlock();
2048 +
2049 +//TODO chipcommon exit
2050 +       /* Free MMIO */
2051 +       bus->mapped_device = NULL;
2052 +       if (bus->bustype == SSB_BUSTYPE_SSB)
2053 +               iounmap(bus->mmio);
2054 +       else
2055 +               pci_iounmap(bus->host_pci, bus->mmio);
2056 +       bus->mmio = NULL;
2057 +}
2058 +EXPORT_SYMBOL(ssb_bus_unregister);
2059 +
2060 +static void ssb_release_dev(struct device *dev)
2061 +{
2062 +       /* Nothing */
2063 +}
2064 +
2065 +/* Needs ssb_buses_lock() */
2066 +static int ssb_attach_queued_buses(void)
2067 +{
2068 +       struct ssb_bus *bus, *n;
2069 +       struct ssb_device *dev;
2070 +       int i, err;
2071 +
2072 +       list_for_each_entry_safe(bus, n, &attach_queue, list) {
2073 +               for (i = 0; i < bus->nr_devices; i++) {
2074 +                       dev = &(bus->devices[i]);
2075 +
2076 +                       dev->dev.release = ssb_release_dev;
2077 +                       err = device_register(&dev->dev);
2078 +                       if (err) {
2079 +                               ssb_printk("Could not register %s\n",
2080 +                                          dev->dev.bus_id);
2081 +                       }
2082 +               }
2083 +               list_move_tail(&bus->list, &buses);
2084 +       }
2085 +       return 0;
2086 +}
2087 +
2088 +static void ssb_get_boardtype(struct ssb_bus *bus)
2089 +{
2090 +       if (bus->bustype != SSB_BUSTYPE_PCI) {
2091 +               /* Must set board_vendor, board_type and board_rev
2092 +                * before calling ssb_bus_*_register() */
2093 +               assert(bus->board_vendor && bus->board_type);
2094 +               return;
2095 +       }
2096 +       ssb_pci_get_boardtype(bus);
2097 +}
2098 +
2099 +static int ssb_bus_register(struct ssb_bus *bus,
2100 +                           unsigned long baseaddr)
2101 +{
2102 +       int err;
2103 +
2104 +       ssb_printk("Sonics Silicon Backplane found at: ");
2105 +       if (bus->bustype == SSB_BUSTYPE_PCI)
2106 +               ssb_printk("PCI device %s\n", bus->host_pci->dev.bus_id);
2107 +       else
2108 +               ssb_printk("Address 0x%08lX\n", baseaddr);
2109 +
2110 +       spin_lock_init(&bus->bar_lock);
2111 +       INIT_LIST_HEAD(&bus->list);
2112 +
2113 +       ssb_get_boardtype(bus);
2114 +       /* Powerup the bus */
2115 +       err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
2116 +       if (err)
2117 +               goto out;
2118 +       /* Scan for devices (cores) */
2119 +       err = ssb_bus_scan(bus, baseaddr);
2120 +       if (err)
2121 +               goto err_disable_xtal;
2122 +       if (bus->bustype == SSB_BUSTYPE_PCI) {
2123 +               err = ssb_pci_sprom_get(bus);
2124 +               if (err)
2125 +                       goto err_unmap;
2126 +       }
2127 +       /* Initialize basic system devices (if available) */
2128 +       ssb_chipcommon_init(&bus->chipco);
2129 +       ssb_mipscore_init(&bus->mipscore);
2130 +       //TODO also register drivers for the basic system stuff later?
2131 +       //     I think the only purpose would be to show them in sysfs.
2132 +
2133 +       ssb_buses_lock();
2134 +       bus->busnumber = nr_buses;
2135 +       /* Queue it for attach */
2136 +       list_add_tail(&bus->list, &attach_queue);
2137 +       if (!is_early_boot()) {
2138 +               /* This is not early boot, so we must attach the bus now */
2139 +               err = ssb_attach_queued_buses();
2140 +               if (err)
2141 +                       goto err_dequeue;
2142 +       }
2143 +       nr_buses++;
2144 +       ssb_buses_unlock();
2145 +
2146 +out:
2147 +       return err;
2148 +
2149 +err_dequeue:
2150 +       list_del(&bus->list);
2151 +       ssb_buses_unlock();
2152 +err_unmap:
2153 +       bus->mapped_device = NULL;
2154 +       if (bus->bustype == SSB_BUSTYPE_SSB)
2155 +               iounmap(bus->mmio);
2156 +       else
2157 +               pci_iounmap(bus->host_pci, bus->mmio);
2158 +       bus->mmio = NULL;
2159 +err_disable_xtal:
2160 +       ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
2161 +       goto out;
2162 +}
2163 +
2164 +int ssb_bus_pcibus_register(struct ssb_bus *bus,
2165 +                           struct pci_dev *host_pci)
2166 +{
2167 +       int err;
2168 +
2169 +       bus->bustype = SSB_BUSTYPE_PCI;
2170 +       bus->host_pci = host_pci;
2171 +
2172 +       err = ssb_bus_register(bus, 0);
2173 +
2174 +       return err;
2175 +}
2176 +EXPORT_SYMBOL(ssb_bus_pcibus_register);
2177 +
2178 +int ssb_bus_ssbbus_register(struct ssb_bus *bus,
2179 +                           unsigned long baseaddr,
2180 +                           void (*fill_sprom)(struct ssb_sprom *sprom))
2181 +{
2182 +       int err;
2183 +
2184 +       bus->bustype = SSB_BUSTYPE_SSB;
2185 +       fill_sprom(&bus->sprom);
2186 +       err = ssb_bus_register(bus, baseaddr);
2187 +
2188 +       return err;
2189 +}
2190 +
2191 +static inline
2192 +int do_select_core(struct ssb_bus *bus,
2193 +                  struct ssb_device *dev,
2194 +                  u16 *offset)
2195 +{
2196 +       int err = 0;
2197 +
2198 +       switch (bus->bustype) {
2199 +       case SSB_BUSTYPE_PCI:
2200 +               if (unlikely(dev != bus->mapped_device))
2201 +                       err = ssb_pci_switch_core(bus, dev);
2202 +               break;
2203 +       case SSB_BUSTYPE_SSB:
2204 +               *offset += dev->core_index * SSB_CORE_SIZE;
2205 +               break;
2206 +       }
2207 +
2208 +       return err;
2209 +}
2210 +
2211 +u16 ssb_read16(struct ssb_device *dev, u16 offset)
2212 +{
2213 +       struct ssb_bus *bus = dev->bus;
2214 +
2215 +       if (unlikely(do_select_core(bus, dev, &offset)))
2216 +               return 0xFFFF;
2217 +       return ssb_raw_read16(bus, offset);
2218 +}
2219 +EXPORT_SYMBOL(ssb_read16);
2220 +
2221 +u32 ssb_read32(struct ssb_device *dev, u16 offset)
2222 +{
2223 +       struct ssb_bus *bus = dev->bus;
2224 +
2225 +       if (unlikely(do_select_core(bus, dev, &offset)))
2226 +               return 0xFFFFFFFF;
2227 +       return ssb_raw_read32(bus, offset);
2228 +}
2229 +EXPORT_SYMBOL(ssb_read32);
2230 +
2231 +void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
2232 +{
2233 +       struct ssb_bus *bus = dev->bus;
2234 +
2235 +       if (unlikely(do_select_core(bus, dev, &offset)))
2236 +               return;
2237 +       ssb_raw_write16(bus, offset, value);
2238 +}
2239 +EXPORT_SYMBOL(ssb_write16);
2240 +
2241 +void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
2242 +{
2243 +       struct ssb_bus *bus = dev->bus;
2244 +
2245 +       if (unlikely(do_select_core(bus, dev, &offset)))
2246 +               return;
2247 +       ssb_raw_write32(bus, offset, value);
2248 +}
2249 +EXPORT_SYMBOL(ssb_write32);
2250 +
2251 +int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
2252 +{
2253 +       drv->drv.name = drv->name;
2254 +       drv->drv.bus = &ssb_bustype;
2255 +       drv->drv.owner = owner;
2256 +
2257 +       return driver_register(&drv->drv);
2258 +}
2259 +EXPORT_SYMBOL(__ssb_driver_register);
2260 +
2261 +void ssb_driver_unregister(struct ssb_driver *drv)
2262 +{
2263 +       driver_unregister(&drv->drv);
2264 +}
2265 +EXPORT_SYMBOL(ssb_driver_unregister);
2266 +
2267 +void ssb_set_devtypedata(struct ssb_device *dev, void *data)
2268 +{
2269 +       struct ssb_bus *bus = dev->bus;
2270 +       struct ssb_device *ent;
2271 +       int i;
2272 +
2273 +       for (i = 0; i < bus->nr_devices; i++) {
2274 +               ent = &(bus->devices[i]);
2275 +               if (ent->id.vendor != dev->id.vendor)
2276 +                       continue;
2277 +               if (ent->id.coreid != dev->id.coreid)
2278 +                       continue;
2279 +
2280 +               ent->devtypedata = data;
2281 +       }
2282 +}
2283 +EXPORT_SYMBOL(ssb_set_devtypedata);
2284 +
2285 +static u32 clkfactor_f6_resolve(u32 v)
2286 +{
2287 +       /* map the magic values */
2288 +       switch (v) {
2289 +       case SSB_CHIPCO_CLK_F6_2:
2290 +               return 2;
2291 +       case SSB_CHIPCO_CLK_F6_3:
2292 +               return 3;
2293 +       case SSB_CHIPCO_CLK_F6_4:
2294 +               return 4;
2295 +       case SSB_CHIPCO_CLK_F6_5:
2296 +               return 5;
2297 +       case SSB_CHIPCO_CLK_F6_6:
2298 +               return 6;
2299 +       case SSB_CHIPCO_CLK_F6_7:
2300 +               return 7;
2301 +       }
2302 +       return 0;
2303 +}
2304 +
2305 +/* Calculate the speed the backplane would run at a given set of clockcontrol values */
2306 +u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
2307 +{
2308 +       u32 n1, n2, clock, m1, m2, m3, mc;
2309 +
2310 +       n1 = (n & SSB_CHIPCO_CLK_N1);
2311 +       n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
2312 +
2313 +       switch (plltype) {
2314 +       case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
2315 +               if (m & SSB_CHIPCO_CLK_T6_MMASK)
2316 +                       return SSB_CHIPCO_CLK_T6_M0;
2317 +               return SSB_CHIPCO_CLK_T6_M1;
2318 +       case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
2319 +       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
2320 +       case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
2321 +       case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
2322 +               n1 = clkfactor_f6_resolve(n1);
2323 +               n2 += SSB_CHIPCO_CLK_F5_BIAS;
2324 +               break;
2325 +       case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
2326 +               n1 += SSB_CHIPCO_CLK_T2_BIAS;
2327 +               n2 += SSB_CHIPCO_CLK_T2_BIAS;
2328 +               assert((n1 >= 2) && (n1 <= 7));
2329 +               assert((n2 >= 5) && (n2 <= 23));
2330 +               break;
2331 +       case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
2332 +               return 100000000;
2333 +       default:
2334 +               assert(0);
2335 +       }
2336 +
2337 +       switch (plltype) {
2338 +       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
2339 +       case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
2340 +               clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
2341 +               break;
2342 +       default:
2343 +               clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
2344 +       }
2345 +       if (!clock)
2346 +               return 0;
2347 +
2348 +       m1 = (m & SSB_CHIPCO_CLK_M1);
2349 +       m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
2350 +       m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
2351 +       mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
2352 +
2353 +       switch (plltype) {
2354 +       case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
2355 +       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
2356 +       case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
2357 +       case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
2358 +               m1 = clkfactor_f6_resolve(m1);
2359 +               if ((plltype == SSB_PLLTYPE_1) ||
2360 +                   (plltype == SSB_PLLTYPE_3))
2361 +                       m2 += SSB_CHIPCO_CLK_F5_BIAS;
2362 +               else
2363 +                       m2 = clkfactor_f6_resolve(m2);
2364 +               m3 = clkfactor_f6_resolve(m3);
2365 +
2366 +               switch (mc) {
2367 +               case SSB_CHIPCO_CLK_MC_BYPASS:
2368 +                       return clock;
2369 +               case SSB_CHIPCO_CLK_MC_M1:
2370 +                       return (clock / m1);
2371 +               case SSB_CHIPCO_CLK_MC_M1M2:
2372 +                       return (clock / (m1 * m2));
2373 +               case SSB_CHIPCO_CLK_MC_M1M2M3:
2374 +                       return (clock / (m1 * m2 * m3));
2375 +               case SSB_CHIPCO_CLK_MC_M1M3:
2376 +                       return (clock / (m1 * m3));
2377 +               }
2378 +               return 0;
2379 +       case SSB_PLLTYPE_2:
2380 +               m1 += SSB_CHIPCO_CLK_T2_BIAS;
2381 +               m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
2382 +               m3 += SSB_CHIPCO_CLK_T2_BIAS;
2383 +               assert((m1 >= 2) && (m1 <= 7));
2384 +               assert((m2 >= 3) && (m2 <= 10));
2385 +               assert((m3 >= 2) && (m3 <= 7));
2386 +
2387 +               if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
2388 +                       clock /= m1;
2389 +               if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
2390 +                       clock /= m2;
2391 +               if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
2392 +                       clock /= m3;
2393 +               return clock;
2394 +       default:
2395 +               assert(0);
2396 +       }
2397 +       return 0;
2398 +}
2399 +
2400 +/* Get the current speed the backplane is running at */
2401 +u32 ssb_clockspeed(struct ssb_bus *bus)
2402 +{
2403 +       u32 rate;
2404 +       u32 plltype;
2405 +       u32 clkctl_n, clkctl_m;
2406 +
2407 +       //TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb
2408 +
2409 +       if (bus->chipco.dev) {
2410 +               ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
2411 +                                           &clkctl_n, &clkctl_m);
2412 +       } else
2413 +               return 0;
2414 +
2415 +       if (bus->chip_id == 0x5365) {
2416 +               rate = 100000000;
2417 +       } else {
2418 +               rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
2419 +               if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
2420 +                       rate /= 2;
2421 +       }
2422 +
2423 +       return rate;
2424 +}
2425 +
2426 +int ssb_device_is_enabled(struct ssb_device *dev)
2427 +{
2428 +       u32 val;
2429 +
2430 +       val = ssb_read32(dev, SSB_TMSLOW);
2431 +       val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT;
2432 +
2433 +       return (val == SSB_TMSLOW_CLOCK);
2434 +}
2435 +EXPORT_SYMBOL(ssb_device_is_enabled);
2436 +
2437 +void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
2438 +{
2439 +       u32 val;
2440 +
2441 +       ssb_device_disable(dev, core_specific_flags);
2442 +       ssb_write32(dev, SSB_TMSLOW,
2443 +                   SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
2444 +                   SSB_TMSLOW_FGC | core_specific_flags);
2445 +       /* flush */
2446 +       ssb_read32(dev, SSB_TMSLOW);
2447 +       udelay(1);
2448 +
2449 +       /* Clear SERR if set. This is a hw bug workaround. */
2450 +       if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
2451 +               ssb_write32(dev, SSB_TMSHIGH, 0);
2452 +
2453 +       val = ssb_read32(dev, SSB_IMSTATE);
2454 +       if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
2455 +               val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
2456 +               ssb_write32(dev, SSB_IMSTATE, val);
2457 +       }
2458 +
2459 +       ssb_write32(dev, SSB_TMSLOW,
2460 +                   SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
2461 +                   core_specific_flags);
2462 +       /* flush */
2463 +       ssb_read32(dev, SSB_TMSLOW);
2464 +       udelay(1);
2465 +
2466 +       ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
2467 +                   core_specific_flags);
2468 +       /* flush */
2469 +       ssb_read32(dev, SSB_TMSLOW);
2470 +       udelay(1);
2471 +}
2472 +EXPORT_SYMBOL(ssb_device_enable);
2473 +
2474 +static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
2475 +                       int timeout, int set)
2476 +{
2477 +       int i;
2478 +       u32 val;
2479 +
2480 +       for (i = 0; i < timeout; i++) {
2481 +               val = ssb_read32(dev, reg);
2482 +               if (set) {
2483 +                       if (val & bitmask)
2484 +                               return 0;
2485 +               } else {
2486 +                       if (!(val & bitmask))
2487 +                               return 0;
2488 +               }
2489 +               udelay(10);
2490 +       }
2491 +       printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
2492 +                           "register %04X to %s.\n",
2493 +              bitmask, reg, (set ? "set" : "clear"));
2494 +
2495 +       return -ETIMEDOUT;
2496 +}
2497 +
2498 +void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
2499 +{
2500 +       if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
2501 +               return;
2502 +
2503 +       ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT | SSB_TMSLOW_CLOCK);
2504 +       ssb_wait_bit(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT, 1000, 1);
2505 +       ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
2506 +       ssb_write32(dev, SSB_TMSLOW,
2507 +                   SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
2508 +                   SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
2509 +                   core_specific_flags);
2510 +       /* flush */
2511 +       ssb_read32(dev, SSB_TMSLOW);
2512 +       udelay(1);
2513 +
2514 +       ssb_write32(dev, SSB_TMSLOW,
2515 +                   SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
2516 +                   core_specific_flags);
2517 +       /* flush */
2518 +       ssb_read32(dev, SSB_TMSLOW);
2519 +       udelay(1);
2520 +}
2521 +EXPORT_SYMBOL(ssb_device_disable);
2522 +
2523 +int __ssb_printk(const char *fmt, ...)
2524 +{
2525 +       va_list args;
2526 +       int res;
2527 +
2528 +       va_start(args, fmt);
2529 +#ifdef CONFIG_CFE
2530 +       if (is_early_boot() && cfe_present()) {
2531 +               res = cfe_vprintk(fmt, args);
2532 +       } else
2533 +#endif
2534 +       {
2535 +               printk(KERN_INFO);
2536 +               res = vprintk(fmt, args);
2537 +       }
2538 +       va_end(args);
2539 +
2540 +       return res;
2541 +}
2542 +
2543 +
2544 +static int ssb_modinit(void)
2545 +{
2546 +       int err;
2547 +
2548 +       ssb_bustype.name = "ssb";
2549 +       err = bus_register(&ssb_bustype);
2550 +       if (err)
2551 +               return err;
2552 +
2553 +       /* Maybe we already registered some buses at early boot.
2554 +        * Check for this and attach them
2555 +        */
2556 +       ssb_buses_lock();
2557 +       err = ssb_attach_queued_buses();
2558 +       ssb_buses_unlock();
2559 +
2560 +       return err;
2561 +}
2562 +subsys_initcall(ssb_modinit);
2563 +
2564 +static void __exit ssb_modexit(void)
2565 +{
2566 +       bus_unregister(&ssb_bustype);
2567 +}
2568 +module_exit(ssb_modexit)
2569 diff -urN linux.old/drivers/ssb/driver_chipcommon/chipcommon.c linux.dev/drivers/ssb/driver_chipcommon/chipcommon.c
2570 --- linux.old/drivers/ssb/driver_chipcommon/chipcommon.c        1970-01-01 01:00:00.000000000 +0100
2571 +++ linux.dev/drivers/ssb/driver_chipcommon/chipcommon.c        2007-01-03 02:29:17.000000000 +0100
2572 @@ -0,0 +1,384 @@
2573 +#include <linux/ssb.h>
2574 +#include <linux/ssb_regs.h>
2575 +#include <linux/pci.h>
2576 +
2577 +#include "../ssb_private.h"
2578 +
2579 +
2580 +/* Clock sources */
2581 +enum {
2582 +       /* PCI clock */
2583 +       SSB_CHIPCO_CLKSRC_PCI,
2584 +       /* Crystal slow clock oscillator */
2585 +       SSB_CHIPCO_CLKSRC_XTALOS,
2586 +       /* Low power oscillator */
2587 +       SSB_CHIPCO_CLKSRC_LOPWROS,
2588 +};
2589 +
2590 +
2591 +static inline u32 chipco_read32(struct ssb_chipcommon *cc,
2592 +                               u16 offset)
2593 +{
2594 +       return ssb_read32(cc->dev, offset);
2595 +}
2596 +
2597 +static inline void chipco_write32(struct ssb_chipcommon *cc,
2598 +                                 u16 offset,
2599 +                                 u32 value)
2600 +{
2601 +       ssb_write32(cc->dev, offset, value);
2602 +}
2603 +
2604 +void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
2605 +                             enum ssb_clkmode mode)
2606 +{
2607 +       struct ssb_device *ccdev = cc->dev;
2608 +       struct ssb_bus *bus;
2609 +       u32 tmp;
2610 +
2611 +       if (!ccdev)
2612 +               return;
2613 +       bus = ccdev->bus;
2614 +       /* chipcommon cores prior to rev6 don't support dynamic clock control */
2615 +       if (ccdev->id.revision < 6)
2616 +               return;
2617 +       /* chipcommon cores rev10 are a whole new ball game */
2618 +       if (ccdev->id.revision >= 10)
2619 +               return;
2620 +       if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
2621 +               return;
2622 +
2623 +       switch (mode) {
2624 +       case SSB_CLKMODE_SLOW:
2625 +               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
2626 +               tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
2627 +               chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
2628 +               break;
2629 +       case SSB_CLKMODE_FAST:
2630 +               ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
2631 +               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
2632 +               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
2633 +               tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
2634 +               chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
2635 +               break;
2636 +       case SSB_CLKMODE_DYNAMIC:
2637 +               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
2638 +               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
2639 +               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
2640 +               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
2641 +               if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
2642 +                       tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
2643 +               chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
2644 +
2645 +               /* for dynamic control, we have to release our xtal_pu "force on" */
2646 +               if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
2647 +                       ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
2648 +               break;
2649 +       default:
2650 +               assert(0);
2651 +       }
2652 +}
2653 +EXPORT_SYMBOL(ssb_chipco_set_clockmode);
2654 +
2655 +/* Get the Slow Clock Source */
2656 +static int chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
2657 +{
2658 +       struct ssb_bus *bus = cc->dev->bus;
2659 +       u32 tmp = 0;
2660 +
2661 +       if (cc->dev->id.revision < 6) {
2662 +               if (bus->bustype == SSB_BUSTYPE_SSB /*TODO ||
2663 +                   bus->bustype == SSB_BUSTYPE_PCMCIA*/)
2664 +                       return SSB_CHIPCO_CLKSRC_XTALOS;
2665 +               if (bus->bustype == SSB_BUSTYPE_PCI) {
2666 +                       pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
2667 +                       if (tmp & 0x10)
2668 +                               return SSB_CHIPCO_CLKSRC_PCI;
2669 +                       return SSB_CHIPCO_CLKSRC_XTALOS;
2670 +               }
2671 +       }
2672 +       if (cc->dev->id.revision < 10) {
2673 +               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
2674 +               tmp &= 0x7;
2675 +               if (tmp == 0)
2676 +                       return SSB_CHIPCO_CLKSRC_LOPWROS;
2677 +               if (tmp == 1)
2678 +                       return SSB_CHIPCO_CLKSRC_XTALOS;
2679 +               if (tmp == 2)
2680 +                       return SSB_CHIPCO_CLKSRC_PCI;
2681 +       }
2682 +
2683 +       return SSB_CHIPCO_CLKSRC_XTALOS;
2684 +}
2685 +
2686 +/* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
2687 +static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
2688 +{
2689 +       int limit;
2690 +       int clocksrc;
2691 +       int divisor;
2692 +       u32 tmp;
2693 +
2694 +       clocksrc = chipco_pctl_get_slowclksrc(cc);
2695 +       if (cc->dev->id.revision < 6) {
2696 +               switch (clocksrc) {
2697 +               case SSB_CHIPCO_CLKSRC_PCI:
2698 +                       divisor = 64;
2699 +                       break;
2700 +               case SSB_CHIPCO_CLKSRC_XTALOS:
2701 +                       divisor = 32;
2702 +                       break;
2703 +               default:
2704 +                       assert(0);
2705 +                       divisor = 1;
2706 +               }
2707 +       } else if (cc->dev->id.revision < 10) {
2708 +               switch (clocksrc) {
2709 +               case SSB_CHIPCO_CLKSRC_LOPWROS:
2710 +                       divisor = 1;
2711 +                       break;
2712 +               case SSB_CHIPCO_CLKSRC_XTALOS:
2713 +               case SSB_CHIPCO_CLKSRC_PCI:
2714 +                       tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
2715 +                       divisor = (tmp >> 16) + 1;
2716 +                       divisor *= 4;
2717 +                       break;
2718 +               default:
2719 +                       assert(0);
2720 +                       divisor = 1;
2721 +               }
2722 +       } else {
2723 +               tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
2724 +               divisor = (tmp >> 16) + 1;
2725 +               divisor *= 4;
2726 +       }
2727 +
2728 +       switch (clocksrc) {
2729 +       case SSB_CHIPCO_CLKSRC_LOPWROS:
2730 +               if (get_max)
2731 +                       limit = 43000;
2732 +               else
2733 +                       limit = 25000;
2734 +               break;
2735 +       case SSB_CHIPCO_CLKSRC_XTALOS:
2736 +               if (get_max)
2737 +                       limit = 20200000;
2738 +               else
2739 +                       limit = 19800000;
2740 +               break;
2741 +       case SSB_CHIPCO_CLKSRC_PCI:
2742 +               if (get_max)
2743 +                       limit = 34000000;
2744 +               else
2745 +                       limit = 25000000;
2746 +               break;
2747 +       default:
2748 +               assert(0);
2749 +               limit = 0;
2750 +       }
2751 +       limit /= divisor;
2752 +
2753 +       return limit;
2754 +}
2755 +
2756 +static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
2757 +{
2758 +       struct ssb_bus *bus = cc->dev->bus;
2759 +
2760 +       if (bus->chip_id == 0x4321) {
2761 +               if (bus->chip_rev == 0)
2762 +                       chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
2763 +               else if (bus->chip_rev == 1)
2764 +                       chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
2765 +       }
2766 +
2767 +       if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
2768 +               return;
2769 +
2770 +       if (cc->dev->id.revision >= 10) {
2771 +               /* Set Idle Power clock rate to 1Mhz */
2772 +               chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
2773 +                              (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
2774 +                               0x0000FFFF) | 0x00040000);
2775 +       } else {
2776 +               int maxfreq;
2777 +
2778 +               maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
2779 +               chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
2780 +                              (maxfreq * 150 + 999999) / 1000000);
2781 +               chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
2782 +                              (maxfreq * 15 + 999999) / 1000000);
2783 +       }
2784 +}
2785 +
2786 +static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
2787 +{
2788 +       struct ssb_bus *bus = cc->dev->bus;
2789 +       int minfreq;
2790 +       unsigned int tmp;
2791 +       u32 pll_on_delay;
2792 +
2793 +       if (bus->bustype != SSB_BUSTYPE_PCI)
2794 +               return;
2795 +       if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
2796 +               return;
2797 +
2798 +       minfreq = chipco_pctl_clockfreqlimit(cc, 0);
2799 +       pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
2800 +       tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
2801 +       assert((tmp & ~0xFFFF) == 0);
2802 +
2803 +       cc->fast_pwrup_delay = tmp;
2804 +}
2805 +
2806 +void ssb_chipcommon_init(struct ssb_chipcommon *cc)
2807 +{
2808 +       if (!cc->dev)
2809 +               return; /* We don't have a ChipCommon */
2810 +       ssb_dprintk("Initializing Chipcommon...\n");
2811 +       ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
2812 +       chipco_powercontrol_init(cc);
2813 +       calc_fast_powerup_delay(cc);
2814 +}
2815 +
2816 +void ssb_chipcommon_exit(struct ssb_chipcommon *cc)
2817 +{
2818 +       //TODO
2819 +}
2820 +
2821 +void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
2822 +                                u32 *plltype, u32 *n, u32 *m)
2823 +{
2824 +       *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
2825 +       *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
2826 +       switch (*plltype) {
2827 +       case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
2828 +               *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
2829 +               break;
2830 +       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
2831 +               if (cc->dev->bus->chip_id != 0x5365) {
2832 +                       *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
2833 +                       break;
2834 +               }
2835 +               /* Fallthough */
2836 +       default:
2837 +               *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
2838 +       }
2839 +}
2840 +
2841 +void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
2842 +                           unsigned long ns)
2843 +{
2844 +       struct ssb_device *dev = cc->dev;
2845 +       struct ssb_bus *bus = dev->bus;
2846 +       u32 tmp;
2847 +
2848 +       /* set register for external IO to control LED. */
2849 +       chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
2850 +       tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;         /* Waitcount-3 = 10ns */
2851 +       tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT;        /* Waitcount-1 = 40ns */
2852 +       tmp |= ceildiv(240, ns);                                /* Waitcount-0 = 240ns */
2853 +       chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);       /* 0x01020a0c for a 100Mhz clock */
2854 +
2855 +       /* Set timing for the flash */
2856 +       tmp = ceildiv(10, ns) << SSB_FLASH_WCNT_3_SHIFT;        /* Waitcount-3 = 10nS */
2857 +       tmp |= ceildiv(10, ns) << SSB_FLASH_WCNT_1_SHIFT;       /* Waitcount-1 = 10nS */
2858 +       tmp |= ceildiv(120, ns);                                /* Waitcount-0 = 120nS */
2859 +       if ((bus->chip_id == 0x5365) ||
2860 +           (dev->id.revision < 9))
2861 +               chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
2862 +       if ((bus->chip_id == 0x5365) ||
2863 +           (dev->id.revision < 9) ||
2864 +           ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
2865 +               chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
2866 +
2867 +       if (bus->chip_id == 0x5350) {
2868 +               /* Enable EXTIF */
2869 +               tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;   /* Waitcount-3 = 10ns */
2870 +               tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT;  /* Waitcount-2 = 20ns */
2871 +               tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
2872 +               tmp |= ceildiv(120, ns);                          /* Waitcount-0 = 120ns */
2873 +               chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
2874 +       }
2875 +}
2876 +
2877 +
2878 +#ifdef CONFIG_SSB_SERIAL
2879 +int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
2880 +                          struct ssb_serial_port *ports)
2881 +{
2882 +       struct ssb_bus *bus = cc->dev->bus;
2883 +       int nr_ports = 0;
2884 +       u32 plltype;
2885 +       unsigned int irq;
2886 +       u32 baud_base, div;
2887 +       u32 i, n;
2888 +
2889 +       plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
2890 +       irq = ssb_mips_irq(cc->dev);
2891 +
2892 +       if (plltype == SSB_PLLTYPE_1) {
2893 +               /* PLL clock */
2894 +               baud_base = ssb_calc_clock_rate(plltype,
2895 +                                               chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
2896 +                                               chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
2897 +               div = 1;
2898 +       } else {
2899 +               if (cc->dev->id.revision >= 11) {
2900 +                       /* Fixed ALP clock */
2901 +                       baud_base = 20000000;
2902 +                       div = 1;
2903 +                       /* Set the override bit so we don't divide it */
2904 +                       chipco_write32(cc, SSB_CHIPCO_CORECTL,
2905 +                                      SSB_CHIPCO_CORECTL_UARTCLK0);
2906 +               } else if (cc->dev->id.revision >= 3) {
2907 +                       /* Internal backplane clock */
2908 +                       baud_base = ssb_clockspeed(bus);
2909 +                       div = 2; /* Minimum divisor */
2910 +                       chipco_write32(cc, SSB_CHIPCO_CLKDIV,
2911 +                                      (chipco_read32(cc, SSB_CHIPCO_CLKDIV)
2912 +                                       & ~SSB_CHIPCO_CLKDIV_UART) | div);
2913 +               } else {
2914 +                       /* Fixed internal backplane clock */
2915 +                       baud_base = 88000000;
2916 +                       div = 48;
2917 +               }
2918 +
2919 +               /* Clock source depends on strapping if UartClkOverride is unset */
2920 +               if ((cc->dev->id.revision > 0) &&
2921 +                   !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
2922 +                       if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
2923 +                           SSB_CHIPCO_CAP_UARTCLK_INT) {
2924 +                               /* Internal divided backplane clock */
2925 +                               baud_base /= div;
2926 +                       } else {
2927 +                               /* Assume external clock of 1.8432 MHz */
2928 +                               baud_base = 1843200;
2929 +                       }
2930 +               }
2931 +       }
2932 +
2933 +       /* Determine the registers of the UARTs */
2934 +       n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
2935 +       for (i = 0; i < n; i++) {
2936 +               void __iomem *cc_mmio;
2937 +               void __iomem *uart_regs;
2938 +
2939 +               cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
2940 +               uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
2941 +               /* Offset changed at after rev 0 */
2942 +               if (cc->dev->id.revision == 0)
2943 +                       uart_regs += (i * 8);
2944 +               else
2945 +                       uart_regs += (i * 256);
2946 +
2947 +               nr_ports++;
2948 +               ports[i].regs = uart_regs;
2949 +               ports[i].irq = irq;
2950 +               ports[i].baud_base = baud_base;
2951 +               ports[i].reg_shift = 0;
2952 +       }
2953 +
2954 +       return nr_ports;
2955 +}
2956 +#endif /* CONFIG_SSB_SERIAL */
2957 diff -urN linux.old/drivers/ssb/driver_chipcommon/Makefile linux.dev/drivers/ssb/driver_chipcommon/Makefile
2958 --- linux.old/drivers/ssb/driver_chipcommon/Makefile    1970-01-01 01:00:00.000000000 +0100
2959 +++ linux.dev/drivers/ssb/driver_chipcommon/Makefile    2007-01-03 02:26:02.000000000 +0100
2960 @@ -0,0 +1 @@
2961 +obj-y += chipcommon.o
2962 diff -urN linux.old/drivers/ssb/driver_mips/Makefile linux.dev/drivers/ssb/driver_mips/Makefile
2963 --- linux.old/drivers/ssb/driver_mips/Makefile  1970-01-01 01:00:00.000000000 +0100
2964 +++ linux.dev/drivers/ssb/driver_mips/Makefile  2007-01-03 02:26:02.000000000 +0100
2965 @@ -0,0 +1 @@
2966 +obj-y += mips.o
2967 diff -urN linux.old/drivers/ssb/driver_mips/mips.c linux.dev/drivers/ssb/driver_mips/mips.c
2968 --- linux.old/drivers/ssb/driver_mips/mips.c    1970-01-01 01:00:00.000000000 +0100
2969 +++ linux.dev/drivers/ssb/driver_mips/mips.c    2007-01-03 02:29:17.000000000 +0100
2970 @@ -0,0 +1,246 @@
2971 +#include <linux/ssb.h>
2972 +
2973 +#include <linux/serial.h>
2974 +#include <linux/serial_core.h>
2975 +#include <linux/serial_reg.h>
2976 +#include <asm/time.h>
2977 +
2978 +#include "../ssb_private.h"
2979 +
2980 +
2981 +static inline u32 mips_read32(struct ssb_mipscore *mcore,
2982 +                             u16 offset)
2983 +{
2984 +       return ssb_read32(mcore->dev, offset);
2985 +}
2986 +
2987 +static inline void mips_write32(struct ssb_mipscore *mcore,
2988 +                               u16 offset,
2989 +                               u32 value)
2990 +{
2991 +       ssb_write32(mcore->dev, offset, value);
2992 +}
2993 +
2994 +static const u32 ipsflag_irq_mask[] = {
2995 +       0,
2996 +       SSB_IPSFLAG_IRQ1,
2997 +       SSB_IPSFLAG_IRQ2,
2998 +       SSB_IPSFLAG_IRQ3,
2999 +       SSB_IPSFLAG_IRQ4,
3000 +};
3001 +
3002 +static const u32 ipsflag_irq_shift[] = {
3003 +       0,
3004 +       SSB_IPSFLAG_IRQ1_SHIFT,
3005 +       SSB_IPSFLAG_IRQ2_SHIFT,
3006 +       SSB_IPSFLAG_IRQ3_SHIFT,
3007 +       SSB_IPSFLAG_IRQ4_SHIFT,
3008 +};
3009 +
3010 +static inline u32 ssb_irqflag(struct ssb_device *dev)
3011 +{
3012 +       return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
3013 +}
3014 +
3015 +/* Get the MIPS IRQ assignment for a specified device.
3016 + * If unassigned, 0 is returned.
3017 + */
3018 +unsigned int ssb_mips_irq(struct ssb_device *dev)
3019 +{
3020 +       struct ssb_bus *bus = dev->bus;
3021 +       u32 irqflag;
3022 +       u32 ipsflag;
3023 +       u32 tmp;
3024 +       unsigned int irq;
3025 +
3026 +       irqflag = ssb_irqflag(dev);
3027 +       ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
3028 +       for (irq = 1; irq <= 4; irq++) {
3029 +               tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
3030 +               if (tmp == irqflag)
3031 +                       break;
3032 +       }
3033 +       if (irq == 5)
3034 +               irq = 0;
3035 +
3036 +       return irq;
3037 +}
3038 +
3039 +static void clear_irq(struct ssb_bus *bus, unsigned int irq)
3040 +{
3041 +       struct ssb_device *dev = bus->mipscore.dev;
3042 +
3043 +       /* Clear the IRQ in the MIPScore backplane registers */
3044 +       if (irq == 0) {
3045 +               ssb_write32(dev, SSB_INTVEC, 0);
3046 +       } else {
3047 +               ssb_write32(dev, SSB_IPSFLAG,
3048 +                           ssb_read32(dev, SSB_IPSFLAG) |
3049 +                           ipsflag_irq_mask[irq]);
3050 +       }
3051 +}
3052 +
3053 +static void set_irq(struct ssb_device *dev, unsigned int irq)
3054 +{
3055 +       unsigned int oldirq = ssb_mips_irq(dev);
3056 +       struct ssb_bus *bus = dev->bus;
3057 +       struct ssb_device *mdev = bus->mipscore.dev;
3058 +       u32 irqflag = ssb_irqflag(dev);
3059 +
3060 +       dev->irq = irq + 2;
3061 +
3062 +       ssb_dprintk("set_irq: core 0x%04x, irq %d => %d\n", dev->id.coreid, oldirq, irq);
3063 +       /* clear the old irq */
3064 +       if (oldirq == 0)
3065 +               ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
3066 +       else
3067 +               clear_irq(bus, oldirq);
3068 +
3069 +       /* assign the new one */
3070 +       if (irq == 0)
3071 +               ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
3072 +
3073 +       irqflag <<= ipsflag_irq_shift[irq];
3074 +       irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
3075 +       ssb_write32(mdev, SSB_IPSFLAG, irqflag);
3076 +}
3077 +
3078 +/* XXX: leave here or move into separate extif driver? */
3079 +static int ssb_extif_serial_init(struct ssb_device *dev, struct ssb_serial_ports *ports)
3080 +{
3081 +
3082 +}
3083 +
3084 +
3085 +static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
3086 +{
3087 +       struct ssb_bus *bus = mcore->dev->bus;
3088 +
3089 +       //TODO if (EXTIF available
3090 +#if 0
3091 +               extifregs_t *eir = (extifregs_t *) regs;
3092 +               sbconfig_t *sb;
3093 +
3094 +               /* Determine external UART register base */
3095 +               sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
3096 +               base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
3097 +
3098 +               /* Determine IRQ */
3099 +               irq = sb_irq(sbh);
3100 +
3101 +               /* Disable GPIO interrupt initially */
3102 +               W_REG(&eir->gpiointpolarity, 0);
3103 +               W_REG(&eir->gpiointmask, 0);
3104 +
3105 +               /* Search for external UARTs */
3106 +               n = 2;
3107 +               for (i = 0; i < 2; i++) {
3108 +                       regs = (void *) REG_MAP(base + (i * 8), 8);
3109 +                       if (BCMINIT(serial_exists)(regs)) {
3110 +                               /* Set GPIO 1 to be the external UART IRQ */
3111 +                               W_REG(&eir->gpiointmask, 2);
3112 +                               if (add)
3113 +                                       add(regs, irq, 13500000, 0);
3114 +                       }
3115 +               }
3116 +
3117 +               /* Add internal UART if enabled */
3118 +               if (R_REG(&eir->corecontrol) & CC_UE)
3119 +                       if (add)
3120 +                               add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
3121 +
3122 +#endif
3123 +       if (bus->extif.dev)
3124 +               mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
3125 +       else if (bus->chipco.dev)
3126 +               mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
3127 +       else
3128 +               mcore->nr_serial_ports = 0;
3129 +}
3130 +
3131 +static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
3132 +{
3133 +       struct ssb_bus *bus = mcore->dev->bus;
3134 +
3135 +       if (bus->chipco.dev) {
3136 +               mcore->flash_window = 0x1c000000;
3137 +               mcore->flash_window_size = 0x800000;
3138 +       } else {
3139 +               mcore->flash_window = 0x1fc00000;
3140 +               mcore->flash_window_size = 0x400000;
3141 +       }
3142 +}
3143 +
3144 +
3145 +static void ssb_cpu_clock(struct ssb_mipscore *mcore)
3146 +{
3147 +}
3148 +
3149 +void ssb_mipscore_init(struct ssb_mipscore *mcore)
3150 +{
3151 +       struct ssb_bus *bus = mcore->dev->bus;
3152 +       struct ssb_device *dev;
3153 +       unsigned long hz, ns;
3154 +       unsigned int irq, i;
3155 +
3156 +       if (!mcore->dev)
3157 +               return; /* We don't have a MIPS core */
3158 +
3159 +       ssb_dprintk("Initializing MIPS core...\n");
3160 +
3161 +       hz = ssb_clockspeed(bus);
3162 +       if (!hz)
3163 +               hz = 100000000;
3164 +       ns = 1000000000 / hz;
3165 +
3166 +//TODO
3167 +#if 0
3168 +       if (have EXTIF) {
3169 +               /* Initialize extif so we can get to the LEDs and external UART */
3170 +               W_REG(&eir->prog_config, CF_EN);
3171 +
3172 +               /* Set timing for the flash */
3173 +               tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
3174 +               tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
3175 +               tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
3176 +               W_REG(&eir->prog_waitcount, tmp);       /* 0x01020a0c for a 100Mhz clock */
3177 +
3178 +               /* Set programmable interface timing for external uart */
3179 +               tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
3180 +               tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
3181 +               tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
3182 +               tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
3183 +               W_REG(&eir->prog_waitcount, tmp);
3184 +       }
3185 +       else... chipcommon
3186 +#endif
3187 +       if (bus->chipco.dev)
3188 +               ssb_chipco_timing_init(&bus->chipco, ns);
3189 +
3190 +       /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
3191 +       for (irq = 2, i = 0; i < bus->nr_devices; i++) {
3192 +               dev = &(bus->devices[i]);
3193 +               dev->irq = ssb_mips_irq(dev) + 2;
3194 +               switch(dev->id.coreid) {
3195 +                       case SSB_DEV_USB11_HOST:
3196 +                               /* shouldn't need a separate irq line for non-4710, most of them have a proper
3197 +                                * external usb controller on the pci */
3198 +                               if ((bus->chip_id == 0x4710) && (irq <= 4)) {
3199 +                                       set_irq(dev, irq++);
3200 +                                       break;
3201 +                               }
3202 +                       case SSB_DEV_PCI:
3203 +                       case SSB_DEV_ETHERNET:
3204 +                       case SSB_DEV_80211:
3205 +                       case SSB_DEV_USB20_HOST:
3206 +                               /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
3207 +                               if (irq <= 4) {
3208 +                                       set_irq(dev, irq++);
3209 +                                       break;
3210 +                               }
3211 +               }
3212 +       }
3213 +
3214 +       ssb_mips_serial_init(mcore);
3215 +       ssb_mips_flash_detect(mcore);
3216 +}
3217 diff -urN linux.old/drivers/ssb/Kconfig linux.dev/drivers/ssb/Kconfig
3218 --- linux.old/drivers/ssb/Kconfig       1970-01-01 01:00:00.000000000 +0100
3219 +++ linux.dev/drivers/ssb/Kconfig       2007-01-03 02:26:02.000000000 +0100
3220 @@ -0,0 +1,59 @@
3221 +menu "Sonics Silicon Backplane"
3222 +
3223 +config SSB
3224 +       tristate "Sonics Silicon Backplane support"
3225 +       depends on PCI
3226 +       help
3227 +         Support for the Sonics Silicon Backplane bus
3228 +
3229 +         The module will be called ssb
3230 +
3231 +         If unsure, say m
3232 +
3233 +config SSB_SILENT
3234 +       bool "No SSB kernel messages"
3235 +       depends on SSB
3236 +       help
3237 +         This option turns off all Sonics Silicon Backplane printks.
3238 +         Note that you won't be able to identify problems, once
3239 +         messages are turned off.
3240 +         This might only be desired for production kernels on
3241 +         embedded devices.
3242 +
3243 +         Say n
3244 +
3245 +config SSB_DEBUG
3246 +       bool "SSB debugging"
3247 +       depends on SSB && !SSB_SILENT
3248 +       # TODO: Default y for now, but change to n later
3249 +       default y
3250 +       help
3251 +         This turns on additional runtime checks and debugging
3252 +         messages. Turn this on for SSB troubleshooting.
3253 +
3254 +         If unsure, say n
3255 +
3256 +config SSB_SERIAL
3257 +       bool
3258 +       depends on SSB
3259 +       # ChipCommon and ExtIf serial support routines.
3260 +
3261 +config SSB_DRIVER_EXTIF
3262 +       bool "SSB Broadcom EXTIF core driver"
3263 +       help
3264 +         Driver for the Sonics Silicon Backplane attached
3265 +         Broadcom EXTIF core
3266 +
3267 +         If unsure, say n
3268 +
3269 +config SSB_DRIVER_MIPS
3270 +       bool "SSB Broadcom MIPS core driver"
3271 +       depends on SSB
3272 +       select SSB_SERIAL
3273 +       help
3274 +         Driver for the Sonics Silicon Backplane attached
3275 +         Broadcom MIPS core
3276 +
3277 +         If unsure, say n
3278 +
3279 +endmenu
3280 diff -urN linux.old/drivers/ssb/Makefile linux.dev/drivers/ssb/Makefile
3281 --- linux.old/drivers/ssb/Makefile      1970-01-01 01:00:00.000000000 +0100
3282 +++ linux.dev/drivers/ssb/Makefile      2007-01-03 02:40:36.000000000 +0100
3283 @@ -0,0 +1,8 @@
3284 +ssb-driver-chipcommon-y                                := driver_chipcommon/chipcommon.o
3285 +ssb-driver-mips-$(CONFIG_SSB_DRIVER_MIPS)      := driver_mips/mips.o
3286 +
3287 +obj-$(CONFIG_SSB) += ssb.o
3288 +
3289 +ssb-objs       := core.o pci.o scan.o \
3290 +                  $(ssb-driver-chipcommon-y) \
3291 +                  $(ssb-driver-mips-y)
3292 diff -urN linux.old/drivers/ssb/pci.c linux.dev/drivers/ssb/pci.c
3293 --- linux.old/drivers/ssb/pci.c 1970-01-01 01:00:00.000000000 +0100
3294 +++ linux.dev/drivers/ssb/pci.c 2007-01-03 02:29:17.000000000 +0100
3295 @@ -0,0 +1,417 @@
3296 +/*
3297 + * Sonics Silicon Backplane PCI-Hostbus related functions.
3298 + *
3299 + * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
3300 + * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
3301 + * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
3302 + * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
3303 + * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
3304 + *
3305 + * Derived from the Broadcom 4400 device driver.
3306 + * Copyright (C) 2002 David S. Miller (davem@redhat.com)
3307 + * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
3308 + * Copyright (C) 2006 Broadcom Corporation.
3309 + *
3310 + * Licensed under the GNU/GPL. See COPYING for details.
3311 + */
3312 +
3313 +#include <linux/ssb.h>
3314 +#include <linux/ssb_regs.h>
3315 +#include <linux/pci.h>
3316 +#include <linux/delay.h>
3317 +
3318 +#include "ssb_private.h"
3319 +
3320 +
3321 +int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
3322 +{
3323 +       int err;
3324 +       int attempts = 0;
3325 +       u32 cur_core;
3326 +
3327 +       while (1) {
3328 +               err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
3329 +                                            (coreidx * SSB_CORE_SIZE)
3330 +                                            + SSB_ENUM_BASE);
3331 +               if (err)
3332 +                       goto error;
3333 +               err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
3334 +                                           &cur_core);
3335 +               if (err)
3336 +                       goto error;
3337 +               cur_core = (cur_core - SSB_ENUM_BASE)
3338 +                          / SSB_CORE_SIZE;
3339 +               if (cur_core == coreidx)
3340 +                       break;
3341 +
3342 +               if (attempts++ > SSB_BAR0_MAX_RETRIES)
3343 +                       goto error;
3344 +               udelay(10);
3345 +       }
3346 +       return 0;
3347 +error:
3348 +       printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
3349 +       return -ENODEV;
3350 +}
3351 +
3352 +int ssb_pci_switch_core(struct ssb_bus *bus,
3353 +                       struct ssb_device *dev)
3354 +{
3355 +       int err;
3356 +       unsigned long flags;
3357 +
3358 +       ssb_dprintk("Switching to core %d\n",
3359 +                   dev->core_index);
3360 +
3361 +       spin_lock_irqsave(&bus->bar_lock, flags);
3362 +       err = ssb_pci_switch_coreidx(bus, dev->core_index);
3363 +       if (!err)
3364 +               bus->mapped_device = dev;
3365 +       spin_unlock_irqrestore(&bus->bar_lock, flags);
3366 +
3367 +       return err;
3368 +}
3369 +
3370 +int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
3371 +{
3372 +       int err;
3373 +       u32 in, out, outenable;
3374 +       u16 pci_status;
3375 +
3376 +       if (bus->bustype != SSB_BUSTYPE_PCI)
3377 +               return 0;
3378 +
3379 +       err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
3380 +       if (err)
3381 +               goto err_pci;
3382 +       err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
3383 +       if (err)
3384 +               goto err_pci;
3385 +       err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
3386 +       if (err)
3387 +               goto err_pci;
3388 +
3389 +       outenable |= what;
3390 +
3391 +       if (turn_on) {
3392 +               /* Avoid glitching the clock if GPRS is already using it.
3393 +                * We can't actually read the state of the PLLPD so we infer it
3394 +                * by the value of XTAL_PU which *is* readable via gpioin.
3395 +                */
3396 +               if (!(in & SSB_GPIO_XTAL)) {
3397 +                       if (what & SSB_GPIO_XTAL) {
3398 +                               /* Turn the crystal on */
3399 +                               out |= SSB_GPIO_XTAL;
3400 +                               if (what & SSB_GPIO_PLL)
3401 +                                       out |= SSB_GPIO_PLL;
3402 +                               err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
3403 +                               if (err)
3404 +                                       goto err_pci;
3405 +                               err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
3406 +                                                            outenable);
3407 +                               if (err)
3408 +                                       goto err_pci;
3409 +                               msleep(1);
3410 +                       }
3411 +                       if (what & SSB_GPIO_PLL) {
3412 +                               /* Turn the PLL on */
3413 +                               out &= ~SSB_GPIO_PLL;
3414 +                               err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
3415 +                               if (err)
3416 +                                       goto err_pci;
3417 +                               msleep(2);
3418 +                       }
3419 +               }
3420 +
3421 +               err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
3422 +               if (err)
3423 +                       goto err_pci;
3424 +               pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
3425 +               err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
3426 +               if (err)
3427 +                       goto err_pci;
3428 +       } else {
3429 +               if (what & SSB_GPIO_XTAL) {
3430 +                       /* Turn the crystal off */
3431 +                       out &= ~SSB_GPIO_XTAL;
3432 +               }
3433 +               if (what & SSB_GPIO_PLL) {
3434 +                       /* Turn the PLL off */
3435 +                       out |= SSB_GPIO_PLL;
3436 +               }
3437 +               err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
3438 +               if (err)
3439 +                       goto err_pci;
3440 +               err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
3441 +               if (err)
3442 +                       goto err_pci;
3443 +       }
3444 +
3445 +out:
3446 +       return err;
3447 +
3448 +err_pci:
3449 +       printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n");
3450 +       err = -EBUSY;
3451 +       goto out;
3452 +}
3453 +
3454 +#define SPOFF(offset)  (((offset) - SSB_SPROM_BASE) / sizeof(u16))
3455 +#define SPEX(_outvar, _offset, _mask, _shift)  \
3456 +       out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
3457 +
3458 +static inline u8 ssb_crc8(u8 crc, u8 data)
3459 +{
3460 +       /* Polynomial:   x^8 + x^7 + x^6 + x^4 + x^2 + 1   */
3461 +       static const u8 t[] = {
3462 +               0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
3463 +               0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
3464 +               0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
3465 +               0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
3466 +               0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
3467 +               0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
3468 +               0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
3469 +               0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
3470 +               0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
3471 +               0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
3472 +               0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
3473 +               0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
3474 +               0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
3475 +               0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
3476 +               0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
3477 +               0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
3478 +               0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
3479 +               0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
3480 +               0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
3481 +               0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
3482 +               0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
3483 +               0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
3484 +               0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
3485 +               0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
3486 +               0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
3487 +               0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
3488 +               0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
3489 +               0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
3490 +               0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
3491 +               0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
3492 +               0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
3493 +               0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
3494 +       };
3495 +       return t[crc ^ data];
3496 +}
3497 +
3498 +static u8 ssb_sprom_crc(const u16 *sprom)
3499 +{
3500 +       int word;
3501 +       u8 crc = 0xFF;
3502 +
3503 +       for (word = 0; word < SSB_SPROMSIZE_WORDS - 1; word++) {
3504 +               crc = ssb_crc8(crc, sprom[word] & 0x00FF);
3505 +               crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
3506 +       }
3507 +       crc = ssb_crc8(crc, sprom[SPOFF(SSB_SPROM_REVISION)] & 0x00FF);
3508 +       crc ^= 0xFF;
3509 +
3510 +       return crc;
3511 +}
3512 +
3513 +static int sprom_check_crc(const u16 *sprom)
3514 +{
3515 +       u8 crc;
3516 +       u8 expected_crc;
3517 +       u16 tmp;
3518 +
3519 +       crc = ssb_sprom_crc(sprom);
3520 +       tmp = sprom[SPOFF(SSB_SPROM_REVISION)] & SSB_SPROM_REVISION_CRC;
3521 +       expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
3522 +       if (crc != expected_crc)
3523 +               return -EPROTO;
3524 +
3525 +       return 0;
3526 +}
3527 +
3528 +static void sprom_do_read(struct ssb_bus *bus, u16 *sprom)
3529 +{
3530 +       int i;
3531 +
3532 +       for (i = 0; i < SSB_SPROMSIZE_WORDS; i++)
3533 +               sprom[i] = ssb_raw_read16(bus, SSB_SPROM_BASE + (i * 2));
3534 +}
3535 +
3536 +static void sprom_extract_r1(struct ssb_sprom_r1 *out, const u16 *in)
3537 +{
3538 +       int i;
3539 +       u16 v;
3540 +
3541 +       SPEX(pci_spid, SSB_SPROM1_SPID, 0xFFFF, 0);
3542 +       SPEX(pci_svid, SSB_SPROM1_SVID, 0xFFFF, 0);
3543 +       SPEX(pci_pid, SSB_SPROM1_PID, 0xFFFF, 0);
3544 +       for (i = 0; i < 3; i++) {
3545 +               v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
3546 +               *(((u16 *)out->il0mac) + i) = cpu_to_be16(v);
3547 +       }
3548 +       for (i = 0; i < 3; i++) {
3549 +               v = in[SPOFF(SSB_SPROM1_ET0MAC) + i];
3550 +               *(((u16 *)out->et0mac) + i) = cpu_to_be16(v);
3551 +       }
3552 +       for (i = 0; i < 3; i++) {
3553 +               v = in[SPOFF(SSB_SPROM1_ET1MAC) + i];
3554 +               *(((u16 *)out->et1mac) + i) = cpu_to_be16(v);
3555 +       }
3556 +       SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
3557 +       SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
3558 +            SSB_SPROM1_ETHPHY_ET1A_SHIFT);
3559 +       SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
3560 +       SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
3561 +       SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
3562 +       SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
3563 +            SSB_SPROM1_BINF_CCODE_SHIFT);
3564 +       SPEX(antenna_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
3565 +            SSB_SPROM1_BINF_ANTA_SHIFT);
3566 +       SPEX(antenna_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
3567 +            SSB_SPROM1_BINF_ANTBG_SHIFT);
3568 +       SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
3569 +       SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
3570 +       SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
3571 +       SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
3572 +       SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
3573 +       SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
3574 +       SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
3575 +       SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
3576 +            SSB_SPROM1_GPIOA_P1_SHIFT);
3577 +       SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
3578 +       SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
3579 +            SSB_SPROM1_GPIOB_P3_SHIFT);
3580 +       SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A, 0);
3581 +       SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG,
3582 +            SSB_SPROM1_MAXPWR_BG_SHIFT);
3583 +       SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A, 0);
3584 +       SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG,
3585 +            SSB_SPROM1_ITSSI_BG_SHIFT);
3586 +       SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
3587 +       SPEX(antenna_gain_a, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_A, 0);
3588 +       SPEX(antenna_gain_bg, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_BG,
3589 +            SSB_SPROM1_AGAIN_BG_SHIFT);
3590 +       for (i = 0; i < 4; i++) {
3591 +               v = in[SPOFF(SSB_SPROM1_OEM) + i];
3592 +               *(((u16 *)out->oem) + i) = cpu_to_le16(v);
3593 +       }
3594 +}
3595 +
3596 +static void sprom_extract_r2(struct ssb_sprom_r2 *out, const u16 *in)
3597 +{
3598 +       int i;
3599 +       u16 v;
3600 +
3601 +       SPEX(boardflags_hi, SSB_SPROM2_BFLHI,  0xFFFF, 0);
3602 +       SPEX(maxpwr_a_hi, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
3603 +       SPEX(maxpwr_a_lo, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
3604 +            SSB_SPROM2_MAXP_A_LO_SHIFT);
3605 +       SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
3606 +       SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
3607 +       SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
3608 +       SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
3609 +       SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
3610 +       SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
3611 +       SPEX(ofdm_pwr_off, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
3612 +       for (i = 0; i < 4; i++) {
3613 +               v = in[SPOFF(SSB_SPROM2_CCODE) + i];
3614 +               *(((u16 *)out->country_str) + i) = cpu_to_le16(v);
3615 +       }
3616 +}
3617 +
3618 +static void sprom_extract_r3(struct ssb_sprom_r3 *out, const u16 *in)
3619 +{
3620 +       out->ofdmapo  = (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0xFF00) >> 8;
3621 +       out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0x00FF) << 8;
3622 +       out->ofdmapo <<= 16;
3623 +       out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0xFF00) >> 8;
3624 +       out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0x00FF) << 8;
3625 +
3626 +       out->ofdmalpo  = (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0xFF00) >> 8;
3627 +       out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0x00FF) << 8;
3628 +       out->ofdmalpo <<= 16;
3629 +       out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0xFF00) >> 8;
3630 +       out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0x00FF) << 8;
3631 +
3632 +       out->ofdmahpo  = (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0xFF00) >> 8;
3633 +       out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0x00FF) << 8;
3634 +       out->ofdmahpo <<= 16;
3635 +       out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0xFF00) >> 8;
3636 +       out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0x00FF) << 8;
3637 +
3638 +       SPEX(gpioldc_on_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_ON,
3639 +            SSB_SPROM3_GPIOLDC_ON_SHIFT);
3640 +       SPEX(gpioldc_off_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_OFF,
3641 +            SSB_SPROM3_GPIOLDC_OFF_SHIFT);
3642 +       SPEX(cckpo_1M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_1M, 0);
3643 +       SPEX(cckpo_2M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_2M,
3644 +            SSB_SPROM3_CCKPO_2M_SHIFT);
3645 +       SPEX(cckpo_55M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_55M,
3646 +            SSB_SPROM3_CCKPO_55M_SHIFT);
3647 +       SPEX(cckpo_11M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_11M,
3648 +            SSB_SPROM3_CCKPO_11M_SHIFT);
3649 +
3650 +       out->ofdmgpo  = (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0xFF00) >> 8;
3651 +       out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0x00FF) << 8;
3652 +       out->ofdmgpo <<= 16;
3653 +       out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0xFF00) >> 8;
3654 +       out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0x00FF) << 8;
3655 +}
3656 +
3657 +static int sprom_extract(struct ssb_sprom *out, const u16 *in)
3658 +{
3659 +       memset(out, 0, sizeof(*out));
3660 +
3661 +       SPEX(revision, SSB_SPROM_REVISION, SSB_SPROM_REVISION_REV, 0);
3662 +       SPEX(crc, SSB_SPROM_REVISION, SSB_SPROM_REVISION_CRC,
3663 +            SSB_SPROM_REVISION_CRC_SHIFT);
3664 +
3665 +       if (out->revision == 0)
3666 +               goto err_unsup;
3667 +       if (out->revision >= 1 && out->revision <= 3)
3668 +               sprom_extract_r1(&out->r1, in);
3669 +       if (out->revision >= 2 && out->revision <= 3)
3670 +               sprom_extract_r2(&out->r2, in);
3671 +       if (out->revision == 3)
3672 +               sprom_extract_r3(&out->r3, in);
3673 +       if (out->revision >= 4)
3674 +               goto err_unsup;
3675 +
3676 +       return 0;
3677 +err_unsup:
3678 +       ssb_printk("ERROR: Unsupported SPROM revision %d\n",
3679 +                  out->revision);
3680 +       return -EOPNOTSUPP;
3681 +}
3682 +
3683 +int ssb_pci_sprom_get(struct ssb_bus *bus)
3684 +{
3685 +       int err = -ENOMEM;
3686 +       u16 *buf;
3687 +
3688 +       assert(bus->bustype == SSB_BUSTYPE_PCI);
3689 +
3690 +       buf = kcalloc(SSB_SPROMSIZE_WORDS, sizeof(u16), GFP_KERNEL);
3691 +       if (!buf)
3692 +               goto out;
3693 +       sprom_do_read(bus, buf);
3694 +       err = sprom_check_crc(buf);
3695 +       if (err)
3696 +               ssb_printk("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
3697 +       err = sprom_extract(&bus->sprom, buf);
3698 +
3699 +       kfree(buf);
3700 +out:
3701 +       return err;
3702 +}
3703 +
3704 +void ssb_pci_get_boardtype(struct ssb_bus *bus)
3705 +{
3706 +       pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
3707 +                            &bus->board_vendor);
3708 +       pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
3709 +                            &bus->board_type);
3710 +       pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
3711 +                            &bus->board_rev);
3712 +}
3713 diff -urN linux.old/drivers/ssb/scan.c linux.dev/drivers/ssb/scan.c
3714 --- linux.old/drivers/ssb/scan.c        1970-01-01 01:00:00.000000000 +0100
3715 +++ linux.dev/drivers/ssb/scan.c        2007-01-03 02:29:17.000000000 +0100
3716 @@ -0,0 +1,296 @@
3717 +#include <linux/ssb.h>
3718 +#include <linux/ssb_regs.h>
3719 +#include <linux/pci.h>
3720 +#include <asm/io.h>
3721 +
3722 +#include "ssb_private.h"
3723 +
3724 +
3725 +static const char * ssb_core_name(u16 coreid)
3726 +{
3727 +       switch (coreid) {
3728 +       case SSB_DEV_CHIPCOMMON:
3729 +               return "ChipCommon";
3730 +       case SSB_DEV_ILINE20:
3731 +               return "ILine 20";
3732 +       case SSB_DEV_SDRAM:
3733 +               return "SDRAM";
3734 +       case SSB_DEV_PCI:
3735 +               return "PCI";
3736 +       case SSB_DEV_MIPS:
3737 +               return "MIPS";
3738 +       case SSB_DEV_ETHERNET:
3739 +               return "Fast Ethernet";
3740 +       case SSB_DEV_V90:
3741 +               return "V90";
3742 +       case SSB_DEV_USB11_HOSTDEV:
3743 +               return "USB 1.1 Hostdev";
3744 +       case SSB_DEV_ADSL:
3745 +               return "ADSL";
3746 +       case SSB_DEV_ILINE100:
3747 +               return "ILine 100";
3748 +       case SSB_DEV_IPSEC:
3749 +               return "IPSEC";
3750 +       case SSB_DEV_PCMCIA:
3751 +               return "PCMCIA";
3752 +       case SSB_DEV_INTERNAL_MEM:
3753 +               return "Internal Memory";
3754 +       case SSB_DEV_MEMC_SDRAM:
3755 +               return "MEMC SDRAM";
3756 +       case SSB_DEV_EXTIF:
3757 +               return "EXTIF";
3758 +       case SSB_DEV_80211:
3759 +               return "IEEE 802.11";
3760 +       case SSB_DEV_MIPS_3302:
3761 +               return "MIPS 3302";
3762 +       case SSB_DEV_USB11_HOST:
3763 +               return "USB 1.1 Host";
3764 +       case SSB_DEV_USB11_DEV:
3765 +               return "USB 1.1 Device";
3766 +       case SSB_DEV_USB20_HOST:
3767 +               return "USB 2.0 Host";
3768 +       case SSB_DEV_USB20_DEV:
3769 +               return "USB 2.0 Device";
3770 +       case SSB_DEV_SDIO_HOST:
3771 +               return "SDIO Host";
3772 +       case SSB_DEV_ROBOSWITCH:
3773 +               return "Roboswitch";
3774 +       case SSB_DEV_PARA_ATA:
3775 +               return "PATA";
3776 +       case SSB_DEV_SATA_XORDMA:
3777 +               return "SATA XOR-DMA";
3778 +       case SSB_DEV_ETHERNET_GBIT:
3779 +               return "GBit Ethernet";
3780 +       case SSB_DEV_PCIE:
3781 +               return "PCI-E";
3782 +       case SSB_DEV_MIMO_PHY:
3783 +               return "MIMO PHY";
3784 +       case SSB_DEV_SRAM_CTRLR:
3785 +               return "SRAM Controller";
3786 +       case SSB_DEV_MINI_MACPHY:
3787 +               return "Mini MACPHY";
3788 +       case SSB_DEV_ARM_1176:
3789 +               return "ARM 1176";
3790 +       case SSB_DEV_ARM_7TDMI:
3791 +               return "ARM 7TDMI";
3792 +       }
3793 +       return "Unknown CoreID";
3794 +}
3795 +
3796 +static u16 pcidev_to_chipid(struct pci_dev *pci_dev)
3797 +{
3798 +       u16 chipid_fallback = 0;
3799 +
3800 +       switch (pci_dev->device) {
3801 +       case 0x4301:
3802 +               chipid_fallback = 0x4301;
3803 +               break;
3804 +       case 0x4305 ... 0x4307:
3805 +               chipid_fallback = 0x4307;
3806 +               break;
3807 +       case 0x4402 ... 0x4403:
3808 +               chipid_fallback = 0x4402;
3809 +               break;
3810 +       case 0x4610 ... 0x4615:
3811 +               chipid_fallback = 0x4610;
3812 +               break;
3813 +       case 0x4710 ... 0x4715:
3814 +               chipid_fallback = 0x4710;
3815 +               break;
3816 +       case 0x4320 ... 0x4325:
3817 +               chipid_fallback = 0x4309;
3818 +               break;
3819 +       default:
3820 +               ssb_printk("PCI-ID not in fallback list\n");
3821 +       }
3822 +
3823 +       return chipid_fallback;
3824 +}
3825 +
3826 +static u8 chipid_to_nrcores(u16 chipid)
3827 +{
3828 +       switch (chipid) {
3829 +       case 0x5365:
3830 +               return 7;
3831 +       case 0x4306:
3832 +               return 6;
3833 +       case 0x4310:
3834 +               return 8;
3835 +       case 0x4307:
3836 +       case 0x4301:
3837 +               return 5;
3838 +       case 0x4402:
3839 +               return 3;
3840 +       case 0x4710:
3841 +       case 0x4610:
3842 +       case 0x4704:
3843 +               return 9;
3844 +       default:
3845 +               ssb_printk("CHIPID not found in nrcores fallback list\n");
3846 +       }
3847 +       return 1;
3848 +}
3849 +
3850 +static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
3851 +                      u16 offset)
3852 +{
3853 +       if (bus->bustype == SSB_BUSTYPE_SSB)
3854 +               offset += current_coreidx * SSB_CORE_SIZE;
3855 +       return ssb_raw_read32(bus, offset);
3856 +}
3857 +
3858 +static int scan_switchcore(struct ssb_bus *bus, u8 coreidx)
3859 +{
3860 +       switch (bus->bustype) {
3861 +       case SSB_BUSTYPE_SSB:
3862 +               break;
3863 +       case SSB_BUSTYPE_PCI:
3864 +               return ssb_pci_switch_coreidx(bus, coreidx);
3865 +       default:
3866 +               assert(0);
3867 +       }
3868 +       return 0;
3869 +}
3870 +
3871 +int ssb_bus_scan(struct ssb_bus *bus,
3872 +                unsigned long baseaddr)
3873 +{
3874 +       int err = -ENOMEM;
3875 +       void __iomem *mmio;
3876 +       u32 idhi, cc, rev, tmp;
3877 +       int i;
3878 +       struct ssb_device *dev;
3879 +
3880 +       if (bus->bustype == SSB_BUSTYPE_SSB) {
3881 +               /* Only map the first core for now. */
3882 +               mmio = ioremap(baseaddr, SSB_CORE_SIZE);
3883 +       } else {
3884 +               assert(bus->host_pci);
3885 +               mmio = pci_iomap(bus->host_pci, 0, ~0UL);
3886 +       }
3887 +       if (!mmio)
3888 +               goto out;
3889 +       bus->mmio = mmio;
3890 +
3891 +       err = scan_switchcore(bus, 0); /* Switch to first core */
3892 +       if (err)
3893 +               goto err_unmap;
3894 +
3895 +       idhi = scan_read32(bus, 0, SSB_IDHIGH);
3896 +       cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
3897 +       rev = (idhi & SSB_IDHIGH_RCLO);
3898 +       rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
3899 +
3900 +       bus->nr_devices = 0;
3901 +       if (cc == SSB_DEV_CHIPCOMMON) {
3902 +               tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID);
3903 +
3904 +               bus->chip_id = (tmp & SSB_CHIPCO_IDMASK);
3905 +               bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >>
3906 +                               SSB_CHIPCO_REVSHIFT;
3907 +               bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >>
3908 +                                   SSB_CHIPCO_PACKSHIFT;
3909 +               if (rev >= 4) {
3910 +                       bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >>
3911 +                                         SSB_CHIPCO_NRCORESSHIFT;
3912 +               }
3913 +               tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP);
3914 +               bus->chipco.capabilities = tmp;
3915 +       } else {
3916 +               if (bus->bustype == SSB_BUSTYPE_SSB) {
3917 +                       bus->chip_id = 0x4710;
3918 +                       bus->chip_rev = 0;
3919 +                       bus->chip_package = 0;
3920 +               } else {
3921 +                       bus->chip_id = pcidev_to_chipid(bus->host_pci);
3922 +                       pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
3923 +                                            &bus->chip_rev);
3924 +                       bus->chip_package = 0;
3925 +               }
3926 +       }
3927 +       if (!bus->nr_devices)
3928 +               bus->nr_devices = chipid_to_nrcores(bus->chip_id);
3929 +       if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
3930 +               ssb_printk("ERR: More than %d ssb cores found (%d)\n",
3931 +                          SSB_MAX_NR_CORES, bus->nr_devices);
3932 +               goto err_unmap;
3933 +       }
3934 +       if (bus->bustype == SSB_BUSTYPE_SSB) {
3935 +               /* Now that we know the number of cores,
3936 +                * remap the whole IO space for all cores.
3937 +                */
3938 +               err = -ENOMEM;
3939 +               iounmap(mmio);
3940 +               mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices);
3941 +               if (!mmio)
3942 +                       goto out;
3943 +               bus->mmio = mmio;
3944 +       }
3945 +
3946 +       /* Fetch basic information about each core/device */
3947 +       for (i = 0; i < bus->nr_devices; i++) {
3948 +               err = scan_switchcore(bus, i);
3949 +               if (err)
3950 +                       goto err_unmap;
3951 +               dev = &(bus->devices[i]);
3952 +
3953 +               idhi = scan_read32(bus, i, SSB_IDHIGH);
3954 +               dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
3955 +               dev->id.revision = (idhi & SSB_IDHIGH_RCLO);
3956 +               dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
3957 +               dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
3958 +               dev->core_index = i;
3959 +               dev->bus = bus;
3960 +               if ((dev->bus->bustype == SSB_BUSTYPE_PCI) && (bus->host_pci))
3961 +                       dev->irq = bus->host_pci->irq;
3962 +
3963 +               ssb_printk("Core %d found: %s "
3964 +                          "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
3965 +                          i, ssb_core_name(dev->id.coreid),
3966 +                          dev->id.coreid, dev->id.revision, dev->id.vendor);
3967 +
3968 +               dev->dev.bus = &ssb_bustype;
3969 +               snprintf(dev->dev.bus_id, sizeof(dev->dev.bus_id),
3970 +                        "ssb%02x:%02x", bus->busnumber, i);
3971 +
3972 +               switch (dev->id.coreid) {
3973 +               case SSB_DEV_EXTIF:
3974 +#ifdef CONFIG_SSB_DRIVER_EXTIF
3975 +                       if (bus->extif.dev) {
3976 +                               ssb_printk("WARNING: Multiple EXTIFs found\n");
3977 +                               break;
3978 +                       }
3979 +                       bus->extif.dev = dev;
3980 +#endif /* CONFIG_SSB_DRIVER_EXTIF */
3981 +                       break;
3982 +               case SSB_DEV_CHIPCOMMON:
3983 +                       if (bus->chipco.dev) {
3984 +                               ssb_printk("WARNING: Multiple Chipcommon found\n");
3985 +                               break;
3986 +                       }
3987 +                       bus->chipco.dev = dev;
3988 +                       break;
3989 +               case SSB_DEV_MIPS:
3990 +               case SSB_DEV_MIPS_3302:
3991 +#ifdef CONFIG_SSB_DRIVER_MIPS
3992 +                       if (bus->mipscore.dev) {
3993 +                               ssb_printk("WARNING: Multiple MIPS cores found\n");
3994 +                               break;
3995 +                       }
3996 +                       bus->mipscore.dev = dev;
3997 +#endif /* CONFIG_SSB_DRIVER_MIPS */
3998 +                       break;
3999 +               default:
4000 +                       break;
4001 +               }
4002 +       }
4003 +       err = 0;
4004 +out:
4005 +       return err;
4006 +err_unmap:
4007 +       if (bus->bustype == SSB_BUSTYPE_SSB)
4008 +               iounmap(mmio);
4009 +       else
4010 +               pci_iounmap(bus->host_pci, mmio);
4011 +       goto out;
4012 +}
4013 diff -urN linux.old/drivers/ssb/sprom.c linux.dev/drivers/ssb/sprom.c
4014 --- linux.old/drivers/ssb/sprom.c       1970-01-01 01:00:00.000000000 +0100
4015 +++ linux.dev/drivers/ssb/sprom.c       2007-01-03 02:26:02.000000000 +0100
4016 @@ -0,0 +1 @@
4017 +
4018 diff -urN linux.old/drivers/ssb/ssb_private.h linux.dev/drivers/ssb/ssb_private.h
4019 --- linux.old/drivers/ssb/ssb_private.h 1970-01-01 01:00:00.000000000 +0100
4020 +++ linux.dev/drivers/ssb/ssb_private.h 2007-01-03 02:29:17.000000000 +0100
4021 @@ -0,0 +1,107 @@
4022 +#ifndef LINUX_SSB_PRIVATE_H_
4023 +#define LINUX_SSB_PRIVATE_H_
4024 +
4025 +#include <linux/ssb.h>
4026 +#include <linux/types.h>
4027 +#include <asm/io.h>
4028 +
4029 +#ifdef CONFIG_CFE
4030 +# include <asm/cfe.h>
4031 +#endif
4032 +
4033 +
4034 +#define PFX    "ssb: "
4035 +
4036 +#ifdef CONFIG_SSB_SILENT
4037 +# define ssb_printk(fmt, x...) do { /* nothing */ } while (0)
4038 +#else
4039 +/* SSB specific printk. If CFE is available, this can be used in early boot.
4040 + * But it does not harm otherwise. It just does not print anything.
4041 + */
4042 +int __ssb_printk(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
4043 +# define ssb_printk(fmt, x...) __ssb_printk(PFX fmt ,##x)
4044 +#endif /* CONFIG_SSB_SILENT */
4045 +
4046 +/* dprintk: Debugging printk; vanishes for non-debug compilation */
4047 +#ifdef CONFIG_SSB_DEBUG
4048 +# define ssb_dprintk(fmt, x...)        ssb_printk(fmt ,##x)
4049 +#else
4050 +# define ssb_dprintk(fmt, x...)        do { /* nothing */ } while (0)
4051 +#endif
4052 +
4053 +/* printkl: Rate limited printk */
4054 +#define ssb_printkl(fmt, x...) do {            \
4055 +       if (printk_ratelimit())                 \
4056 +               ssb_printk(fmt ,##x);           \
4057 +                               } while (0)
4058 +
4059 +/* dprintkl: Rate limited debugging printk */
4060 +#ifdef CONFIG_SSB_DEBUG
4061 +# define ssb_dprintkl                  ssb_printkl
4062 +#else
4063 +# define ssb_dprintkl(fmt, x...)       do { /* nothing */ } while (0)
4064 +#endif
4065 +
4066 +#define assert(cond)   do {                                            \
4067 +       if (unlikely(!(cond))) {                                        \
4068 +               ssb_dprintk(KERN_ERR PFX "BUG: Assertion failed (%s) "  \
4069 +                           "at: %s:%d:%s()\n",                         \
4070 +                           #cond, __FILE__, __LINE__, __func__);       \
4071 +       }                                                               \
4072 +                      } while (0)
4073 +
4074 +
4075 +extern struct bus_type ssb_bustype;
4076 +
4077 +/* pci.c */
4078 +extern int ssb_pci_switch_core(struct ssb_bus *bus,
4079 +                              struct ssb_device *dev);
4080 +extern int ssb_pci_switch_coreidx(struct ssb_bus *bus,
4081 +                                 u8 coreidx);
4082 +extern int ssb_pci_xtal(struct ssb_bus *bus, u32 what,
4083 +                       int turn_on);
4084 +extern int ssb_pci_sprom_get(struct ssb_bus *bus);
4085 +extern void ssb_pci_get_boardtype(struct ssb_bus *bus);
4086 +
4087 +
4088 +/* scan.c */
4089 +extern int ssb_bus_scan(struct ssb_bus *bus,
4090 +                       unsigned long baseaddr);
4091 +
4092 +
4093 +/* core.c */
4094 +extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
4095 +
4096 +static inline
4097 +u16 ssb_raw_read16(struct ssb_bus *bus, u16 offset)
4098 +{
4099 +       return readw(bus->mmio + offset);
4100 +}
4101 +
4102 +static inline
4103 +u32 ssb_raw_read32(struct ssb_bus *bus, u16 offset)
4104 +{
4105 +       return readl(bus->mmio + offset);
4106 +}
4107 +
4108 +static inline
4109 +void ssb_raw_write16(struct ssb_bus *bus, u16 offset, u16 value)
4110 +{
4111 +       writew(value, bus->mmio + offset);
4112 +}
4113 +
4114 +static inline
4115 +void ssb_raw_write32(struct ssb_bus *bus, u16 offset, u32 value)
4116 +{
4117 +       writel(value, bus->mmio + offset);
4118 +}
4119 +
4120 +
4121 +static inline
4122 +unsigned long ceildiv(unsigned long x, unsigned long y)
4123 +{
4124 +       return ((x + (y - 1)) / y);
4125 +}
4126 +
4127 +
4128 +#endif /* LINUX_SSB_PRIVATE_H_ */
4129 diff -urN linux.old/include/asm-mips/asm-offsets.h linux.dev/include/asm-mips/asm-offsets.h
4130 --- linux.old/include/asm-mips/asm-offsets.h    1970-01-01 01:00:00.000000000 +0100
4131 +++ linux.dev/include/asm-mips/asm-offsets.h    2007-01-03 02:26:02.000000000 +0100
4132 @@ -0,0 +1,214 @@
4133 +#ifndef __ASM_OFFSETS_H__
4134 +#define __ASM_OFFSETS_H__
4135 +/*
4136 + * DO NOT MODIFY.
4137 + *
4138 + * This file was generated by Kbuild
4139 + *
4140 + */
4141 +
4142 +/* MIPS pt_regs offsets. */
4143 +#define PT_R0     24
4144 +#define PT_R1     28
4145 +#define PT_R2     32
4146 +#define PT_R3     36
4147 +#define PT_R4     40
4148 +#define PT_R5     44
4149 +#define PT_R6     48
4150 +#define PT_R7     52
4151 +#define PT_R8     56
4152 +#define PT_R9     60
4153 +#define PT_R10    64
4154 +#define PT_R11    68
4155 +#define PT_R12    72
4156 +#define PT_R13    76
4157 +#define PT_R14    80
4158 +#define PT_R15    84
4159 +#define PT_R16    88
4160 +#define PT_R17    92
4161 +#define PT_R18    96
4162 +#define PT_R19    100
4163 +#define PT_R20    104
4164 +#define PT_R21    108
4165 +#define PT_R22    112
4166 +#define PT_R23    116
4167 +#define PT_R24    120
4168 +#define PT_R25    124
4169 +#define PT_R26    128
4170 +#define PT_R27    132
4171 +#define PT_R28    136
4172 +#define PT_R29    140
4173 +#define PT_R30    144
4174 +#define PT_R31    148
4175 +#define PT_LO     160
4176 +#define PT_HI     156
4177 +#define PT_EPC    172
4178 +#define PT_BVADDR 164
4179 +#define PT_STATUS 152
4180 +#define PT_CAUSE  168
4181 +#define PT_SIZE   176
4182 +
4183 +/* MIPS task_struct offsets. */
4184 +#define TASK_STATE         0
4185 +#define TASK_THREAD_INFO   4
4186 +#define TASK_FLAGS         12
4187 +#define TASK_MM            132
4188 +#define TASK_PID           168
4189 +#define TASK_STRUCT_SIZE   1048
4190 +
4191 +/* MIPS thread_info offsets. */
4192 +#define TI_TASK            0
4193 +#define TI_EXEC_DOMAIN     4
4194 +#define TI_FLAGS           8
4195 +#define TI_TP_VALUE       12
4196 +#define TI_CPU             16
4197 +#define TI_PRE_COUNT       20
4198 +#define TI_ADDR_LIMIT      24
4199 +#define TI_RESTART_BLOCK   28
4200 +#define TI_REGS            48
4201 +#define _THREAD_SIZE_ORDER 0x1
4202 +#define _THREAD_SIZE       0x2000
4203 +#define _THREAD_MASK       0x1fff
4204 +
4205 +/* MIPS specific thread_struct offsets. */
4206 +#define THREAD_REG16   432
4207 +#define THREAD_REG17   436
4208 +#define THREAD_REG18   440
4209 +#define THREAD_REG19   444
4210 +#define THREAD_REG20   448
4211 +#define THREAD_REG21   452
4212 +#define THREAD_REG22   456
4213 +#define THREAD_REG23   460
4214 +#define THREAD_REG29   464
4215 +#define THREAD_REG30   468
4216 +#define THREAD_REG31   472
4217 +#define THREAD_STATUS  476
4218 +#define THREAD_FPU     480
4219 +#define THREAD_BVADDR  772
4220 +#define THREAD_BUADDR  776
4221 +#define THREAD_ECODE   780
4222 +#define THREAD_TRAPNO  784
4223 +#define THREAD_MFLAGS  788
4224 +#define THREAD_TRAMP   792
4225 +#define THREAD_OLDCTX  796
4226 +
4227 +#define THREAD_FPR0    480
4228 +#define THREAD_FPR1    488
4229 +#define THREAD_FPR2    496
4230 +#define THREAD_FPR3    504
4231 +#define THREAD_FPR4    512
4232 +#define THREAD_FPR5    520
4233 +#define THREAD_FPR6    528
4234 +#define THREAD_FPR7    536
4235 +#define THREAD_FPR8    544
4236 +#define THREAD_FPR9    552
4237 +#define THREAD_FPR10   560
4238 +#define THREAD_FPR11   568
4239 +#define THREAD_FPR12   576
4240 +#define THREAD_FPR13   584
4241 +#define THREAD_FPR14   592
4242 +#define THREAD_FPR15   600
4243 +#define THREAD_FPR16   608
4244 +#define THREAD_FPR17   616
4245 +#define THREAD_FPR18   624
4246 +#define THREAD_FPR19   632
4247 +#define THREAD_FPR20   640
4248 +#define THREAD_FPR21   648
4249 +#define THREAD_FPR22   656
4250 +#define THREAD_FPR23   664
4251 +#define THREAD_FPR24   672
4252 +#define THREAD_FPR25   680
4253 +#define THREAD_FPR26   688
4254 +#define THREAD_FPR27   696
4255 +#define THREAD_FPR28   704
4256 +#define THREAD_FPR29   712
4257 +#define THREAD_FPR30   720
4258 +#define THREAD_FPR31   728
4259 +#define THREAD_FCR31   736
4260 +
4261 +/* Linux sigcontext offsets. */
4262 +#define SC_REGS       16
4263 +#define SC_FPREGS     272
4264 +#define SC_MDHI       552
4265 +#define SC_MDLO       560
4266 +#define SC_PC         8
4267 +#define SC_STATUS     4
4268 +#define SC_FPC_CSR    532
4269 +#define SC_FPC_EIR    536
4270 +#define SC_HI1        568
4271 +#define SC_LO1        572
4272 +#define SC_HI2        576
4273 +#define SC_LO2        580
4274 +#define SC_HI3        584
4275 +#define SC_LO3        588
4276 +
4277 +/* Linux signal numbers. */
4278 +#define _SIGHUP     0x1
4279 +#define _SIGINT     0x2
4280 +#define _SIGQUIT    0x3
4281 +#define _SIGILL     0x4
4282 +#define _SIGTRAP    0x5
4283 +#define _SIGIOT     0x6
4284 +#define _SIGABRT    0x6
4285 +#define _SIGEMT     0x7
4286 +#define _SIGFPE     0x8
4287 +#define _SIGKILL    0x9
4288 +#define _SIGBUS     0xa
4289 +#define _SIGSEGV    0xb
4290 +#define _SIGSYS     0xc
4291 +#define _SIGPIPE    0xd
4292 +#define _SIGALRM    0xe
4293 +#define _SIGTERM    0xf
4294 +#define _SIGUSR1    0x10
4295 +#define _SIGUSR2    0x11
4296 +#define _SIGCHLD    0x12
4297 +#define _SIGPWR     0x13
4298 +#define _SIGWINCH   0x14
4299 +#define _SIGURG     0x15
4300 +#define _SIGIO      0x16
4301 +#define _SIGSTOP    0x17
4302 +#define _SIGTSTP    0x18
4303 +#define _SIGCONT    0x19
4304 +#define _SIGTTIN    0x1a
4305 +#define _SIGTTOU    0x1b
4306 +#define _SIGVTALRM  0x1c
4307 +#define _SIGPROF    0x1d
4308 +#define _SIGXCPU    0x1e
4309 +#define _SIGXFSZ    0x1f
4310 +
4311 +/* Linux irq_cpustat_t offsets. */
4312 +#define IC_SOFTIRQ_PENDING 0
4313 +#define IC_IRQ_CPUSTAT_T   32
4314 +
4315 +/* Size of struct page  */
4316 +#define STRUCT_PAGE_SIZE   32
4317 +
4318 +/* Linux mm_struct offsets. */
4319 +#define MM_USERS      40
4320 +#define MM_PGD        36
4321 +#define MM_CONTEXT    348
4322 +
4323 +#define _PAGE_SIZE     0x1000
4324 +#define _PAGE_SHIFT    0xc
4325 +
4326 +#define _PGD_T_SIZE    0x4
4327 +#define _PMD_T_SIZE    0x4
4328 +#define _PTE_T_SIZE    0x4
4329 +
4330 +#define _PGD_T_LOG2    $2
4331 +#define _PMD_T_LOG2    $2
4332 +#define _PTE_T_LOG2    $2
4333 +
4334 +#define _PMD_SHIFT     0x16
4335 +#define _PGDIR_SHIFT   0x16
4336 +
4337 +#define _PGD_ORDER     0x0
4338 +#define _PMD_ORDER     0x1
4339 +#define _PTE_ORDER     0x0
4340 +
4341 +#define _PTRS_PER_PGD  0x400
4342 +#define _PTRS_PER_PMD  0x1
4343 +#define _PTRS_PER_PTE  0x400
4344 +
4345 +
4346 +#endif
4347 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
4348 --- linux.old/include/asm-mips/bootinfo.h       2006-12-11 20:32:53.000000000 +0100
4349 +++ linux.dev/include/asm-mips/bootinfo.h       2007-01-03 02:26:02.000000000 +0100
4350 @@ -212,6 +212,12 @@
4351  #define MACH_GROUP_NEC_EMMA2RH 25      /* NEC EMMA2RH (was 23)         */
4352  #define  MACH_NEC_MARKEINS     0       /* NEC EMMA2RH Mark-eins        */
4353
4354 +/*
4355 + * Valid machtype for group Broadcom
4356 + */
4357 +#define MACH_GROUP_BRCM                23      /* Broadcom                     */
4358 +#define MACH_BCM47XX           1       /* Broadcom BCM47xx             */
4359 +
4360  #define CL_SIZE                        COMMAND_LINE_SIZE
4361
4362  const char *get_system_type(void);
4363 diff -urN linux.old/include/asm-mips/cfe.h linux.dev/include/asm-mips/cfe.h
4364 --- linux.old/include/asm-mips/cfe.h    1970-01-01 01:00:00.000000000 +0100
4365 +++ linux.dev/include/asm-mips/cfe.h    2007-01-03 02:26:02.000000000 +0100
4366 @@ -0,0 +1,189 @@
4367 +/*
4368 + * Broadcom Common Firmware Environment (CFE) support
4369 + *
4370 + * Copyright 2000, 2001, 2002
4371 + * Broadcom Corporation. All rights reserved.
4372 + *
4373 + * Copyright (C) 2006 Michael Buesch
4374 + *
4375 + * Original Authors:  Mitch Lichtenberg, Chris Demetriou
4376 + *
4377 + * This software is furnished under license and may be used and copied only
4378 + * in accordance with the following terms and conditions.  Subject to these
4379 + * conditions, you may download, copy, install, use, modify and distribute
4380 + * modified or unmodified copies of this software in source and/or binary
4381 + * form. No title or ownership is transferred hereby.
4382 + *
4383 + * 1) Any source code used, modified or distributed must reproduce and
4384 + *    retain this copyright notice and list of conditions as they appear in
4385 + *    the source file.
4386 + *
4387 + * 2) No right is granted to use any trade name, trademark, or logo of
4388 + *    Broadcom Corporation.  The "Broadcom Corporation" name may not be
4389 + *    used to endorse or promote products derived from this software
4390 + *    without the prior written permission of Broadcom Corporation.
4391 + *
4392 + * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
4393 + *    WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
4394 + *    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
4395 + *    NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
4396 + *    FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
4397 + *    LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
4398 + *    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
4399 + *    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
4400 + *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
4401 + *    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
4402 + *    OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4403 + */
4404 +
4405 +#ifndef LINUX_CFE_API_H_
4406 +#define LINUX_CFE_API_H_
4407 +
4408 +#include <linux/types.h>
4409 +
4410 +
4411 +#define CFE_MI_RESERVED                0               /* memory is reserved, do not use */
4412 +#define CFE_MI_AVAILABLE       1               /* memory is available */
4413 +
4414 +#define CFE_FLG_WARMSTART      0x00000001
4415 +#define CFE_FLG_FULL_ARENA     0x00000001
4416 +#define CFE_FLG_ENV_PERMANENT  0x00000001
4417 +
4418 +#define CFE_CPU_CMD_START      1
4419 +#define CFE_CPU_CMD_STOP       0
4420 +
4421 +#define CFE_STDHANDLE_CONSOLE  0
4422 +
4423 +#define CFE_DEV_NETWORK        1
4424 +#define CFE_DEV_DISK           2
4425 +#define CFE_DEV_FLASH          3
4426 +#define CFE_DEV_SERIAL         4
4427 +#define CFE_DEV_CPU            5
4428 +#define CFE_DEV_NVRAM          6
4429 +#define CFE_DEV_CLOCK           7
4430 +#define CFE_DEV_OTHER          8
4431 +#define CFE_DEV_MASK           0x0F
4432 +
4433 +#define CFE_CACHE_FLUSH_D      1
4434 +#define CFE_CACHE_INVAL_I      2
4435 +#define CFE_CACHE_INVAL_D      4
4436 +#define CFE_CACHE_INVAL_L2     8
4437 +
4438 +#define CFE_FWI_64BIT          0x00000001
4439 +#define CFE_FWI_32BIT          0x00000002
4440 +#define CFE_FWI_RELOC          0x00000004
4441 +#define CFE_FWI_UNCACHED       0x00000008
4442 +#define CFE_FWI_MULTICPU       0x00000010
4443 +#define CFE_FWI_FUNCSIM                0x00000020
4444 +#define CFE_FWI_RTLSIM         0x00000040
4445 +
4446 +struct cfe_fwinfo {
4447 +       s64 version;            /* major, minor, eco version */
4448 +       s64 totalmem;           /* total installed mem */
4449 +       s64 flags;              /* various flags */
4450 +       s64 boardid;            /* board ID */
4451 +       s64 bootarea_va;        /* VA of boot area */
4452 +       s64 bootarea_pa;        /* PA of boot area */
4453 +       s64 bootarea_size;      /* size of boot area */
4454 +};
4455 +
4456 +
4457 +/* The public CFE API */
4458 +
4459 +int cfe_present(void); /* Check if we booted from CFE. Returns bool */
4460 +
4461 +int cfe_getticks(s64 *ticks);
4462 +int cfe_close(int handle);
4463 +int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1);
4464 +int cfe_cpu_stop(int cpu);
4465 +int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
4466 +int cfe_enumdev(int idx, char *name, int namelen);
4467 +int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
4468 +               u64 *type);
4469 +int cfe_exit(int warm, int status);
4470 +int cfe_flushcache(int flags);
4471 +int cfe_getdevinfo(char *name);
4472 +int cfe_getenv(char *name, char *dest, int destlen);
4473 +int cfe_getfwinfo(struct cfe_fwinfo *info);
4474 +int cfe_getstdhandle(int handletype);
4475 +int cfe_inpstat(int handle);
4476 +int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
4477 +             int length, int *retlen, u64 offset);
4478 +int cfe_open(char *name);
4479 +int cfe_read(int handle, unsigned char *buffer, int length);
4480 +int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length);
4481 +int cfe_setenv(char *name, char *val);
4482 +int cfe_write(int handle, unsigned char *buffer, int length);
4483 +int cfe_writeblk(int handle, s64 offset, unsigned char *buffer,
4484 +                int length);
4485 +
4486 +
4487 +/* High level API */
4488 +
4489 +/* Print some information to CFE's console (most likely serial line) */
4490 +int cfe_printk(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
4491 +int cfe_vprintk(const char *fmt, va_list args);
4492 +
4493 +
4494 +
4495 +/* Error codes returned by the low API functions */
4496 +
4497 +#define CFE_ISERR(errcode)     (errcode < 0)
4498 +
4499 +#define CFE_OK                  0
4500 +#define CFE_ERR                 -1     /* generic error */
4501 +#define CFE_ERR_INV_COMMAND    -2
4502 +#define CFE_ERR_EOF            -3
4503 +#define CFE_ERR_IOERR          -4
4504 +#define CFE_ERR_NOMEM          -5
4505 +#define CFE_ERR_DEVNOTFOUND    -6
4506 +#define CFE_ERR_DEVOPEN                -7
4507 +#define CFE_ERR_INV_PARAM      -8
4508 +#define CFE_ERR_ENVNOTFOUND    -9
4509 +#define CFE_ERR_ENVREADONLY    -10
4510 +
4511 +#define CFE_ERR_NOTELF         -11
4512 +#define CFE_ERR_NOT32BIT       -12
4513 +#define CFE_ERR_WRONGENDIAN    -13
4514 +#define CFE_ERR_BADELFVERS     -14
4515 +#define CFE_ERR_NOTMIPS        -15
4516 +#define CFE_ERR_BADELFFMT      -16
4517 +#define CFE_ERR_BADADDR        -17
4518 +
4519 +#define CFE_ERR_FILENOTFOUND   -18
4520 +#define CFE_ERR_UNSUPPORTED    -19
4521 +
4522 +#define CFE_ERR_HOSTUNKNOWN    -20
4523 +
4524 +#define CFE_ERR_TIMEOUT                -21
4525 +
4526 +#define CFE_ERR_PROTOCOLERR    -22
4527 +
4528 +#define CFE_ERR_NETDOWN                -23
4529 +#define CFE_ERR_NONAMESERVER   -24
4530 +
4531 +#define CFE_ERR_NOHANDLES      -25
4532 +#define CFE_ERR_ALREADYBOUND   -26
4533 +
4534 +#define CFE_ERR_CANNOTSET      -27
4535 +#define CFE_ERR_NOMORE         -28
4536 +#define CFE_ERR_BADFILESYS     -29
4537 +#define CFE_ERR_FSNOTAVAIL     -30
4538 +
4539 +#define CFE_ERR_INVBOOTBLOCK   -31
4540 +#define CFE_ERR_WRONGDEVTYPE   -32
4541 +#define CFE_ERR_BBCHECKSUM     -33
4542 +#define CFE_ERR_BOOTPROGCHKSUM -34
4543 +
4544 +#define CFE_ERR_LDRNOTAVAIL    -35
4545 +
4546 +#define CFE_ERR_NOTREADY       -36
4547 +
4548 +#define CFE_ERR_GETMEM          -37
4549 +#define CFE_ERR_SETMEM          -38
4550 +
4551 +#define CFE_ERR_NOTCONN                -39
4552 +#define CFE_ERR_ADDRINUSE      -40
4553 +
4554 +
4555 +#endif /* LINUX_CFE_API_H_ */
4556 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
4557 --- linux.old/include/asm-mips/cpu.h    2006-12-11 20:32:53.000000000 +0100
4558 +++ linux.dev/include/asm-mips/cpu.h    2007-01-03 02:26:02.000000000 +0100
4559 @@ -104,6 +104,13 @@
4560  #define PRID_IMP_SR71000        0x0400
4561
4562  /*
4563 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
4564 + */
4565 +
4566 +#define PRID_IMP_BCM4710       0x4000
4567 +#define PRID_IMP_BCM3302       0x9000
4568 +
4569 +/*
4570   * Definitions for 7:0 on legacy processors
4571   */
4572
4573 @@ -200,7 +207,9 @@
4574  #define CPU_SB1A               62
4575  #define CPU_74K                        63
4576  #define CPU_R14000             64
4577 -#define CPU_LAST               64
4578 +#define CPU_BCM3302            65
4579 +#define CPU_BCM4710            66
4580 +#define CPU_LAST               66
4581
4582  /*
4583   * ISA Level encodings
4584 diff -urN linux.old/include/asm-mips/mach-bcm947xx/kernel-entry-init.h linux.dev/include/asm-mips/mach-bcm947xx/kernel-entry-init.h
4585 --- linux.old/include/asm-mips/mach-bcm947xx/kernel-entry-init.h        1970-01-01 01:00:00.000000000 +0100
4586 +++ linux.dev/include/asm-mips/mach-bcm947xx/kernel-entry-init.h        2007-01-03 02:26:02.000000000 +0100
4587 @@ -0,0 +1,26 @@
4588 +/*
4589 + * This file is subject to the terms and conditions of the GNU General Public
4590 + * License.  See the file "COPYING" in the main directory of this archive
4591 + * for more details.
4592 + *
4593 + * Copyright (C) 2005 Embedded Alley Solutions, Inc
4594 + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
4595 + * Copyright (C) 2006 Michael Buesch
4596 + */
4597 +#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
4598 +#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
4599 +
4600 +/* Intentionally empty macro, used in head.S. Override in
4601 + * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
4602 + */
4603 +       .macro  kernel_entry_setup
4604 +       .endm
4605 +
4606 +/*
4607 + * Do SMP slave processor setup necessary before we can savely execute C code.
4608 + */
4609 +       .macro  smp_slave_setup
4610 +       .endm
4611 +
4612 +
4613 +#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
4614 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
4615 --- linux.old/include/linux/pci_ids.h   2006-12-11 20:32:53.000000000 +0100
4616 +++ linux.dev/include/linux/pci_ids.h   2007-01-03 02:26:02.000000000 +0100
4617 @@ -1950,6 +1950,7 @@
4618  #define PCI_DEVICE_ID_TIGON3_5906M     0x1713
4619  #define PCI_DEVICE_ID_BCM4401          0x4401
4620  #define PCI_DEVICE_ID_BCM4401B0                0x4402
4621 +#define PCI_DEVICE_ID_BCM4713          0x4713
4622
4623  #define PCI_VENDOR_ID_TOPIC            0x151f
4624  #define PCI_DEVICE_ID_TOPIC_TP560      0x0000
4625 diff -urN linux.old/include/linux/pci_ids.h.orig linux.dev/include/linux/pci_ids.h.orig
4626 --- linux.old/include/linux/pci_ids.h.orig      1970-01-01 01:00:00.000000000 +0100
4627 +++ linux.dev/include/linux/pci_ids.h.orig      2006-12-11 20:32:53.000000000 +0100
4628 @@ -0,0 +1,2356 @@
4629 +/*
4630 + *     PCI Class, Vendor and Device IDs
4631 + *
4632 + *     Please keep sorted.
4633 + */
4634 +
4635 +/* Device classes and subclasses */
4636 +
4637 +#define PCI_CLASS_NOT_DEFINED          0x0000
4638 +#define PCI_CLASS_NOT_DEFINED_VGA      0x0001
4639 +
4640 +#define PCI_BASE_CLASS_STORAGE         0x01
4641 +#define PCI_CLASS_STORAGE_SCSI         0x0100
4642 +#define PCI_CLASS_STORAGE_IDE          0x0101
4643 +#define PCI_CLASS_STORAGE_FLOPPY       0x0102
4644 +#define PCI_CLASS_STORAGE_IPI          0x0103
4645 +#define PCI_CLASS_STORAGE_RAID         0x0104
4646 +#define PCI_CLASS_STORAGE_SAS          0x0107
4647 +#define PCI_CLASS_STORAGE_OTHER                0x0180
4648 +
4649 +#define PCI_BASE_CLASS_NETWORK         0x02
4650 +#define PCI_CLASS_NETWORK_ETHERNET     0x0200
4651 +#define PCI_CLASS_NETWORK_TOKEN_RING   0x0201
4652 +#define PCI_CLASS_NETWORK_FDDI         0x0202
4653 +#define PCI_CLASS_NETWORK_ATM          0x0203
4654 +#define PCI_CLASS_NETWORK_OTHER                0x0280
4655 +
4656 +#define PCI_BASE_CLASS_DISPLAY         0x03
4657 +#define PCI_CLASS_DISPLAY_VGA          0x0300
4658 +#define PCI_CLASS_DISPLAY_XGA          0x0301
4659 +#define PCI_CLASS_DISPLAY_3D           0x0302
4660 +#define PCI_CLASS_DISPLAY_OTHER                0x0380
4661 +
4662 +#define PCI_BASE_CLASS_MULTIMEDIA      0x04
4663 +#define PCI_CLASS_MULTIMEDIA_VIDEO     0x0400
4664 +#define PCI_CLASS_MULTIMEDIA_AUDIO     0x0401
4665 +#define PCI_CLASS_MULTIMEDIA_PHONE     0x0402
4666 +#define PCI_CLASS_MULTIMEDIA_OTHER     0x0480
4667 +
4668 +#define PCI_BASE_CLASS_MEMORY          0x05
4669 +#define PCI_CLASS_MEMORY_RAM           0x0500
4670 +#define PCI_CLASS_MEMORY_FLASH         0x0501
4671 +#define PCI_CLASS_MEMORY_OTHER         0x0580
4672 +
4673 +#define PCI_BASE_CLASS_BRIDGE          0x06
4674 +#define PCI_CLASS_BRIDGE_HOST          0x0600
4675 +#define PCI_CLASS_BRIDGE_ISA           0x0601
4676 +#define PCI_CLASS_BRIDGE_EISA          0x0602
4677 +#define PCI_CLASS_BRIDGE_MC            0x0603
4678 +#define PCI_CLASS_BRIDGE_PCI           0x0604
4679 +#define PCI_CLASS_BRIDGE_PCMCIA                0x0605
4680 +#define PCI_CLASS_BRIDGE_NUBUS         0x0606
4681 +#define PCI_CLASS_BRIDGE_CARDBUS       0x0607
4682 +#define PCI_CLASS_BRIDGE_RACEWAY       0x0608
4683 +#define PCI_CLASS_BRIDGE_OTHER         0x0680
4684 +
4685 +#define PCI_BASE_CLASS_COMMUNICATION   0x07
4686 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
4687 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
4688 +#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
4689 +#define PCI_CLASS_COMMUNICATION_MODEM  0x0703
4690 +#define PCI_CLASS_COMMUNICATION_OTHER  0x0780
4691 +
4692 +#define PCI_BASE_CLASS_SYSTEM          0x08
4693 +#define PCI_CLASS_SYSTEM_PIC           0x0800
4694 +#define PCI_CLASS_SYSTEM_PIC_IOAPIC    0x080010
4695 +#define PCI_CLASS_SYSTEM_PIC_IOXAPIC   0x080020
4696 +#define PCI_CLASS_SYSTEM_DMA           0x0801
4697 +#define PCI_CLASS_SYSTEM_TIMER         0x0802
4698 +#define PCI_CLASS_SYSTEM_RTC           0x0803
4699 +#define PCI_CLASS_SYSTEM_PCI_HOTPLUG   0x0804
4700 +#define PCI_CLASS_SYSTEM_SDHCI         0x0805
4701 +#define PCI_CLASS_SYSTEM_OTHER         0x0880
4702 +
4703 +#define PCI_BASE_CLASS_INPUT           0x09
4704 +#define PCI_CLASS_INPUT_KEYBOARD       0x0900
4705 +#define PCI_CLASS_INPUT_PEN            0x0901
4706 +#define PCI_CLASS_INPUT_MOUSE          0x0902
4707 +#define PCI_CLASS_INPUT_SCANNER                0x0903
4708 +#define PCI_CLASS_INPUT_GAMEPORT       0x0904
4709 +#define PCI_CLASS_INPUT_OTHER          0x0980
4710 +
4711 +#define PCI_BASE_CLASS_DOCKING         0x0a
4712 +#define PCI_CLASS_DOCKING_GENERIC      0x0a00
4713 +#define PCI_CLASS_DOCKING_OTHER                0x0a80
4714 +
4715 +#define PCI_BASE_CLASS_PROCESSOR       0x0b
4716 +#define PCI_CLASS_PROCESSOR_386                0x0b00
4717 +#define PCI_CLASS_PROCESSOR_486                0x0b01
4718 +#define PCI_CLASS_PROCESSOR_PENTIUM    0x0b02
4719 +#define PCI_CLASS_PROCESSOR_ALPHA      0x0b10
4720 +#define PCI_CLASS_PROCESSOR_POWERPC    0x0b20
4721 +#define PCI_CLASS_PROCESSOR_MIPS       0x0b30
4722 +#define PCI_CLASS_PROCESSOR_CO         0x0b40
4723 +
4724 +#define PCI_BASE_CLASS_SERIAL          0x0c
4725 +#define PCI_CLASS_SERIAL_FIREWIRE      0x0c00
4726 +#define PCI_CLASS_SERIAL_ACCESS                0x0c01
4727 +#define PCI_CLASS_SERIAL_SSA           0x0c02
4728 +#define PCI_CLASS_SERIAL_USB           0x0c03
4729 +#define PCI_CLASS_SERIAL_USB_UHCI      0x0c0300
4730 +#define PCI_CLASS_SERIAL_USB_OHCI      0x0c0310
4731 +#define PCI_CLASS_SERIAL_USB_EHCI      0x0c0320
4732 +#define PCI_CLASS_SERIAL_FIBER         0x0c04
4733 +#define PCI_CLASS_SERIAL_SMBUS         0x0c05
4734 +
4735 +#define PCI_BASE_CLASS_INTELLIGENT     0x0e
4736 +#define PCI_CLASS_INTELLIGENT_I2O      0x0e00
4737 +
4738 +#define PCI_BASE_CLASS_SATELLITE       0x0f
4739 +#define PCI_CLASS_SATELLITE_TV         0x0f00
4740 +#define PCI_CLASS_SATELLITE_AUDIO      0x0f01
4741 +#define PCI_CLASS_SATELLITE_VOICE      0x0f03
4742 +#define PCI_CLASS_SATELLITE_DATA       0x0f04
4743 +
4744 +#define PCI_BASE_CLASS_CRYPT           0x10
4745 +#define PCI_CLASS_CRYPT_NETWORK                0x1000
4746 +#define PCI_CLASS_CRYPT_ENTERTAINMENT  0x1001
4747 +#define PCI_CLASS_CRYPT_OTHER          0x1080
4748 +
4749 +#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
4750 +#define PCI_CLASS_SP_DPIO              0x1100
4751 +#define PCI_CLASS_SP_OTHER             0x1180
4752 +
4753 +#define PCI_CLASS_OTHERS               0xff
4754 +
4755 +/* Vendors and devices.  Sort key: vendor first, device next. */
4756 +
4757 +#define PCI_VENDOR_ID_DYNALINK         0x0675
4758 +#define PCI_DEVICE_ID_DYNALINK_IS64PH  0x1702
4759 +
4760 +#define PCI_VENDOR_ID_BERKOM                   0x0871
4761 +#define PCI_DEVICE_ID_BERKOM_A1T               0xffa1
4762 +#define PCI_DEVICE_ID_BERKOM_T_CONCEPT         0xffa2
4763 +#define PCI_DEVICE_ID_BERKOM_A4T               0xffa4
4764 +#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO     0xffa8
4765 +
4766 +#define PCI_VENDOR_ID_COMPAQ           0x0e11
4767 +#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508
4768 +#define PCI_DEVICE_ID_COMPAQ_TACHYON   0xa0fc
4769 +#define PCI_DEVICE_ID_COMPAQ_SMART2P   0xae10
4770 +#define PCI_DEVICE_ID_COMPAQ_NETEL100  0xae32
4771 +#define PCI_DEVICE_ID_COMPAQ_NETEL10   0xae34
4772 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
4773 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35
4774 +#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40
4775 +#define PCI_DEVICE_ID_COMPAQ_NETEL100PI        0xae43
4776 +#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011
4777 +#define PCI_DEVICE_ID_COMPAQ_CISS      0xb060
4778 +#define PCI_DEVICE_ID_COMPAQ_CISSB     0xb178
4779 +#define PCI_DEVICE_ID_COMPAQ_CISSC     0x46
4780 +#define PCI_DEVICE_ID_COMPAQ_THUNDER   0xf130
4781 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150
4782 +
4783 +#define PCI_VENDOR_ID_NCR              0x1000
4784 +#define PCI_VENDOR_ID_LSI_LOGIC                0x1000
4785 +#define PCI_DEVICE_ID_NCR_53C810       0x0001
4786 +#define PCI_DEVICE_ID_NCR_53C820       0x0002
4787 +#define PCI_DEVICE_ID_NCR_53C825       0x0003
4788 +#define PCI_DEVICE_ID_NCR_53C815       0x0004
4789 +#define PCI_DEVICE_ID_LSI_53C810AP     0x0005
4790 +#define PCI_DEVICE_ID_NCR_53C860       0x0006
4791 +#define PCI_DEVICE_ID_LSI_53C1510      0x000a
4792 +#define PCI_DEVICE_ID_NCR_53C896       0x000b
4793 +#define PCI_DEVICE_ID_NCR_53C895       0x000c
4794 +#define PCI_DEVICE_ID_NCR_53C885       0x000d
4795 +#define PCI_DEVICE_ID_NCR_53C875       0x000f
4796 +#define PCI_DEVICE_ID_NCR_53C1510      0x0010
4797 +#define PCI_DEVICE_ID_LSI_53C895A      0x0012
4798 +#define PCI_DEVICE_ID_LSI_53C875A      0x0013
4799 +#define PCI_DEVICE_ID_LSI_53C1010_33   0x0020
4800 +#define PCI_DEVICE_ID_LSI_53C1010_66   0x0021
4801 +#define PCI_DEVICE_ID_LSI_53C1030      0x0030
4802 +#define PCI_DEVICE_ID_LSI_1030_53C1035 0x0032
4803 +#define PCI_DEVICE_ID_LSI_53C1035      0x0040
4804 +#define PCI_DEVICE_ID_NCR_53C875J      0x008f
4805 +#define PCI_DEVICE_ID_LSI_FC909                0x0621
4806 +#define PCI_DEVICE_ID_LSI_FC929                0x0622
4807 +#define PCI_DEVICE_ID_LSI_FC929_LAN    0x0623
4808 +#define PCI_DEVICE_ID_LSI_FC919                0x0624
4809 +#define PCI_DEVICE_ID_LSI_FC919_LAN    0x0625
4810 +#define PCI_DEVICE_ID_LSI_FC929X       0x0626
4811 +#define PCI_DEVICE_ID_LSI_FC939X       0x0642
4812 +#define PCI_DEVICE_ID_LSI_FC949X       0x0640
4813 +#define PCI_DEVICE_ID_LSI_FC949ES      0x0646
4814 +#define PCI_DEVICE_ID_LSI_FC919X       0x0628
4815 +#define PCI_DEVICE_ID_NCR_YELLOWFIN    0x0701
4816 +#define PCI_DEVICE_ID_LSI_61C102       0x0901
4817 +#define PCI_DEVICE_ID_LSI_63C815       0x1000
4818 +#define PCI_DEVICE_ID_LSI_SAS1064      0x0050
4819 +#define PCI_DEVICE_ID_LSI_SAS1064R     0x0411
4820 +#define PCI_DEVICE_ID_LSI_SAS1066      0x005E
4821 +#define PCI_DEVICE_ID_LSI_SAS1068      0x0054
4822 +#define PCI_DEVICE_ID_LSI_SAS1064A     0x005C
4823 +#define PCI_DEVICE_ID_LSI_SAS1064E     0x0056
4824 +#define PCI_DEVICE_ID_LSI_SAS1066E     0x005A
4825 +#define PCI_DEVICE_ID_LSI_SAS1068E     0x0058
4826 +#define PCI_DEVICE_ID_LSI_SAS1078      0x0060
4827 +
4828 +#define PCI_VENDOR_ID_ATI              0x1002
4829 +/* Mach64 */
4830 +#define PCI_DEVICE_ID_ATI_68800                0x4158
4831 +#define PCI_DEVICE_ID_ATI_215CT222     0x4354
4832 +#define PCI_DEVICE_ID_ATI_210888CX     0x4358
4833 +#define PCI_DEVICE_ID_ATI_215ET222     0x4554
4834 +/* Mach64 / Rage */
4835 +#define PCI_DEVICE_ID_ATI_215GB                0x4742
4836 +#define PCI_DEVICE_ID_ATI_215GD                0x4744
4837 +#define PCI_DEVICE_ID_ATI_215GI                0x4749
4838 +#define PCI_DEVICE_ID_ATI_215GP                0x4750
4839 +#define PCI_DEVICE_ID_ATI_215GQ                0x4751
4840 +#define PCI_DEVICE_ID_ATI_215XL                0x4752
4841 +#define PCI_DEVICE_ID_ATI_215GT                0x4754
4842 +#define PCI_DEVICE_ID_ATI_215GTB       0x4755
4843 +#define PCI_DEVICE_ID_ATI_215_IV       0x4756
4844 +#define PCI_DEVICE_ID_ATI_215_IW       0x4757
4845 +#define PCI_DEVICE_ID_ATI_215_IZ       0x475A
4846 +#define PCI_DEVICE_ID_ATI_210888GX     0x4758
4847 +#define PCI_DEVICE_ID_ATI_215_LB       0x4c42
4848 +#define PCI_DEVICE_ID_ATI_215_LD       0x4c44
4849 +#define PCI_DEVICE_ID_ATI_215_LG       0x4c47
4850 +#define PCI_DEVICE_ID_ATI_215_LI       0x4c49
4851 +#define PCI_DEVICE_ID_ATI_215_LM       0x4c4D
4852 +#define PCI_DEVICE_ID_ATI_215_LN       0x4c4E
4853 +#define PCI_DEVICE_ID_ATI_215_LR       0x4c52
4854 +#define PCI_DEVICE_ID_ATI_215_LS       0x4c53
4855 +#define PCI_DEVICE_ID_ATI_264_LT       0x4c54
4856 +/* Mach64 VT */
4857 +#define PCI_DEVICE_ID_ATI_264VT                0x5654
4858 +#define PCI_DEVICE_ID_ATI_264VU                0x5655
4859 +#define PCI_DEVICE_ID_ATI_264VV                0x5656
4860 +/* Rage128 GL */
4861 +#define PCI_DEVICE_ID_ATI_RAGE128_RE   0x5245
4862 +#define PCI_DEVICE_ID_ATI_RAGE128_RF   0x5246
4863 +#define PCI_DEVICE_ID_ATI_RAGE128_RG   0x5247
4864 +/* Rage128 VR */
4865 +#define PCI_DEVICE_ID_ATI_RAGE128_RK   0x524b
4866 +#define PCI_DEVICE_ID_ATI_RAGE128_RL   0x524c
4867 +#define PCI_DEVICE_ID_ATI_RAGE128_SE   0x5345
4868 +#define PCI_DEVICE_ID_ATI_RAGE128_SF   0x5346
4869 +#define PCI_DEVICE_ID_ATI_RAGE128_SG   0x5347
4870 +#define PCI_DEVICE_ID_ATI_RAGE128_SH   0x5348
4871 +#define PCI_DEVICE_ID_ATI_RAGE128_SK   0x534b
4872 +#define PCI_DEVICE_ID_ATI_RAGE128_SL   0x534c
4873 +#define PCI_DEVICE_ID_ATI_RAGE128_SM   0x534d
4874 +#define PCI_DEVICE_ID_ATI_RAGE128_SN   0x534e
4875 +/* Rage128 Ultra */
4876 +#define PCI_DEVICE_ID_ATI_RAGE128_TF   0x5446
4877 +#define PCI_DEVICE_ID_ATI_RAGE128_TL   0x544c
4878 +#define PCI_DEVICE_ID_ATI_RAGE128_TR   0x5452
4879 +#define PCI_DEVICE_ID_ATI_RAGE128_TS   0x5453
4880 +#define PCI_DEVICE_ID_ATI_RAGE128_TT   0x5454
4881 +#define PCI_DEVICE_ID_ATI_RAGE128_TU   0x5455
4882 +/* Rage128 M3 */
4883 +#define PCI_DEVICE_ID_ATI_RAGE128_LE   0x4c45
4884 +#define PCI_DEVICE_ID_ATI_RAGE128_LF   0x4c46
4885 +/* Rage128 M4 */
4886 +#define PCI_DEVICE_ID_ATI_RAGE128_MF    0x4d46
4887 +#define PCI_DEVICE_ID_ATI_RAGE128_ML    0x4d4c
4888 +/* Rage128 Pro GL */
4889 +#define PCI_DEVICE_ID_ATI_RAGE128_PA   0x5041
4890 +#define PCI_DEVICE_ID_ATI_RAGE128_PB   0x5042
4891 +#define PCI_DEVICE_ID_ATI_RAGE128_PC   0x5043
4892 +#define PCI_DEVICE_ID_ATI_RAGE128_PD   0x5044
4893 +#define PCI_DEVICE_ID_ATI_RAGE128_PE   0x5045
4894 +#define PCI_DEVICE_ID_ATI_RAGE128_PF   0x5046
4895 +/* Rage128 Pro VR */
4896 +#define PCI_DEVICE_ID_ATI_RAGE128_PG   0x5047
4897 +#define PCI_DEVICE_ID_ATI_RAGE128_PH   0x5048
4898 +#define PCI_DEVICE_ID_ATI_RAGE128_PI   0x5049
4899 +#define PCI_DEVICE_ID_ATI_RAGE128_PJ   0x504A
4900 +#define PCI_DEVICE_ID_ATI_RAGE128_PK   0x504B
4901 +#define PCI_DEVICE_ID_ATI_RAGE128_PL   0x504C
4902 +#define PCI_DEVICE_ID_ATI_RAGE128_PM   0x504D
4903 +#define PCI_DEVICE_ID_ATI_RAGE128_PN   0x504E
4904 +#define PCI_DEVICE_ID_ATI_RAGE128_PO   0x504F
4905 +#define PCI_DEVICE_ID_ATI_RAGE128_PP   0x5050
4906 +#define PCI_DEVICE_ID_ATI_RAGE128_PQ   0x5051
4907 +#define PCI_DEVICE_ID_ATI_RAGE128_PR   0x5052
4908 +#define PCI_DEVICE_ID_ATI_RAGE128_PS   0x5053
4909 +#define PCI_DEVICE_ID_ATI_RAGE128_PT   0x5054
4910 +#define PCI_DEVICE_ID_ATI_RAGE128_PU   0x5055
4911 +#define PCI_DEVICE_ID_ATI_RAGE128_PV   0x5056
4912 +#define PCI_DEVICE_ID_ATI_RAGE128_PW   0x5057
4913 +#define PCI_DEVICE_ID_ATI_RAGE128_PX   0x5058
4914 +/* Rage128 M4 */
4915 +/* Radeon R100 */
4916 +#define PCI_DEVICE_ID_ATI_RADEON_QD    0x5144
4917 +#define PCI_DEVICE_ID_ATI_RADEON_QE    0x5145
4918 +#define PCI_DEVICE_ID_ATI_RADEON_QF    0x5146
4919 +#define PCI_DEVICE_ID_ATI_RADEON_QG    0x5147
4920 +/* Radeon RV100 (VE) */
4921 +#define PCI_DEVICE_ID_ATI_RADEON_QY    0x5159
4922 +#define PCI_DEVICE_ID_ATI_RADEON_QZ    0x515a
4923 +/* Radeon R200 (8500) */
4924 +#define PCI_DEVICE_ID_ATI_RADEON_QL    0x514c
4925 +#define PCI_DEVICE_ID_ATI_RADEON_QN    0x514e
4926 +#define PCI_DEVICE_ID_ATI_RADEON_QO    0x514f
4927 +#define PCI_DEVICE_ID_ATI_RADEON_Ql    0x516c
4928 +#define PCI_DEVICE_ID_ATI_RADEON_BB    0x4242
4929 +/* Radeon R200 (9100) */
4930 +#define PCI_DEVICE_ID_ATI_RADEON_QM    0x514d
4931 +/* Radeon RV200 (7500) */
4932 +#define PCI_DEVICE_ID_ATI_RADEON_QW    0x5157
4933 +#define PCI_DEVICE_ID_ATI_RADEON_QX    0x5158
4934 +/* Radeon NV-100 */
4935 +/* Radeon RV250 (9000) */
4936 +#define PCI_DEVICE_ID_ATI_RADEON_Id    0x4964
4937 +#define PCI_DEVICE_ID_ATI_RADEON_Ie    0x4965
4938 +#define PCI_DEVICE_ID_ATI_RADEON_If    0x4966
4939 +#define PCI_DEVICE_ID_ATI_RADEON_Ig    0x4967
4940 +/* Radeon RV280 (9200) */
4941 +#define PCI_DEVICE_ID_ATI_RADEON_Ya    0x5961
4942 +#define PCI_DEVICE_ID_ATI_RADEON_Yd    0x5964
4943 +/* Radeon R300 (9500) */
4944 +/* Radeon R300 (9700) */
4945 +#define PCI_DEVICE_ID_ATI_RADEON_ND    0x4e44
4946 +#define PCI_DEVICE_ID_ATI_RADEON_NE    0x4e45
4947 +#define PCI_DEVICE_ID_ATI_RADEON_NF    0x4e46
4948 +#define PCI_DEVICE_ID_ATI_RADEON_NG    0x4e47
4949 +/* Radeon R350 (9800) */
4950 +/* Radeon RV350 (9600) */
4951 +/* Radeon M6 */
4952 +#define PCI_DEVICE_ID_ATI_RADEON_LY    0x4c59
4953 +#define PCI_DEVICE_ID_ATI_RADEON_LZ    0x4c5a
4954 +/* Radeon M7 */
4955 +#define PCI_DEVICE_ID_ATI_RADEON_LW    0x4c57
4956 +#define PCI_DEVICE_ID_ATI_RADEON_LX    0x4c58
4957 +/* Radeon M9 */
4958 +#define PCI_DEVICE_ID_ATI_RADEON_Ld    0x4c64
4959 +#define PCI_DEVICE_ID_ATI_RADEON_Le    0x4c65
4960 +#define PCI_DEVICE_ID_ATI_RADEON_Lf    0x4c66
4961 +#define PCI_DEVICE_ID_ATI_RADEON_Lg    0x4c67
4962 +/* Radeon */
4963 +/* RadeonIGP */
4964 +#define PCI_DEVICE_ID_ATI_RS100                0xcab0
4965 +#define PCI_DEVICE_ID_ATI_RS200                0xcab2
4966 +#define PCI_DEVICE_ID_ATI_RS200_B      0xcbb2
4967 +#define PCI_DEVICE_ID_ATI_RS250                0xcab3
4968 +#define PCI_DEVICE_ID_ATI_RS300_100    0x5830
4969 +#define PCI_DEVICE_ID_ATI_RS300_133    0x5831
4970 +#define PCI_DEVICE_ID_ATI_RS300_166    0x5832
4971 +#define PCI_DEVICE_ID_ATI_RS300_200    0x5833
4972 +#define PCI_DEVICE_ID_ATI_RS350_100     0x7830
4973 +#define PCI_DEVICE_ID_ATI_RS350_133     0x7831
4974 +#define PCI_DEVICE_ID_ATI_RS350_166     0x7832
4975 +#define PCI_DEVICE_ID_ATI_RS350_200     0x7833
4976 +#define PCI_DEVICE_ID_ATI_RS400_100     0x5a30
4977 +#define PCI_DEVICE_ID_ATI_RS400_133     0x5a31
4978 +#define PCI_DEVICE_ID_ATI_RS400_166     0x5a32
4979 +#define PCI_DEVICE_ID_ATI_RS400_200     0x5a33
4980 +#define PCI_DEVICE_ID_ATI_RS480         0x5950
4981 +/* ATI IXP Chipset */
4982 +#define PCI_DEVICE_ID_ATI_IXP200_IDE   0x4349
4983 +#define PCI_DEVICE_ID_ATI_IXP200_SMBUS 0x4353
4984 +#define PCI_DEVICE_ID_ATI_IXP300_SMBUS 0x4363
4985 +#define PCI_DEVICE_ID_ATI_IXP300_IDE   0x4369
4986 +#define PCI_DEVICE_ID_ATI_IXP300_SATA   0x436e
4987 +#define PCI_DEVICE_ID_ATI_IXP400_SMBUS 0x4372
4988 +#define PCI_DEVICE_ID_ATI_IXP400_IDE   0x4376
4989 +#define PCI_DEVICE_ID_ATI_IXP400_SATA   0x4379
4990 +#define PCI_DEVICE_ID_ATI_IXP400_SATA2 0x437a
4991 +#define PCI_DEVICE_ID_ATI_IXP600_SATA  0x4380
4992 +#define PCI_DEVICE_ID_ATI_IXP600_SRAID 0x4381
4993 +#define PCI_DEVICE_ID_ATI_IXP600_IDE   0x438c
4994 +
4995 +#define PCI_VENDOR_ID_VLSI             0x1004
4996 +#define PCI_DEVICE_ID_VLSI_82C592      0x0005
4997 +#define PCI_DEVICE_ID_VLSI_82C593      0x0006
4998 +#define PCI_DEVICE_ID_VLSI_82C594      0x0007
4999 +#define PCI_DEVICE_ID_VLSI_82C597      0x0009
5000 +#define PCI_DEVICE_ID_VLSI_82C541      0x000c
5001 +#define PCI_DEVICE_ID_VLSI_82C543      0x000d
5002 +#define PCI_DEVICE_ID_VLSI_82C532      0x0101
5003 +#define PCI_DEVICE_ID_VLSI_82C534      0x0102
5004 +#define PCI_DEVICE_ID_VLSI_82C535      0x0104
5005 +#define PCI_DEVICE_ID_VLSI_82C147      0x0105
5006 +#define PCI_DEVICE_ID_VLSI_VAS96011    0x0702
5007 +
5008 +#define PCI_VENDOR_ID_ADL              0x1005
5009 +#define PCI_DEVICE_ID_ADL_2301         0x2301
5010 +
5011 +#define PCI_VENDOR_ID_NS               0x100b
5012 +#define PCI_DEVICE_ID_NS_87415         0x0002
5013 +#define PCI_DEVICE_ID_NS_87560_LIO     0x000e
5014 +#define PCI_DEVICE_ID_NS_87560_USB     0x0012
5015 +#define PCI_DEVICE_ID_NS_83815         0x0020
5016 +#define PCI_DEVICE_ID_NS_83820         0x0022
5017 +#define PCI_DEVICE_ID_NS_CS5535_ISA    0x002b
5018 +#define PCI_DEVICE_ID_NS_CS5535_IDE    0x002d
5019 +#define PCI_DEVICE_ID_NS_CS5535_AUDIO  0x002e
5020 +#define PCI_DEVICE_ID_NS_CS5535_USB    0x002f
5021 +#define PCI_DEVICE_ID_NS_CS5535_VIDEO  0x0030
5022 +#define PCI_DEVICE_ID_NS_SATURN                0x0035
5023 +#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500
5024 +#define PCI_DEVICE_ID_NS_SCx200_SMI    0x0501
5025 +#define PCI_DEVICE_ID_NS_SCx200_IDE    0x0502
5026 +#define PCI_DEVICE_ID_NS_SCx200_AUDIO  0x0503
5027 +#define PCI_DEVICE_ID_NS_SCx200_VIDEO  0x0504
5028 +#define PCI_DEVICE_ID_NS_SCx200_XBUS   0x0505
5029 +#define PCI_DEVICE_ID_NS_SC1100_BRIDGE 0x0510
5030 +#define PCI_DEVICE_ID_NS_SC1100_SMI    0x0511
5031 +#define PCI_DEVICE_ID_NS_SC1100_XBUS   0x0515
5032 +#define PCI_DEVICE_ID_NS_87410         0xd001
5033 +
5034 +#define PCI_DEVICE_ID_NS_CS5535_HOST_BRIDGE  0x0028
5035 +#define PCI_DEVICE_ID_NS_CS5535_ISA_BRIDGE   0x002b
5036 +
5037 +#define PCI_VENDOR_ID_TSENG            0x100c
5038 +#define PCI_DEVICE_ID_TSENG_W32P_2     0x3202
5039 +#define PCI_DEVICE_ID_TSENG_W32P_b     0x3205
5040 +#define PCI_DEVICE_ID_TSENG_W32P_c     0x3206
5041 +#define PCI_DEVICE_ID_TSENG_W32P_d     0x3207
5042 +#define PCI_DEVICE_ID_TSENG_ET6000     0x3208
5043 +
5044 +#define PCI_VENDOR_ID_WEITEK           0x100e
5045 +#define PCI_DEVICE_ID_WEITEK_P9000     0x9001
5046 +#define PCI_DEVICE_ID_WEITEK_P9100     0x9100
5047 +
5048 +#define PCI_VENDOR_ID_DEC              0x1011
5049 +#define PCI_DEVICE_ID_DEC_BRD          0x0001
5050 +#define PCI_DEVICE_ID_DEC_TULIP                0x0002
5051 +#define PCI_DEVICE_ID_DEC_TGA          0x0004
5052 +#define PCI_DEVICE_ID_DEC_TULIP_FAST   0x0009
5053 +#define PCI_DEVICE_ID_DEC_TGA2         0x000D
5054 +#define PCI_DEVICE_ID_DEC_FDDI         0x000F
5055 +#define PCI_DEVICE_ID_DEC_TULIP_PLUS   0x0014
5056 +#define PCI_DEVICE_ID_DEC_21142                0x0019
5057 +#define PCI_DEVICE_ID_DEC_21052                0x0021
5058 +#define PCI_DEVICE_ID_DEC_21150                0x0022
5059 +#define PCI_DEVICE_ID_DEC_21152                0x0024
5060 +#define PCI_DEVICE_ID_DEC_21153                0x0025
5061 +#define PCI_DEVICE_ID_DEC_21154                0x0026
5062 +#define PCI_DEVICE_ID_DEC_21285                0x1065
5063 +#define PCI_DEVICE_ID_COMPAQ_42XX      0x0046
5064 +
5065 +#define PCI_VENDOR_ID_CIRRUS           0x1013
5066 +#define PCI_DEVICE_ID_CIRRUS_7548      0x0038
5067 +#define PCI_DEVICE_ID_CIRRUS_5430      0x00a0
5068 +#define PCI_DEVICE_ID_CIRRUS_5434_4    0x00a4
5069 +#define PCI_DEVICE_ID_CIRRUS_5434_8    0x00a8
5070 +#define PCI_DEVICE_ID_CIRRUS_5436      0x00ac
5071 +#define PCI_DEVICE_ID_CIRRUS_5446      0x00b8
5072 +#define PCI_DEVICE_ID_CIRRUS_5480      0x00bc
5073 +#define PCI_DEVICE_ID_CIRRUS_5462      0x00d0
5074 +#define PCI_DEVICE_ID_CIRRUS_5464      0x00d4
5075 +#define PCI_DEVICE_ID_CIRRUS_5465      0x00d6
5076 +#define PCI_DEVICE_ID_CIRRUS_6729      0x1100
5077 +#define PCI_DEVICE_ID_CIRRUS_6832      0x1110
5078 +#define PCI_DEVICE_ID_CIRRUS_7543      0x1202
5079 +#define PCI_DEVICE_ID_CIRRUS_4610      0x6001
5080 +#define PCI_DEVICE_ID_CIRRUS_4612      0x6003
5081 +#define PCI_DEVICE_ID_CIRRUS_4615      0x6004
5082 +
5083 +#define PCI_VENDOR_ID_IBM              0x1014
5084 +#define PCI_DEVICE_ID_IBM_TR           0x0018
5085 +#define PCI_DEVICE_ID_IBM_TR_WAKE      0x003e
5086 +#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc
5087 +#define PCI_DEVICE_ID_IBM_SNIPE                0x0180
5088 +#define PCI_DEVICE_ID_IBM_CITRINE              0x028C
5089 +#define PCI_DEVICE_ID_IBM_GEMSTONE             0xB166
5090 +#define PCI_DEVICE_ID_IBM_OBSIDIAN             0x02BD
5091 +#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1        0x0031
5092 +#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2        0x0219
5093 +#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX                0x021A
5094 +#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM    0x0251
5095 +#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252
5096 +
5097 +#define PCI_VENDOR_ID_COMPEX2          0x101a /* pci.ids says "AT&T GIS (NCR)" */
5098 +#define PCI_DEVICE_ID_COMPEX2_100VG    0x0005
5099 +
5100 +#define PCI_VENDOR_ID_WD               0x101c
5101 +#define PCI_DEVICE_ID_WD_90C           0xc24a
5102 +
5103 +#define PCI_VENDOR_ID_AMI              0x101e
5104 +#define PCI_DEVICE_ID_AMI_MEGARAID3    0x1960
5105 +#define PCI_DEVICE_ID_AMI_MEGARAID     0x9010
5106 +#define PCI_DEVICE_ID_AMI_MEGARAID2    0x9060
5107 +
5108 +#define PCI_VENDOR_ID_AMD              0x1022
5109 +#define PCI_DEVICE_ID_AMD_K8_NB                0x1100
5110 +#define PCI_DEVICE_ID_AMD_K8_NB_MISC   0x1103
5111 +#define PCI_DEVICE_ID_AMD_LANCE                0x2000
5112 +#define PCI_DEVICE_ID_AMD_LANCE_HOME   0x2001
5113 +#define PCI_DEVICE_ID_AMD_SCSI         0x2020
5114 +#define PCI_DEVICE_ID_AMD_SERENADE     0x36c0
5115 +#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006
5116 +#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007
5117 +#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C
5118 +#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E
5119 +#define PCI_DEVICE_ID_AMD_COBRA_7401   0x7401
5120 +#define PCI_DEVICE_ID_AMD_VIPER_7409   0x7409
5121 +#define PCI_DEVICE_ID_AMD_VIPER_740B   0x740B
5122 +#define PCI_DEVICE_ID_AMD_VIPER_7410   0x7410
5123 +#define PCI_DEVICE_ID_AMD_VIPER_7411   0x7411
5124 +#define PCI_DEVICE_ID_AMD_VIPER_7413   0x7413
5125 +#define PCI_DEVICE_ID_AMD_VIPER_7440   0x7440
5126 +#define PCI_DEVICE_ID_AMD_OPUS_7441    0x7441
5127 +#define PCI_DEVICE_ID_AMD_OPUS_7443    0x7443
5128 +#define PCI_DEVICE_ID_AMD_VIPER_7443   0x7443
5129 +#define PCI_DEVICE_ID_AMD_OPUS_7445    0x7445
5130 +#define PCI_DEVICE_ID_AMD_8111_LPC     0x7468
5131 +#define PCI_DEVICE_ID_AMD_8111_IDE     0x7469
5132 +#define PCI_DEVICE_ID_AMD_8111_SMBUS2  0x746a
5133 +#define PCI_DEVICE_ID_AMD_8111_SMBUS   0x746b
5134 +#define PCI_DEVICE_ID_AMD_8111_AUDIO   0x746d
5135 +#define PCI_DEVICE_ID_AMD_8151_0       0x7454
5136 +#define PCI_DEVICE_ID_AMD_8131_BRIDGE  0x7450
5137 +#define PCI_DEVICE_ID_AMD_8131_APIC    0x7451
5138 +#define PCI_DEVICE_ID_AMD_8132_BRIDGE  0x7458
5139 +#define PCI_DEVICE_ID_AMD_CS5536_ISA    0x2090
5140 +#define PCI_DEVICE_ID_AMD_CS5536_FLASH  0x2091
5141 +#define PCI_DEVICE_ID_AMD_CS5536_AUDIO  0x2093
5142 +#define PCI_DEVICE_ID_AMD_CS5536_OHC    0x2094
5143 +#define PCI_DEVICE_ID_AMD_CS5536_EHC    0x2095
5144 +#define PCI_DEVICE_ID_AMD_CS5536_UDC    0x2096
5145 +#define PCI_DEVICE_ID_AMD_CS5536_UOC    0x2097
5146 +#define PCI_DEVICE_ID_AMD_CS5536_IDE    0x209A
5147 +
5148 +#define PCI_DEVICE_ID_AMD_LX_VIDEO  0x2081
5149 +#define PCI_DEVICE_ID_AMD_LX_AES    0x2082
5150 +
5151 +#define PCI_VENDOR_ID_TRIDENT          0x1023
5152 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX        0x2000
5153 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX        0x2001
5154 +#define PCI_DEVICE_ID_TRIDENT_9320     0x9320
5155 +#define PCI_DEVICE_ID_TRIDENT_9388     0x9388
5156 +#define PCI_DEVICE_ID_TRIDENT_9397     0x9397
5157 +#define PCI_DEVICE_ID_TRIDENT_939A     0x939A
5158 +#define PCI_DEVICE_ID_TRIDENT_9520     0x9520
5159 +#define PCI_DEVICE_ID_TRIDENT_9525     0x9525
5160 +#define PCI_DEVICE_ID_TRIDENT_9420     0x9420
5161 +#define PCI_DEVICE_ID_TRIDENT_9440     0x9440
5162 +#define PCI_DEVICE_ID_TRIDENT_9660     0x9660
5163 +#define PCI_DEVICE_ID_TRIDENT_9750     0x9750
5164 +#define PCI_DEVICE_ID_TRIDENT_9850     0x9850
5165 +#define PCI_DEVICE_ID_TRIDENT_9880     0x9880
5166 +#define PCI_DEVICE_ID_TRIDENT_8400     0x8400
5167 +#define PCI_DEVICE_ID_TRIDENT_8420     0x8420
5168 +#define PCI_DEVICE_ID_TRIDENT_8500     0x8500
5169 +
5170 +#define PCI_VENDOR_ID_AI               0x1025
5171 +#define PCI_DEVICE_ID_AI_M1435         0x1435
5172 +
5173 +#define PCI_VENDOR_ID_DELL             0x1028
5174 +#define PCI_DEVICE_ID_DELL_RACIII      0x0008
5175 +#define PCI_DEVICE_ID_DELL_RAC4                0x0012
5176 +#define PCI_DEVICE_ID_DELL_PERC5       0x0015
5177 +
5178 +#define PCI_VENDOR_ID_MATROX           0x102B
5179 +#define PCI_DEVICE_ID_MATROX_MGA_2     0x0518
5180 +#define PCI_DEVICE_ID_MATROX_MIL       0x0519
5181 +#define PCI_DEVICE_ID_MATROX_MYS       0x051A
5182 +#define PCI_DEVICE_ID_MATROX_MIL_2     0x051b
5183 +#define PCI_DEVICE_ID_MATROX_MYS_AGP   0x051e
5184 +#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f
5185 +#define PCI_DEVICE_ID_MATROX_MGA_IMP   0x0d10
5186 +#define PCI_DEVICE_ID_MATROX_G100_MM   0x1000
5187 +#define PCI_DEVICE_ID_MATROX_G100_AGP  0x1001
5188 +#define PCI_DEVICE_ID_MATROX_G200_PCI  0x0520
5189 +#define PCI_DEVICE_ID_MATROX_G200_AGP  0x0521
5190 +#define        PCI_DEVICE_ID_MATROX_G400       0x0525
5191 +#define PCI_DEVICE_ID_MATROX_G550      0x2527
5192 +#define PCI_DEVICE_ID_MATROX_VIA       0x4536
5193 +
5194 +#define PCI_VENDOR_ID_CT               0x102c
5195 +#define PCI_DEVICE_ID_CT_69000         0x00c0
5196 +#define PCI_DEVICE_ID_CT_65545         0x00d8
5197 +#define PCI_DEVICE_ID_CT_65548         0x00dc
5198 +#define PCI_DEVICE_ID_CT_65550         0x00e0
5199 +#define PCI_DEVICE_ID_CT_65554         0x00e4
5200 +#define PCI_DEVICE_ID_CT_65555         0x00e5
5201 +
5202 +#define PCI_VENDOR_ID_MIRO             0x1031
5203 +#define PCI_DEVICE_ID_MIRO_36050       0x5601
5204 +#define PCI_DEVICE_ID_MIRO_DC10PLUS    0x7efe
5205 +#define PCI_DEVICE_ID_MIRO_DC30PLUS    0xd801
5206 +
5207 +#define PCI_VENDOR_ID_NEC              0x1033
5208 +#define PCI_DEVICE_ID_NEC_CBUS_1       0x0001 /* PCI-Cbus Bridge */
5209 +#define PCI_DEVICE_ID_NEC_LOCAL                0x0002 /* Local Bridge */
5210 +#define PCI_DEVICE_ID_NEC_ATM          0x0003 /* ATM LAN Controller */
5211 +#define PCI_DEVICE_ID_NEC_R4000                0x0004 /* R4000 Bridge */
5212 +#define PCI_DEVICE_ID_NEC_486          0x0005 /* 486 Like Peripheral Bus Bridge */
5213 +#define PCI_DEVICE_ID_NEC_ACCEL_1      0x0006 /* Graphic Accelerator */
5214 +#define PCI_DEVICE_ID_NEC_UXBUS                0x0007 /* UX-Bus Bridge */
5215 +#define PCI_DEVICE_ID_NEC_ACCEL_2      0x0008 /* Graphic Accelerator */
5216 +#define PCI_DEVICE_ID_NEC_GRAPH                0x0009 /* PCI-CoreGraph Bridge */
5217 +#define PCI_DEVICE_ID_NEC_VL           0x0016 /* PCI-VL Bridge */
5218 +#define PCI_DEVICE_ID_NEC_STARALPHA2   0x002c /* STAR ALPHA2 */
5219 +#define PCI_DEVICE_ID_NEC_CBUS_2       0x002d /* PCI-Cbus Bridge */
5220 +#define PCI_DEVICE_ID_NEC_USB          0x0035 /* PCI-USB Host */
5221 +#define PCI_DEVICE_ID_NEC_CBUS_3       0x003b
5222 +#define PCI_DEVICE_ID_NEC_NAPCCARD     0x003e
5223 +#define PCI_DEVICE_ID_NEC_PCX2         0x0046 /* PowerVR */
5224 +#define PCI_DEVICE_ID_NEC_NILE4                0x005a
5225 +#define PCI_DEVICE_ID_NEC_VRC5476       0x009b
5226 +#define PCI_DEVICE_ID_NEC_VRC4173      0x00a5
5227 +#define PCI_DEVICE_ID_NEC_VRC5477_AC97  0x00a6
5228 +#define PCI_DEVICE_ID_NEC_PC9821CS01    0x800c /* PC-9821-CS01 */
5229 +#define PCI_DEVICE_ID_NEC_PC9821NRB06   0x800d /* PC-9821NR-B06 */
5230 +
5231 +#define PCI_VENDOR_ID_FD               0x1036
5232 +#define PCI_DEVICE_ID_FD_36C70         0x0000
5233 +
5234 +#define PCI_VENDOR_ID_SI               0x1039
5235 +#define PCI_DEVICE_ID_SI_5591_AGP      0x0001
5236 +#define PCI_DEVICE_ID_SI_6202          0x0002
5237 +#define PCI_DEVICE_ID_SI_503           0x0008
5238 +#define PCI_DEVICE_ID_SI_ACPI          0x0009
5239 +#define PCI_DEVICE_ID_SI_SMBUS         0x0016
5240 +#define PCI_DEVICE_ID_SI_LPC           0x0018
5241 +#define PCI_DEVICE_ID_SI_5597_VGA      0x0200
5242 +#define PCI_DEVICE_ID_SI_6205          0x0205
5243 +#define PCI_DEVICE_ID_SI_501           0x0406
5244 +#define PCI_DEVICE_ID_SI_496           0x0496
5245 +#define PCI_DEVICE_ID_SI_300           0x0300
5246 +#define PCI_DEVICE_ID_SI_315H          0x0310
5247 +#define PCI_DEVICE_ID_SI_315           0x0315
5248 +#define PCI_DEVICE_ID_SI_315PRO                0x0325
5249 +#define PCI_DEVICE_ID_SI_530           0x0530
5250 +#define PCI_DEVICE_ID_SI_540           0x0540
5251 +#define PCI_DEVICE_ID_SI_550           0x0550
5252 +#define PCI_DEVICE_ID_SI_540_VGA       0x5300
5253 +#define PCI_DEVICE_ID_SI_550_VGA       0x5315
5254 +#define PCI_DEVICE_ID_SI_620           0x0620
5255 +#define PCI_DEVICE_ID_SI_630           0x0630
5256 +#define PCI_DEVICE_ID_SI_633           0x0633
5257 +#define PCI_DEVICE_ID_SI_635           0x0635
5258 +#define PCI_DEVICE_ID_SI_640           0x0640
5259 +#define PCI_DEVICE_ID_SI_645           0x0645
5260 +#define PCI_DEVICE_ID_SI_646           0x0646
5261 +#define PCI_DEVICE_ID_SI_648           0x0648
5262 +#define PCI_DEVICE_ID_SI_650           0x0650
5263 +#define PCI_DEVICE_ID_SI_651           0x0651
5264 +#define PCI_DEVICE_ID_SI_655           0x0655
5265 +#define PCI_DEVICE_ID_SI_661           0x0661
5266 +#define PCI_DEVICE_ID_SI_730           0x0730
5267 +#define PCI_DEVICE_ID_SI_733           0x0733
5268 +#define PCI_DEVICE_ID_SI_630_VGA       0x6300
5269 +#define PCI_DEVICE_ID_SI_735           0x0735
5270 +#define PCI_DEVICE_ID_SI_740           0x0740
5271 +#define PCI_DEVICE_ID_SI_741           0x0741
5272 +#define PCI_DEVICE_ID_SI_745           0x0745
5273 +#define PCI_DEVICE_ID_SI_746           0x0746
5274 +#define PCI_DEVICE_ID_SI_755           0x0755
5275 +#define PCI_DEVICE_ID_SI_760           0x0760
5276 +#define PCI_DEVICE_ID_SI_900           0x0900
5277 +#define PCI_DEVICE_ID_SI_961           0x0961
5278 +#define PCI_DEVICE_ID_SI_962           0x0962
5279 +#define PCI_DEVICE_ID_SI_963           0x0963
5280 +#define PCI_DEVICE_ID_SI_965           0x0965
5281 +#define PCI_DEVICE_ID_SI_966           0x0966
5282 +#define PCI_DEVICE_ID_SI_968           0x0968
5283 +#define PCI_DEVICE_ID_SI_5511          0x5511
5284 +#define PCI_DEVICE_ID_SI_5513          0x5513
5285 +#define PCI_DEVICE_ID_SI_5517          0x5517
5286 +#define PCI_DEVICE_ID_SI_5518          0x5518
5287 +#define PCI_DEVICE_ID_SI_5571          0x5571
5288 +#define PCI_DEVICE_ID_SI_5581          0x5581
5289 +#define PCI_DEVICE_ID_SI_5582          0x5582
5290 +#define PCI_DEVICE_ID_SI_5591          0x5591
5291 +#define PCI_DEVICE_ID_SI_5596          0x5596
5292 +#define PCI_DEVICE_ID_SI_5597          0x5597
5293 +#define PCI_DEVICE_ID_SI_5598          0x5598
5294 +#define PCI_DEVICE_ID_SI_5600          0x5600
5295 +#define PCI_DEVICE_ID_SI_7012          0x7012
5296 +#define PCI_DEVICE_ID_SI_7013          0x7013
5297 +#define PCI_DEVICE_ID_SI_7016          0x7016
5298 +#define PCI_DEVICE_ID_SI_7018          0x7018
5299 +
5300 +#define PCI_VENDOR_ID_HP               0x103c
5301 +#define PCI_DEVICE_ID_HP_VISUALIZE_EG  0x1005
5302 +#define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006
5303 +#define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008
5304 +#define PCI_DEVICE_ID_HP_VISUALIZE_FX2 0x100a
5305 +#define PCI_DEVICE_ID_HP_TACHYON       0x1028
5306 +#define PCI_DEVICE_ID_HP_TACHLITE      0x1029
5307 +#define PCI_DEVICE_ID_HP_J2585A                0x1030
5308 +#define PCI_DEVICE_ID_HP_J2585B                0x1031
5309 +#define PCI_DEVICE_ID_HP_J2973A                0x1040
5310 +#define PCI_DEVICE_ID_HP_J2970A                0x1042
5311 +#define PCI_DEVICE_ID_HP_DIVA          0x1048
5312 +#define PCI_DEVICE_ID_HP_DIVA_TOSCA1   0x1049
5313 +#define PCI_DEVICE_ID_HP_DIVA_TOSCA2   0x104A
5314 +#define PCI_DEVICE_ID_HP_DIVA_MAESTRO  0x104B
5315 +#define PCI_DEVICE_ID_HP_REO_IOC       0x10f1
5316 +#define PCI_DEVICE_ID_HP_VISUALIZE_FXE 0x108b
5317 +#define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223
5318 +#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226
5319 +#define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227
5320 +#define PCI_DEVICE_ID_HP_ZX1_IOC       0x122a
5321 +#define PCI_DEVICE_ID_HP_PCIX_LBA      0x122e
5322 +#define PCI_DEVICE_ID_HP_SX1000_IOC    0x127c
5323 +#define PCI_DEVICE_ID_HP_DIVA_EVEREST  0x1282
5324 +#define PCI_DEVICE_ID_HP_DIVA_AUX      0x1290
5325 +#define PCI_DEVICE_ID_HP_DIVA_RMP3     0x1301
5326 +#define PCI_DEVICE_ID_HP_DIVA_HURRICANE        0x132a
5327 +#define PCI_DEVICE_ID_HP_CISSA         0x3220
5328 +#define PCI_DEVICE_ID_HP_CISSC         0x3230
5329 +#define PCI_DEVICE_ID_HP_CISSD         0x3238
5330 +#define PCI_DEVICE_ID_HP_ZX2_IOC       0x4031
5331 +
5332 +#define PCI_VENDOR_ID_PCTECH           0x1042
5333 +#define PCI_DEVICE_ID_PCTECH_RZ1000    0x1000
5334 +#define PCI_DEVICE_ID_PCTECH_RZ1001    0x1001
5335 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
5336 +
5337 +#define PCI_VENDOR_ID_ASUSTEK          0x1043
5338 +#define PCI_DEVICE_ID_ASUSTEK_0675     0x0675
5339 +
5340 +#define PCI_VENDOR_ID_DPT              0x1044
5341 +#define PCI_DEVICE_ID_DPT              0xa400
5342 +
5343 +#define PCI_VENDOR_ID_OPTI             0x1045
5344 +#define PCI_DEVICE_ID_OPTI_82C558      0xc558
5345 +#define PCI_DEVICE_ID_OPTI_82C621      0xc621
5346 +#define PCI_DEVICE_ID_OPTI_82C700      0xc700
5347 +#define PCI_DEVICE_ID_OPTI_82C825      0xd568
5348 +
5349 +#define PCI_VENDOR_ID_ELSA             0x1048
5350 +#define PCI_DEVICE_ID_ELSA_MICROLINK   0x1000
5351 +#define PCI_DEVICE_ID_ELSA_QS3000      0x3000
5352 +
5353 +
5354 +#define PCI_VENDOR_ID_BUSLOGIC               0x104B
5355 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
5356 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER    0x1040
5357 +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130
5358 +
5359 +#define PCI_VENDOR_ID_TI               0x104c
5360 +#define PCI_DEVICE_ID_TI_TVP4020       0x3d07
5361 +#define PCI_DEVICE_ID_TI_4450          0x8011
5362 +#define PCI_DEVICE_ID_TI_XX21_XX11     0x8031
5363 +#define PCI_DEVICE_ID_TI_XX21_XX11_SD  0x8034
5364 +#define PCI_DEVICE_ID_TI_X515          0x8036
5365 +#define PCI_DEVICE_ID_TI_XX12          0x8039
5366 +#define PCI_DEVICE_ID_TI_1130          0xac12
5367 +#define PCI_DEVICE_ID_TI_1031          0xac13
5368 +#define PCI_DEVICE_ID_TI_1131          0xac15
5369 +#define PCI_DEVICE_ID_TI_1250          0xac16
5370 +#define PCI_DEVICE_ID_TI_1220          0xac17
5371 +#define PCI_DEVICE_ID_TI_1221          0xac19
5372 +#define PCI_DEVICE_ID_TI_1210          0xac1a
5373 +#define PCI_DEVICE_ID_TI_1450          0xac1b
5374 +#define PCI_DEVICE_ID_TI_1225          0xac1c
5375 +#define PCI_DEVICE_ID_TI_1251A         0xac1d
5376 +#define PCI_DEVICE_ID_TI_1211          0xac1e
5377 +#define PCI_DEVICE_ID_TI_1251B         0xac1f
5378 +#define PCI_DEVICE_ID_TI_4410          0xac41
5379 +#define PCI_DEVICE_ID_TI_4451          0xac42
5380 +#define PCI_DEVICE_ID_TI_4510          0xac44
5381 +#define PCI_DEVICE_ID_TI_4520          0xac46
5382 +#define PCI_DEVICE_ID_TI_7510          0xac47
5383 +#define PCI_DEVICE_ID_TI_7610          0xac48
5384 +#define PCI_DEVICE_ID_TI_7410          0xac49
5385 +#define PCI_DEVICE_ID_TI_1410          0xac50
5386 +#define PCI_DEVICE_ID_TI_1420          0xac51
5387 +#define PCI_DEVICE_ID_TI_1451A         0xac52
5388 +#define PCI_DEVICE_ID_TI_1620          0xac54
5389 +#define PCI_DEVICE_ID_TI_1520          0xac55
5390 +#define PCI_DEVICE_ID_TI_1510          0xac56
5391 +#define PCI_DEVICE_ID_TI_X620          0xac8d
5392 +#define PCI_DEVICE_ID_TI_X420          0xac8e
5393 +
5394 +#define PCI_VENDOR_ID_SONY             0x104d
5395 +
5396 +
5397 +/* Winbond have two vendor IDs! See 0x10ad as well */
5398 +#define PCI_VENDOR_ID_WINBOND2         0x1050
5399 +#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a
5400 +#define PCI_DEVICE_ID_WINBOND2_6692    0x6692
5401 +
5402 +#define PCI_VENDOR_ID_ANIGMA           0x1051
5403 +#define PCI_DEVICE_ID_ANIGMA_MC145575  0x0100
5404 +
5405 +#define PCI_VENDOR_ID_EFAR             0x1055
5406 +#define PCI_DEVICE_ID_EFAR_SLC90E66_1  0x9130
5407 +#define PCI_DEVICE_ID_EFAR_SLC90E66_3  0x9463
5408 +
5409 +#define PCI_VENDOR_ID_MOTOROLA         0x1057
5410 +#define PCI_DEVICE_ID_MOTOROLA_MPC105  0x0001
5411 +#define PCI_DEVICE_ID_MOTOROLA_MPC106  0x0002
5412 +#define PCI_DEVICE_ID_MOTOROLA_MPC107  0x0004
5413 +#define PCI_DEVICE_ID_MOTOROLA_RAVEN   0x4801
5414 +#define PCI_DEVICE_ID_MOTOROLA_FALCON  0x4802
5415 +#define PCI_DEVICE_ID_MOTOROLA_HAWK    0x4803
5416 +#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b
5417 +#define PCI_DEVICE_ID_MOTOROLA_MPC5200 0x5803
5418 +#define PCI_DEVICE_ID_MOTOROLA_MPC5200B        0x5809
5419 +
5420 +#define PCI_VENDOR_ID_PROMISE          0x105a
5421 +#define PCI_DEVICE_ID_PROMISE_20265    0x0d30
5422 +#define PCI_DEVICE_ID_PROMISE_20267    0x4d30
5423 +#define PCI_DEVICE_ID_PROMISE_20246    0x4d33
5424 +#define PCI_DEVICE_ID_PROMISE_20262    0x4d38
5425 +#define PCI_DEVICE_ID_PROMISE_20263    0x0D38
5426 +#define PCI_DEVICE_ID_PROMISE_20268    0x4d68
5427 +#define PCI_DEVICE_ID_PROMISE_20269    0x4d69
5428 +#define PCI_DEVICE_ID_PROMISE_20270    0x6268
5429 +#define PCI_DEVICE_ID_PROMISE_20271    0x6269
5430 +#define PCI_DEVICE_ID_PROMISE_20275    0x1275
5431 +#define PCI_DEVICE_ID_PROMISE_20276    0x5275
5432 +#define PCI_DEVICE_ID_PROMISE_20277    0x7275
5433 +
5434 +
5435 +#define PCI_VENDOR_ID_UMC              0x1060
5436 +#define PCI_DEVICE_ID_UMC_UM8673F      0x0101
5437 +#define PCI_DEVICE_ID_UMC_UM8886BF     0x673a
5438 +#define PCI_DEVICE_ID_UMC_UM8886A      0x886a
5439 +
5440 +
5441 +#define PCI_VENDOR_ID_MYLEX            0x1069
5442 +#define PCI_DEVICE_ID_MYLEX_DAC960_P   0x0001
5443 +#define PCI_DEVICE_ID_MYLEX_DAC960_PD  0x0002
5444 +#define PCI_DEVICE_ID_MYLEX_DAC960_PG  0x0010
5445 +#define PCI_DEVICE_ID_MYLEX_DAC960_LA  0x0020
5446 +#define PCI_DEVICE_ID_MYLEX_DAC960_LP  0x0050
5447 +#define PCI_DEVICE_ID_MYLEX_DAC960_BA  0xBA56
5448 +#define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166
5449 +
5450 +
5451 +#define PCI_VENDOR_ID_APPLE            0x106b
5452 +#define PCI_DEVICE_ID_APPLE_BANDIT     0x0001
5453 +#define PCI_DEVICE_ID_APPLE_HYDRA      0x000e
5454 +#define PCI_DEVICE_ID_APPLE_UNI_N_FW   0x0018
5455 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP  0x0020
5456 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021
5457 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP        0x0024
5458 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P        0x0027
5459 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15        0x002d
5460 +#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15        0x002e
5461 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2        0x0032
5462 +#define PCI_DEVICE_ID_APPLE_UNI_N_ATA  0x0033
5463 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034
5464 +#define PCI_DEVICE_ID_APPLE_IPID_ATA100        0x003b
5465 +#define PCI_DEVICE_ID_APPLE_K2_ATA100  0x0043
5466 +#define PCI_DEVICE_ID_APPLE_U3_AGP     0x004b
5467 +#define PCI_DEVICE_ID_APPLE_K2_GMAC    0x004c
5468 +#define PCI_DEVICE_ID_APPLE_SH_ATA      0x0050
5469 +#define PCI_DEVICE_ID_APPLE_SH_SUNGEM   0x0051
5470 +#define PCI_DEVICE_ID_APPLE_U3L_AGP    0x0058
5471 +#define PCI_DEVICE_ID_APPLE_U3H_AGP    0x0059
5472 +#define PCI_DEVICE_ID_APPLE_IPID2_AGP  0x0066
5473 +#define PCI_DEVICE_ID_APPLE_IPID2_ATA  0x0069
5474 +#define PCI_DEVICE_ID_APPLE_IPID2_FW   0x006a
5475 +#define PCI_DEVICE_ID_APPLE_IPID2_GMAC 0x006b
5476 +#define PCI_DEVICE_ID_APPLE_TIGON3     0x1645
5477 +
5478 +#define PCI_VENDOR_ID_YAMAHA           0x1073
5479 +#define PCI_DEVICE_ID_YAMAHA_724       0x0004
5480 +#define PCI_DEVICE_ID_YAMAHA_724F      0x000d
5481 +#define PCI_DEVICE_ID_YAMAHA_740       0x000a
5482 +#define PCI_DEVICE_ID_YAMAHA_740C      0x000c
5483 +#define PCI_DEVICE_ID_YAMAHA_744       0x0010
5484 +#define PCI_DEVICE_ID_YAMAHA_754       0x0012
5485 +
5486 +
5487 +#define PCI_VENDOR_ID_QLOGIC           0x1077
5488 +#define PCI_DEVICE_ID_QLOGIC_ISP10160  0x1016
5489 +#define PCI_DEVICE_ID_QLOGIC_ISP1020   0x1020
5490 +#define PCI_DEVICE_ID_QLOGIC_ISP1080   0x1080
5491 +#define PCI_DEVICE_ID_QLOGIC_ISP12160  0x1216
5492 +#define PCI_DEVICE_ID_QLOGIC_ISP1240   0x1240
5493 +#define PCI_DEVICE_ID_QLOGIC_ISP1280   0x1280
5494 +#define PCI_DEVICE_ID_QLOGIC_ISP2100   0x2100
5495 +#define PCI_DEVICE_ID_QLOGIC_ISP2200   0x2200
5496 +#define PCI_DEVICE_ID_QLOGIC_ISP2300   0x2300
5497 +#define PCI_DEVICE_ID_QLOGIC_ISP2312   0x2312
5498 +#define PCI_DEVICE_ID_QLOGIC_ISP2322   0x2322
5499 +#define PCI_DEVICE_ID_QLOGIC_ISP6312   0x6312
5500 +#define PCI_DEVICE_ID_QLOGIC_ISP6322   0x6322
5501 +#define PCI_DEVICE_ID_QLOGIC_ISP2422   0x2422
5502 +#define PCI_DEVICE_ID_QLOGIC_ISP2432   0x2432
5503 +#define PCI_DEVICE_ID_QLOGIC_ISP2512   0x2512
5504 +#define PCI_DEVICE_ID_QLOGIC_ISP2522   0x2522
5505 +#define PCI_DEVICE_ID_QLOGIC_ISP5422   0x5422
5506 +#define PCI_DEVICE_ID_QLOGIC_ISP5432   0x5432
5507 +
5508 +#define PCI_VENDOR_ID_CYRIX            0x1078
5509 +#define PCI_DEVICE_ID_CYRIX_5510       0x0000
5510 +#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001
5511 +#define PCI_DEVICE_ID_CYRIX_5520       0x0002
5512 +#define PCI_DEVICE_ID_CYRIX_5530_LEGACY        0x0100
5513 +#define PCI_DEVICE_ID_CYRIX_5530_IDE   0x0102
5514 +#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103
5515 +#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104
5516 +
5517 +
5518 +
5519 +#define PCI_VENDOR_ID_CONTAQ           0x1080
5520 +#define PCI_DEVICE_ID_CONTAQ_82C693    0xc693
5521 +
5522 +
5523 +#define PCI_VENDOR_ID_OLICOM           0x108d
5524 +#define PCI_DEVICE_ID_OLICOM_OC2325    0x0012
5525 +#define PCI_DEVICE_ID_OLICOM_OC2183    0x0013
5526 +#define PCI_DEVICE_ID_OLICOM_OC2326    0x0014
5527 +
5528 +#define PCI_VENDOR_ID_SUN              0x108e
5529 +#define PCI_DEVICE_ID_SUN_EBUS         0x1000
5530 +#define PCI_DEVICE_ID_SUN_HAPPYMEAL    0x1001
5531 +#define PCI_DEVICE_ID_SUN_RIO_EBUS     0x1100
5532 +#define PCI_DEVICE_ID_SUN_RIO_GEM      0x1101
5533 +#define PCI_DEVICE_ID_SUN_RIO_1394     0x1102
5534 +#define PCI_DEVICE_ID_SUN_RIO_USB      0x1103
5535 +#define PCI_DEVICE_ID_SUN_GEM          0x2bad
5536 +#define PCI_DEVICE_ID_SUN_SIMBA                0x5000
5537 +#define PCI_DEVICE_ID_SUN_PBM          0x8000
5538 +#define PCI_DEVICE_ID_SUN_SCHIZO       0x8001
5539 +#define PCI_DEVICE_ID_SUN_SABRE                0xa000
5540 +#define PCI_DEVICE_ID_SUN_HUMMINGBIRD  0xa001
5541 +#define PCI_DEVICE_ID_SUN_TOMATILLO    0xa801
5542 +#define PCI_DEVICE_ID_SUN_CASSINI      0xabba
5543 +
5544 +#define PCI_VENDOR_ID_CMD              0x1095
5545 +#define PCI_DEVICE_ID_CMD_643          0x0643
5546 +#define PCI_DEVICE_ID_CMD_646          0x0646
5547 +#define PCI_DEVICE_ID_CMD_648          0x0648
5548 +#define PCI_DEVICE_ID_CMD_649          0x0649
5549 +
5550 +#define PCI_DEVICE_ID_SII_680          0x0680
5551 +#define PCI_DEVICE_ID_SII_3112         0x3112
5552 +#define PCI_DEVICE_ID_SII_1210SA       0x0240
5553 +
5554 +
5555 +#define PCI_VENDOR_ID_BROOKTREE                0x109e
5556 +#define PCI_DEVICE_ID_BROOKTREE_878    0x0878
5557 +#define PCI_DEVICE_ID_BROOKTREE_879    0x0879
5558 +
5559 +
5560 +#define PCI_VENDOR_ID_SGI              0x10a9
5561 +#define PCI_DEVICE_ID_SGI_IOC3         0x0003
5562 +#define PCI_DEVICE_ID_SGI_IOC4         0x100a
5563 +#define PCI_VENDOR_ID_SGI_LITHIUM      0x1002
5564 +
5565 +
5566 +#define PCI_VENDOR_ID_WINBOND          0x10ad
5567 +#define PCI_DEVICE_ID_WINBOND_82C105   0x0105
5568 +#define PCI_DEVICE_ID_WINBOND_83C553   0x0565
5569 +
5570 +
5571 +#define PCI_VENDOR_ID_PLX              0x10b5
5572 +#define PCI_DEVICE_ID_PLX_R685         0x1030
5573 +#define PCI_DEVICE_ID_PLX_ROMULUS      0x106a
5574 +#define PCI_DEVICE_ID_PLX_SPCOM800     0x1076
5575 +#define PCI_DEVICE_ID_PLX_1077         0x1077
5576 +#define PCI_DEVICE_ID_PLX_SPCOM200     0x1103
5577 +#define PCI_DEVICE_ID_PLX_DJINN_ITOO   0x1151
5578 +#define PCI_DEVICE_ID_PLX_R753         0x1152
5579 +#define PCI_DEVICE_ID_PLX_OLITEC       0x1187
5580 +#define PCI_DEVICE_ID_PLX_PCI200SYN    0x3196
5581 +#define PCI_DEVICE_ID_PLX_9050         0x9050
5582 +#define PCI_DEVICE_ID_PLX_9080         0x9080
5583 +#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001
5584 +
5585 +#define PCI_VENDOR_ID_MADGE            0x10b6
5586 +#define PCI_DEVICE_ID_MADGE_MK2                0x0002
5587 +
5588 +#define PCI_VENDOR_ID_3COM             0x10b7
5589 +#define PCI_DEVICE_ID_3COM_3C985       0x0001
5590 +#define PCI_DEVICE_ID_3COM_3C940       0x1700
5591 +#define PCI_DEVICE_ID_3COM_3C339       0x3390
5592 +#define PCI_DEVICE_ID_3COM_3C359       0x3590
5593 +#define PCI_DEVICE_ID_3COM_3C940B      0x80eb
5594 +#define PCI_DEVICE_ID_3COM_3CR990      0x9900
5595 +#define PCI_DEVICE_ID_3COM_3CR990_TX_95        0x9902
5596 +#define PCI_DEVICE_ID_3COM_3CR990_TX_97        0x9903
5597 +#define PCI_DEVICE_ID_3COM_3CR990B     0x9904
5598 +#define PCI_DEVICE_ID_3COM_3CR990_FX   0x9905
5599 +#define PCI_DEVICE_ID_3COM_3CR990SVR95 0x9908
5600 +#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909
5601 +#define PCI_DEVICE_ID_3COM_3CR990SVR   0x990a
5602 +
5603 +
5604 +#define PCI_VENDOR_ID_AL               0x10b9
5605 +#define PCI_DEVICE_ID_AL_M1533         0x1533
5606 +#define PCI_DEVICE_ID_AL_M1535                 0x1535
5607 +#define PCI_DEVICE_ID_AL_M1541         0x1541
5608 +#define PCI_DEVICE_ID_AL_M1563         0x1563
5609 +#define PCI_DEVICE_ID_AL_M1621         0x1621
5610 +#define PCI_DEVICE_ID_AL_M1631         0x1631
5611 +#define PCI_DEVICE_ID_AL_M1632         0x1632
5612 +#define PCI_DEVICE_ID_AL_M1641         0x1641
5613 +#define PCI_DEVICE_ID_AL_M1644         0x1644
5614 +#define PCI_DEVICE_ID_AL_M1647         0x1647
5615 +#define PCI_DEVICE_ID_AL_M1651         0x1651
5616 +#define PCI_DEVICE_ID_AL_M1671         0x1671
5617 +#define PCI_DEVICE_ID_AL_M1681         0x1681
5618 +#define PCI_DEVICE_ID_AL_M1683         0x1683
5619 +#define PCI_DEVICE_ID_AL_M1689         0x1689
5620 +#define PCI_DEVICE_ID_AL_M5219         0x5219
5621 +#define PCI_DEVICE_ID_AL_M5228         0x5228
5622 +#define PCI_DEVICE_ID_AL_M5229         0x5229
5623 +#define PCI_DEVICE_ID_AL_M5451         0x5451
5624 +#define PCI_DEVICE_ID_AL_M7101         0x7101
5625 +
5626 +
5627 +
5628 +#define PCI_VENDOR_ID_NEOMAGIC         0x10c8
5629 +#define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005
5630 +#define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006
5631 +#define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016
5632 +
5633 +
5634 +#define PCI_VENDOR_ID_TCONRAD          0x10da
5635 +#define PCI_DEVICE_ID_TCONRAD_TOKENRING        0x0508
5636 +
5637 +
5638 +#define PCI_VENDOR_ID_NVIDIA                   0x10de
5639 +#define PCI_DEVICE_ID_NVIDIA_TNT               0x0020
5640 +#define PCI_DEVICE_ID_NVIDIA_TNT2              0x0028
5641 +#define PCI_DEVICE_ID_NVIDIA_UTNT2             0x0029
5642 +#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN        0x002a
5643 +#define PCI_DEVICE_ID_NVIDIA_VTNT2             0x002C
5644 +#define PCI_DEVICE_ID_NVIDIA_UVTNT2            0x002D
5645 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS        0x0034
5646 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE  0x0035
5647 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA 0x0036
5648 +#define PCI_DEVICE_ID_NVIDIA_NVENET_10         0x0037
5649 +#define PCI_DEVICE_ID_NVIDIA_NVENET_11         0x0038
5650 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2        0x003e
5651 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040
5652 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800       0x0041
5653 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE    0x0042
5654 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT    0x0045
5655 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000     0x004E
5656 +#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS     0x0052
5657 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE  0x0053
5658 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA 0x0054
5659 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2        0x0055
5660 +#define PCI_DEVICE_ID_NVIDIA_NVENET_8          0x0056
5661 +#define PCI_DEVICE_ID_NVIDIA_NVENET_9          0x0057
5662 +#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO       0x0059
5663 +#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE                0x005d
5664 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS     0x0064
5665 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE       0x0065
5666 +#define PCI_DEVICE_ID_NVIDIA_NVENET_2          0x0066
5667 +#define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM                0x0069
5668 +#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO                0x006a
5669 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS    0x0084
5670 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE      0x0085
5671 +#define PCI_DEVICE_ID_NVIDIA_NVENET_4          0x0086
5672 +#define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM       0x0089
5673 +#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO         0x008a
5674 +#define PCI_DEVICE_ID_NVIDIA_NVENET_5          0x008c
5675 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA     0x008e
5676 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT   0x0090
5677 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX  0x0091
5678 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800   0x0098
5679 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX 0x0099
5680 +#define PCI_DEVICE_ID_NVIDIA_ITNT2             0x00A0
5681 +#define PCI_DEVICE_ID_GEFORCE_6800A             0x00c1
5682 +#define PCI_DEVICE_ID_GEFORCE_6800A_LE          0x00c2
5683 +#define PCI_DEVICE_ID_GEFORCE_GO_6800           0x00c8
5684 +#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA     0x00c9
5685 +#define PCI_DEVICE_ID_QUADRO_FX_GO1400          0x00cc
5686 +#define PCI_DEVICE_ID_QUADRO_FX_1400            0x00ce
5687 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3           0x00d1
5688 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS     0x00d4
5689 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE       0x00d5
5690 +#define PCI_DEVICE_ID_NVIDIA_NVENET_3          0x00d6
5691 +#define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM                0x00d9
5692 +#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO                0x00da
5693 +#define PCI_DEVICE_ID_NVIDIA_NVENET_7          0x00df
5694 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S          0x00e1
5695 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA     0x00e3
5696 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS    0x00e4
5697 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE      0x00e5
5698 +#define PCI_DEVICE_ID_NVIDIA_NVENET_6          0x00e6
5699 +#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO                0x00ea
5700 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2    0x00ee
5701 +#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1 0x00f0
5702 +#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1 0x00f1
5703 +#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2 0x00f2
5704 +#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1 0x00f3
5705 +#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT   0x00f9
5706 +#define PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280    0x00fd
5707 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR       0x0100
5708 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR       0x0101
5709 +#define PCI_DEVICE_ID_NVIDIA_QUADRO            0x0103
5710 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX       0x0110
5711 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2      0x0111
5712 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO       0x0112
5713 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR       0x0113
5714 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT   0x0140
5715 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600      0x0141
5716 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL   0x0145
5717 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540     0x014E
5718 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200      0x014F
5719 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS      0x0150
5720 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2     0x0151
5721 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA    0x0152
5722 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO       0x0153
5723 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161
5724 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200    0x0164
5725 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250    0x0166
5726 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1  0x0167
5727 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1  0x0168
5728 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460   0x0170
5729 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440   0x0171
5730 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420   0x0172
5731 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE        0x0173
5732 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO   0x0174
5733 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO   0x0175
5734 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176
5735 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO    0x0177
5736 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL    0x0178
5737 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179
5738 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200       0x017A
5739 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL    0x017B
5740 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL  0x017C
5741 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D
5742 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181
5743 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182
5744 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183
5745 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000   0x0185
5746 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO    0x0186
5747 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO    0x0187
5748 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL    0x0188
5749 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC    0x0189
5750 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS    0x018A
5751 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL    0x018B
5752 +#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2         0x01a0
5753 +#define PCI_DEVICE_ID_NVIDIA_NFORCE            0x01a4
5754 +#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO                0x01b1
5755 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS      0x01b4
5756 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE                0x01bc
5757 +#define PCI_DEVICE_ID_NVIDIA_MCP1_MODEM                0x01c1
5758 +#define PCI_DEVICE_ID_NVIDIA_NVENET_1          0x01c3
5759 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2           0x01e0
5760 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3          0x0200
5761 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1                0x0201
5762 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2                0x0202
5763 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC                0x0203
5764 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B      0x0211
5765 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE   0x0212
5766 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT   0x0215
5767 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600  0x0250
5768 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400  0x0251
5769 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200  0x0253
5770 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL    0x0258
5771 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL    0x0259
5772 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL    0x025B
5773 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS        0x0264
5774 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE  0x0265
5775 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA 0x0266
5776 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2        0x0267
5777 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS        0x0368
5778 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE  0x036E
5779 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA 0x037E
5780 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2        0x037F
5781 +#define PCI_DEVICE_ID_NVIDIA_NVENET_12         0x0268
5782 +#define PCI_DEVICE_ID_NVIDIA_NVENET_13         0x0269
5783 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800  0x0280
5784 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X    0x0281
5785 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE     0x0282
5786 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO       0x0286
5787 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL        0x0288
5788 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL        0x0289
5789 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL       0x028C
5790 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA  0x0301
5791 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800        0x0302
5792 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000         0x0308
5793 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000         0x0309
5794 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA  0x0311
5795 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600        0x0312
5796 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE      0x0314
5797 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600      0x031A
5798 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650      0x031B
5799 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700        0x031C
5800 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200        0x0320
5801 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA  0x0321
5802 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1      0x0322
5803 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE      0x0323
5804 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200      0x0324
5805 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250      0x0325
5806 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500        0x0326
5807 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100        0x0327
5808 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32   0x0328
5809 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200            0x0329
5810 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI     0x032A
5811 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500          0x032B
5812 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300      0x032C
5813 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100      0x032D
5814 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA  0x0330
5815 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900        0x0331
5816 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT      0x0332
5817 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA  0x0333
5818 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT      0x0334
5819 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000         0x0338
5820 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700          0x033F
5821 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA  0x0341
5822 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700        0x0342
5823 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE      0x0343
5824 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE      0x0344
5825 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1    0x0347
5826 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2    0x0348
5827 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000       0x034C
5828 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100         0x034E
5829 +#define PCI_DEVICE_ID_NVIDIA_NVENET_14              0x0372
5830 +#define PCI_DEVICE_ID_NVIDIA_NVENET_15              0x0373
5831 +#define PCI_DEVICE_ID_NVIDIA_NVENET_16              0x03E5
5832 +#define PCI_DEVICE_ID_NVIDIA_NVENET_17              0x03E6
5833 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA      0x03E7
5834 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE       0x03EC
5835 +#define PCI_DEVICE_ID_NVIDIA_NVENET_18              0x03EE
5836 +#define PCI_DEVICE_ID_NVIDIA_NVENET_19              0x03EF
5837 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2     0x03F6
5838 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3     0x03F7
5839 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE      0x0448
5840 +#define PCI_DEVICE_ID_NVIDIA_NVENET_20              0x0450
5841 +#define PCI_DEVICE_ID_NVIDIA_NVENET_21              0x0451
5842 +#define PCI_DEVICE_ID_NVIDIA_NVENET_22              0x0452
5843 +#define PCI_DEVICE_ID_NVIDIA_NVENET_23              0x0453
5844 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE       0x0560
5845 +
5846 +#define PCI_VENDOR_ID_IMS              0x10e0
5847 +#define PCI_DEVICE_ID_IMS_TT128                0x9128
5848 +#define PCI_DEVICE_ID_IMS_TT3D         0x9135
5849 +
5850 +
5851 +
5852 +
5853 +#define PCI_VENDOR_ID_INTERG           0x10ea
5854 +#define PCI_DEVICE_ID_INTERG_1682      0x1682
5855 +#define PCI_DEVICE_ID_INTERG_2000      0x2000
5856 +#define PCI_DEVICE_ID_INTERG_2010      0x2010
5857 +#define PCI_DEVICE_ID_INTERG_5000      0x5000
5858 +#define PCI_DEVICE_ID_INTERG_5050      0x5050
5859 +
5860 +#define PCI_VENDOR_ID_REALTEK          0x10ec
5861 +#define PCI_DEVICE_ID_REALTEK_8139     0x8139
5862 +
5863 +#define PCI_VENDOR_ID_XILINX           0x10ee
5864 +#define PCI_DEVICE_ID_RME_DIGI96       0x3fc0
5865 +#define PCI_DEVICE_ID_RME_DIGI96_8     0x3fc1
5866 +#define PCI_DEVICE_ID_RME_DIGI96_8_PRO 0x3fc2
5867 +#define PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST 0x3fc3
5868 +#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
5869 +#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6
5870 +
5871 +
5872 +#define PCI_VENDOR_ID_INIT             0x1101
5873 +
5874 +#define PCI_VENDOR_ID_CREATIVE         0x1102 /* duplicate: ECTIVA */
5875 +#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002
5876 +
5877 +#define PCI_VENDOR_ID_ECTIVA           0x1102 /* duplicate: CREATIVE */
5878 +#define PCI_DEVICE_ID_ECTIVA_EV1938    0x8938
5879 +
5880 +#define PCI_VENDOR_ID_TTI              0x1103
5881 +#define PCI_DEVICE_ID_TTI_HPT343       0x0003
5882 +#define PCI_DEVICE_ID_TTI_HPT366       0x0004
5883 +#define PCI_DEVICE_ID_TTI_HPT372       0x0005
5884 +#define PCI_DEVICE_ID_TTI_HPT302       0x0006
5885 +#define PCI_DEVICE_ID_TTI_HPT371       0x0007
5886 +#define PCI_DEVICE_ID_TTI_HPT374       0x0008
5887 +#define PCI_DEVICE_ID_TTI_HPT372N      0x0009  /* apparently a 372N variant? */
5888 +
5889 +#define PCI_VENDOR_ID_VIA              0x1106
5890 +#define PCI_DEVICE_ID_VIA_8763_0       0x0198
5891 +#define PCI_DEVICE_ID_VIA_8380_0       0x0204
5892 +#define PCI_DEVICE_ID_VIA_3238_0       0x0238
5893 +#define PCI_DEVICE_ID_VIA_PT880                0x0258
5894 +#define PCI_DEVICE_ID_VIA_PT880ULTRA   0x0308
5895 +#define PCI_DEVICE_ID_VIA_PX8X0_0      0x0259
5896 +#define PCI_DEVICE_ID_VIA_3269_0       0x0269
5897 +#define PCI_DEVICE_ID_VIA_K8T800PRO_0  0x0282
5898 +#define PCI_DEVICE_ID_VIA_3296_0       0x0296
5899 +#define PCI_DEVICE_ID_VIA_8363_0       0x0305
5900 +#define PCI_DEVICE_ID_VIA_P4M800CE     0x0314
5901 +#define PCI_DEVICE_ID_VIA_8371_0       0x0391
5902 +#define PCI_DEVICE_ID_VIA_8501_0       0x0501
5903 +#define PCI_DEVICE_ID_VIA_82C561       0x0561
5904 +#define PCI_DEVICE_ID_VIA_82C586_1     0x0571
5905 +#define PCI_DEVICE_ID_VIA_82C576       0x0576
5906 +#define PCI_DEVICE_ID_VIA_SATA_EIDE    0x0581
5907 +#define PCI_DEVICE_ID_VIA_82C586_0     0x0586
5908 +#define PCI_DEVICE_ID_VIA_82C596       0x0596
5909 +#define PCI_DEVICE_ID_VIA_82C597_0     0x0597
5910 +#define PCI_DEVICE_ID_VIA_82C598_0     0x0598
5911 +#define PCI_DEVICE_ID_VIA_8601_0       0x0601
5912 +#define PCI_DEVICE_ID_VIA_8605_0       0x0605
5913 +#define PCI_DEVICE_ID_VIA_82C686       0x0686
5914 +#define PCI_DEVICE_ID_VIA_82C691_0     0x0691
5915 +#define PCI_DEVICE_ID_VIA_82C576_1     0x1571
5916 +#define PCI_DEVICE_ID_VIA_82C586_2     0x3038
5917 +#define PCI_DEVICE_ID_VIA_82C586_3     0x3040
5918 +#define PCI_DEVICE_ID_VIA_82C596_3     0x3050
5919 +#define PCI_DEVICE_ID_VIA_82C596B_3    0x3051
5920 +#define PCI_DEVICE_ID_VIA_82C686_4     0x3057
5921 +#define PCI_DEVICE_ID_VIA_82C686_5     0x3058
5922 +#define PCI_DEVICE_ID_VIA_8233_5       0x3059
5923 +#define PCI_DEVICE_ID_VIA_8233_0       0x3074
5924 +#define PCI_DEVICE_ID_VIA_8633_0       0x3091
5925 +#define PCI_DEVICE_ID_VIA_8367_0       0x3099
5926 +#define PCI_DEVICE_ID_VIA_8653_0       0x3101
5927 +#define PCI_DEVICE_ID_VIA_8622         0x3102
5928 +#define PCI_DEVICE_ID_VIA_8235_USB_2   0x3104
5929 +#define PCI_DEVICE_ID_VIA_8233C_0      0x3109
5930 +#define PCI_DEVICE_ID_VIA_8361         0x3112
5931 +#define PCI_DEVICE_ID_VIA_XM266                0x3116
5932 +#define PCI_DEVICE_ID_VIA_612X         0x3119
5933 +#define PCI_DEVICE_ID_VIA_862X_0       0x3123
5934 +#define PCI_DEVICE_ID_VIA_8753_0       0x3128
5935 +#define PCI_DEVICE_ID_VIA_8233A                0x3147
5936 +#define PCI_DEVICE_ID_VIA_8703_51_0    0x3148
5937 +#define PCI_DEVICE_ID_VIA_8237_SATA    0x3149
5938 +#define PCI_DEVICE_ID_VIA_XN266                0x3156
5939 +#define PCI_DEVICE_ID_VIA_6410         0x3164
5940 +#define PCI_DEVICE_ID_VIA_8754C_0      0x3168
5941 +#define PCI_DEVICE_ID_VIA_8235         0x3177
5942 +#define PCI_DEVICE_ID_VIA_8385_0       0x3188
5943 +#define PCI_DEVICE_ID_VIA_8377_0       0x3189
5944 +#define PCI_DEVICE_ID_VIA_8378_0       0x3205
5945 +#define PCI_DEVICE_ID_VIA_8783_0       0x3208
5946 +#define PCI_DEVICE_ID_VIA_8237         0x3227
5947 +#define PCI_DEVICE_ID_VIA_8251         0x3287
5948 +#define PCI_DEVICE_ID_VIA_8237A                0x3337
5949 +#define PCI_DEVICE_ID_VIA_8231         0x8231
5950 +#define PCI_DEVICE_ID_VIA_8231_4       0x8235
5951 +#define PCI_DEVICE_ID_VIA_8365_1       0x8305
5952 +#define PCI_DEVICE_ID_VIA_CX700                0x8324
5953 +#define PCI_DEVICE_ID_VIA_8371_1       0x8391
5954 +#define PCI_DEVICE_ID_VIA_82C598_1     0x8598
5955 +#define PCI_DEVICE_ID_VIA_838X_1       0xB188
5956 +#define PCI_DEVICE_ID_VIA_83_87XX_1    0xB198
5957 +
5958 +#define PCI_VENDOR_ID_SIEMENS           0x110A
5959 +#define PCI_DEVICE_ID_SIEMENS_DSCC4     0x2102
5960 +
5961 +
5962 +#define PCI_VENDOR_ID_VORTEX           0x1119
5963 +#define PCI_DEVICE_ID_VORTEX_GDT60x0   0x0000
5964 +#define PCI_DEVICE_ID_VORTEX_GDT6000B  0x0001
5965 +#define PCI_DEVICE_ID_VORTEX_GDT6x10   0x0002
5966 +#define PCI_DEVICE_ID_VORTEX_GDT6x20   0x0003
5967 +#define PCI_DEVICE_ID_VORTEX_GDT6530   0x0004
5968 +#define PCI_DEVICE_ID_VORTEX_GDT6550   0x0005
5969 +#define PCI_DEVICE_ID_VORTEX_GDT6x17   0x0006
5970 +#define PCI_DEVICE_ID_VORTEX_GDT6x27   0x0007
5971 +#define PCI_DEVICE_ID_VORTEX_GDT6537   0x0008
5972 +#define PCI_DEVICE_ID_VORTEX_GDT6557   0x0009
5973 +#define PCI_DEVICE_ID_VORTEX_GDT6x15   0x000a
5974 +#define PCI_DEVICE_ID_VORTEX_GDT6x25   0x000b
5975 +#define PCI_DEVICE_ID_VORTEX_GDT6535   0x000c
5976 +#define PCI_DEVICE_ID_VORTEX_GDT6555   0x000d
5977 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100
5978 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101
5979 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102
5980 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103
5981 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104
5982 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105
5983 +
5984 +#define PCI_VENDOR_ID_EF               0x111a
5985 +#define PCI_DEVICE_ID_EF_ATM_FPGA      0x0000
5986 +#define PCI_DEVICE_ID_EF_ATM_ASIC      0x0002
5987 +#define PCI_VENDOR_ID_EF_ATM_LANAI2    0x0003
5988 +#define PCI_VENDOR_ID_EF_ATM_LANAIHB   0x0005
5989 +
5990 +#define PCI_VENDOR_ID_IDT              0x111d
5991 +#define PCI_DEVICE_ID_IDT_IDT77201     0x0001
5992 +
5993 +#define PCI_VENDOR_ID_FORE             0x1127
5994 +#define PCI_DEVICE_ID_FORE_PCA200E     0x0300
5995 +
5996 +
5997 +#define PCI_VENDOR_ID_PHILIPS          0x1131
5998 +#define PCI_DEVICE_ID_PHILIPS_SAA7146  0x7146
5999 +#define PCI_DEVICE_ID_PHILIPS_SAA9730  0x9730
6000 +
6001 +#define PCI_VENDOR_ID_EICON            0x1133
6002 +#define PCI_DEVICE_ID_EICON_DIVA20     0xe002
6003 +#define PCI_DEVICE_ID_EICON_DIVA20_U   0xe004
6004 +#define PCI_DEVICE_ID_EICON_DIVA201    0xe005
6005 +#define PCI_DEVICE_ID_EICON_DIVA202    0xe00b
6006 +#define PCI_DEVICE_ID_EICON_MAESTRA    0xe010
6007 +#define PCI_DEVICE_ID_EICON_MAESTRAQ   0xe012
6008 +#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013
6009 +#define PCI_DEVICE_ID_EICON_MAESTRAP   0xe014
6010 +
6011 +#define PCI_VENDOR_ID_ZIATECH          0x1138
6012 +#define PCI_DEVICE_ID_ZIATECH_5550_HC  0x5550
6013 +
6014 +
6015 +
6016 +#define PCI_VENDOR_ID_SYSKONNECT       0x1148
6017 +#define PCI_DEVICE_ID_SYSKONNECT_TR    0x4200
6018 +#define PCI_DEVICE_ID_SYSKONNECT_GE    0x4300
6019 +#define PCI_DEVICE_ID_SYSKONNECT_YU    0x4320
6020 +#define PCI_DEVICE_ID_SYSKONNECT_9DXX  0x4400
6021 +#define PCI_DEVICE_ID_SYSKONNECT_9MXX  0x4500
6022 +
6023 +
6024 +#define PCI_VENDOR_ID_DIGI             0x114f
6025 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070
6026 +#define PCI_DEVICE_ID_DIGI_DF_M_E      0x0071
6027 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072
6028 +#define PCI_DEVICE_ID_DIGI_DF_M_A      0x0073
6029 +#define PCI_DEVICE_ID_NEO_2DB9          0x00C8
6030 +#define PCI_DEVICE_ID_NEO_2DB9PRI       0x00C9
6031 +#define PCI_DEVICE_ID_NEO_2RJ45         0x00CA
6032 +#define PCI_DEVICE_ID_NEO_2RJ45PRI      0x00CB
6033 +
6034 +
6035 +#define PCI_VENDOR_ID_XIRCOM           0x115d
6036 +#define PCI_DEVICE_ID_XIRCOM_RBM56G    0x0101
6037 +#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103
6038 +
6039 +
6040 +#define PCI_VENDOR_ID_SERVERWORKS        0x1166
6041 +#define PCI_DEVICE_ID_SERVERWORKS_HE     0x0008
6042 +#define PCI_DEVICE_ID_SERVERWORKS_LE     0x0009
6043 +#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
6044 +#define PCI_DEVICE_ID_SERVERWORKS_EPB    0x0103
6045 +#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE  0x0132
6046 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4   0x0200
6047 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5   0x0201
6048 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6    0x0203
6049 +#define PCI_DEVICE_ID_SERVERWORKS_HT1000SB 0x0205
6050 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
6051 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
6052 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
6053 +#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214
6054 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
6055 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
6056 +
6057 +#define PCI_VENDOR_ID_SBE              0x1176
6058 +#define PCI_DEVICE_ID_SBE_WANXL100     0x0301
6059 +#define PCI_DEVICE_ID_SBE_WANXL200     0x0302
6060 +#define PCI_DEVICE_ID_SBE_WANXL400     0x0104
6061 +
6062 +#define PCI_VENDOR_ID_TOSHIBA          0x1179
6063 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO  0x0102
6064 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1        0x0103
6065 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2        0x0105
6066 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95  0x060a
6067 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC97  0x060f
6068 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC100 0x0617
6069 +
6070 +#define PCI_VENDOR_ID_TOSHIBA_2                0x102f
6071 +#define PCI_DEVICE_ID_TOSHIBA_TC35815CF        0x0030
6072 +#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC    0x0108
6073 +#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3
6074 +
6075 +#define PCI_VENDOR_ID_RICOH            0x1180
6076 +#define PCI_DEVICE_ID_RICOH_RL5C465    0x0465
6077 +#define PCI_DEVICE_ID_RICOH_RL5C466    0x0466
6078 +#define PCI_DEVICE_ID_RICOH_RL5C475    0x0475
6079 +#define PCI_DEVICE_ID_RICOH_RL5C476    0x0476
6080 +#define PCI_DEVICE_ID_RICOH_RL5C478    0x0478
6081 +#define PCI_DEVICE_ID_RICOH_R5C822     0x0822
6082 +
6083 +#define PCI_VENDOR_ID_DLINK            0x1186
6084 +#define PCI_DEVICE_ID_DLINK_DGE510T    0x4c00
6085 +
6086 +#define PCI_VENDOR_ID_ARTOP            0x1191
6087 +#define PCI_DEVICE_ID_ARTOP_ATP850UF   0x0005
6088 +#define PCI_DEVICE_ID_ARTOP_ATP860     0x0006
6089 +#define PCI_DEVICE_ID_ARTOP_ATP860R    0x0007
6090 +#define PCI_DEVICE_ID_ARTOP_ATP865     0x0008
6091 +#define PCI_DEVICE_ID_ARTOP_ATP865R    0x0009
6092 +#define PCI_DEVICE_ID_ARTOP_AEC7610    0x8002
6093 +#define PCI_DEVICE_ID_ARTOP_AEC7612UW  0x8010
6094 +#define PCI_DEVICE_ID_ARTOP_AEC7612U   0x8020
6095 +#define PCI_DEVICE_ID_ARTOP_AEC7612S   0x8030
6096 +#define PCI_DEVICE_ID_ARTOP_AEC7612D   0x8040
6097 +#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050
6098 +#define PCI_DEVICE_ID_ARTOP_8060       0x8060
6099 +
6100 +#define PCI_VENDOR_ID_ZEITNET          0x1193
6101 +#define PCI_DEVICE_ID_ZEITNET_1221     0x0001
6102 +#define PCI_DEVICE_ID_ZEITNET_1225     0x0002
6103 +
6104 +
6105 +#define PCI_VENDOR_ID_FUJITSU_ME       0x119e
6106 +#define PCI_DEVICE_ID_FUJITSU_FS155    0x0001
6107 +#define PCI_DEVICE_ID_FUJITSU_FS50     0x0003
6108 +
6109 +#define PCI_SUBVENDOR_ID_KEYSPAN       0x11a9
6110 +#define PCI_SUBDEVICE_ID_KEYSPAN_SX2   0x5334
6111 +
6112 +#define PCI_VENDOR_ID_MARVELL          0x11ab
6113 +#define PCI_DEVICE_ID_MARVELL_GT64111  0x4146
6114 +#define PCI_DEVICE_ID_MARVELL_GT64260  0x6430
6115 +#define PCI_DEVICE_ID_MARVELL_MV64360  0x6460
6116 +#define PCI_DEVICE_ID_MARVELL_MV64460  0x6480
6117 +
6118 +#define PCI_VENDOR_ID_V3               0x11b0
6119 +#define PCI_DEVICE_ID_V3_V960          0x0001
6120 +#define PCI_DEVICE_ID_V3_V351          0x0002
6121 +
6122 +
6123 +#define PCI_VENDOR_ID_ATT              0x11c1
6124 +#define PCI_DEVICE_ID_ATT_VENUS_MODEM  0x480
6125 +
6126 +
6127 +#define PCI_VENDOR_ID_SPECIALIX                0x11cb
6128 +#define PCI_DEVICE_ID_SPECIALIX_IO8    0x2000
6129 +#define PCI_DEVICE_ID_SPECIALIX_RIO    0x8000
6130 +#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
6131 +
6132 +
6133 +#define PCI_VENDOR_ID_ANALOG_DEVICES   0x11d4
6134 +#define PCI_DEVICE_ID_AD1889JS         0x1889
6135 +
6136 +
6137 +#define PCI_DEVICE_ID_SEGA_BBA         0x1234
6138 +
6139 +#define PCI_VENDOR_ID_ZORAN            0x11de
6140 +#define PCI_DEVICE_ID_ZORAN_36057      0x6057
6141 +#define PCI_DEVICE_ID_ZORAN_36120      0x6120
6142 +
6143 +
6144 +#define PCI_VENDOR_ID_COMPEX           0x11f6
6145 +#define PCI_DEVICE_ID_COMPEX_ENET100VG4        0x0112
6146 +
6147 +#define PCI_VENDOR_ID_RP               0x11fe
6148 +#define PCI_DEVICE_ID_RP32INTF         0x0001
6149 +#define PCI_DEVICE_ID_RP8INTF          0x0002
6150 +#define PCI_DEVICE_ID_RP16INTF         0x0003
6151 +#define PCI_DEVICE_ID_RP4QUAD          0x0004
6152 +#define PCI_DEVICE_ID_RP8OCTA          0x0005
6153 +#define PCI_DEVICE_ID_RP8J             0x0006
6154 +#define PCI_DEVICE_ID_RP4J             0x0007
6155 +#define PCI_DEVICE_ID_RP8SNI           0x0008
6156 +#define PCI_DEVICE_ID_RP16SNI          0x0009
6157 +#define PCI_DEVICE_ID_RPP4             0x000A
6158 +#define PCI_DEVICE_ID_RPP8             0x000B
6159 +#define PCI_DEVICE_ID_RP4M             0x000D
6160 +#define PCI_DEVICE_ID_RP2_232          0x000E
6161 +#define PCI_DEVICE_ID_RP2_422          0x000F
6162 +#define PCI_DEVICE_ID_URP32INTF                0x0801
6163 +#define PCI_DEVICE_ID_URP8INTF         0x0802
6164 +#define PCI_DEVICE_ID_URP16INTF                0x0803
6165 +#define PCI_DEVICE_ID_URP8OCTA         0x0805
6166 +#define PCI_DEVICE_ID_UPCI_RM3_8PORT   0x080C
6167 +#define PCI_DEVICE_ID_UPCI_RM3_4PORT   0x080D
6168 +#define PCI_DEVICE_ID_CRP16INTF                0x0903
6169 +
6170 +#define PCI_VENDOR_ID_CYCLADES         0x120e
6171 +#define PCI_DEVICE_ID_CYCLOM_Y_Lo      0x0100
6172 +#define PCI_DEVICE_ID_CYCLOM_Y_Hi      0x0101
6173 +#define PCI_DEVICE_ID_CYCLOM_4Y_Lo     0x0102
6174 +#define PCI_DEVICE_ID_CYCLOM_4Y_Hi     0x0103
6175 +#define PCI_DEVICE_ID_CYCLOM_8Y_Lo     0x0104
6176 +#define PCI_DEVICE_ID_CYCLOM_8Y_Hi     0x0105
6177 +#define PCI_DEVICE_ID_CYCLOM_Z_Lo      0x0200
6178 +#define PCI_DEVICE_ID_CYCLOM_Z_Hi      0x0201
6179 +#define PCI_DEVICE_ID_PC300_RX_2       0x0300
6180 +#define PCI_DEVICE_ID_PC300_RX_1       0x0301
6181 +#define PCI_DEVICE_ID_PC300_TE_2       0x0310
6182 +#define PCI_DEVICE_ID_PC300_TE_1       0x0311
6183 +#define PCI_DEVICE_ID_PC300_TE_M_2     0x0320
6184 +#define PCI_DEVICE_ID_PC300_TE_M_1     0x0321
6185 +
6186 +#define PCI_VENDOR_ID_ESSENTIAL                0x120f
6187 +#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER     0x0001
6188 +
6189 +#define PCI_VENDOR_ID_O2               0x1217
6190 +#define PCI_DEVICE_ID_O2_6729          0x6729
6191 +#define PCI_DEVICE_ID_O2_6730          0x673a
6192 +#define PCI_DEVICE_ID_O2_6832          0x6832
6193 +#define PCI_DEVICE_ID_O2_6836          0x6836
6194 +
6195 +#define PCI_VENDOR_ID_3DFX             0x121a
6196 +#define PCI_DEVICE_ID_3DFX_VOODOO      0x0001
6197 +#define PCI_DEVICE_ID_3DFX_VOODOO2     0x0002
6198 +#define PCI_DEVICE_ID_3DFX_BANSHEE     0x0003
6199 +#define PCI_DEVICE_ID_3DFX_VOODOO3     0x0005
6200 +#define PCI_DEVICE_ID_3DFX_VOODOO5     0x0009
6201 +
6202 +
6203 +
6204 +#define PCI_VENDOR_ID_AVM              0x1244
6205 +#define PCI_DEVICE_ID_AVM_B1           0x0700
6206 +#define PCI_DEVICE_ID_AVM_C4           0x0800
6207 +#define PCI_DEVICE_ID_AVM_A1           0x0a00
6208 +#define PCI_DEVICE_ID_AVM_A1_V2                0x0e00
6209 +#define PCI_DEVICE_ID_AVM_C2           0x1100
6210 +#define PCI_DEVICE_ID_AVM_T1           0x1200
6211 +
6212 +
6213 +#define PCI_VENDOR_ID_STALLION         0x124d
6214 +
6215 +/* Allied Telesyn */
6216 +#define PCI_VENDOR_ID_AT               0x1259
6217 +#define PCI_SUBDEVICE_ID_AT_2700FX     0x2701
6218 +#define PCI_SUBDEVICE_ID_AT_2701FX     0x2703
6219 +
6220 +#define PCI_VENDOR_ID_ESS              0x125d
6221 +#define PCI_DEVICE_ID_ESS_ESS1968      0x1968
6222 +#define PCI_DEVICE_ID_ESS_ESS1978      0x1978
6223 +#define PCI_DEVICE_ID_ESS_ALLEGRO_1    0x1988
6224 +#define PCI_DEVICE_ID_ESS_ALLEGRO      0x1989
6225 +#define PCI_DEVICE_ID_ESS_CANYON3D_2LE 0x1990
6226 +#define PCI_DEVICE_ID_ESS_CANYON3D_2   0x1992
6227 +#define PCI_DEVICE_ID_ESS_MAESTRO3     0x1998
6228 +#define PCI_DEVICE_ID_ESS_MAESTRO3_1   0x1999
6229 +#define PCI_DEVICE_ID_ESS_MAESTRO3_HW  0x199a
6230 +#define PCI_DEVICE_ID_ESS_MAESTRO3_2   0x199b
6231 +
6232 +#define PCI_VENDOR_ID_SATSAGEM         0x1267
6233 +#define PCI_DEVICE_ID_SATSAGEM_NICCY   0x1016
6234 +
6235 +
6236 +#define PCI_VENDOR_ID_ENSONIQ          0x1274
6237 +#define PCI_DEVICE_ID_ENSONIQ_CT5880   0x5880
6238 +#define PCI_DEVICE_ID_ENSONIQ_ES1370   0x5000
6239 +#define PCI_DEVICE_ID_ENSONIQ_ES1371   0x1371
6240 +
6241 +#define PCI_VENDOR_ID_TRANSMETA                0x1279
6242 +#define PCI_DEVICE_ID_EFFICEON         0x0060
6243 +
6244 +#define PCI_VENDOR_ID_ROCKWELL         0x127A
6245 +
6246 +#define PCI_VENDOR_ID_ITE              0x1283
6247 +#define PCI_DEVICE_ID_ITE_8211         0x8211
6248 +#define PCI_DEVICE_ID_ITE_8212         0x8212
6249 +#define PCI_DEVICE_ID_ITE_8872         0x8872
6250 +#define PCI_DEVICE_ID_ITE_IT8330G_0    0xe886
6251 +
6252 +/* formerly Platform Tech */
6253 +#define PCI_DEVICE_ID_ESS_ESS0100      0x0100
6254 +
6255 +#define PCI_VENDOR_ID_ALTEON           0x12ae
6256 +
6257 +
6258 +#define PCI_SUBVENDOR_ID_CONNECT_TECH                  0x12c4
6259 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232          0x0001
6260 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232          0x0002
6261 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232          0x0003
6262 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485          0x0004
6263 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4      0x0005
6264 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485          0x0006
6265 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2      0x0007
6266 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485          0x0008
6267 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6      0x0009
6268 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1       0x000A
6269 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1       0x000B
6270 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ                0x000C
6271 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM          0x000D
6272 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI         0x0100
6273 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2          0x0201
6274 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4          0x0202
6275 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232   0x0300
6276 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232   0x0301
6277 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232   0x0302
6278 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1     0x0310
6279 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2     0x0311
6280 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4     0x0312
6281 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2       0x0320
6282 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4       0x0321
6283 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8       0x0322
6284 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485   0x0330
6285 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485   0x0331
6286 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485   0x0332
6287 +
6288 +
6289 +#define PCI_VENDOR_ID_NVIDIA_SGS       0x12d2
6290 +#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
6291 +
6292 +#define PCI_SUBVENDOR_ID_CHASE_PCIFAST         0x12E0
6293 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4                0x0031
6294 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8                0x0021
6295 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16       0x0011
6296 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC    0x0041
6297 +#define PCI_SUBVENDOR_ID_CHASE_PCIRAS          0x124D
6298 +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4         0xF001
6299 +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8         0xF010
6300 +
6301 +#define PCI_VENDOR_ID_AUREAL           0x12eb
6302 +#define PCI_DEVICE_ID_AUREAL_VORTEX_1  0x0001
6303 +#define PCI_DEVICE_ID_AUREAL_VORTEX_2  0x0002
6304 +#define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003
6305 +
6306 +#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8
6307 +#define PCI_DEVICE_ID_LML_33R10                0x8a02
6308 +
6309 +
6310 +#define PCI_VENDOR_ID_SIIG             0x131f
6311 +#define PCI_SUBVENDOR_ID_SIIG          0x131f
6312 +#define PCI_DEVICE_ID_SIIG_1S_10x_550  0x1000
6313 +#define PCI_DEVICE_ID_SIIG_1S_10x_650  0x1001
6314 +#define PCI_DEVICE_ID_SIIG_1S_10x_850  0x1002
6315 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_550        0x1010
6316 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_650        0x1011
6317 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_850        0x1012
6318 +#define PCI_DEVICE_ID_SIIG_1P_10x      0x1020
6319 +#define PCI_DEVICE_ID_SIIG_2P_10x      0x1021
6320 +#define PCI_DEVICE_ID_SIIG_2S_10x_550  0x1030
6321 +#define PCI_DEVICE_ID_SIIG_2S_10x_650  0x1031
6322 +#define PCI_DEVICE_ID_SIIG_2S_10x_850  0x1032
6323 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_550        0x1034
6324 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_650        0x1035
6325 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_850        0x1036
6326 +#define PCI_DEVICE_ID_SIIG_4S_10x_550  0x1050
6327 +#define PCI_DEVICE_ID_SIIG_4S_10x_650  0x1051
6328 +#define PCI_DEVICE_ID_SIIG_4S_10x_850  0x1052
6329 +#define PCI_DEVICE_ID_SIIG_1S_20x_550  0x2000
6330 +#define PCI_DEVICE_ID_SIIG_1S_20x_650  0x2001
6331 +#define PCI_DEVICE_ID_SIIG_1S_20x_850  0x2002
6332 +#define PCI_DEVICE_ID_SIIG_1P_20x      0x2020
6333 +#define PCI_DEVICE_ID_SIIG_2P_20x      0x2021
6334 +#define PCI_DEVICE_ID_SIIG_2S_20x_550  0x2030
6335 +#define PCI_DEVICE_ID_SIIG_2S_20x_650  0x2031
6336 +#define PCI_DEVICE_ID_SIIG_2S_20x_850  0x2032
6337 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_550        0x2040
6338 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_650        0x2041
6339 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_850        0x2042
6340 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_550        0x2010
6341 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_650        0x2011
6342 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_850        0x2012
6343 +#define PCI_DEVICE_ID_SIIG_4S_20x_550  0x2050
6344 +#define PCI_DEVICE_ID_SIIG_4S_20x_650  0x2051
6345 +#define PCI_DEVICE_ID_SIIG_4S_20x_850  0x2052
6346 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_550        0x2060
6347 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_650        0x2061
6348 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_850        0x2062
6349 +#define PCI_DEVICE_ID_SIIG_8S_20x_550  0x2080
6350 +#define PCI_DEVICE_ID_SIIG_8S_20x_650  0x2081
6351 +#define PCI_DEVICE_ID_SIIG_8S_20x_850  0x2082
6352 +#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL   0x2050
6353 +
6354 +#define PCI_VENDOR_ID_RADISYS          0x1331
6355 +
6356 +#define PCI_VENDOR_ID_DOMEX            0x134a
6357 +#define PCI_DEVICE_ID_DOMEX_DMX3191D   0x0001
6358 +
6359 +#define PCI_VENDOR_ID_INTASHIELD       0x135a
6360 +#define PCI_DEVICE_ID_INTASHIELD_IS200 0x0d80
6361 +
6362 +#define PCI_VENDOR_ID_QUATECH          0x135C
6363 +#define PCI_DEVICE_ID_QUATECH_QSC100   0x0010
6364 +#define PCI_DEVICE_ID_QUATECH_DSC100   0x0020
6365 +#define PCI_DEVICE_ID_QUATECH_ESC100D  0x0050
6366 +#define PCI_DEVICE_ID_QUATECH_ESC100M  0x0060
6367 +
6368 +#define PCI_VENDOR_ID_SEALEVEL         0x135e
6369 +#define PCI_DEVICE_ID_SEALEVEL_U530    0x7101
6370 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM2  0x7201
6371 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM422        0x7402
6372 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM232        0x7202
6373 +#define PCI_DEVICE_ID_SEALEVEL_COMM4   0x7401
6374 +#define PCI_DEVICE_ID_SEALEVEL_COMM8   0x7801
6375 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM8  0x7804
6376 +
6377 +#define PCI_VENDOR_ID_HYPERCOPE                0x1365
6378 +#define PCI_DEVICE_ID_HYPERCOPE_PLX    0x9050
6379 +#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO    0x0104
6380 +#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO                0x0106
6381 +#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO       0x0107
6382 +#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2      0x0108
6383 +
6384 +#define PCI_VENDOR_ID_KAWASAKI         0x136b
6385 +#define PCI_DEVICE_ID_MCHIP_KL5A72002  0xff01
6386 +
6387 +#define PCI_VENDOR_ID_CNET             0x1371
6388 +#define PCI_DEVICE_ID_CNET_GIGACARD    0x434e
6389 +
6390 +#define PCI_VENDOR_ID_LMC              0x1376
6391 +#define PCI_DEVICE_ID_LMC_HSSI         0x0003
6392 +#define PCI_DEVICE_ID_LMC_DS3          0x0004
6393 +#define PCI_DEVICE_ID_LMC_SSI          0x0005
6394 +#define PCI_DEVICE_ID_LMC_T1           0x0006
6395 +
6396 +
6397 +#define PCI_VENDOR_ID_NETGEAR          0x1385
6398 +#define PCI_DEVICE_ID_NETGEAR_GA620    0x620a
6399 +
6400 +#define PCI_VENDOR_ID_APPLICOM         0x1389
6401 +#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
6402 +#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002
6403 +#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003
6404 +
6405 +#define PCI_VENDOR_ID_MOXA             0x1393
6406 +#define PCI_DEVICE_ID_MOXA_RC7000      0x0001
6407 +#define PCI_DEVICE_ID_MOXA_CP102       0x1020
6408 +#define PCI_DEVICE_ID_MOXA_CP102UL     0x1021
6409 +#define PCI_DEVICE_ID_MOXA_CP102U      0x1022
6410 +#define PCI_DEVICE_ID_MOXA_C104                0x1040
6411 +#define PCI_DEVICE_ID_MOXA_CP104U      0x1041
6412 +#define PCI_DEVICE_ID_MOXA_CP104JU     0x1042
6413 +#define PCI_DEVICE_ID_MOXA_CT114       0x1140
6414 +#define PCI_DEVICE_ID_MOXA_CP114       0x1141
6415 +#define PCI_DEVICE_ID_MOXA_CP118U      0x1180
6416 +#define PCI_DEVICE_ID_MOXA_CP132       0x1320
6417 +#define PCI_DEVICE_ID_MOXA_CP132U      0x1321
6418 +#define PCI_DEVICE_ID_MOXA_CP134U      0x1340
6419 +#define PCI_DEVICE_ID_MOXA_C168                0x1680
6420 +#define PCI_DEVICE_ID_MOXA_CP168U      0x1681
6421 +
6422 +#define PCI_VENDOR_ID_CCD              0x1397
6423 +#define PCI_DEVICE_ID_CCD_2BD0         0x2bd0
6424 +#define PCI_DEVICE_ID_CCD_B000         0xb000
6425 +#define PCI_DEVICE_ID_CCD_B006         0xb006
6426 +#define PCI_DEVICE_ID_CCD_B007         0xb007
6427 +#define PCI_DEVICE_ID_CCD_B008         0xb008
6428 +#define PCI_DEVICE_ID_CCD_B009         0xb009
6429 +#define PCI_DEVICE_ID_CCD_B00A         0xb00a
6430 +#define PCI_DEVICE_ID_CCD_B00B         0xb00b
6431 +#define PCI_DEVICE_ID_CCD_B00C         0xb00c
6432 +#define PCI_DEVICE_ID_CCD_B100         0xb100
6433 +#define PCI_DEVICE_ID_CCD_B700         0xb700
6434 +#define PCI_DEVICE_ID_CCD_B701         0xb701
6435 +
6436 +#define PCI_VENDOR_ID_EXAR             0x13a8
6437 +#define PCI_DEVICE_ID_EXAR_XR17C152    0x0152
6438 +#define PCI_DEVICE_ID_EXAR_XR17C154    0x0154
6439 +#define PCI_DEVICE_ID_EXAR_XR17C158    0x0158
6440 +
6441 +#define PCI_VENDOR_ID_MICROGATE                0x13c0
6442 +#define PCI_DEVICE_ID_MICROGATE_USC    0x0010
6443 +#define PCI_DEVICE_ID_MICROGATE_SCA    0x0030
6444 +
6445 +#define PCI_VENDOR_ID_3WARE            0x13C1
6446 +#define PCI_DEVICE_ID_3WARE_1000       0x1000
6447 +#define PCI_DEVICE_ID_3WARE_7000       0x1001
6448 +#define PCI_DEVICE_ID_3WARE_9000       0x1002
6449 +
6450 +#define PCI_VENDOR_ID_IOMEGA           0x13ca
6451 +#define PCI_DEVICE_ID_IOMEGA_BUZ       0x4231
6452 +
6453 +#define PCI_VENDOR_ID_ABOCOM           0x13D1
6454 +#define PCI_DEVICE_ID_ABOCOM_2BD1       0x2BD1
6455 +
6456 +#define PCI_VENDOR_ID_CMEDIA           0x13f6
6457 +#define PCI_DEVICE_ID_CMEDIA_CM8338A   0x0100
6458 +#define PCI_DEVICE_ID_CMEDIA_CM8338B   0x0101
6459 +#define PCI_DEVICE_ID_CMEDIA_CM8738    0x0111
6460 +#define PCI_DEVICE_ID_CMEDIA_CM8738B   0x0112
6461 +
6462 +#define PCI_VENDOR_ID_LAVA             0x1407
6463 +#define PCI_DEVICE_ID_LAVA_DSERIAL     0x0100 /* 2x 16550 */
6464 +#define PCI_DEVICE_ID_LAVA_QUATRO_A    0x0101 /* 2x 16550, half of 4 port */
6465 +#define PCI_DEVICE_ID_LAVA_QUATRO_B    0x0102 /* 2x 16550, half of 4 port */
6466 +#define PCI_DEVICE_ID_LAVA_OCTO_A      0x0180 /* 4x 16550A, half of 8 port */
6467 +#define PCI_DEVICE_ID_LAVA_OCTO_B      0x0181 /* 4x 16550A, half of 8 port */
6468 +#define PCI_DEVICE_ID_LAVA_PORT_PLUS   0x0200 /* 2x 16650 */
6469 +#define PCI_DEVICE_ID_LAVA_QUAD_A      0x0201 /* 2x 16650, half of 4 port */
6470 +#define PCI_DEVICE_ID_LAVA_QUAD_B      0x0202 /* 2x 16650, half of 4 port */
6471 +#define PCI_DEVICE_ID_LAVA_SSERIAL     0x0500 /* 1x 16550 */
6472 +#define PCI_DEVICE_ID_LAVA_PORT_650    0x0600 /* 1x 16650 */
6473 +#define PCI_DEVICE_ID_LAVA_PARALLEL    0x8000
6474 +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A  0x8002 /* The Lava Dual Parallel is */
6475 +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B  0x8003 /* two PCI devices on a card */
6476 +#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR 0x8800
6477 +
6478 +#define PCI_VENDOR_ID_TIMEDIA          0x1409
6479 +#define PCI_DEVICE_ID_TIMEDIA_1889     0x7168
6480 +
6481 +#define PCI_VENDOR_ID_ICE              0x1412
6482 +#define PCI_DEVICE_ID_ICE_1712         0x1712
6483 +#define PCI_DEVICE_ID_VT1724           0x1724
6484 +
6485 +#define PCI_VENDOR_ID_OXSEMI           0x1415
6486 +#define PCI_DEVICE_ID_OXSEMI_12PCI840  0x8403
6487 +#define PCI_DEVICE_ID_OXSEMI_16PCI954  0x9501
6488 +#define PCI_DEVICE_ID_OXSEMI_16PCI95N  0x9511
6489 +#define PCI_DEVICE_ID_OXSEMI_16PCI954PP        0x9513
6490 +#define PCI_DEVICE_ID_OXSEMI_16PCI952  0x9521
6491 +
6492 +#define PCI_VENDOR_ID_SAMSUNG          0x144d
6493 +
6494 +#define PCI_VENDOR_ID_MYRICOM          0x14c1
6495 +
6496 +#define PCI_VENDOR_ID_TITAN            0x14D2
6497 +#define PCI_DEVICE_ID_TITAN_010L       0x8001
6498 +#define PCI_DEVICE_ID_TITAN_100L       0x8010
6499 +#define PCI_DEVICE_ID_TITAN_110L       0x8011
6500 +#define PCI_DEVICE_ID_TITAN_200L       0x8020
6501 +#define PCI_DEVICE_ID_TITAN_210L       0x8021
6502 +#define PCI_DEVICE_ID_TITAN_400L       0x8040
6503 +#define PCI_DEVICE_ID_TITAN_800L       0x8080
6504 +#define PCI_DEVICE_ID_TITAN_100                0xA001
6505 +#define PCI_DEVICE_ID_TITAN_200                0xA005
6506 +#define PCI_DEVICE_ID_TITAN_400                0xA003
6507 +#define PCI_DEVICE_ID_TITAN_800B       0xA004
6508 +
6509 +#define PCI_VENDOR_ID_PANACOM          0x14d4
6510 +#define PCI_DEVICE_ID_PANACOM_QUADMODEM        0x0400
6511 +#define PCI_DEVICE_ID_PANACOM_DUALMODEM        0x0402
6512 +
6513 +#define PCI_VENDOR_ID_SIPACKETS                0x14d9
6514 +#define PCI_DEVICE_ID_SP1011           0x0010
6515 +
6516 +#define PCI_VENDOR_ID_AFAVLAB          0x14db
6517 +#define PCI_DEVICE_ID_AFAVLAB_P028     0x2180
6518 +#define PCI_DEVICE_ID_AFAVLAB_P030     0x2182
6519 +#define PCI_SUBDEVICE_ID_AFAVLAB_P061          0x2150
6520 +
6521 +#define PCI_VENDOR_ID_BROADCOM         0x14e4
6522 +#define PCI_DEVICE_ID_TIGON3_5752      0x1600
6523 +#define PCI_DEVICE_ID_TIGON3_5752M     0x1601
6524 +#define PCI_DEVICE_ID_TIGON3_5700      0x1644
6525 +#define PCI_DEVICE_ID_TIGON3_5701      0x1645
6526 +#define PCI_DEVICE_ID_TIGON3_5702      0x1646
6527 +#define PCI_DEVICE_ID_TIGON3_5703      0x1647
6528 +#define PCI_DEVICE_ID_TIGON3_5704      0x1648
6529 +#define PCI_DEVICE_ID_TIGON3_5704S_2   0x1649
6530 +#define PCI_DEVICE_ID_NX2_5706         0x164a
6531 +#define PCI_DEVICE_ID_NX2_5708         0x164c
6532 +#define PCI_DEVICE_ID_TIGON3_5702FE    0x164d
6533 +#define PCI_DEVICE_ID_TIGON3_5705      0x1653
6534 +#define PCI_DEVICE_ID_TIGON3_5705_2    0x1654
6535 +#define PCI_DEVICE_ID_TIGON3_5720      0x1658
6536 +#define PCI_DEVICE_ID_TIGON3_5721      0x1659
6537 +#define PCI_DEVICE_ID_TIGON3_5722      0x165a
6538 +#define PCI_DEVICE_ID_TIGON3_5705M     0x165d
6539 +#define PCI_DEVICE_ID_TIGON3_5705M_2   0x165e
6540 +#define PCI_DEVICE_ID_TIGON3_5714      0x1668
6541 +#define PCI_DEVICE_ID_TIGON3_5714S     0x1669
6542 +#define PCI_DEVICE_ID_TIGON3_5780      0x166a
6543 +#define PCI_DEVICE_ID_TIGON3_5780S     0x166b
6544 +#define PCI_DEVICE_ID_TIGON3_5705F     0x166e
6545 +#define PCI_DEVICE_ID_TIGON3_5754M     0x1672
6546 +#define PCI_DEVICE_ID_TIGON3_5755M     0x1673
6547 +#define PCI_DEVICE_ID_TIGON3_5756      0x1674
6548 +#define PCI_DEVICE_ID_TIGON3_5750      0x1676
6549 +#define PCI_DEVICE_ID_TIGON3_5751      0x1677
6550 +#define PCI_DEVICE_ID_TIGON3_5715      0x1678
6551 +#define PCI_DEVICE_ID_TIGON3_5715S     0x1679
6552 +#define PCI_DEVICE_ID_TIGON3_5754      0x167a
6553 +#define PCI_DEVICE_ID_TIGON3_5755      0x167b
6554 +#define PCI_DEVICE_ID_TIGON3_5750M     0x167c
6555 +#define PCI_DEVICE_ID_TIGON3_5751M     0x167d
6556 +#define PCI_DEVICE_ID_TIGON3_5751F     0x167e
6557 +#define PCI_DEVICE_ID_TIGON3_5787M     0x1693
6558 +#define PCI_DEVICE_ID_TIGON3_5782      0x1696
6559 +#define PCI_DEVICE_ID_TIGON3_5786      0x169a
6560 +#define PCI_DEVICE_ID_TIGON3_5787      0x169b
6561 +#define PCI_DEVICE_ID_TIGON3_5788      0x169c
6562 +#define PCI_DEVICE_ID_TIGON3_5789      0x169d
6563 +#define PCI_DEVICE_ID_TIGON3_5702X     0x16a6
6564 +#define PCI_DEVICE_ID_TIGON3_5703X     0x16a7
6565 +#define PCI_DEVICE_ID_TIGON3_5704S     0x16a8
6566 +#define PCI_DEVICE_ID_NX2_5706S                0x16aa
6567 +#define PCI_DEVICE_ID_NX2_5708S                0x16ac
6568 +#define PCI_DEVICE_ID_TIGON3_5702A3    0x16c6
6569 +#define PCI_DEVICE_ID_TIGON3_5703A3    0x16c7
6570 +#define PCI_DEVICE_ID_TIGON3_5781      0x16dd
6571 +#define PCI_DEVICE_ID_TIGON3_5753      0x16f7
6572 +#define PCI_DEVICE_ID_TIGON3_5753M     0x16fd
6573 +#define PCI_DEVICE_ID_TIGON3_5753F     0x16fe
6574 +#define PCI_DEVICE_ID_TIGON3_5901      0x170d
6575 +#define PCI_DEVICE_ID_BCM4401B1                0x170c
6576 +#define PCI_DEVICE_ID_TIGON3_5901_2    0x170e
6577 +#define PCI_DEVICE_ID_TIGON3_5906      0x1712
6578 +#define PCI_DEVICE_ID_TIGON3_5906M     0x1713
6579 +#define PCI_DEVICE_ID_BCM4401          0x4401
6580 +#define PCI_DEVICE_ID_BCM4401B0                0x4402
6581 +
6582 +#define PCI_VENDOR_ID_TOPIC            0x151f
6583 +#define PCI_DEVICE_ID_TOPIC_TP560      0x0000
6584 +
6585 +#define PCI_VENDOR_ID_ENE              0x1524
6586 +#define PCI_DEVICE_ID_ENE_1211         0x1211
6587 +#define PCI_DEVICE_ID_ENE_1225         0x1225
6588 +#define PCI_DEVICE_ID_ENE_1410         0x1410
6589 +#define PCI_DEVICE_ID_ENE_710          0x1411
6590 +#define PCI_DEVICE_ID_ENE_712          0x1412
6591 +#define PCI_DEVICE_ID_ENE_1420         0x1420
6592 +#define PCI_DEVICE_ID_ENE_720          0x1421
6593 +#define PCI_DEVICE_ID_ENE_722          0x1422
6594 +
6595 +#define PCI_VENDOR_ID_CHELSIO          0x1425
6596 +
6597 +
6598 +#define PCI_VENDOR_ID_SYBA             0x1592
6599 +#define PCI_DEVICE_ID_SYBA_2P_EPP      0x0782
6600 +#define PCI_DEVICE_ID_SYBA_1P_ECP      0x0783
6601 +
6602 +#define PCI_VENDOR_ID_MORETON          0x15aa
6603 +#define PCI_DEVICE_ID_RASTEL_2PORT     0x2000
6604 +
6605 +#define PCI_VENDOR_ID_ZOLTRIX          0x15b0
6606 +#define PCI_DEVICE_ID_ZOLTRIX_2BD0     0x2bd0
6607 +
6608 +#define PCI_VENDOR_ID_MELLANOX         0x15b3
6609 +#define PCI_DEVICE_ID_MELLANOX_TAVOR   0x5a44
6610 +#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE    0x5a46
6611 +#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
6612 +#define PCI_DEVICE_ID_MELLANOX_ARBEL   0x6282
6613 +#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
6614 +#define PCI_DEVICE_ID_MELLANOX_SINAI   0x6274
6615 +
6616 +#define PCI_VENDOR_ID_PDC              0x15e9
6617 +
6618 +
6619 +#define PCI_VENDOR_ID_FARSITE           0x1619
6620 +#define PCI_DEVICE_ID_FARSITE_T2P       0x0400
6621 +#define PCI_DEVICE_ID_FARSITE_T4P       0x0440
6622 +#define PCI_DEVICE_ID_FARSITE_T1U       0x0610
6623 +#define PCI_DEVICE_ID_FARSITE_T2U       0x0620
6624 +#define PCI_DEVICE_ID_FARSITE_T4U       0x0640
6625 +#define PCI_DEVICE_ID_FARSITE_TE1       0x1610
6626 +#define PCI_DEVICE_ID_FARSITE_TE1C      0x1612
6627 +
6628 +#define PCI_VENDOR_ID_SIBYTE           0x166d
6629 +#define PCI_DEVICE_ID_BCM1250_PCI      0x0001
6630 +#define PCI_DEVICE_ID_BCM1250_HT       0x0002
6631 +
6632 +#define PCI_VENDOR_ID_NETCELL          0x169c
6633 +#define PCI_DEVICE_ID_REVOLUTION       0x0044
6634 +
6635 +#define PCI_VENDOR_ID_VITESSE          0x1725
6636 +#define PCI_DEVICE_ID_VITESSE_VSC7174  0x7174
6637 +
6638 +#define PCI_VENDOR_ID_LINKSYS          0x1737
6639 +#define PCI_DEVICE_ID_LINKSYS_EG1064   0x1064
6640 +
6641 +#define PCI_VENDOR_ID_ALTIMA           0x173b
6642 +#define PCI_DEVICE_ID_ALTIMA_AC1000    0x03e8
6643 +#define PCI_DEVICE_ID_ALTIMA_AC1001    0x03e9
6644 +#define PCI_DEVICE_ID_ALTIMA_AC9100    0x03ea
6645 +#define PCI_DEVICE_ID_ALTIMA_AC1003    0x03eb
6646 +
6647 +#define PCI_VENDOR_ID_ARECA            0x17d3
6648 +#define PCI_DEVICE_ID_ARECA_1110       0x1110
6649 +#define PCI_DEVICE_ID_ARECA_1120       0x1120
6650 +#define PCI_DEVICE_ID_ARECA_1130       0x1130
6651 +#define PCI_DEVICE_ID_ARECA_1160       0x1160
6652 +#define PCI_DEVICE_ID_ARECA_1170       0x1170
6653 +#define PCI_DEVICE_ID_ARECA_1210       0x1210
6654 +#define PCI_DEVICE_ID_ARECA_1220       0x1220
6655 +#define PCI_DEVICE_ID_ARECA_1230       0x1230
6656 +#define PCI_DEVICE_ID_ARECA_1260       0x1260
6657 +#define PCI_DEVICE_ID_ARECA_1270       0x1270
6658 +#define PCI_DEVICE_ID_ARECA_1280       0x1280
6659 +#define PCI_DEVICE_ID_ARECA_1380       0x1380
6660 +#define PCI_DEVICE_ID_ARECA_1381       0x1381
6661 +#define PCI_DEVICE_ID_ARECA_1680       0x1680
6662 +#define PCI_DEVICE_ID_ARECA_1681       0x1681
6663 +
6664 +#define PCI_VENDOR_ID_S2IO             0x17d5
6665 +#define        PCI_DEVICE_ID_S2IO_WIN          0x5731
6666 +#define        PCI_DEVICE_ID_S2IO_UNI          0x5831
6667 +#define PCI_DEVICE_ID_HERC_WIN         0x5732
6668 +#define PCI_DEVICE_ID_HERC_UNI         0x5832
6669 +
6670 +
6671 +#define PCI_VENDOR_ID_SITECOM          0x182d
6672 +#define PCI_DEVICE_ID_SITECOM_DC105V2  0x3069
6673 +
6674 +#define PCI_VENDOR_ID_TOPSPIN          0x1867
6675 +
6676 +#define PCI_VENDOR_ID_TDI               0x192E
6677 +#define PCI_DEVICE_ID_TDI_EHCI          0x0101
6678 +
6679 +#define PCI_VENDOR_ID_JMICRON          0x197B
6680 +#define PCI_DEVICE_ID_JMICRON_JMB360   0x2360
6681 +#define PCI_DEVICE_ID_JMICRON_JMB361   0x2361
6682 +#define PCI_DEVICE_ID_JMICRON_JMB363   0x2363
6683 +#define PCI_DEVICE_ID_JMICRON_JMB365   0x2365
6684 +#define PCI_DEVICE_ID_JMICRON_JMB366   0x2366
6685 +#define PCI_DEVICE_ID_JMICRON_JMB368   0x2368
6686 +
6687 +#define PCI_VENDOR_ID_TEKRAM           0x1de1
6688 +#define PCI_DEVICE_ID_TEKRAM_DC290     0xdc29
6689 +
6690 +#define PCI_VENDOR_ID_HINT             0x3388
6691 +#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
6692 +
6693 +#define PCI_VENDOR_ID_3DLABS           0x3d3d
6694 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007
6695 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V        0x0009
6696 +
6697 +
6698 +#define PCI_VENDOR_ID_AKS              0x416c
6699 +#define PCI_DEVICE_ID_AKS_ALADDINCARD  0x0100
6700 +
6701 +
6702 +
6703 +#define PCI_VENDOR_ID_S3               0x5333
6704 +#define PCI_DEVICE_ID_S3_TRIO          0x8811
6705 +#define PCI_DEVICE_ID_S3_868           0x8880
6706 +#define PCI_DEVICE_ID_S3_968           0x88f0
6707 +#define PCI_DEVICE_ID_S3_SAVAGE4       0x8a25
6708 +#define PCI_DEVICE_ID_S3_PROSAVAGE8    0x8d04
6709 +#define PCI_DEVICE_ID_S3_SONICVIBES    0xca00
6710 +
6711 +#define PCI_VENDOR_ID_DUNORD           0x5544
6712 +#define PCI_DEVICE_ID_DUNORD_I3000     0x0001
6713 +
6714 +
6715 +#define PCI_VENDOR_ID_DCI              0x6666
6716 +#define PCI_DEVICE_ID_DCI_PCCOM4       0x0001
6717 +#define PCI_DEVICE_ID_DCI_PCCOM8       0x0002
6718 +#define PCI_DEVICE_ID_DCI_PCCOM2       0x0004
6719 +
6720 +#define PCI_VENDOR_ID_INTEL            0x8086
6721 +#define PCI_DEVICE_ID_INTEL_EESSC      0x0008
6722 +#define PCI_DEVICE_ID_INTEL_PXHD_0     0x0320
6723 +#define PCI_DEVICE_ID_INTEL_PXHD_1     0x0321
6724 +#define PCI_DEVICE_ID_INTEL_PXH_0      0x0329
6725 +#define PCI_DEVICE_ID_INTEL_PXH_1      0x032A
6726 +#define PCI_DEVICE_ID_INTEL_PXHV       0x032C
6727 +#define PCI_DEVICE_ID_INTEL_82375      0x0482
6728 +#define PCI_DEVICE_ID_INTEL_82424      0x0483
6729 +#define PCI_DEVICE_ID_INTEL_82378      0x0484
6730 +#define PCI_DEVICE_ID_INTEL_I960       0x0960
6731 +#define PCI_DEVICE_ID_INTEL_I960RM     0x0962
6732 +#define PCI_DEVICE_ID_INTEL_82815_MC   0x1130
6733 +#define PCI_DEVICE_ID_INTEL_82815_CGC  0x1132
6734 +#define PCI_DEVICE_ID_INTEL_82092AA_0  0x1221
6735 +#define PCI_DEVICE_ID_INTEL_7505_0     0x2550
6736 +#define PCI_DEVICE_ID_INTEL_7205_0     0x255d
6737 +#define PCI_DEVICE_ID_INTEL_82437      0x122d
6738 +#define PCI_DEVICE_ID_INTEL_82371FB_0  0x122e
6739 +#define PCI_DEVICE_ID_INTEL_82371FB_1  0x1230
6740 +#define PCI_DEVICE_ID_INTEL_82371MX    0x1234
6741 +#define PCI_DEVICE_ID_INTEL_82441      0x1237
6742 +#define PCI_DEVICE_ID_INTEL_82380FB    0x124b
6743 +#define PCI_DEVICE_ID_INTEL_82439      0x1250
6744 +#define PCI_DEVICE_ID_INTEL_80960_RP   0x1960
6745 +#define PCI_DEVICE_ID_INTEL_82840_HB   0x1a21
6746 +#define PCI_DEVICE_ID_INTEL_82845_HB   0x1a30
6747 +#define PCI_DEVICE_ID_INTEL_IOAT       0x1a38
6748 +#define PCI_DEVICE_ID_INTEL_82801AA_0  0x2410
6749 +#define PCI_DEVICE_ID_INTEL_82801AA_1  0x2411
6750 +#define PCI_DEVICE_ID_INTEL_82801AA_3  0x2413
6751 +#define PCI_DEVICE_ID_INTEL_82801AA_5  0x2415
6752 +#define PCI_DEVICE_ID_INTEL_82801AA_6  0x2416
6753 +#define PCI_DEVICE_ID_INTEL_82801AA_8  0x2418
6754 +#define PCI_DEVICE_ID_INTEL_82801AB_0  0x2420
6755 +#define PCI_DEVICE_ID_INTEL_82801AB_1  0x2421
6756 +#define PCI_DEVICE_ID_INTEL_82801AB_3  0x2423
6757 +#define PCI_DEVICE_ID_INTEL_82801AB_5  0x2425
6758 +#define PCI_DEVICE_ID_INTEL_82801AB_6  0x2426
6759 +#define PCI_DEVICE_ID_INTEL_82801AB_8  0x2428
6760 +#define PCI_DEVICE_ID_INTEL_82801BA_0  0x2440
6761 +#define PCI_DEVICE_ID_INTEL_82801BA_2  0x2443
6762 +#define PCI_DEVICE_ID_INTEL_82801BA_4  0x2445
6763 +#define PCI_DEVICE_ID_INTEL_82801BA_6  0x2448
6764 +#define PCI_DEVICE_ID_INTEL_82801BA_8  0x244a
6765 +#define PCI_DEVICE_ID_INTEL_82801BA_9  0x244b
6766 +#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c
6767 +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e
6768 +#define PCI_DEVICE_ID_INTEL_82801E_0   0x2450
6769 +#define PCI_DEVICE_ID_INTEL_82801E_11  0x245b
6770 +#define PCI_DEVICE_ID_INTEL_82801CA_0  0x2480
6771 +#define PCI_DEVICE_ID_INTEL_82801CA_3  0x2483
6772 +#define PCI_DEVICE_ID_INTEL_82801CA_5  0x2485
6773 +#define PCI_DEVICE_ID_INTEL_82801CA_6  0x2486
6774 +#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a
6775 +#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b
6776 +#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c
6777 +#define PCI_DEVICE_ID_INTEL_82801DB_0  0x24c0
6778 +#define PCI_DEVICE_ID_INTEL_82801DB_1  0x24c1
6779 +#define PCI_DEVICE_ID_INTEL_82801DB_3  0x24c3
6780 +#define PCI_DEVICE_ID_INTEL_82801DB_5  0x24c5
6781 +#define PCI_DEVICE_ID_INTEL_82801DB_6  0x24c6
6782 +#define PCI_DEVICE_ID_INTEL_82801DB_9  0x24c9
6783 +#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca
6784 +#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb
6785 +#define PCI_DEVICE_ID_INTEL_82801DB_12  0x24cc
6786 +#define PCI_DEVICE_ID_INTEL_82801EB_0  0x24d0
6787 +#define PCI_DEVICE_ID_INTEL_82801EB_1  0x24d1
6788 +#define PCI_DEVICE_ID_INTEL_82801EB_3  0x24d3
6789 +#define PCI_DEVICE_ID_INTEL_82801EB_5  0x24d5
6790 +#define PCI_DEVICE_ID_INTEL_82801EB_6  0x24d6
6791 +#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db
6792 +#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd
6793 +#define PCI_DEVICE_ID_INTEL_ESB_1      0x25a1
6794 +#define PCI_DEVICE_ID_INTEL_ESB_2      0x25a2
6795 +#define PCI_DEVICE_ID_INTEL_ESB_4      0x25a4
6796 +#define PCI_DEVICE_ID_INTEL_ESB_5      0x25a6
6797 +#define PCI_DEVICE_ID_INTEL_ESB_9      0x25ab
6798 +#define PCI_DEVICE_ID_INTEL_82820_HB   0x2500
6799 +#define PCI_DEVICE_ID_INTEL_82820_UP_HB        0x2501
6800 +#define PCI_DEVICE_ID_INTEL_82850_HB   0x2530
6801 +#define PCI_DEVICE_ID_INTEL_82860_HB   0x2531
6802 +#define PCI_DEVICE_ID_INTEL_E7501_MCH  0x254c
6803 +#define PCI_DEVICE_ID_INTEL_82845G_HB  0x2560
6804 +#define PCI_DEVICE_ID_INTEL_82845G_IG  0x2562
6805 +#define PCI_DEVICE_ID_INTEL_82865_HB   0x2570
6806 +#define PCI_DEVICE_ID_INTEL_82865_IG   0x2572
6807 +#define PCI_DEVICE_ID_INTEL_82875_HB   0x2578
6808 +#define PCI_DEVICE_ID_INTEL_82915G_HB  0x2580
6809 +#define PCI_DEVICE_ID_INTEL_82915G_IG  0x2582
6810 +#define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590
6811 +#define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592
6812 +#define PCI_DEVICE_ID_INTEL_82945G_HB  0x2770
6813 +#define PCI_DEVICE_ID_INTEL_82945G_IG  0x2772
6814 +#define PCI_DEVICE_ID_INTEL_82945GM_HB 0x27A0
6815 +#define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2
6816 +#define PCI_DEVICE_ID_INTEL_ICH6_0     0x2640
6817 +#define PCI_DEVICE_ID_INTEL_ICH6_1     0x2641
6818 +#define PCI_DEVICE_ID_INTEL_ICH6_2     0x2642
6819 +#define PCI_DEVICE_ID_INTEL_ICH6_16    0x266a
6820 +#define PCI_DEVICE_ID_INTEL_ICH6_17    0x266d
6821 +#define PCI_DEVICE_ID_INTEL_ICH6_18    0x266e
6822 +#define PCI_DEVICE_ID_INTEL_ICH6_19    0x266f
6823 +#define PCI_DEVICE_ID_INTEL_ESB2_0     0x2670
6824 +#define PCI_DEVICE_ID_INTEL_ESB2_14    0x2698
6825 +#define PCI_DEVICE_ID_INTEL_ESB2_17    0x269b
6826 +#define PCI_DEVICE_ID_INTEL_ESB2_18    0x269e
6827 +#define PCI_DEVICE_ID_INTEL_ICH7_0     0x27b8
6828 +#define PCI_DEVICE_ID_INTEL_ICH7_1     0x27b9
6829 +#define PCI_DEVICE_ID_INTEL_ICH7_30    0x27b0
6830 +#define PCI_DEVICE_ID_INTEL_ICH7_31    0x27bd
6831 +#define PCI_DEVICE_ID_INTEL_ICH7_17    0x27da
6832 +#define PCI_DEVICE_ID_INTEL_ICH7_19    0x27dd
6833 +#define PCI_DEVICE_ID_INTEL_ICH7_20    0x27de
6834 +#define PCI_DEVICE_ID_INTEL_ICH7_21    0x27df
6835 +#define PCI_DEVICE_ID_INTEL_ICH8_0     0x2810
6836 +#define PCI_DEVICE_ID_INTEL_ICH8_1     0x2811
6837 +#define PCI_DEVICE_ID_INTEL_ICH8_2     0x2812
6838 +#define PCI_DEVICE_ID_INTEL_ICH8_3     0x2814
6839 +#define PCI_DEVICE_ID_INTEL_ICH8_4     0x2815
6840 +#define PCI_DEVICE_ID_INTEL_ICH8_5     0x283e
6841 +#define PCI_DEVICE_ID_INTEL_ICH8_6     0x2850
6842 +#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340
6843 +#define PCI_DEVICE_ID_INTEL_82830_HB   0x3575
6844 +#define PCI_DEVICE_ID_INTEL_82830_CGC  0x3577
6845 +#define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580
6846 +#define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582
6847 +#define PCI_DEVICE_ID_INTEL_E7520_MCH  0x3590
6848 +#define PCI_DEVICE_ID_INTEL_E7320_MCH  0x3592
6849 +#define PCI_DEVICE_ID_INTEL_MCH_PA     0x3595
6850 +#define PCI_DEVICE_ID_INTEL_MCH_PA1    0x3596
6851 +#define PCI_DEVICE_ID_INTEL_MCH_PB     0x3597
6852 +#define PCI_DEVICE_ID_INTEL_MCH_PB1    0x3598
6853 +#define PCI_DEVICE_ID_INTEL_MCH_PC     0x3599
6854 +#define PCI_DEVICE_ID_INTEL_MCH_PC1    0x359a
6855 +#define PCI_DEVICE_ID_INTEL_E7525_MCH  0x359e
6856 +#define PCI_DEVICE_ID_INTEL_82371SB_0  0x7000
6857 +#define PCI_DEVICE_ID_INTEL_82371SB_1  0x7010
6858 +#define PCI_DEVICE_ID_INTEL_82371SB_2  0x7020
6859 +#define PCI_DEVICE_ID_INTEL_82437VX    0x7030
6860 +#define PCI_DEVICE_ID_INTEL_82439TX    0x7100
6861 +#define PCI_DEVICE_ID_INTEL_82371AB_0  0x7110
6862 +#define PCI_DEVICE_ID_INTEL_82371AB    0x7111
6863 +#define PCI_DEVICE_ID_INTEL_82371AB_2  0x7112
6864 +#define PCI_DEVICE_ID_INTEL_82371AB_3  0x7113
6865 +#define PCI_DEVICE_ID_INTEL_82810_MC1  0x7120
6866 +#define PCI_DEVICE_ID_INTEL_82810_IG1  0x7121
6867 +#define PCI_DEVICE_ID_INTEL_82810_MC3  0x7122
6868 +#define PCI_DEVICE_ID_INTEL_82810_IG3  0x7123
6869 +#define PCI_DEVICE_ID_INTEL_82810E_MC  0x7124
6870 +#define PCI_DEVICE_ID_INTEL_82810E_IG  0x7125
6871 +#define PCI_DEVICE_ID_INTEL_82443LX_0  0x7180
6872 +#define PCI_DEVICE_ID_INTEL_82443LX_1  0x7181
6873 +#define PCI_DEVICE_ID_INTEL_82443BX_0  0x7190
6874 +#define PCI_DEVICE_ID_INTEL_82443BX_1  0x7191
6875 +#define PCI_DEVICE_ID_INTEL_82443BX_2  0x7192
6876 +#define PCI_DEVICE_ID_INTEL_440MX      0x7195
6877 +#define PCI_DEVICE_ID_INTEL_440MX_6    0x7196
6878 +#define PCI_DEVICE_ID_INTEL_82443MX_0  0x7198
6879 +#define PCI_DEVICE_ID_INTEL_82443MX_1  0x7199
6880 +#define PCI_DEVICE_ID_INTEL_82443MX_3  0x719b
6881 +#define PCI_DEVICE_ID_INTEL_82443GX_0  0x71a0
6882 +#define PCI_DEVICE_ID_INTEL_82443GX_2  0x71a2
6883 +#define PCI_DEVICE_ID_INTEL_82372FB_1  0x7601
6884 +#define PCI_DEVICE_ID_INTEL_82454GX    0x84c4
6885 +#define PCI_DEVICE_ID_INTEL_82450GX    0x84c5
6886 +#define PCI_DEVICE_ID_INTEL_82451NX    0x84ca
6887 +#define PCI_DEVICE_ID_INTEL_82454NX     0x84cb
6888 +#define PCI_DEVICE_ID_INTEL_84460GX    0x84ea
6889 +#define PCI_DEVICE_ID_INTEL_IXP4XX     0x8500
6890 +#define PCI_DEVICE_ID_INTEL_IXP2800    0x9004
6891 +#define PCI_DEVICE_ID_INTEL_S21152BB   0xb152
6892 +
6893 +#define PCI_VENDOR_ID_SCALEMP          0x8686
6894 +#define PCI_DEVICE_ID_SCALEMP_VSMP_CTL 0x1010
6895 +
6896 +#define PCI_VENDOR_ID_COMPUTONE                0x8e0e
6897 +#define PCI_DEVICE_ID_COMPUTONE_IP2EX  0x0291
6898 +#define PCI_DEVICE_ID_COMPUTONE_PG     0x0302
6899 +#define PCI_SUBVENDOR_ID_COMPUTONE     0x8e0e
6900 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG4 0x0001
6901 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG8 0x0002
6902 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003
6903 +
6904 +#define PCI_VENDOR_ID_KTI              0x8e2e
6905 +
6906 +#define PCI_VENDOR_ID_ADAPTEC          0x9004
6907 +#define PCI_DEVICE_ID_ADAPTEC_7810     0x1078
6908 +#define PCI_DEVICE_ID_ADAPTEC_7821     0x2178
6909 +#define PCI_DEVICE_ID_ADAPTEC_38602    0x3860
6910 +#define PCI_DEVICE_ID_ADAPTEC_7850     0x5078
6911 +#define PCI_DEVICE_ID_ADAPTEC_7855     0x5578
6912 +#define PCI_DEVICE_ID_ADAPTEC_3860     0x6038
6913 +#define PCI_DEVICE_ID_ADAPTEC_1480A    0x6075
6914 +#define PCI_DEVICE_ID_ADAPTEC_7860     0x6078
6915 +#define PCI_DEVICE_ID_ADAPTEC_7861     0x6178
6916 +#define PCI_DEVICE_ID_ADAPTEC_7870     0x7078
6917 +#define PCI_DEVICE_ID_ADAPTEC_7871     0x7178
6918 +#define PCI_DEVICE_ID_ADAPTEC_7872     0x7278
6919 +#define PCI_DEVICE_ID_ADAPTEC_7873     0x7378
6920 +#define PCI_DEVICE_ID_ADAPTEC_7874     0x7478
6921 +#define PCI_DEVICE_ID_ADAPTEC_7895     0x7895
6922 +#define PCI_DEVICE_ID_ADAPTEC_7880     0x8078
6923 +#define PCI_DEVICE_ID_ADAPTEC_7881     0x8178
6924 +#define PCI_DEVICE_ID_ADAPTEC_7882     0x8278
6925 +#define PCI_DEVICE_ID_ADAPTEC_7883     0x8378
6926 +#define PCI_DEVICE_ID_ADAPTEC_7884     0x8478
6927 +#define PCI_DEVICE_ID_ADAPTEC_7885     0x8578
6928 +#define PCI_DEVICE_ID_ADAPTEC_7886     0x8678
6929 +#define PCI_DEVICE_ID_ADAPTEC_7887     0x8778
6930 +#define PCI_DEVICE_ID_ADAPTEC_7888     0x8878
6931 +
6932 +#define PCI_VENDOR_ID_ADAPTEC2         0x9005
6933 +#define PCI_DEVICE_ID_ADAPTEC2_2940U2  0x0010
6934 +#define PCI_DEVICE_ID_ADAPTEC2_2930U2  0x0011
6935 +#define PCI_DEVICE_ID_ADAPTEC2_7890B   0x0013
6936 +#define PCI_DEVICE_ID_ADAPTEC2_7890    0x001f
6937 +#define PCI_DEVICE_ID_ADAPTEC2_3940U2  0x0050
6938 +#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051
6939 +#define PCI_DEVICE_ID_ADAPTEC2_7896    0x005f
6940 +#define PCI_DEVICE_ID_ADAPTEC2_7892A   0x0080
6941 +#define PCI_DEVICE_ID_ADAPTEC2_7892B   0x0081
6942 +#define PCI_DEVICE_ID_ADAPTEC2_7892D   0x0083
6943 +#define PCI_DEVICE_ID_ADAPTEC2_7892P   0x008f
6944 +#define PCI_DEVICE_ID_ADAPTEC2_7899A   0x00c0
6945 +#define PCI_DEVICE_ID_ADAPTEC2_7899B   0x00c1
6946 +#define PCI_DEVICE_ID_ADAPTEC2_7899D   0x00c3
6947 +#define PCI_DEVICE_ID_ADAPTEC2_7899P   0x00cf
6948 +#define PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN   0x0500
6949 +#define PCI_DEVICE_ID_ADAPTEC2_SCAMP   0x0503
6950 +
6951 +
6952 +#define PCI_VENDOR_ID_HOLTEK           0x9412
6953 +#define PCI_DEVICE_ID_HOLTEK_6565      0x6565
6954 +
6955 +#define PCI_VENDOR_ID_NETMOS           0x9710
6956 +#define PCI_DEVICE_ID_NETMOS_9705      0x9705
6957 +#define PCI_DEVICE_ID_NETMOS_9715      0x9715
6958 +#define PCI_DEVICE_ID_NETMOS_9735      0x9735
6959 +#define PCI_DEVICE_ID_NETMOS_9745      0x9745
6960 +#define PCI_DEVICE_ID_NETMOS_9755      0x9755
6961 +#define PCI_DEVICE_ID_NETMOS_9805      0x9805
6962 +#define PCI_DEVICE_ID_NETMOS_9815      0x9815
6963 +#define PCI_DEVICE_ID_NETMOS_9835      0x9835
6964 +#define PCI_DEVICE_ID_NETMOS_9845      0x9845
6965 +#define PCI_DEVICE_ID_NETMOS_9855      0x9855
6966 +
6967 +#define PCI_SUBVENDOR_ID_EXSYS         0xd84d
6968 +#define PCI_SUBDEVICE_ID_EXSYS_4014    0x4014
6969 +#define PCI_SUBDEVICE_ID_EXSYS_4055    0x4055
6970 +
6971 +#define PCI_VENDOR_ID_TIGERJET         0xe159
6972 +#define PCI_DEVICE_ID_TIGERJET_300     0x0001
6973 +#define PCI_DEVICE_ID_TIGERJET_100     0x0002
6974 +
6975 +#define PCI_VENDOR_ID_TTTECH           0x0357
6976 +#define PCI_DEVICE_ID_TTTECH_MC322     0x000A
6977 +
6978 +#define PCI_VENDOR_ID_XILINX_RME       0xea60
6979 +#define PCI_DEVICE_ID_RME_DIGI32       0x9896
6980 +#define PCI_DEVICE_ID_RME_DIGI32_PRO   0x9897
6981 +#define PCI_DEVICE_ID_RME_DIGI32_8     0x9898
6982 +
6983 +#define PCI_VENDOR_ID_QUICKNET         0x15E2
6984 +#define PCI_DEVICE_ID_QUICKNET_XJ      0x0500
6985 diff -urN linux.old/include/linux/ssb_driver_chipcommon.h linux.dev/include/linux/ssb_driver_chipcommon.h
6986 --- linux.old/include/linux/ssb_driver_chipcommon.h     1970-01-01 01:00:00.000000000 +0100
6987 +++ linux.dev/include/linux/ssb_driver_chipcommon.h     2007-01-03 02:26:02.000000000 +0100
6988 @@ -0,0 +1,379 @@
6989 +#ifndef LINUX_SSB_CHIPCO_H_
6990 +#define LINUX_SSB_CHIPCO_H_
6991 +
6992 +/* SonicsSiliconBackplane CHIPCOMMON core hardware definitions
6993 + *
6994 + * The chipcommon core provides chip identification, SB control,
6995 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6996 + * gpio interface, extbus, and support for serial and parallel flashes.
6997 + *
6998 + * Copyright 2005, Broadcom Corporation
6999 + * Copyright 2006, Michael Buesch <mb@bu3sch.de>
7000 + *
7001 + * Licensed under the GPL version 2. See COPYING for details.
7002 + */
7003 +#ifdef __KERNEL__
7004 +
7005 +/** ChipCommon core registers. **/
7006 +
7007 +#define SSB_CHIPCO_CHIPID              0x0000
7008 +#define  SSB_CHIPCO_IDMASK             0x0000FFFF
7009 +#define  SSB_CHIPCO_REVMASK            0x000F0000
7010 +#define  SSB_CHIPCO_REVSHIFT           16
7011 +#define  SSB_CHIPCO_PACKMASK           0x00F00000
7012 +#define  SSB_CHIPCO_PACKSHIFT          20
7013 +#define  SSB_CHIPCO_NRCORESMASK                0x0F000000
7014 +#define  SSB_CHIPCO_NRCORESSHIFT       24
7015 +#define SSB_CHIPCO_CAP                 0x0004          /* Capabilities */
7016 +#define  SSB_CHIPCO_CAP_NRUART         0x00000003      /* # of UARTs */
7017 +#define  SSB_CHIPCO_CAP_MIPSEB         0x00000004      /* MIPS in BigEndian Mode */
7018 +#define  SSB_CHIPCO_CAP_UARTCLK                0x00000018      /* UART clock select */
7019 +#define   SSB_CHIPCO_CAP_UARTCLK_INT   0x00000008      /* UARTs are driven by internal divided clock */
7020 +#define  SSB_CHIPCO_CAP_UARTGPIO       0x00000020      /* UARTs on GPIO 15-12 */
7021 +#define  SSB_CHIPCO_CAP_EXTBUS         0x000000C0      /* External buses present */
7022 +#define  SSB_CHIPCO_CAP_FLASHT         0x00000700      /* Flash Type */
7023 +#define   SSB_CHIPCO_FLASHT_NONE       0x00000000      /* No flash */
7024 +#define   SSB_CHIPCO_FLASHT_STSER      0x00000100      /* ST serial flash */
7025 +#define   SSB_CHIPCO_FLASHT_ATSER      0x00000200      /* Atmel serial flash */
7026 +#define          SSB_CHIPCO_FLASHT_PARA        0x00000700      /* Parallel flash */
7027 +#define  SSB_CHIPCO_CAP_PLLT           0x00038000      /* PLL Type */
7028 +#define   SSB_PLLTYPE_NONE             0x00000000
7029 +#define   SSB_PLLTYPE_1                        0x00010000      /* 48Mhz base, 3 dividers */
7030 +#define   SSB_PLLTYPE_2                        0x00020000      /* 48Mhz, 4 dividers */
7031 +#define   SSB_PLLTYPE_3                        0x00030000      /* 25Mhz, 2 dividers */
7032 +#define   SSB_PLLTYPE_4                        0x00008000      /* 48Mhz, 4 dividers */
7033 +#define   SSB_PLLTYPE_5                        0x00018000      /* 25Mhz, 4 dividers */
7034 +#define   SSB_PLLTYPE_6                        0x00028000      /* 100/200 or 120/240 only */
7035 +#define   SSB_PLLTYPE_7                        0x00038000      /* 25Mhz, 4 dividers */
7036 +#define  SSB_CHIPCO_CAP_PCTL           0x00040000      /* Power Control */
7037 +#define  SSB_CHIPCO_CAP_OTPS           0x00380000      /* OTP size */
7038 +#define  SSB_CHIPCO_CAP_OTPS_SHIFT     19
7039 +#define  SSB_CHIPCO_CAP_OTPS_BASE      5
7040 +#define  SSB_CHIPCO_CAP_JTAGM          0x00400000      /* JTAG master present */
7041 +#define  SSB_CHIPCO_CAP_BROM           0x00800000      /* Internal boot ROM active */
7042 +#define  SSB_CHIPCO_CAP_64BIT          0x08000000      /* 64-bit Backplane */
7043 +#define SSB_CHIPCO_CORECTL             0x0008
7044 +#define  SSB_CHIPCO_CORECTL_UARTCLK0   0x00000001      /* Drive UART with internal clock */
7045 +#define         SSB_CHIPCO_CORECTL_SE          0x00000002      /* sync clk out enable (corerev >= 3) */
7046 +#define SSB_CHIPCO_BIST                        0x000C
7047 +#define SSB_CHIPCO_OTPS                        0x0010          /* OTP status */
7048 +#define         SSB_CHIPCO_OTPS_PROGFAIL       0x80000000
7049 +#define         SSB_CHIPCO_OTPS_PROTECT        0x00000007
7050 +#define         SSB_CHIPCO_OTPS_HW_PROTECT     0x00000001
7051 +#define         SSB_CHIPCO_OTPS_SW_PROTECT     0x00000002
7052 +#define         SSB_CHIPCO_OTPS_CID_PROTECT    0x00000004
7053 +#define SSB_CHIPCO_OTPC                        0x0014          /* OTP control */
7054 +#define         SSB_CHIPCO_OTPC_RECWAIT        0xFF000000
7055 +#define         SSB_CHIPCO_OTPC_PROGWAIT       0x00FFFF00
7056 +#define         SSB_CHIPCO_OTPC_PRW_SHIFT      8
7057 +#define         SSB_CHIPCO_OTPC_MAXFAIL        0x00000038
7058 +#define         SSB_CHIPCO_OTPC_VSEL           0x00000006
7059 +#define         SSB_CHIPCO_OTPC_SELVL          0x00000001
7060 +#define SSB_CHIPCO_OTPP                        0x0018          /* OTP prog */
7061 +#define         SSB_CHIPCO_OTPP_COL            0x000000FF
7062 +#define         SSB_CHIPCO_OTPP_ROW            0x0000FF00
7063 +#define         SSB_CHIPCO_OTPP_ROW_SHIFT      8
7064 +#define         SSB_CHIPCO_OTPP_READERR        0x10000000
7065 +#define         SSB_CHIPCO_OTPP_VALUE          0x20000000
7066 +#define         SSB_CHIPCO_OTPP_READ           0x40000000
7067 +#define         SSB_CHIPCO_OTPP_START          0x80000000
7068 +#define         SSB_CHIPCO_OTPP_BUSY           0x80000000
7069 +#define SSB_CHIPCO_IRQSTAT             0x0020
7070 +#define SSB_CHIPCO_IRQMASK             0x0024
7071 +#define         SSB_CHIPCO_IRQ_GPIO            0x00000001      /* gpio intr */
7072 +#define         SSB_CHIPCO_IRQ_EXT             0x00000002      /* ro: ext intr pin (corerev >= 3) */
7073 +#define         SSB_CHIPCO_IRQ_WDRESET         0x80000000      /* watchdog reset occurred */
7074 +#define SSB_CHIPCO_CHIPCTL             0x0028          /* Rev >= 11 only */
7075 +#define SSB_CHIPCO_CHIPSTAT            0x002C          /* Rev >= 11 only */
7076 +#define SSB_CHIPCO_JCMD                        0x0030          /* Rev >= 10 only */
7077 +#define  SSB_CHIPCO_JCMD_START         0x80000000
7078 +#define  SSB_CHIPCO_JCMD_BUSY          0x80000000
7079 +#define  SSB_CHIPCO_JCMD_PAUSE         0x40000000
7080 +#define  SSB_CHIPCO_JCMD0_ACC_MASK     0x0000F000
7081 +#define  SSB_CHIPCO_JCMD0_ACC_IRDR     0x00000000
7082 +#define  SSB_CHIPCO_JCMD0_ACC_DR       0x00001000
7083 +#define  SSB_CHIPCO_JCMD0_ACC_IR       0x00002000
7084 +#define  SSB_CHIPCO_JCMD0_ACC_RESET    0x00003000
7085 +#define  SSB_CHIPCO_JCMD0_ACC_IRPDR    0x00004000
7086 +#define  SSB_CHIPCO_JCMD0_ACC_PDR      0x00005000
7087 +#define  SSB_CHIPCO_JCMD0_IRW_MASK     0x00000F00
7088 +#define  SSB_CHIPCO_JCMD_ACC_MASK      0x000F0000      /* Changes for corerev 11 */
7089 +#define  SSB_CHIPCO_JCMD_ACC_IRDR      0x00000000
7090 +#define  SSB_CHIPCO_JCMD_ACC_DR                0x00010000
7091 +#define  SSB_CHIPCO_JCMD_ACC_IR                0x00020000
7092 +#define  SSB_CHIPCO_JCMD_ACC_RESET     0x00030000
7093 +#define  SSB_CHIPCO_JCMD_ACC_IRPDR     0x00040000
7094 +#define  SSB_CHIPCO_JCMD_ACC_PDR       0x00050000
7095 +#define  SSB_CHIPCO_JCMD_IRW_MASK      0x00001F00
7096 +#define  SSB_CHIPCO_JCMD_IRW_SHIFT     8
7097 +#define  SSB_CHIPCO_JCMD_DRW_MASK      0x0000003F
7098 +#define SSB_CHIPCO_JIR                 0x0034          /* Rev >= 10 only */
7099 +#define SSB_CHIPCO_JDR                 0x0038          /* Rev >= 10 only */
7100 +#define SSB_CHIPCO_JCTL                        0x003C          /* Rev >= 10 only */
7101 +#define  SSB_CHIPCO_JCTL_FORCE_CLK     4               /* Force clock */
7102 +#define  SSB_CHIPCO_JCTL_EXT_EN                2               /* Enable external targets */
7103 +#define  SSB_CHIPCO_JCTL_EN            1               /* Enable Jtag master */
7104 +#define SSB_CHIPCO_FLASHCTL            0x0040
7105 +#define  SSB_CHIPCO_FLASHCTL_START     0x80000000
7106 +#define  SSB_CHIPCO_FLASHCTL_BUSY      SSB_CHIPCO_FLASHCTL_START
7107 +#define SSB_CHIPCO_FLASHADDR           0x0044
7108 +#define SSB_CHIPCO_FLASHDATA           0x0048
7109 +#define SSB_CHIPCO_BCAST_ADDR          0x0050
7110 +#define SSB_CHIPCO_BCAST_DATA          0x0054
7111 +#define SSB_CHIPCO_GPIOIN              0x0060
7112 +#define SSB_CHIPCO_GPIOOUT             0x0064
7113 +#define SSB_CHIPCO_GPIOOUTEN           0x0068
7114 +#define SSB_CHIPCO_GPIOCTL             0x006C
7115 +#define SSB_CHIPCO_GPIOPOL             0x0070
7116 +#define SSB_CHIPCO_GPIOIRQ             0x0074
7117 +#define SSB_CHIPCO_WATCHDOG            0x0080
7118 +#define SSB_CHIPCO_GPIOTIMER           0x0088          /* LED powersave (corerev >= 16) */
7119 +#define  SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT     16
7120 +#define SSB_CHIPCO_GPIOTOUTM           0x008C          /* LED powersave (corerev >= 16) */
7121 +#define SSB_CHIPCO_CLOCK_N             0x0090
7122 +#define SSB_CHIPCO_CLOCK_SB            0x0094
7123 +#define SSB_CHIPCO_CLOCK_PCI           0x0098
7124 +#define SSB_CHIPCO_CLOCK_M2            0x009C
7125 +#define SSB_CHIPCO_CLOCK_MIPS          0x00A0
7126 +#define SSB_CHIPCO_CLKDIV              0x00A4          /* Rev >= 3 only */
7127 +#define         SSB_CHIPCO_CLKDIV_SFLASH       0x0F000000
7128 +#define         SSB_CHIPCO_CLKDIV_SFLASH_SHIFT 24
7129 +#define         SSB_CHIPCO_CLKDIV_OTP          0x000F0000
7130 +#define         SSB_CHIPCO_CLKDIV_OTP_SHIFT    16
7131 +#define         SSB_CHIPCO_CLKDIV_JTAG         0x00000F00
7132 +#define         SSB_CHIPCO_CLKDIV_JTAG_SHIFT   8
7133 +#define         SSB_CHIPCO_CLKDIV_UART         0x000000FF
7134 +#define SSB_CHIPCO_PLLONDELAY          0x00B0          /* Rev >= 4 only */
7135 +#define SSB_CHIPCO_FREFSELDELAY                0x00B4          /* Rev >= 4 only */
7136 +#define SSB_CHIPCO_SLOWCLKCTL          0x00B8          /* 6 <= Rev <= 9 only */
7137 +#define  SSB_CHIPCO_SLOWCLKCTL_SRC     0x00000007      /* slow clock source mask */
7138 +#define          SSB_CHIPCO_SLOWCLKCTL_SRC_LPO         0x00000000      /* source of slow clock is LPO */
7139 +#define   SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL       0x00000001      /* source of slow clock is crystal */
7140 +#define          SSB_CHIPCO_SLOECLKCTL_SRC_PCI         0x00000002      /* source of slow clock is PCI */
7141 +#define  SSB_CHIPCO_SLOWCLKCTL_LPOFREQ 0x00000200      /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
7142 +#define  SSB_CHIPCO_SLOWCLKCTL_LPOPD   0x00000400      /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
7143 +#define  SSB_CHIPCO_SLOWCLKCTL_FSLOW   0x00000800      /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
7144 +#define  SSB_CHIPCO_SLOWCLKCTL_IPLL    0x00001000      /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
7145 +#define  SSB_CHIPCO_SLOWCLKCTL_ENXTAL  0x00002000      /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
7146 +#define  SSB_CHIPCO_SLOWCLKCTL_XTALPU  0x00004000      /* XtalPU (RO), 1/0: crystal running/disabled */
7147 +#define  SSB_CHIPCO_SLOWCLKCTL_CLKDIV  0xFFFF0000      /* ClockDivider (SlowClk = 1/(4+divisor)) */
7148 +#define  SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT    16
7149 +#define SSB_CHIPCO_SYSCLKCTL           0x00C0          /* Rev >= 3 only */
7150 +#define         SSB_CHIPCO_SYSCLKCTL_IDLPEN    0x00000001      /* ILPen: Enable Idle Low Power */
7151 +#define         SSB_CHIPCO_SYSCLKCTL_ALPEN     0x00000002      /* ALPen: Enable Active Low Power */
7152 +#define         SSB_CHIPCO_SYSCLKCTL_PLLEN     0x00000004      /* ForcePLLOn */
7153 +#define         SSB_CHIPCO_SYSCLKCTL_FORCEALP  0x00000008      /* Force ALP (or HT if ALPen is not set */
7154 +#define         SSB_CHIPCO_SYSCLKCTL_FORCEHT   0x00000010      /* Force HT */
7155 +#define  SSB_CHIPCO_SYSCLKCTL_CLKDIV   0xFFFF0000      /* ClkDiv  (ILP = 1/(4+divisor)) */
7156 +#define  SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT     16
7157 +#define SSB_CHIPCO_CLKSTSTR            0x00C4          /* Rev >= 3 only */
7158 +#define SSB_CHIPCO_PCMCIA_CFG          0x0100
7159 +#define SSB_CHIPCO_PCMCIA_MEMWAIT      0x0104
7160 +#define SSB_CHIPCO_PCMCIA_ATTRWAIT     0x0108
7161 +#define SSB_CHIPCO_PCMCIA_IOWAIT       0x010C
7162 +#define SSB_CHIPCO_IDE_CFG             0x0110
7163 +#define SSB_CHIPCO_IDE_MEMWAIT         0x0114
7164 +#define SSB_CHIPCO_IDE_ATTRWAIT                0x0118
7165 +#define SSB_CHIPCO_IDE_IOWAIT          0x011C
7166 +#define SSB_CHIPCO_PROG_CFG            0x0120
7167 +#define SSB_CHIPCO_PROG_WAITCNT                0x0124
7168 +#define SSB_CHIPCO_FLASH_CFG           0x0128
7169 +#define SSB_CHIPCO_FLASH_WAITCNT       0x012C
7170 +#define SSB_CHIPCO_UART0_DATA          0x0300
7171 +#define SSB_CHIPCO_UART0_IMR           0x0304
7172 +#define SSB_CHIPCO_UART0_FCR           0x0308
7173 +#define SSB_CHIPCO_UART0_LCR           0x030C
7174 +#define SSB_CHIPCO_UART0_MCR           0x0310
7175 +#define SSB_CHIPCO_UART0_LSR           0x0314
7176 +#define SSB_CHIPCO_UART0_MSR           0x0318
7177 +#define SSB_CHIPCO_UART0_SCRATCH       0x031C
7178 +#define SSB_CHIPCO_UART1_DATA          0x0400
7179 +#define SSB_CHIPCO_UART1_IMR           0x0404
7180 +#define SSB_CHIPCO_UART1_FCR           0x0408
7181 +#define SSB_CHIPCO_UART1_LCR           0x040C
7182 +#define SSB_CHIPCO_UART1_MCR           0x0410
7183 +#define SSB_CHIPCO_UART1_LSR           0x0414
7184 +#define SSB_CHIPCO_UART1_MSR           0x0418
7185 +#define SSB_CHIPCO_UART1_SCRATCH       0x041C
7186 +
7187 +
7188 +
7189 +/** Clockcontrol masks and values **/
7190 +
7191 +/* SSB_CHIPCO_CLOCK_N */
7192 +#define        SSB_CHIPCO_CLK_N1               0x0000003F      /* n1 control */
7193 +#define        SSB_CHIPCO_CLK_N2               0x00003F00      /* n2 control */
7194 +#define        SSB_CHIPCO_CLK_N2_SHIFT         8
7195 +#define        SSB_CHIPCO_CLK_PLLC             0x000F0000      /* pll control */
7196 +#define        SSB_CHIPCO_CLK_PLLC_SHIFT       16
7197 +
7198 +/* SSB_CHIPCO_CLOCK_SB/PCI/UART */
7199 +#define        SSB_CHIPCO_CLK_M1               0x0000003F      /* m1 control */
7200 +#define        SSB_CHIPCO_CLK_M2               0x00003F00      /* m2 control */
7201 +#define        SSB_CHIPCO_CLK_M2_SHIFT         8
7202 +#define        SSB_CHIPCO_CLK_M3               0x003F0000      /* m3 control */
7203 +#define        SSB_CHIPCO_CLK_M3_SHIFT         16
7204 +#define        SSB_CHIPCO_CLK_MC               0x1F000000      /* mux control */
7205 +#define        SSB_CHIPCO_CLK_MC_SHIFT         24
7206 +
7207 +/* N3M Clock control magic field values */
7208 +#define        SSB_CHIPCO_CLK_F6_2             0x02            /* A factor of 2 in */
7209 +#define        SSB_CHIPCO_CLK_F6_3             0x03            /* 6-bit fields like */
7210 +#define        SSB_CHIPCO_CLK_F6_4             0x05            /* N1, M1 or M3 */
7211 +#define        SSB_CHIPCO_CLK_F6_5             0x09
7212 +#define        SSB_CHIPCO_CLK_F6_6             0x11
7213 +#define        SSB_CHIPCO_CLK_F6_7             0x21
7214 +
7215 +#define        SSB_CHIPCO_CLK_F5_BIAS          5               /* 5-bit fields get this added */
7216 +
7217 +#define        SSB_CHIPCO_CLK_MC_BYPASS        0x08
7218 +#define        SSB_CHIPCO_CLK_MC_M1            0x04
7219 +#define        SSB_CHIPCO_CLK_MC_M1M2          0x02
7220 +#define        SSB_CHIPCO_CLK_MC_M1M2M3        0x01
7221 +#define        SSB_CHIPCO_CLK_MC_M1M3          0x11
7222 +
7223 +/* Type 2 Clock control magic field values */
7224 +#define        SSB_CHIPCO_CLK_T2_BIAS          2               /* n1, n2, m1 & m3 bias */
7225 +#define        SSB_CHIPCO_CLK_T2M2_BIAS        3               /* m2 bias */
7226 +
7227 +#define        SSB_CHIPCO_CLK_T2MC_M1BYP       1
7228 +#define        SSB_CHIPCO_CLK_T2MC_M2BYP       2
7229 +#define        SSB_CHIPCO_CLK_T2MC_M3BYP       4
7230 +
7231 +/* Type 6 Clock control magic field values */
7232 +#define        SSB_CHIPCO_CLK_T6_MMASK         1               /* bits of interest in m */
7233 +#define        SSB_CHIPCO_CLK_T6_M0            120000000       /* sb clock for m = 0 */
7234 +#define        SSB_CHIPCO_CLK_T6_M1            100000000       /* sb clock for m = 1 */
7235 +#define        SSB_CHIPCO_CLK_SB2MIPS_T6(sb)   (2 * (sb))
7236 +
7237 +/* Common clock base */
7238 +#define        SSB_CHIPCO_CLK_BASE1            24000000        /* Half the clock freq */
7239 +#define SSB_CHIPCO_CLK_BASE2           12500000        /* Alternate crystal on some PLL's */
7240 +
7241 +/* Clock control values for 200Mhz in 5350 */
7242 +#define        SSB_CHIPCO_CLK_5350_N           0x0311
7243 +#define        SSB_CHIPCO_CLK_5350_M           0x04020009
7244 +
7245 +
7246 +/** Bits in the config registers **/
7247 +
7248 +#define        SSB_CHIPCO_CFG_EN               0x0001          /* Enable */
7249 +#define        SSB_CHIPCO_CFG_EXTM             0x000E          /* Extif Mode */
7250 +#define         SSB_CHIPCO_CFG_EXTM_ASYNC      0x0002          /* Async/Parallel flash */
7251 +#define         SSB_CHIPCO_CFG_EXTM_SYNC       0x0004          /* Synchronous */
7252 +#define         SSB_CHIPCO_CFG_EXTM_PCMCIA     0x0008          /* PCMCIA */
7253 +#define         SSB_CHIPCO_CFG_EXTM_IDE        0x000A          /* IDE */
7254 +#define        SSB_CHIPCO_CFG_DS16             0x0010          /* Data size, 0=8bit, 1=16bit */
7255 +#define        SSB_CHIPCO_CFG_CLKDIV           0x0060          /* Sync: Clock divisor */
7256 +#define        SSB_CHIPCO_CFG_CLKEN            0x0080          /* Sync: Clock enable */
7257 +#define        SSB_CHIPCO_CFG_BSTRO            0x0100          /* Sync: Size/Bytestrobe */
7258 +
7259 +
7260 +/** Flash-specific control/status values */
7261 +
7262 +/* flashcontrol opcodes for ST flashes */
7263 +#define SSB_CHIPCO_FLASHCTL_ST_WREN    0x0006          /* Write Enable */
7264 +#define SSB_CHIPCO_FLASHCTL_ST_WRDIS   0x0004          /* Write Disable */
7265 +#define SSB_CHIPCO_FLASHCTL_ST_RDSR    0x0105          /* Read Status Register */
7266 +#define SSB_CHIPCO_FLASHCTL_ST_WRSR    0x0101          /* Write Status Register */
7267 +#define SSB_CHIPCO_FLASHCTL_ST_READ    0x0303          /* Read Data Bytes */
7268 +#define SSB_CHIPCO_FLASHCTL_ST_PP      0x0302          /* Page Program */
7269 +#define SSB_CHIPCO_FLASHCTL_ST_SE      0x02D8          /* Sector Erase */
7270 +#define SSB_CHIPCO_FLASHCTL_ST_BE      0x00C7          /* Bulk Erase */
7271 +#define SSB_CHIPCO_FLASHCTL_ST_DP      0x00B9          /* Deep Power-down */
7272 +#define SSB_CHIPCO_FLASHCTL_ST_RSIG    0x03AB          /* Read Electronic Signature */
7273 +
7274 +/* Status register bits for ST flashes */
7275 +#define SSB_CHIPCO_FLASHSTA_ST_WIP     0x01            /* Write In Progress */
7276 +#define SSB_CHIPCO_FLASHSTA_ST_WEL     0x02            /* Write Enable Latch */
7277 +#define SSB_CHIPCO_FLASHSTA_ST_BP      0x1C            /* Block Protect */
7278 +#define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT        2
7279 +#define SSB_CHIPCO_FLASHSTA_ST_SRWD    0x80            /* Status Register Write Disable */
7280 +
7281 +/* flashcontrol opcodes for Atmel flashes */
7282 +#define SSB_CHIPCO_FLASHCTL_AT_READ            0x07E8
7283 +#define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ       0x07D2
7284 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ       /* FIXME */
7285 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ       /* FIXME */
7286 +#define SSB_CHIPCO_FLASHCTL_AT_STATUS          0x01D7
7287 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE      0x0384
7288 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE      0x0387
7289 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM 0x0283  /* Erase program */
7290 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM 0x0286  /* Erase program */
7291 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM    0x0288
7292 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM    0x0289
7293 +#define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE      0x0281
7294 +#define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE     0x0250
7295 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM  0x0382  /* Write erase program */
7296 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM  0x0385  /* Write erase program */
7297 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD       0x0253
7298 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD       0x0255
7299 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE    0x0260
7300 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE    0x0261
7301 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM  0x0258
7302 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM  0x0259
7303 +
7304 +/* Status register bits for Atmel flashes */
7305 +#define SSB_CHIPCO_FLASHSTA_AT_READY   0x80
7306 +#define SSB_CHIPCO_FLASHSTA_AT_MISMATCH        0x40
7307 +#define SSB_CHIPCO_FLASHSTA_AT_ID      0x38
7308 +#define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT        3
7309 +
7310 +
7311 +/** OTP **/
7312 +
7313 +/* OTP regions */
7314 +#define        SSB_CHIPCO_OTP_HW_REGION        SSB_CHIPCO_OTPS_HW_PROTECT
7315 +#define        SSB_CHIPCO_OTP_SW_REGION        SSB_CHIPCO_OTPS_SW_PROTECT
7316 +#define        SSB_CHIPCO_OTP_CID_REGION       SSB_CHIPCO_OTPS_CID_PROTECT
7317 +
7318 +/* OTP regions (Byte offsets from otp size) */
7319 +#define        SSB_CHIPCO_OTP_SWLIM_OFF        (-8)
7320 +#define        SSB_CHIPCO_OTP_CIDBASE_OFF      0
7321 +#define        SSB_CHIPCO_OTP_CIDLIM_OFF       8
7322 +
7323 +/* Predefined OTP words (Word offset from otp size) */
7324 +#define        SSB_CHIPCO_OTP_BOUNDARY_OFF     (-4)
7325 +#define        SSB_CHIPCO_OTP_HWSIGN_OFF       (-3)
7326 +#define        SSB_CHIPCO_OTP_SWSIGN_OFF       (-2)
7327 +#define        SSB_CHIPCO_OTP_CIDSIGN_OFF      (-1)
7328 +
7329 +#define        SSB_CHIPCO_OTP_CID_OFF          0
7330 +#define        SSB_CHIPCO_OTP_PKG_OFF          1
7331 +#define        SSB_CHIPCO_OTP_FID_OFF          2
7332 +#define        SSB_CHIPCO_OTP_RSV_OFF          3
7333 +#define        SSB_CHIPCO_OTP_LIM_OFF          4
7334 +
7335 +#define        SSB_CHIPCO_OTP_SIGNATURE        0x578A
7336 +#define        SSB_CHIPCO_OTP_MAGIC            0x4E56
7337 +
7338 +
7339 +struct ssb_device;
7340 +struct ssb_serial_port;
7341 +
7342 +struct ssb_chipcommon {
7343 +       struct ssb_device *dev;
7344 +       u32 capabilities;
7345 +};
7346 +
7347 +enum ssb_clkmode {
7348 +       SSB_CLKMODE_SLOW,
7349 +       SSB_CLKMODE_FAST,
7350 +       SSB_CLKMODE_DYNAMIC,
7351 +};
7352 +
7353 +extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
7354 +extern void ssb_chipcommon_exit(struct ssb_chipcommon *cc);
7355 +
7356 +extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
7357 +                                       u32 *plltype, u32 *n, u32 *m);
7358 +extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
7359 +                                  unsigned long ns_per_cycle);
7360 +
7361 +#ifdef CONFIG_SSB_SERIAL
7362 +extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
7363 +                                 struct ssb_serial_port *ports);
7364 +#endif /* CONFIG_SSB_SERIAL */
7365 +
7366 +#endif /* __KERNEL__ */
7367 +#endif /* LINUX_SSB_CHIPCO_H_ */
7368 diff -urN linux.old/include/linux/ssb_driver_extif.h linux.dev/include/linux/ssb_driver_extif.h
7369 --- linux.old/include/linux/ssb_driver_extif.h  1970-01-01 01:00:00.000000000 +0100
7370 +++ linux.dev/include/linux/ssb_driver_extif.h  2007-01-03 02:26:02.000000000 +0100
7371 @@ -0,0 +1,159 @@
7372 +/*
7373 + * Hardware-specific External Interface I/O core definitions
7374 + * for the BCM47xx family of SiliconBackplane-based chips.
7375 + *
7376 + * The External Interface core supports a total of three external chip selects
7377 + * supporting external interfaces. One of the external chip selects is
7378 + * used for Flash, one is used for PCMCIA, and the other may be
7379 + * programmed to support either a synchronous interface or an
7380 + * asynchronous interface. The asynchronous interface can be used to
7381 + * support external devices such as UARTs and the BCM2019 Bluetooth
7382 + * baseband processor.
7383 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
7384 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
7385 + *
7386 + * Copyright 2005, Broadcom Corporation
7387 + * Copyright 2006, Michael Buesch
7388 + *
7389 + * Licensed under the GPL version 2. See COPYING for details.
7390 + */
7391 +#ifndef LINUX_SSB_EXTIFCORE_H_
7392 +#define LINUX_SSB_EXTIFCORE_H_
7393 +
7394 +#ifdef __KERNEL__
7395 +
7396 +/* external interface address space */
7397 +#define        SSB_EXTIF_PCMCIA_MEMBASE(x)     (x)
7398 +#define        SSB_EXTIF_PCMCIA_IOBASE(x)      ((x) + 0x100000)
7399 +#define        SSB_EXTIF_PCMCIA_CFGBASE(x)     ((x) + 0x200000)
7400 +#define        SSB_EXTIF_CFGIF_BASE(x)         ((x) + 0x800000)
7401 +#define        SSB_EXTIF_FLASH_BASE(x)         ((x) + 0xc00000)
7402 +
7403 +#define SSB_EXTIF_NR_GPIOOUT           5
7404 +/* GPIO NOTE:
7405 + * The multiple instances of output and output enable registers
7406 + * are present to allow driver software for multiple cores to control
7407 + * gpio outputs without needing to share a single register pair.
7408 + * Use the following helper macro to get a register offset value.
7409 + */
7410 +#define SSB_EXTIF_GPIO_OUT(index)      ({              \
7411 +       BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT);    \
7412 +       SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8);        \
7413 +                                       })
7414 +#define SSB_EXTIF_GPIO_OUTEN(index)    ({              \
7415 +       BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT);    \
7416 +       SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8);      \
7417 +                                       })
7418 +
7419 +/** EXTIF core registers **/
7420 +
7421 +#define SSB_EXTIF_CTL                  0x0000
7422 +#define  SSB_EXTIF_CTL_UARTEN          (1 << 0) /* UART enable */
7423 +#define SSB_EXTIF_EXTSTAT              0x0004
7424 +#define  SSB_EXTIF_EXTSTAT_EMODE       (1 << 0) /* Endian mode (ro) */
7425 +#define  SSB_EXTIF_EXTSTAT_EIRQPIN     (1 << 1) /* External interrupt pin (ro) */
7426 +#define  SSB_EXTIF_EXTSTAT_GPIOIRQPIN  (1 << 2) /* GPIO interrupt pin (ro) */
7427 +#define SSB_EXTIF_PCMCIA_CFG           0x0010
7428 +#define SSB_EXTIF_PCMCIA_MEMWAIT       0x0014
7429 +#define SSB_EXTIF_PCMCIA_ATTRWAIT      0x0018
7430 +#define SSB_EXTIF_PCMCIA_IOWAIT                0x001C
7431 +#define SSB_EXTIF_PROG_CFG             0x0020
7432 +#define SSB_EXTIF_PROG_WAITCNT         0x0024
7433 +#define SSB_EXTIF_FLASH_CFG            0x0028
7434 +#define SSB_EXTIF_FLASH_WAITCNT                0x002C
7435 +#define SSB_EXTIF_WATCHDOG             0x0040
7436 +#define SSB_EXTIF_CLOCK_N              0x0044
7437 +#define SSB_EXTIF_CLOCK_SB             0x0048
7438 +#define SSB_EXTIF_CLOCK_PCI            0x004C
7439 +#define SSB_EXTIF_CLOCK_MII            0x0050
7440 +#define SSB_EXTIF_GPIO_IN              0x0060
7441 +#define SSB_EXTIF_GPIO_OUT_BASE                0x0064
7442 +#define SSB_EXTIF_GPIO_OUTEN_BASE      0x0068
7443 +#define SSB_EXTIF_EJTAG_OUTEN          0x0090
7444 +#define SSB_EXTIF_GPIO_INTPOL          0x0094
7445 +#define SSB_EXTIF_GPIO_INTMASK         0x0098
7446 +#define SSB_EXTIF_UART_DATA            0x0300
7447 +#define SSB_EXTIF_UART_TIMER           0x0310
7448 +#define SSB_EXTIF_UART_FCR             0x0320
7449 +#define SSB_EXTIF_UART_LCR             0x0330
7450 +#define SSB_EXTIF_UART_MCR             0x0340
7451 +#define SSB_EXTIF_UART_LSR             0x0350
7452 +#define SSB_EXTIF_UART_MSR             0x0360
7453 +#define SSB_EXTIF_UART_SCRATCH         0x0370
7454 +
7455 +
7456 +
7457 +
7458 +/* pcmcia/prog/flash_config */
7459 +#define        SSB_EXTCFG_EN                   (1 << 0)        /* enable */
7460 +#define        SSB_EXTCFG_MODE                 0xE             /* mode */
7461 +#define        SSB_EXTCFG_MODE_SHIFT           1
7462 +#define         SSB_EXTCFG_MODE_FLASH          0x0             /* flash/asynchronous mode */
7463 +#define         SSB_EXTCFG_MODE_SYNC           0x2             /* synchronous mode */
7464 +#define         SSB_EXTCFG_MODE_PCMCIA         0x4             /* pcmcia mode */
7465 +#define        SSB_EXTCFG_DS16                 (1 << 4)        /* destsize:  0=8bit, 1=16bit */
7466 +#define        SSB_EXTCFG_BSWAP                (1 << 5)        /* byteswap */
7467 +#define        SSB_EXTCFG_CLKDIV               0xC0            /* clock divider */
7468 +#define        SSB_EXTCFG_CLKDIV_SHIFT         6
7469 +#define         SSB_EXTCFG_CLKDIV_2            0x0             /* backplane/2 */
7470 +#define         SSB_EXTCFG_CLKDIV_3            0x40            /* backplane/3 */
7471 +#define         SSB_EXTCFG_CLKDIV_4            0x80            /* backplane/4 */
7472 +#define        SSB_EXTCFG_CLKEN                (1 << 8)        /* clock enable */
7473 +#define        SSB_EXTCFG_STROBE               (1 << 9)        /* size/bytestrobe (synch only) */
7474 +
7475 +/* pcmcia_memwait */
7476 +#define        SSB_PCMCIA_MEMW_0               0x0000003F      /* waitcount0 */
7477 +#define        SSB_PCMCIA_MEMW_1               0x00001F00      /* waitcount1 */
7478 +#define        SSB_PCMCIA_MEMW_1_SHIFT         8
7479 +#define        SSB_PCMCIA_MEMW_2               0x001F0000      /* waitcount2 */
7480 +#define        SSB_PCMCIA_MEMW_2_SHIFT         16
7481 +#define        SSB_PCMCIA_MEMW_3               0x1F000000      /* waitcount3 */
7482 +#define        SSB_PCMCIA_MEMW_3_SHIFT         24
7483 +
7484 +/* pcmcia_attrwait */
7485 +#define        SSB_PCMCIA_ATTW_0               0x0000003F      /* waitcount0 */
7486 +#define        SSB_PCMCIA_ATTW_1               0x00001F00      /* waitcount1 */
7487 +#define        SSB_PCMCIA_ATTW_1_SHIFT         8
7488 +#define        SSB_PCMCIA_ATTW_2               0x001F0000      /* waitcount2 */
7489 +#define        SSB_PCMCIA_ATTW_2_SHIFT         16
7490 +#define        SSB_PCMCIA_ATTW_3               0x1F000000      /* waitcount3 */
7491 +#define        SSB_PCMCIA_ATTW_3_SHIFT         24
7492 +
7493 +/* pcmcia_iowait */
7494 +#define        SSB_PCMCIA_IOW_0                0x0000003F      /* waitcount0 */
7495 +#define        SSB_PCMCIA_IOW_1                0x00001F00      /* waitcount1 */
7496 +#define        SSB_PCMCIA_IOW_1_SHIFT          8
7497 +#define        SSB_PCMCIA_IOW_2                0x001F0000      /* waitcount2 */
7498 +#define        SSB_PCMCIA_IOW_2_SHIFT          16
7499 +#define        SSB_PCMCIA_IOW_3                0x1F000000      /* waitcount3 */
7500 +#define        SSB_PCMCIA_IOW_3_SHIFT          24
7501 +
7502 +/* prog_waitcount */
7503 +#define        SSB_PROG_WCNT_0                 0x0000001F      /* waitcount0 */
7504 +#define        SSB_PROG_WCNT_1                 0x00001F00      /* waitcount1 */
7505 +#define        SSB_PROG_WCNT_1_SHIFT           8
7506 +#define        SSB_PROG_WCNT_2                 0x001F0000      /* waitcount2 */
7507 +#define        SSB_PROG_WCNT_2_SHIFT           16
7508 +#define        SSB_PROG_WCNT_3                 0x1F000000      /* waitcount3 */
7509 +#define        SSB_PROG_WCNT_3_SHIFT           24
7510 +
7511 +#define SSB_PROG_W0                    0x0000000C
7512 +#define SSB_PROG_W1                    0x00000A00
7513 +#define SSB_PROG_W2                    0x00020000
7514 +#define SSB_PROG_W3                    0x01000000
7515 +
7516 +/* flash_waitcount */
7517 +#define        SSB_FLASH_WCNT_0                0x0000001F      /* waitcount0 */
7518 +#define        SSB_FLASH_WCNT_1                0x00001F00      /* waitcount1 */
7519 +#define        SSB_FLASH_WCNT_1_SHIFT          8
7520 +#define        SSB_FLASH_WCNT_2                0x001F0000      /* waitcount2 */
7521 +#define        SSB_FLASH_WCNT_2_SHIFT          16
7522 +#define        SSB_FLASH_WCNT_3                0x1F000000      /* waitcount3 */
7523 +#define        SSB_FLASH_WCNT_3_SHIFT          24
7524 +
7525 +/* watchdog */
7526 +#define SSB_EXTIF_WATCHDOG_CLK         48000000        /* Hz */
7527 +
7528 +
7529 +#endif /* __KERNEL__ */
7530 +#endif /* LINUX_SSB_EXTIFCORE_H_ */
7531 diff -urN linux.old/include/linux/ssb_driver_mips.h linux.dev/include/linux/ssb_driver_mips.h
7532 --- linux.old/include/linux/ssb_driver_mips.h   1970-01-01 01:00:00.000000000 +0100
7533 +++ linux.dev/include/linux/ssb_driver_mips.h   2007-01-03 02:26:02.000000000 +0100
7534 @@ -0,0 +1,46 @@
7535 +#ifndef LINUX_SSB_MIPSCORE_H_
7536 +#define LINUX_SSB_MIPSCORE_H_
7537 +
7538 +#ifdef __KERNEL__
7539 +
7540 +#ifdef CONFIG_SSB_DRIVER_MIPS
7541 +
7542 +struct ssb_device;
7543 +
7544 +struct ssb_serial_port {
7545 +       void *regs;
7546 +       unsigned int irq;
7547 +       unsigned int baud_base;
7548 +       unsigned int reg_shift;
7549 +};
7550 +
7551 +
7552 +struct ssb_mipscore {
7553 +       struct ssb_device *dev;
7554 +
7555 +       int nr_serial_ports;
7556 +       struct ssb_serial_port serial_ports[4];
7557 +
7558 +       u32 flash_window;
7559 +       u32 flash_window_size;
7560 +};
7561 +
7562 +extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
7563 +
7564 +extern unsigned int ssb_mips_irq(struct ssb_device *dev);
7565 +
7566 +
7567 +#else /* CONFIG_SSB_DRIVER_MIPS */
7568 +
7569 +struct ssb_mipscore {
7570 +};
7571 +
7572 +static inline
7573 +void ssb_mipscore_init(struct ssb_mipscore *mcore)
7574 +{
7575 +}
7576 +
7577 +#endif /* CONFIG_SSB_DRIVER_MIPS */
7578 +
7579 +#endif /* __KERNEL__ */
7580 +#endif /* LINUX_SSB_MIPSCORE_H_ */
7581 diff -urN linux.old/include/linux/ssb_driver_pci.h linux.dev/include/linux/ssb_driver_pci.h
7582 --- linux.old/include/linux/ssb_driver_pci.h    1970-01-01 01:00:00.000000000 +0100
7583 +++ linux.dev/include/linux/ssb_driver_pci.h    2007-01-03 02:26:02.000000000 +0100
7584 @@ -0,0 +1,35 @@
7585 +#ifndef LINUX_SSB_PCICORE_H_
7586 +#define LINUX_SSB_PCICORE_H_
7587 +#ifndef __KERNEL__
7588 +
7589 +
7590 +/* PCI core registers. */
7591 +#define SSB_PCICORE_CTL                0x0000  /* PCI Control */
7592 +#define SSB_PCICORE_ARBCTL     0x0010  /* PCI Arbiter Control */
7593 +#define SSB_PCICORE_ISTAT      0x0020  /* Interrupt status */
7594 +#define SSB_PCICORE_IMASK      0x0024  /* Interrupt mask */
7595 +#define SSB_PCICORE_MBOX       0x0028  /* Backplane to PCI Mailbox */
7596 +#define SSB_PCICORE_BCAST_ADDR 0x0050  /* Backplane Broadcast Address */
7597 +#define SSB_PCICORE_BCAST_DATA 0x0054  /* Backplane Broadcast Data */
7598 +#define SSB_PCICORE_GPIO_IN    0x0060  /* rev >= 2 only */
7599 +#define SSB_PCICORE_GPIO_OUT   0x0064  /* rev >= 2 only */
7600 +#define SSB_PCICORE_GPIO_ENABLE        0x0068  /* rev >= 2 only */
7601 +#define SSB_PCICORE_GPIO_CTL   0x006C  /* rev >= 2 only */
7602 +#define SSB_PCICORE_TRANS0     0x0100  /* Backplane to PCI translation 0 (sbtopci0) */
7603 +#define SSB_PCICORE_TRANS1     0x0104  /* Backplane to PCI translation 1 (sbtopci1) */
7604 +#define SSB_PCICORE_TRANS2     0x0108  /* Backplane to PCI translation 2 (dbtopci2) */
7605 +#define  SSB_PCICORE_TRANS2_MEM                0x00000000
7606 +#define  SSB_PCICORE_TRANS2_IO         0x00000001
7607 +#define  SSB_PCICORE_TRANS2_CFG0       0x00000002
7608 +#define  SSB_PCICORE_TRANS2_CFG1       0x00000003
7609 +#define  SSB_PCICORE_TRANS2_PREF       0x00000004      /* Prefetch enable */
7610 +#define  SSB_PCICORE_TRANS2_BURST      0x00000008      /* Burst enable */
7611 +#define  SSB_PCICORE_TRANS2_MRM                0x00000020      /* Memory Read Multiple */
7612 +#define  SSB_PCICORE_TRANS2_MASK0      0xfc000000
7613 +#define  SSB_PCICORE_TRANS2_MASK1      0xfc000000
7614 +#define  SSB_PCICORE_TRANS2_MASK2      0xc0000000
7615 +
7616 +
7617 +
7618 +#endif /* __KERNEL__ */
7619 +#endif /* LINUX_SSB_PCICORE_H_ */
7620 diff -urN linux.old/include/linux/ssb.h linux.dev/include/linux/ssb.h
7621 --- linux.old/include/linux/ssb.h       1970-01-01 01:00:00.000000000 +0100
7622 +++ linux.dev/include/linux/ssb.h       2007-01-03 02:26:02.000000000 +0100
7623 @@ -0,0 +1,263 @@
7624 +#ifndef LINUX_SSB_H_
7625 +#define LINUX_SSB_H_
7626 +#ifdef __KERNEL__
7627 +
7628 +#include <linux/device.h>
7629 +#include <linux/list.h>
7630 +#include <linux/types.h>
7631 +#include <linux/spinlock.h>
7632 +
7633 +#include <linux/ssb_regs.h>
7634 +
7635 +
7636 +struct ssb_bus;
7637 +struct ssb_driver;
7638 +
7639 +
7640 +struct ssb_sprom_r1 {
7641 +       u16 pci_spid;           /* Subsystem Product ID for PCI */
7642 +       u16 pci_svid;           /* Subsystem Vendor ID for PCI */
7643 +       u16 pci_pid;            /* Product ID for PCI */
7644 +       u8 il0mac[6];           /* MAC address for 802.11b/g */
7645 +       u8 et0mac[6];           /* MAC address for Ethernet */
7646 +       u8 et1mac[6];           /* MAC address for 802.11a */
7647 +       u8 et0phyaddr:5;        /* MII address for enet0 */
7648 +       u8 et1phyaddr:5;        /* MII address for enet1 */
7649 +       u8 et0mdcport:1;        /* MDIO for enet0 */
7650 +       u8 et1mdcport:1;        /* MDIO for enet1 */
7651 +       u8 board_rev;           /* Board revision */
7652 +       u8 country_code:4;      /* Country Code */
7653 +       u8 antenna_a:2;         /* Antenna 0/1 available for A-PHY */
7654 +       u8 antenna_bg:2;        /* Antenna 0/1 available for B-PHY and G-PHY */
7655 +       u16 pa0b0;
7656 +       u16 pa0b1;
7657 +       u16 pa0b2;
7658 +       u16 pa1b0;
7659 +       u16 pa1b1;
7660 +       u16 pa1b2;
7661 +       u8 gpio0;               /* GPIO pin 0 */
7662 +       u8 gpio1;               /* GPIO pin 1 */
7663 +       u8 gpio2;               /* GPIO pin 2 */
7664 +       u8 gpio3;               /* GPIO pin 3 */
7665 +       u16 maxpwr_a;           /* A-PHY Power Amplifier Max Power (in dBm Q5.2) */
7666 +       u16 maxpwr_bg;          /* B/G-PHY Power Amplifier Max Power (in dBm Q5.2) */
7667 +       u8 itssi_a;             /* Idle TSSI Target for A-PHY */
7668 +       u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */
7669 +       u16 boardflags_lo;      /* Boardflags (low 16 bits) */
7670 +       u8 antenna_gain_a;      /* A-PHY Antenna gain (in dBm Q5.2) */
7671 +       u8 antenna_gain_bg;     /* B/G-PHY Antenna gain (in dBm Q5.2) */
7672 +       u8 oem[8];              /* OEM string (rev 1 only) */
7673 +};
7674 +
7675 +struct ssb_sprom_r2 {
7676 +       u16 boardflags_hi;      /* Boardflags (high 16 bits) */
7677 +       u8 maxpwr_a_lo;         /* A-PHY Max Power Low */
7678 +       u8 maxpwr_a_hi;         /* A-PHY Max Power High */
7679 +       u16 pa1lob0;            /* A-PHY PA Low Settings */
7680 +       u16 pa1lob1;            /* A-PHY PA Low Settings */
7681 +       u16 pa1lob2;            /* A-PHY PA Low Settings */
7682 +       u16 pa1hib0;            /* A-PHY PA High Settings */
7683 +       u16 pa1hib1;            /* A-PHY PA High Settings */
7684 +       u16 pa1hib2;            /* A-PHY PA High Settings */
7685 +       u8 ofdm_pwr_off;        /* OFDM Power Offset from CCK Level */
7686 +       u8 country_str[2];      /* Two char Country Code */
7687 +};
7688 +
7689 +struct ssb_sprom_r3 {
7690 +       u32 ofdmapo;            /* A-PHY OFDM Mid Power Offset */
7691 +       u32 ofdmalpo;           /* A-PHY OFDM Low Power Offset */
7692 +       u32 ofdmahpo;           /* A-PHY OFDM High Power Offset */
7693 +       u8 gpioldc_on_cnt;      /* GPIO LED Powersave Duty Cycle ON count */
7694 +       u8 gpioldc_off_cnt;     /* GPIO LED Powersave Duty Cycle OFF count */
7695 +       u8 cckpo_1M:4;          /* CCK Power Offset for Rate 1M */
7696 +       u8 cckpo_2M:4;          /* CCK Power Offset for Rate 2M */
7697 +       u8 cckpo_55M:4;         /* CCK Power Offset for Rate 5.5M */
7698 +       u8 cckpo_11M:4;         /* CCK Power Offset for Rate 11M */
7699 +       u32 ofdmgpo;            /* G-PHY OFDM Power Offset */
7700 +};
7701 +
7702 +struct ssb_sprom_r4 {
7703 +       /* TODO */
7704 +};
7705 +
7706 +struct ssb_sprom {
7707 +       u8 revision;
7708 +       u8 crc;
7709 +       /* The valid r# fields are selected by the "revision".
7710 +        * Revision 3 and lower inherit from lower revisions.
7711 +        */
7712 +       union {
7713 +               struct {
7714 +                       struct ssb_sprom_r1 r1;
7715 +                       struct ssb_sprom_r2 r2;
7716 +                       struct ssb_sprom_r3 r3;
7717 +               };
7718 +               struct ssb_sprom_r4 r4;
7719 +       };
7720 +};
7721 +
7722 +
7723 +/* Core-ID values. */
7724 +#define SSB_DEV_CHIPCOMMON     0x800
7725 +#define SSB_DEV_ILINE20                0x801
7726 +#define SSB_DEV_SDRAM          0x803
7727 +#define SSB_DEV_PCI            0x804
7728 +#define SSB_DEV_MIPS           0x805
7729 +#define SSB_DEV_ETHERNET       0x806
7730 +#define SSB_DEV_V90            0x807
7731 +#define SSB_DEV_USB11_HOSTDEV  0x808
7732 +#define SSB_DEV_ADSL           0x809
7733 +#define SSB_DEV_ILINE100       0x80A
7734 +#define SSB_DEV_IPSEC          0x80B
7735 +#define SSB_DEV_PCMCIA         0x80D
7736 +#define SSB_DEV_INTERNAL_MEM   0x80E
7737 +#define SSB_DEV_MEMC_SDRAM     0x80F
7738 +#define SSB_DEV_EXTIF          0x811
7739 +#define SSB_DEV_80211          0x812
7740 +#define SSB_DEV_MIPS_3302      0x816
7741 +#define SSB_DEV_USB11_HOST     0x817
7742 +#define SSB_DEV_USB11_DEV      0x818
7743 +#define SSB_DEV_USB20_HOST     0x819
7744 +#define SSB_DEV_USB20_DEV      0x81A
7745 +#define SSB_DEV_SDIO_HOST      0x81B
7746 +#define SSB_DEV_ROBOSWITCH     0x81C
7747 +#define SSB_DEV_PARA_ATA       0x81D
7748 +#define SSB_DEV_SATA_XORDMA    0x81E
7749 +#define SSB_DEV_ETHERNET_GBIT  0x81F
7750 +#define SSB_DEV_PCIE           0x820
7751 +#define SSB_DEV_MIMO_PHY       0x821
7752 +#define SSB_DEV_SRAM_CTRLR     0x822
7753 +#define SSB_DEV_MINI_MACPHY    0x823
7754 +#define SSB_DEV_ARM_1176       0x824
7755 +#define SSB_DEV_ARM_7TDMI      0x825
7756 +
7757 +/* Vendor-ID values */
7758 +#define SSB_VENDOR_BROADCOM    0x4243
7759 +
7760 +struct ssb_device_id {
7761 +       u16 vendor;
7762 +       u16 coreid;
7763 +       u8 revision;
7764 +};
7765 +#define SSB_DEVICE(_vendor, _coreid, _revision)  \
7766 +       { .vendor = _vendor, .coreid = _coreid, .revision = _revision, }
7767 +#define SSB_DEVTABLE_END  \
7768 +       { 0, },
7769 +
7770 +#define SSB_ANY_VENDOR         0xFFFF
7771 +#define SSB_ANY_ID             0xFFFF
7772 +#define SSB_ANY_REV            0xFF
7773 +
7774 +
7775 +struct ssb_device {
7776 +       struct device dev;
7777 +       struct ssb_bus *bus;
7778 +       struct ssb_device_id id;
7779 +
7780 +       u8 core_index;
7781 +       u32 dma_routing;        //FIXME assign this! move to bus? Use helper function?
7782 +       unsigned int irq;
7783 +       void *drvdata;
7784 +};
7785 +#define dev_to_ssb_dev(_dev) container_of(_dev, struct ssb_device, dev)
7786 +
7787 +static inline
7788 +void ssb_set_drvdata(struct ssb_device *dev, void *data)
7789 +{
7790 +       dev->drvdata = data;
7791 +}
7792 +static inline
7793 +void * ssb_get_drvdata(struct ssb_device *dev)
7794 +{
7795 +       return dev->drvdata;
7796 +}
7797 +
7798 +u16 ssb_read16(struct ssb_device *dev, u16 offset);
7799 +u32 ssb_read32(struct ssb_device *dev, u16 offset);
7800 +void ssb_write16(struct ssb_device *dev, u16 offset, u16 value);
7801 +void ssb_write32(struct ssb_device *dev, u16 offset, u32 value);
7802 +
7803 +
7804 +struct ssb_driver {
7805 +       const char *name;
7806 +       const struct ssb_device_id *id_table;
7807 +
7808 +       int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
7809 +       void (*remove)(struct ssb_device *dev);
7810 +       int (*suspend)(struct ssb_device *dev, pm_message_t state);
7811 +       int (*resume)(struct ssb_device *dev);
7812 +       void (*shutdown)(struct ssb_device *dev);
7813 +
7814 +       struct device_driver drv;
7815 +};
7816 +#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
7817 +
7818 +extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
7819 +static inline int ssb_driver_register(struct ssb_driver *drv)
7820 +{
7821 +       return __ssb_driver_register(drv, THIS_MODULE);
7822 +}
7823 +extern void ssb_driver_unregister(struct ssb_driver *drv);
7824 +
7825 +
7826 +
7827 +
7828 +enum ssb_bustype {
7829 +       SSB_BUSTYPE_SSB,        /* This SSB bus is the system bus */
7830 +       SSB_BUSTYPE_PCI,        /* SSB is connected to PCI bus */
7831 +       //FIXME JTAG?
7832 +};
7833 +
7834 +#include <linux/ssb_driver_chipcommon.h>
7835 +#include <linux/ssb_driver_mips.h>
7836 +#include <linux/ssb_driver_extif.h>
7837 +
7838 +struct ssb_bus {
7839 +       enum ssb_bustype bustype;
7840 +       struct pci_dev *host_pci;
7841 +       void __iomem *mmio;
7842 +
7843 +       u16 chip_id;
7844 +       u16 chip_rev;
7845 +       u8 chip_package;
7846 +       struct ssb_sprom sprom;
7847 +
7848 +       spinlock_t bar_lock;
7849 +       struct ssb_device *mapped_device;
7850 +       int nr_devices;
7851 +       struct ssb_device devices[SSB_MAX_NR_CORES]; /* cores */
7852 +
7853 +       struct ssb_chipcommon chipco;
7854 +       struct ssb_mipscore mipscore;
7855 +
7856 +       int busnumber;
7857 +       struct list_head list;
7858 +};
7859 +
7860 +extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
7861 +                                  unsigned long baseaddr,
7862 +                                  void (*fill_sprom)(struct ssb_sprom *sprom));
7863 +extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
7864 +                                  struct pci_dev *host_pci);
7865 +extern void ssb_bus_unregister(struct ssb_bus *bus);
7866 +extern u32 ssb_clockspeed(struct ssb_bus *bus);
7867 +
7868 +int ssb_core_is_enabled(struct ssb_device *dev);
7869 +void ssb_core_enable(struct ssb_device *dev, u32 core_specific_flags);
7870 +void ssb_core_disable(struct ssb_device *dev, u32 core_specific_flags);
7871 +
7872 +static inline dma_addr_t ssb_dma_offset(struct ssb_device *dev)
7873 +{
7874 +       switch(dev->bus->bustype) {
7875 +       case SSB_BUSTYPE_SSB:
7876 +               return 0;
7877 +       case SSB_BUSTYPE_PCI:
7878 +               return SSB_PCI_DMA;
7879 +       }
7880 +       return 0;
7881 +}
7882 +
7883 +
7884 +
7885 +#endif /* __KERNEL__ */
7886 +#endif /* LINUX_SSB_H_ */
7887 diff -urN linux.old/include/linux/ssb_regs.h linux.dev/include/linux/ssb_regs.h
7888 --- linux.old/include/linux/ssb_regs.h  1970-01-01 01:00:00.000000000 +0100
7889 +++ linux.dev/include/linux/ssb_regs.h  2007-01-03 02:26:02.000000000 +0100
7890 @@ -0,0 +1,267 @@
7891 +#ifndef LINUX_SSB_REGS_H_
7892 +#define LINUX_SSB_REGS_H_
7893 +#ifdef __KERNEL__
7894 +
7895 +
7896 +/* SiliconBackplane Address Map.
7897 + * All regions may not exist on all chips.
7898 + */
7899 +#define SSB_SDRAM_BASE         0x00000000      /* Physical SDRAM */
7900 +#define SSB_PCI_MEM            0x08000000      /* Host Mode sb2pcitranslation0 (64 MB) */
7901 +#define SSB_PCI_CFG            0x0c000000      /* Host Mode sb2pcitranslation1 (64 MB) */
7902 +#define        SSB_SDRAM_SWAPPED       0x10000000      /* Byteswapped Physical SDRAM */
7903 +#define SSB_ENUM_BASE          0x18000000      /* Enumeration space base */
7904 +#define        SSB_ENUM_LIMIT          0x18010000      /* Enumeration space limit */
7905 +
7906 +#define        SSB_FLASH2              0x1c000000      /* Flash Region 2 (region 1 shadowed here) */
7907 +#define        SSB_FLASH2_SZ           0x02000000      /* Size of Flash Region 2 */
7908 +
7909 +#define        SSB_EXTIF_BASE          0x1f000000      /* External Interface region base address */
7910 +#define        SSB_FLASH1              0x1fc00000      /* Flash Region 1 */
7911 +#define        SSB_FLASH1_SZ           0x00400000      /* Size of Flash Region 1 */
7912 +
7913 +#define SSB_PCI_DMA            0x40000000      /* Client Mode sb2pcitranslation2 (1 GB) */
7914 +#define SSB_PCI_DMA_SZ         0x40000000      /* Client Mode sb2pcitranslation2 size in bytes */
7915 +#define SSB_PCIE_DMA_L32               0x00000000      /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
7916 +#define SSB_PCIE_DMA_H32               0x80000000      /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
7917 +#define        SSB_EUART               (SB_EXTIF_BASE + 0x00800000)
7918 +#define        SSB_LED                 (SB_EXTIF_BASE + 0x00900000)
7919 +
7920 +
7921 +/* Enumeration space constants */
7922 +#define SSB_CORE_SIZE          0x1000  /* Size of a core MMIO area */
7923 +#define SSB_MAX_NR_CORES       ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
7924 +
7925 +
7926 +/* mips address */
7927 +#define        SSB_EJTAG               0xff200000      /* MIPS EJTAG space (2M) */
7928 +
7929 +
7930 +/* SSB PCI config space registers. */
7931 +#define        SSB_BAR0_WIN            0x80    /* Backplane address space 0 */
7932 +#define        SSB_BAR1_WIN            0x84    /* Backplane address space 1 */
7933 +#define        SSB_SPROMCTL            0x88    /* SPROM control */
7934 +#define  SSB_SPROMCTL_WE       0x10    /* SPROM write enable */
7935 +#define        SSB_BAR1_CONTROL        0x8c    /* Address space 1 burst control */
7936 +#define SSB_PCI_IRQS           0x90    /* PCI interrupts */
7937 +#define SSB_PCI_IRQMASK                0x94    /* PCI IRQ control and mask (pcirev >= 6 only) */
7938 +#define SSB_BACKPLANE_IRQS     0x98    /* Backplane Interrupts */
7939 +#define SSB_GPIO_IN            0xB0    /* GPIO Input (pcirev >= 3 only) */
7940 +#define SSB_GPIO_OUT           0xB4    /* GPIO Output (pcirev >= 3 only) */
7941 +#define SSB_GPIO_OUT_ENABLE    0xB8    /* GPIO Output Enable/Disable (pcirev >= 3 only) */
7942 +#define  SSB_GPIO_SCS          0x10    /* PCI config space bit 4 for 4306c0 slow clock source */
7943 +#define  SSB_GPIO_HWRAD                0x20    /* PCI config space GPIO 13 for hw radio disable */
7944 +#define  SSB_GPIO_XTAL         0x40    /* PCI config space GPIO 14 for Xtal powerup */
7945 +#define  SSB_GPIO_PLL          0x80    /* PCI config space GPIO 15 for PLL powerdown */
7946 +
7947 +
7948 +#define SSB_BAR0_MAX_RETRIES   50
7949 +
7950 +/* Silicon backplane configuration register definitions */
7951 +#define SSB_IPSFLAG            0x0F08
7952 +#define         SSB_IPSFLAG_IRQ1       0x0000003F /* which sbflags get routed to mips interrupt 1 */
7953 +#define         SSB_IPSFLAG_IRQ1_SHIFT 0
7954 +#define         SSB_IPSFLAG_IRQ2       0x00003F00 /* which sbflags get routed to mips interrupt 2 */
7955 +#define         SSB_IPSFLAG_IRQ2_SHIFT 8
7956 +#define         SSB_IPSFLAG_IRQ3       0x003F0000 /* which sbflags get routed to mips interrupt 3 */
7957 +#define         SSB_IPSFLAG_IRQ3_SHIFT 16
7958 +#define         SSB_IPSFLAG_IRQ4       0x3F000000 /* which sbflags get routed to mips interrupt 4 */
7959 +#define         SSB_IPSFLAG_IRQ4_SHIFT 24
7960 +#define SSB_TPSFLAG            0x0F18
7961 +#define  SSB_TPSFLAG_BPFLAG    0x0000003F /* Backplane flag # */
7962 +#define  SSB_TPSFLAG_ALWAYSIRQ 0x00000040 /* IRQ is always sent on the Backplane */
7963 +#define SSB_TMERRLOGA          0x0F48
7964 +#define SSB_TMERRLOG           0x0F50
7965 +#define SSB_ADMATCH3           0x0F60
7966 +#define SSB_ADMATCH2           0x0F68
7967 +#define SSB_ADMATCH1           0x0F70
7968 +#define SSB_IMSTATE            0x0F90     /* SB Initiator Agent State */
7969 +#define  SSB_IMSTATE_PC                0x0000000f /* Pipe Count */
7970 +#define  SSB_IMSTATE_AP_MASK   0x00000030 /* Arbitration Priority */
7971 +#define  SSB_IMSTATE_AP_BOTH   0x00000000 /* Use both timeslices and token */
7972 +#define  SSB_IMSTATE_AP_TS     0x00000010 /* Use timeslices only */
7973 +#define  SSB_IMSTATE_AP_TK     0x00000020 /* Use token only */
7974 +#define  SSB_IMSTATE_AP_RSV    0x00000030 /* Reserved */
7975 +#define  SSB_IMSTATE_IBE       0x00020000 /* In Band Error */
7976 +#define  SSB_IMSTATE_TO                0x00040000 /* Timeout */
7977 +#define SSB_INTVEC             0x0F94     /* SB Interrupt Mask */
7978 +#define  SSB_INTVEC_PCI                0x00000001 /* Enable interrupts for PCI */
7979 +#define  SSB_INTVEC_ENET0      0x00000002 /* Enable interrupts for enet 0 */
7980 +#define  SSB_INTVEC_ILINE20    0x00000004 /* Enable interrupts for iline20 */
7981 +#define  SSB_INTVEC_CODEC      0x00000008 /* Enable interrupts for v90 codec */
7982 +#define  SSB_INTVEC_USB                0x00000010 /* Enable interrupts for usb */
7983 +#define  SSB_INTVEC_EXTIF      0x00000020 /* Enable interrupts for external i/f */
7984 +#define  SSB_INTVEC_ENET1      0x00000040 /* Enable interrupts for enet 1 */
7985 +#define SSB_TMSLOW             0x0F98     /* SB Target State Low */
7986 +#define  SSB_TMSLOW_RESET      0x00000001 /* Reset */
7987 +#define  SSB_TMSLOW_REJECT     0x00000002 /* Reject */
7988 +#define  SSB_TMSLOW_CLOCK      0x00010000 /* Clock Enable */
7989 +#define  SSB_TMSLOW_FGC                0x00020000 /* Force Gated Clocks On */
7990 +#define  SSB_TMSLOW_PE         0x40000000 /* Power Management Enable */
7991 +#define  SSB_TMSLOW_BE         0x80000000 /* BIST Enable */
7992 +#define SSB_TMSHIGH            0x0F9C     /* SB Target State High */
7993 +#define  SSB_TMSHIGH_SERR      0x00000001 /* S-error */
7994 +#define  SSB_TMSHIGH_INT       0x00000002 /* Interrupt */
7995 +#define  SSB_TMSHIGH_BUSY      0x00000004 /* Busy */
7996 +#define  SSB_TMSHIGH_TO                0x00000020 /* Timeout. Backplane rev >= 2.3 only */
7997 +#define  SSB_TMSHIGH_COREFL    0x1FFF0000 /* Core specific flags */
7998 +#define  SSB_TMSHIGH_COREFL_SHIFT      16
7999 +#define  SSB_TMSHIGH_DMA64     0x10000000 /* 64bit DMA supported */
8000 +#define  SSB_TMSHIGH_GCR       0x20000000 /* Gated Clock Request */
8001 +#define  SSB_TMSHIGH_BISTF     0x40000000 /* BIST Failed */
8002 +#define  SSB_TMSHIGH_BISTD     0x80000000 /* BIST Done */
8003 +#define SSB_BWA0               0x0FA0
8004 +#define SSB_IMCFGLO            0x0FA8
8005 +#define  SSB_IMCFGLO_SERTO     0x00000007 /* Service timeout */
8006 +#define  SSB_IMCFGLO_REQTO     0x00000070 /* Request timeout */
8007 +#define  SSB_IMCFGLO_REQTO_SHIFT       4
8008 +#define  SSB_IMCFGLO_CONNID    0x00FF0000 /* Connection ID */
8009 +#define  SSB_IMCFGLO_CONNID_SHIFT      16
8010 +#define SSB_IMCFGHI            0x0FAC
8011 +#define SSB_BCONFIG            0x0FC0
8012 +#define SSB_BSTATE             0x0FC8
8013 +#define SSB_ACTCFG             0x0FD8
8014 +#define SSB_FLAGST             0x0FE8
8015 +#define SSB_IDLOW              0x0FF8
8016 +#define  SSB_IDLOW_CFGSP       0x00000003 /* Config Space */
8017 +#define  SSB_IDLOW_ADDRNGE     0x00000038 /* Address Ranges supported */
8018 +#define  SSB_IDLOW_ADDRNGE_SHIFT       3
8019 +#define  SSB_IDLOW_SYNC                0x00000040
8020 +#define  SSB_IDLOW_INITIATOR   0x00000080
8021 +#define  SSB_IDLOW_MIBL                0x00000F00 /* Minimum Backplane latency */
8022 +#define  SSB_IDLOW_MIBL_SHIFT  8
8023 +#define  SSB_IDLOW_MABL                0x0000F000 /* Maximum Backplane latency */
8024 +#define  SSB_IDLOW_MABL_SHIFT  12
8025 +#define  SSB_IDLOW_TIF         0x00010000 /* This Initiator is first */
8026 +#define  SSB_IDLOW_CCW         0x000C0000 /* Cycle counter width */
8027 +#define  SSB_IDLOW_CCW_SHIFT   18
8028 +#define  SSB_IDLOW_TPT         0x00F00000 /* Target ports */
8029 +#define  SSB_IDLOW_TPT_SHIFT   20
8030 +#define  SSB_IDLOW_INITP       0x0F000000 /* Initiator ports */
8031 +#define  SSB_IDLOW_INITP_SHIFT 24
8032 +#define  SSB_IDLOW_SSBREV      0xF0000000 /* Sonics Backplane Revision code */
8033 +#define  SSB_IDLOW_SSBREV_22   0x00000000 /* <= 2.2 */
8034 +#define  SSB_IDLOW_SSBREV_23   0x10000000 /* 2.3 */
8035 +#define SSB_IDHIGH             0x0FFC     /* SB Identification High */
8036 +#define  SSB_IDHIGH_RCLO       0x0000000F /* Revision Code (low part) */
8037 +#define  SSB_IDHIGH_CC         0x00008FF0 /* Core Code */
8038 +#define  SSB_IDHIGH_CC_SHIFT   4
8039 +#define  SSB_IDHIGH_RCHI       0x00007000 /* Revision Code (high part) */
8040 +#define  SSB_IDHIGH_RCHI_SHIFT 8          /* yes, shift 8 is right */
8041 +#define  SSB_IDHIGH_VC         0xFFFF0000 /* Vendor Code */
8042 +#define  SSB_IDHIGH_VC_SHIFT   16
8043 +
8044 +/* SPROM shadow area. If not otherwise noted, fields are
8045 + * two bytes wide. Note that the SPROM can _only_ be read
8046 + * in two-byte quantinies.
8047 + */
8048 +#define SSB_SPROMSIZE_WORDS            64
8049 +#define SSB_SPROMSIZE_BYTES            (SSB_SPROMSIZE_WORDS * sizeof(u16))
8050 +#define SSB_SPROM_BASE                 0x1000
8051 +#define SSB_SPROM_REVISION             0x107E
8052 +#define  SSB_SPROM_REVISION_REV                0x00FF  /* SPROM Revision number */
8053 +#define  SSB_SPROM_REVISION_CRC                0xFF00  /* SPROM CRC8 value */
8054 +#define  SSB_SPROM_REVISION_CRC_SHIFT  8
8055 +/* SPROM Revision 1 */
8056 +#define SSB_SPROM1_SPID                        0x1004  /* Subsystem Product ID for PCI */
8057 +#define SSB_SPROM1_SVID                        0x1006  /* Subsystem Vendor ID for PCI */
8058 +#define SSB_SPROM1_PID                 0x1008  /* Product ID for PCI */
8059 +#define SSB_SPROM1_IL0MAC              0x1048  /* 6 bytes MAC address for 802.11b/g */
8060 +#define SSB_SPROM1_ET0MAC              0x104E  /* 6 bytes MAC address for Ethernet */
8061 +#define SSB_SPROM1_ET1MAC              0x1054  /* 6 bytes MAC address for 802.11a */
8062 +#define SSB_SPROM1_ETHPHY              0x105A  /* Ethernet PHY settings */
8063 +#define  SSB_SPROM1_ETHPHY_ET0A                0x001F  /* MII Address for enet0 */
8064 +#define  SSB_SPROM1_ETHPHY_ET1A                0x03E0  /* MII Address for enet1 */
8065 +#define  SSB_SPROM1_ETHPHY_ET1A_SHIFT  5
8066 +#define  SSB_SPROM1_ETHPHY_ET0M                (1<<14) /* MDIO for enet0 */
8067 +#define  SSB_SPROM1_ETHPHY_ET1M                (1<<15) /* MDIO for enet1 */
8068 +#define SSB_SPROM1_BINF                        0x105C  /* Board info */
8069 +#define  SSB_SPROM1_BINF_BREV          0x00FF  /* Board Revision */
8070 +#define  SSB_SPROM1_BINF_CCODE         0x0F00  /* Country Code */
8071 +#define  SSB_SPROM1_BINF_CCODE_SHIFT   8
8072 +#define  SSB_SPROM1_BINF_ANTA          0x3000  /* Available A-PHY antennas */
8073 +#define  SSB_SPROM1_BINF_ANTA_SHIFT    12
8074 +#define  SSB_SPROM1_BINF_ANTBG         0xC000  /* Available B-PHY antennas */
8075 +#define  SSB_SPROM1_BINF_ANTBG_SHIFT   14
8076 +#define SSB_SPROM1_PA0B0               0x105E
8077 +#define SSB_SPROM1_PA0B1               0x1060
8078 +#define SSB_SPROM1_PA0B2               0x1062
8079 +#define SSB_SPROM1_GPIOA               0x1064  /* General Purpose IO pins 0 and 1 */
8080 +#define  SSB_SPROM1_GPIOA_P0           0x00FF  /* Pin 0 */
8081 +#define  SSB_SPROM1_GPIOA_P1           0xFF00  /* Pin 1 */
8082 +#define  SSB_SPROM1_GPIOA_P1_SHIFT     8
8083 +#define SSB_SPROM1_GPIOB               0x1066  /* General Purpuse IO pins 2 and 3 */
8084 +#define  SSB_SPROM1_GPIOB_P2           0x00FF  /* Pin 2 */
8085 +#define  SSB_SPROM1_GPIOB_P3           0xFF00  /* Pin 3 */
8086 +#define  SSB_SPROM1_GPIOB_P3_SHIFT     8
8087 +#define SSB_SPROM1_MAXPWR              0x1068  /* Power Amplifier Max Power */
8088 +#define  SSB_SPROM1_MAXPWR_A           0x00FF  /* A-PHY (in dBm Q5.2) */
8089 +#define  SSB_SPROM1_MAXPWR_BG          0xFF00  /* B-PHY and G-PHY (in dBm Q5.2) */
8090 +#define  SSB_SPROM1_MAXPWR_BG_SHIFT    8
8091 +#define SSB_SPROM1_PA1B0               0x106A
8092 +#define SSB_SPROM1_PA1B1               0x106C
8093 +#define SSB_SPROM1_PA1B2               0x106E
8094 +#define SSB_SPROM1_ITSSI               0x1070  /* Idle TSSI Target */
8095 +#define  SSB_SPROM1_ITSSI_A            0x00FF  /* A-PHY */
8096 +#define  SSB_SPROM1_ITSSI_BG           0xFF00  /* B-PHY and G-PHY */
8097 +#define  SSB_SPROM1_ITSSI_BG_SHIFT     8
8098 +#define SSB_SPROM1_BFLLO               0x1072  /* Boardflags (low 16 bits) */
8099 +#define SSB_SPROM1_AGAIN               0x1074  /* Antenna Gain (in dBm Q5.2) */
8100 +#define  SSB_SPROM1_AGAIN_A            0x00FF  /* A-PHY */
8101 +#define  SSB_SPROM1_AGAIN_BG           0xFF00  /* B-PHY and G-PHY */
8102 +#define  SSB_SPROM1_AGAIN_BG_SHIFT     8
8103 +#define SSB_SPROM1_OEM                 0x1076  /* 8 bytes OEM string (rev 1 only) */
8104 +/* SPROM Revision 2 (inherits from rev 1) */
8105 +#define SSB_SPROM2_BFLHI               0x1038  /* Boardflags (high 16 bits) */
8106 +#define SSB_SPROM2_MAXP_A              0x103A  /* A-PHY Max Power */
8107 +#define  SSB_SPROM2_MAXP_A_HI          0x00FF  /* Max Power High */
8108 +#define  SSB_SPROM2_MAXP_A_LO          0xFF00  /* Max Power Low */
8109 +#define  SSB_SPROM2_MAXP_A_LO_SHIFT    8
8110 +#define SSB_SPROM2_PA1LOB0             0x103C  /* A-PHY PowerAmplifier Low Settings */
8111 +#define SSB_SPROM2_PA1LOB1             0x103E  /* A-PHY PowerAmplifier Low Settings */
8112 +#define SSB_SPROM2_PA1LOB2             0x1040  /* A-PHY PowerAmplifier Low Settings */
8113 +#define SSB_SPROM2_PA1HIB0             0x1042  /* A-PHY PowerAmplifier High Settings */
8114 +#define SSB_SPROM2_PA1HIB1             0x1044  /* A-PHY PowerAmplifier High Settings */
8115 +#define SSB_SPROM2_PA1HIB2             0x1046  /* A-PHY PowerAmplifier High Settings */
8116 +#define SSB_SPROM2_OPO                 0x1078  /* OFDM Power Offset from CCK Level */
8117 +#define  SSB_SPROM2_OPO_VALUE          0x00FF
8118 +#define  SSB_SPROM2_OPO_UNUSED         0xFF00
8119 +#define SSB_SPROM2_CCODE               0x107C  /* Two char Country Code */
8120 +/* SPROM Revision 3 (inherits from rev 2) */
8121 +#define SSB_SPROM3_OFDMAPO             0x102C  /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
8122 +#define SSB_SPROM3_OFDMALPO            0x1030  /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
8123 +#define SSB_SPROM3_OFDMAHPO            0x1034  /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
8124 +#define SSB_SPROM3_GPIOLDC             0x1042  /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
8125 +#define  SSB_SPROM3_GPIOLDC_OFF                0x0000FF00      /* Off Count */
8126 +#define  SSB_SPROM3_GPIOLDC_OFF_SHIFT  8
8127 +#define  SSB_SPROM3_GPIOLDC_ON         0x00FF0000      /* On Count */
8128 +#define  SSB_SPROM3_GPIOLDC_ON_SHIFT   16
8129 +#define SSB_SPROM3_CCKPO               0x1078  /* CCK Power Offset */
8130 +#define  SSB_SPROM3_CCKPO_1M           0x000F  /* 1M Rate PO */
8131 +#define  SSB_SPROM3_CCKPO_2M           0x00F0  /* 2M Rate PO */
8132 +#define  SSB_SPROM3_CCKPO_2M_SHIFT     4
8133 +#define  SSB_SPROM3_CCKPO_55M          0x0F00  /* 5.5M Rate PO */
8134 +#define  SSB_SPROM3_CCKPO_55M_SHIFT    8
8135 +#define  SSB_SPROM3_CCKPO_11M          0xF000  /* 11M Rate PO */
8136 +#define  SSB_SPROM3_CCKPO_11M_SHIFT    12
8137 +#define  SSB_SPROM3_OFDMGPO            0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
8138 +
8139 +/* Values for SSB_SPROM1_BINF_CCODE */
8140 +enum {
8141 +       SSB_SPROM1CCODE_WORLD = 0,
8142 +       SSB_SPROM1CCODE_THAILAND,
8143 +       SSB_SPROM1CCODE_ISRAEL,
8144 +       SSB_SPROM1CCODE_JORDAN,
8145 +       SSB_SPROM1CCODE_CHINA,
8146 +       SSB_SPROM1CCODE_JAPAN,
8147 +       SSB_SPROM1CCODE_USA_CANADA_ANZ,
8148 +       SSB_SPROM1CCODE_EUROPE,
8149 +       SSB_SPROM1CCODE_USA_LOW,
8150 +       SSB_SPROM1CCODE_JAPAN_HIGH,
8151 +       SSB_SPROM1CCODE_ALL,
8152 +       SSB_SPROM1CCODE_NONE,
8153 +};
8154 +
8155 +
8156 +#endif /* __KERNEL__ */
8157 +#endif /* LINUX_SSB_REGS_H_ */