1 From a4d16d8d405371163b4dd7d7fc8d8e23569e1d63 Mon Sep 17 00:00:00 2001
2 From: Florian Meier <florian.meier@koalo.de>
3 Date: Fri, 22 Nov 2013 14:33:38 +0100
4 Subject: [PATCH 116/196] ASoC: Add support for BCM2708
6 This driver adds support for digital audio (I2S)
7 for the BCM2708 SoC that is used by the
8 Raspberry Pi. External audio codecs can be
9 connected to the Raspberry Pi via P5 header.
11 It relies on cyclic DMA engine support for BCM2708.
13 Signed-off-by: Florian Meier <florian.meier@koalo.de>
15 sound/soc/Kconfig | 1 +
16 sound/soc/Makefile | 1 +
17 sound/soc/bcm/Kconfig | 10 +
18 sound/soc/bcm/Makefile | 4 +
19 sound/soc/bcm/bcm2708-i2s.c | 940 ++++++++++++++++++++++++++++++++++++++++++++
20 5 files changed, 956 insertions(+)
21 create mode 100644 sound/soc/bcm/Kconfig
22 create mode 100644 sound/soc/bcm/Makefile
23 create mode 100644 sound/soc/bcm/bcm2708-i2s.c
25 diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
26 index 9e675c7..0e63522 100644
27 --- a/sound/soc/Kconfig
28 +++ b/sound/soc/Kconfig
29 @@ -36,6 +36,7 @@ config SND_SOC_GENERIC_DMAENGINE_PCM
30 # All the supported SoCs
31 source "sound/soc/atmel/Kconfig"
32 source "sound/soc/au1x/Kconfig"
33 +source "sound/soc/bcm/Kconfig"
34 source "sound/soc/blackfin/Kconfig"
35 source "sound/soc/cirrus/Kconfig"
36 source "sound/soc/davinci/Kconfig"
37 diff --git a/sound/soc/Makefile b/sound/soc/Makefile
38 index 197b6ae..e61febc 100644
39 --- a/sound/soc/Makefile
40 +++ b/sound/soc/Makefile
41 @@ -14,6 +14,7 @@ obj-$(CONFIG_SND_SOC) += codecs/
42 obj-$(CONFIG_SND_SOC) += generic/
43 obj-$(CONFIG_SND_SOC) += atmel/
44 obj-$(CONFIG_SND_SOC) += au1x/
45 +obj-$(CONFIG_SND_SOC) += bcm/
46 obj-$(CONFIG_SND_SOC) += blackfin/
47 obj-$(CONFIG_SND_SOC) += cirrus/
48 obj-$(CONFIG_SND_SOC) += davinci/
49 diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig
51 index 0000000..37c8f8c
53 +++ b/sound/soc/bcm/Kconfig
55 +config SND_BCM2708_SOC_I2S
56 + tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
57 + depends on MACH_BCM2708
59 + select SND_SOC_DMAENGINE_PCM
60 + select SND_SOC_GENERIC_DMAENGINE_PCM
62 + Say Y or M if you want to add support for codecs attached to
63 + the BCM2708 I2S interface. You will also need
64 + to select the audio interfaces to support below.
65 diff --git a/sound/soc/bcm/Makefile b/sound/soc/bcm/Makefile
67 index 0000000..486ea09
69 +++ b/sound/soc/bcm/Makefile
71 +# BCM2708 Platform Support
72 +snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o
74 +obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o
75 diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c
77 index 0000000..ebaf3d6
79 +++ b/sound/soc/bcm/bcm2708-i2s.c
82 + * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC
84 + * Author: Florian Meier <florian.meier@koalo.de>
88 + * Raspberry Pi PCM I2S ALSA Driver
89 + * Copyright (c) by Phil Poole 2013
91 + * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
92 + * Vladimir Barinov, <vbarinov@embeddedalley.com>
93 + * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
95 + * OMAP ALSA SoC DAI driver using McBSP port
96 + * Copyright (C) 2008 Nokia Corporation
97 + * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
98 + * Peter Ujfalusi <peter.ujfalusi@ti.com>
100 + * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
101 + * Author: Timur Tabi <timur@freescale.com>
102 + * Copyright 2007-2010 Freescale Semiconductor, Inc.
104 + * This program is free software; you can redistribute it and/or
105 + * modify it under the terms of the GNU General Public License
106 + * version 2 as published by the Free Software Foundation.
108 + * This program is distributed in the hope that it will be useful, but
109 + * WITHOUT ANY WARRANTY; without even the implied warranty of
110 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
111 + * General Public License for more details.
114 +#include <linux/init.h>
115 +#include <linux/module.h>
116 +#include <linux/device.h>
117 +#include <linux/slab.h>
118 +#include <linux/delay.h>
119 +#include <linux/io.h>
120 +#include <linux/clk.h>
122 +#include <sound/core.h>
123 +#include <sound/pcm.h>
124 +#include <sound/pcm_params.h>
125 +#include <sound/initval.h>
126 +#include <sound/soc.h>
127 +#include <sound/dmaengine_pcm.h>
129 +/* Clock registers */
130 +#define BCM2708_CLK_PCMCTL_REG 0x00
131 +#define BCM2708_CLK_PCMDIV_REG 0x04
133 +/* Clock register settings */
134 +#define BCM2708_CLK_PASSWD (0x5a000000)
135 +#define BCM2708_CLK_PASSWD_MASK (0xff000000)
136 +#define BCM2708_CLK_MASH(v) ((v) << 9)
137 +#define BCM2708_CLK_FLIP BIT(8)
138 +#define BCM2708_CLK_BUSY BIT(7)
139 +#define BCM2708_CLK_KILL BIT(5)
140 +#define BCM2708_CLK_ENAB BIT(4)
141 +#define BCM2708_CLK_SRC(v) (v)
143 +#define BCM2708_CLK_SHIFT (12)
144 +#define BCM2708_CLK_DIVI(v) ((v) << BCM2708_CLK_SHIFT)
145 +#define BCM2708_CLK_DIVF(v) (v)
146 +#define BCM2708_CLK_DIVF_MASK (0xFFF)
149 + BCM2708_CLK_MASH_0 = 0,
150 + BCM2708_CLK_MASH_1,
151 + BCM2708_CLK_MASH_2,
152 + BCM2708_CLK_MASH_3,
156 + BCM2708_CLK_SRC_GND = 0,
157 + BCM2708_CLK_SRC_OSC,
158 + BCM2708_CLK_SRC_DBG0,
159 + BCM2708_CLK_SRC_DBG1,
160 + BCM2708_CLK_SRC_PLLA,
161 + BCM2708_CLK_SRC_PLLC,
162 + BCM2708_CLK_SRC_PLLD,
163 + BCM2708_CLK_SRC_HDMI,
166 +/* Most clocks are not useable (freq = 0) */
167 +static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = {
168 + [BCM2708_CLK_SRC_GND] = 0,
169 + [BCM2708_CLK_SRC_OSC] = 19200000,
170 + [BCM2708_CLK_SRC_DBG0] = 0,
171 + [BCM2708_CLK_SRC_DBG1] = 0,
172 + [BCM2708_CLK_SRC_PLLA] = 0,
173 + [BCM2708_CLK_SRC_PLLC] = 0,
174 + [BCM2708_CLK_SRC_PLLD] = 500000000,
175 + [BCM2708_CLK_SRC_HDMI] = 0,
179 +#define BCM2708_I2S_CS_A_REG 0x00
180 +#define BCM2708_I2S_FIFO_A_REG 0x04
181 +#define BCM2708_I2S_MODE_A_REG 0x08
182 +#define BCM2708_I2S_RXC_A_REG 0x0c
183 +#define BCM2708_I2S_TXC_A_REG 0x10
184 +#define BCM2708_I2S_DREQ_A_REG 0x14
185 +#define BCM2708_I2S_INTEN_A_REG 0x18
186 +#define BCM2708_I2S_INTSTC_A_REG 0x1c
187 +#define BCM2708_I2S_GRAY_REG 0x20
189 +/* I2S register settings */
190 +#define BCM2708_I2S_STBY BIT(25)
191 +#define BCM2708_I2S_SYNC BIT(24)
192 +#define BCM2708_I2S_RXSEX BIT(23)
193 +#define BCM2708_I2S_RXF BIT(22)
194 +#define BCM2708_I2S_TXE BIT(21)
195 +#define BCM2708_I2S_RXD BIT(20)
196 +#define BCM2708_I2S_TXD BIT(19)
197 +#define BCM2708_I2S_RXR BIT(18)
198 +#define BCM2708_I2S_TXW BIT(17)
199 +#define BCM2708_I2S_CS_RXERR BIT(16)
200 +#define BCM2708_I2S_CS_TXERR BIT(15)
201 +#define BCM2708_I2S_RXSYNC BIT(14)
202 +#define BCM2708_I2S_TXSYNC BIT(13)
203 +#define BCM2708_I2S_DMAEN BIT(9)
204 +#define BCM2708_I2S_RXTHR(v) ((v) << 7)
205 +#define BCM2708_I2S_TXTHR(v) ((v) << 5)
206 +#define BCM2708_I2S_RXCLR BIT(4)
207 +#define BCM2708_I2S_TXCLR BIT(3)
208 +#define BCM2708_I2S_TXON BIT(2)
209 +#define BCM2708_I2S_RXON BIT(1)
210 +#define BCM2708_I2S_EN (1)
212 +#define BCM2708_I2S_CLKDIS BIT(28)
213 +#define BCM2708_I2S_PDMN BIT(27)
214 +#define BCM2708_I2S_PDME BIT(26)
215 +#define BCM2708_I2S_FRXP BIT(25)
216 +#define BCM2708_I2S_FTXP BIT(24)
217 +#define BCM2708_I2S_CLKM BIT(23)
218 +#define BCM2708_I2S_CLKI BIT(22)
219 +#define BCM2708_I2S_FSM BIT(21)
220 +#define BCM2708_I2S_FSI BIT(20)
221 +#define BCM2708_I2S_FLEN(v) ((v) << 10)
222 +#define BCM2708_I2S_FSLEN(v) (v)
224 +#define BCM2708_I2S_CHWEX BIT(15)
225 +#define BCM2708_I2S_CHEN BIT(14)
226 +#define BCM2708_I2S_CHPOS(v) ((v) << 4)
227 +#define BCM2708_I2S_CHWID(v) (v)
228 +#define BCM2708_I2S_CH1(v) ((v) << 16)
229 +#define BCM2708_I2S_CH2(v) (v)
231 +#define BCM2708_I2S_TX_PANIC(v) ((v) << 24)
232 +#define BCM2708_I2S_RX_PANIC(v) ((v) << 16)
233 +#define BCM2708_I2S_TX(v) ((v) << 8)
234 +#define BCM2708_I2S_RX(v) (v)
236 +#define BCM2708_I2S_INT_RXERR BIT(3)
237 +#define BCM2708_I2S_INT_TXERR BIT(2)
238 +#define BCM2708_I2S_INT_RXR BIT(1)
239 +#define BCM2708_I2S_INT_TXW BIT(0)
241 +/* I2S DMA interface */
242 +#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004
243 +#define BCM2708_DMA_DREQ_PCM_TX 2
244 +#define BCM2708_DMA_DREQ_PCM_RX 3
246 +/* General device struct */
247 +struct bcm2708_i2s_dev {
248 + struct device *dev;
249 + struct snd_dmaengine_dai_dma_data dma_data[2];
251 + unsigned int bclk_ratio;
253 + struct regmap *i2s_regmap;
254 + struct regmap *clk_regmap;
257 +static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev)
259 + /* Start the clock if in master mode */
260 + unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
263 + case SND_SOC_DAIFMT_CBS_CFS:
264 + case SND_SOC_DAIFMT_CBS_CFM:
265 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
266 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
267 + BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
274 +static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev)
277 + int timeout = 1000;
280 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
281 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
282 + BCM2708_CLK_PASSWD);
284 + /* Wait for the BUSY flag going down */
285 + while (--timeout) {
286 + regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
287 + if (!(clkreg & BCM2708_CLK_BUSY))
292 + /* KILL the clock */
293 + dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n");
294 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
295 + BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK,
296 + BCM2708_CLK_KILL | BCM2708_CLK_PASSWD);
300 +static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev,
303 + int timeout = 1000;
306 + uint32_t i2s_active_state;
308 + uint32_t clk_active_state;
312 + off = tx ? BCM2708_I2S_TXON : 0;
313 + off |= rx ? BCM2708_I2S_RXON : 0;
315 + clr = tx ? BCM2708_I2S_TXCLR : 0;
316 + clr |= rx ? BCM2708_I2S_RXCLR : 0;
318 + /* Backup the current state */
319 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
320 + i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON);
322 + regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
323 + clk_active_state = clkreg & BCM2708_CLK_ENAB;
325 + /* Start clock if not running */
326 + if (!clk_active_state) {
327 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
328 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
329 + BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
332 + /* Stop I2S module */
333 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0);
337 + * Requires at least 2 PCM clock cycles to take effect
339 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr);
341 + /* Wait for 2 PCM clock cycles */
344 + * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
345 + * FIXME: This does not seem to work for slave mode!
347 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval);
348 + syncval &= BCM2708_I2S_SYNC;
350 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
351 + BCM2708_I2S_SYNC, ~syncval);
353 + /* Wait for the SYNC flag changing it's state */
354 + while (--timeout) {
355 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
356 + if ((csreg & BCM2708_I2S_SYNC) != syncval)
361 + dev_err(dev->dev, "I2S SYNC error!\n");
363 + /* Stop clock if it was not running before */
364 + if (!clk_active_state)
365 + bcm2708_i2s_stop_clock(dev);
367 + /* Restore I2S state */
368 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
369 + BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state);
372 +static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai,
375 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
380 +static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
381 + unsigned int ratio)
383 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
384 + dev->bclk_ratio = ratio;
388 +static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream,
389 + struct snd_pcm_hw_params *params,
390 + struct snd_soc_dai *dai)
392 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
394 + unsigned int sampling_rate = params_rate(params);
395 + unsigned int data_length, data_delay, bclk_ratio;
396 + unsigned int ch1pos, ch2pos, mode, format;
397 + unsigned int mash = BCM2708_CLK_MASH_1;
398 + unsigned int divi, divf, target_frequency;
400 + unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
401 + bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS
402 + || master == SND_SOC_DAIFMT_CBS_CFM);
404 + bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS
405 + || master == SND_SOC_DAIFMT_CBM_CFS);
409 + * If a stream is already enabled,
410 + * the registers are already set properly.
412 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
414 + if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON))
418 + * Adjust the data length according to the format.
419 + * We prefill the half frame length with an integer
420 + * divider of 2400 as explained at the clock settings.
421 + * Maybe it is overwritten there, if the Integer mode
424 + switch (params_format(params)) {
425 + case SNDRV_PCM_FORMAT_S16_LE:
429 + case SNDRV_PCM_FORMAT_S32_LE:
437 + /* If bclk_ratio already set, use that one. */
438 + if (dev->bclk_ratio)
439 + bclk_ratio = dev->bclk_ratio;
444 + * The target frequency of the bit clock is
445 + * sampling rate * frame length
448 + * Sampling rates that are multiples of 8000 kHz
449 + * can be driven by the oscillator of 19.2 MHz
450 + * with an integer divider as long as the frame length
451 + * is an integer divider of 19200000/8000=2400 as set up above.
452 + * This is no longer possible if the sampling rate
453 + * is too high (e.g. 192 kHz), because the oscillator is too slow.
456 + * For all other sampling rates, it is not possible to
457 + * have an integer divider. Approximate the clock
458 + * with the MASH module that induces a slight frequency
459 + * variance. To minimize that it is best to have the fastest
460 + * clock here. That is PLLD with 500 MHz.
462 + target_frequency = sampling_rate * bclk_ratio;
463 + clk_src = BCM2708_CLK_SRC_OSC;
464 + mash = BCM2708_CLK_MASH_0;
466 + if (bcm2708_clk_freq[clk_src] % target_frequency == 0
467 + && bit_master && frame_master) {
468 + divi = bcm2708_clk_freq[clk_src] / target_frequency;
473 + if (!dev->bclk_ratio) {
475 + * Overwrite bclk_ratio, because the
476 + * above trick is not needed or can
479 + bclk_ratio = 2 * data_length;
482 + target_frequency = sampling_rate * bclk_ratio;
484 + clk_src = BCM2708_CLK_SRC_PLLD;
485 + mash = BCM2708_CLK_MASH_1;
487 + dividend = bcm2708_clk_freq[clk_src];
488 + dividend <<= BCM2708_CLK_SHIFT;
489 + do_div(dividend, target_frequency);
490 + divi = dividend >> BCM2708_CLK_SHIFT;
491 + divf = dividend & BCM2708_CLK_DIVF_MASK;
494 + /* Set clock divider */
495 + regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD
496 + | BCM2708_CLK_DIVI(divi)
497 + | BCM2708_CLK_DIVF(divf));
499 + /* Setup clock, but don't start it yet */
500 + regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD
501 + | BCM2708_CLK_MASH(mash)
502 + | BCM2708_CLK_SRC(clk_src));
504 + /* Setup the frame format */
505 + format = BCM2708_I2S_CHEN;
507 + if (data_length > 24)
508 + format |= BCM2708_I2S_CHWEX;
510 + format |= BCM2708_I2S_CHWID((data_length-8)&0xf);
512 + switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
513 + case SND_SOC_DAIFMT_I2S:
519 + * Others are possible but are not implemented at the moment.
521 + dev_err(dev->dev, "%s:bad format\n", __func__);
525 + ch1pos = data_delay;
526 + ch2pos = bclk_ratio / 2 + data_delay;
528 + switch (params_channels(params)) {
530 + format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format);
531 + format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos));
532 + format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos));
539 + * Set format for both streams.
540 + * We cannot set another frame length
541 + * (and therefore word length) anyway,
542 + * so the format will be the same.
544 + regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format);
545 + regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format);
547 + /* Setup the I2S mode */
550 + if (data_length <= 16) {
552 + * Use frame packed mode (2 channels per 32 bit word)
553 + * We cannot set another frame length in the second stream
554 + * (and therefore word length) anyway,
555 + * so the format will be the same.
557 + mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP;
560 + mode |= BCM2708_I2S_FLEN(bclk_ratio - 1);
561 + mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2);
563 + /* Master or slave? */
564 + switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
565 + case SND_SOC_DAIFMT_CBS_CFS:
566 + /* CPU is master */
568 + case SND_SOC_DAIFMT_CBM_CFS:
570 + * CODEC is bit clock master
571 + * CPU is frame master
573 + mode |= BCM2708_I2S_CLKM;
575 + case SND_SOC_DAIFMT_CBS_CFM:
577 + * CODEC is frame master
578 + * CPU is bit clock master
580 + mode |= BCM2708_I2S_FSM;
582 + case SND_SOC_DAIFMT_CBM_CFM:
583 + /* CODEC is master */
584 + mode |= BCM2708_I2S_CLKM;
585 + mode |= BCM2708_I2S_FSM;
588 + dev_err(dev->dev, "%s:bad master\n", __func__);
595 + * The BCM approach seems to be inverted to the classical I2S approach.
597 + switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
598 + case SND_SOC_DAIFMT_NB_NF:
599 + /* None. Therefore, both for BCM */
600 + mode |= BCM2708_I2S_CLKI;
601 + mode |= BCM2708_I2S_FSI;
603 + case SND_SOC_DAIFMT_IB_IF:
604 + /* Both. Therefore, none for BCM */
606 + case SND_SOC_DAIFMT_NB_IF:
608 + * Invert only frame sync. Therefore,
609 + * invert only bit clock for BCM
611 + mode |= BCM2708_I2S_CLKI;
613 + case SND_SOC_DAIFMT_IB_NF:
615 + * Invert only bit clock. Therefore,
616 + * invert only frame sync for BCM
618 + mode |= BCM2708_I2S_FSI;
624 + regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode);
626 + /* Setup the DMA parameters */
627 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
628 + BCM2708_I2S_RXTHR(1)
629 + | BCM2708_I2S_TXTHR(1)
630 + | BCM2708_I2S_DMAEN, 0xffffffff);
632 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG,
633 + BCM2708_I2S_TX_PANIC(0x10)
634 + | BCM2708_I2S_RX_PANIC(0x30)
635 + | BCM2708_I2S_TX(0x30)
636 + | BCM2708_I2S_RX(0x20), 0xffffffff);
639 + bcm2708_i2s_clear_fifos(dev, true, true);
644 +static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream,
645 + struct snd_soc_dai *dai)
647 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
650 + bcm2708_i2s_start_clock(dev);
653 + * Clear both FIFOs if the one that should be started
654 + * is not empty at the moment. This should only happen
655 + * after overrun. Otherwise, hw_params would have cleared
658 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg);
660 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
661 + && !(cs_reg & BCM2708_I2S_TXE))
662 + bcm2708_i2s_clear_fifos(dev, true, false);
663 + else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
664 + && (cs_reg & BCM2708_I2S_RXD))
665 + bcm2708_i2s_clear_fifos(dev, false, true);
670 +static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev,
671 + struct snd_pcm_substream *substream,
672 + struct snd_soc_dai *dai)
676 + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
677 + mask = BCM2708_I2S_RXON;
679 + mask = BCM2708_I2S_TXON;
681 + regmap_update_bits(dev->i2s_regmap,
682 + BCM2708_I2S_CS_A_REG, mask, 0);
684 + /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
685 + if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
686 + bcm2708_i2s_stop_clock(dev);
689 +static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
690 + struct snd_soc_dai *dai)
692 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
696 + case SNDRV_PCM_TRIGGER_START:
697 + case SNDRV_PCM_TRIGGER_RESUME:
698 + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
699 + bcm2708_i2s_start_clock(dev);
701 + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
702 + mask = BCM2708_I2S_RXON;
704 + mask = BCM2708_I2S_TXON;
706 + regmap_update_bits(dev->i2s_regmap,
707 + BCM2708_I2S_CS_A_REG, mask, mask);
710 + case SNDRV_PCM_TRIGGER_STOP:
711 + case SNDRV_PCM_TRIGGER_SUSPEND:
712 + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
713 + bcm2708_i2s_stop(dev, substream, dai);
722 +static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
723 + struct snd_soc_dai *dai)
725 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
730 + /* Should this still be running stop it */
731 + bcm2708_i2s_stop_clock(dev);
733 + /* Enable PCM block */
734 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
735 + BCM2708_I2S_EN, BCM2708_I2S_EN);
739 + * Requires at least 4 PCM clock cycles to take effect.
741 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
742 + BCM2708_I2S_STBY, BCM2708_I2S_STBY);
747 +static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream,
748 + struct snd_soc_dai *dai)
750 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
752 + bcm2708_i2s_stop(dev, substream, dai);
754 + /* If both streams are stopped, disable module and clock */
758 + /* Disable the module */
759 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
760 + BCM2708_I2S_EN, 0);
763 + * Stopping clock is necessary, because stop does
764 + * not stop the clock when SND_SOC_DAIFMT_CONT
766 + bcm2708_i2s_stop_clock(dev);
769 +static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = {
770 + .startup = bcm2708_i2s_startup,
771 + .shutdown = bcm2708_i2s_shutdown,
772 + .prepare = bcm2708_i2s_prepare,
773 + .trigger = bcm2708_i2s_trigger,
774 + .hw_params = bcm2708_i2s_hw_params,
775 + .set_fmt = bcm2708_i2s_set_dai_fmt,
776 + .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio
779 +static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai)
781 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
783 + dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
784 + dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
789 +static struct snd_soc_dai_driver bcm2708_i2s_dai = {
790 + .name = "bcm2708-i2s",
791 + .probe = bcm2708_i2s_dai_probe,
795 + .rates = SNDRV_PCM_RATE_8000_192000,
796 + .formats = SNDRV_PCM_FMTBIT_S16_LE
797 + | SNDRV_PCM_FMTBIT_S32_LE
802 + .rates = SNDRV_PCM_RATE_8000_192000,
803 + .formats = SNDRV_PCM_FMTBIT_S16_LE
804 + | SNDRV_PCM_FMTBIT_S32_LE
806 + .ops = &bcm2708_i2s_dai_ops,
807 + .symmetric_rates = 1
810 +static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg)
813 + case BCM2708_I2S_CS_A_REG:
814 + case BCM2708_I2S_FIFO_A_REG:
815 + case BCM2708_I2S_INTSTC_A_REG:
816 + case BCM2708_I2S_GRAY_REG:
823 +static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg)
826 + case BCM2708_I2S_FIFO_A_REG:
833 +static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg)
836 + case BCM2708_CLK_PCMCTL_REG:
843 +static const struct regmap_config bcm2708_regmap_config[] = {
848 + .max_register = BCM2708_I2S_GRAY_REG,
849 + .precious_reg = bcm2708_i2s_precious_reg,
850 + .volatile_reg = bcm2708_i2s_volatile_reg,
851 + .cache_type = REGCACHE_RBTREE,
857 + .max_register = BCM2708_CLK_PCMDIV_REG,
858 + .volatile_reg = bcm2708_clk_volatile_reg,
859 + .cache_type = REGCACHE_RBTREE,
863 +static const struct snd_soc_component_driver bcm2708_i2s_component = {
864 + .name = "bcm2708-i2s-comp",
868 +static void bcm2708_i2s_setup_gpio(void)
871 + * This is the common way to handle the GPIO pins for
872 + * the Raspberry Pi.
873 + * TODO Better way would be to handle
874 + * this in the device tree!
876 +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
877 +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
879 + unsigned int *gpio;
881 + gpio = ioremap(GPIO_BASE, SZ_16K);
883 + /* SPI is on GPIO 7..11 */
884 + for (pin = 28; pin <= 31; pin++) {
885 + INP_GPIO(pin); /* set mode to GPIO input first */
886 + SET_GPIO_ALT(pin, 2); /* set mode to ALT 0 */
892 +static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
893 + .info = SNDRV_PCM_INFO_MMAP |
894 + SNDRV_PCM_INFO_MMAP_VALID |
895 + SNDRV_PCM_INFO_INTERLEAVED |
896 + SNDRV_PCM_INFO_JOINT_DUPLEX,
897 + .formats = SNDRV_PCM_FMTBIT_S16_LE |
898 + SNDRV_PCM_FMTBIT_S32_LE,
899 + .period_bytes_min = 32,
900 + .period_bytes_max = 64 * PAGE_SIZE,
902 + .periods_max = 255,
903 + .buffer_bytes_max = 128 * PAGE_SIZE,
906 +static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = {
907 + .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
908 + .pcm_hardware = &bcm2708_pcm_hardware,
909 + .prealloc_buffer_size = 256 * PAGE_SIZE,
913 +static int bcm2708_i2s_probe(struct platform_device *pdev)
915 + struct bcm2708_i2s_dev *dev;
918 + struct regmap *regmap[2];
919 + struct resource *mem[2];
921 + /* Request both ioareas */
922 + for (i = 0; i <= 1; i++) {
923 + void __iomem *base;
925 + mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
926 + base = devm_ioremap_resource(&pdev->dev, mem[i]);
928 + return PTR_ERR(base);
930 + regmap[i] = devm_regmap_init_mmio(&pdev->dev, base,
931 + &bcm2708_regmap_config[i]);
932 + if (IS_ERR(regmap[i])) {
933 + dev_err(&pdev->dev, "I2S probe: regmap init failed\n");
934 + return PTR_ERR(regmap[i]);
938 + dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
941 + return PTR_ERR(dev);
943 + bcm2708_i2s_setup_gpio();
945 + dev->i2s_regmap = regmap[0];
946 + dev->clk_regmap = regmap[1];
948 + /* Set the DMA address */
949 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
950 + (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
952 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
953 + (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
956 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id =
957 + BCM2708_DMA_DREQ_PCM_TX;
958 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id =
959 + BCM2708_DMA_DREQ_PCM_RX;
961 + /* Set the bus width */
962 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
963 + DMA_SLAVE_BUSWIDTH_4_BYTES;
964 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
965 + DMA_SLAVE_BUSWIDTH_4_BYTES;
968 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
969 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
971 + /* BCLK ratio - use default */
972 + dev->bclk_ratio = 0;
974 + /* Store the pdev */
975 + dev->dev = &pdev->dev;
976 + dev_set_drvdata(&pdev->dev, dev);
978 + ret = snd_soc_register_component(&pdev->dev,
979 + &bcm2708_i2s_component, &bcm2708_i2s_dai, 1);
982 + dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
987 + ret = snd_dmaengine_pcm_register(&pdev->dev,
988 + &bcm2708_dmaengine_pcm_config,
989 + SND_DMAENGINE_PCM_FLAG_COMPAT);
991 + dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
992 + snd_soc_unregister_component(&pdev->dev);
999 +static int bcm2708_i2s_remove(struct platform_device *pdev)
1001 + snd_dmaengine_pcm_unregister(&pdev->dev);
1002 + snd_soc_unregister_component(&pdev->dev);
1006 +static struct platform_driver bcm2708_i2s_driver = {
1007 + .probe = bcm2708_i2s_probe,
1008 + .remove = bcm2708_i2s_remove,
1010 + .name = "bcm2708-i2s",
1011 + .owner = THIS_MODULE,
1015 +module_platform_driver(bcm2708_i2s_driver);
1017 +MODULE_ALIAS("platform:bcm2708-i2s");
1018 +MODULE_DESCRIPTION("BCM2708 I2S interface");
1019 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
1020 +MODULE_LICENSE("GPL v2");