target/linux/bcm53xx/patches-4.4/031-ARM-dts-enable-clock-support-for-BCM5301X.patch

   1 From cdc36b22f0e4b8badf3db14395f0aa44dcbce4b3 Mon Sep 17 00:00:00 2001
   2 From: Jon Mason <jonmason@broadcom.com>
   3 Date: Fri, 20 Nov 2015 10:17:18 -0500
   4 Subject: [PATCH] ARM: dts: enable clock support for BCM5301X
   5
   6 Replace current device tree dummy clocks with real clock support for
   7 Broadcom Northstar SoCs.
   8
   9 Signed-off-by: Jon Mason <jonmason@broadcom.com>
  10 Reviewed-by: Ray Jui <rjui@broadcom.com>
  11 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  12 ---
  13  arch/arm/boot/dts/bcm5301x.dtsi | 92 +++++++++++++++++++++++++++++++----------
  14  1 file changed, 71 insertions(+), 21 deletions(-)
  15
  16 --- a/arch/arm/boot/dts/bcm5301x.dtsi
  17 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
  18 @@ -8,6 +8,7 @@
  19   * Licensed under the GNU/GPL. See COPYING for details.
  20   */
  21
  22 +#include <dt-bindings/clock/bcm-nsp.h>
  23  #include <dt-bindings/gpio/gpio.h>
  24  #include <dt-bindings/input/input.h>
  25  #include <dt-bindings/interrupt-controller/irq.h>
  26 @@ -27,7 +28,7 @@
  27                         compatible = "ns16550";
  28                         reg = <0x0300 0x100>;
  29                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  30 -                       clock-frequency = <100000000>;
  31 +                       clocks = <&iprocslow>;
  32                         status = "disabled";
  33                 };
  34
  35 @@ -35,48 +36,55 @@
  36                         compatible = "ns16550";
  37                         reg = <0x0400 0x100>;
  38                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  39 -                       clock-frequency = <100000000>;
  40 +                       clocks = <&iprocslow>;
  41                         status = "disabled";
  42                 };
  43         };
  44
  45         mpcore {
  46                 compatible = "simple-bus";
  47 -               ranges = <0x00000000 0x19020000 0x00003000>;
  48 +               ranges = <0x00000000 0x19000000 0x00023000>;
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51
  52 -               scu@0000 {
  53 +               a9pll: arm_clk@00000 {
  54 +                       #clock-cells = <0>;
  55 +                       compatible = "brcm,nsp-armpll";
  56 +                       clocks = <&osc>;
  57 +                       reg = <0x00000 0x1000>;
  58 +               };
  59 +
  60 +               scu@20000 {
  61                         compatible = "arm,cortex-a9-scu";
  62 -                       reg = <0x0000 0x100>;
  63 +                       reg = <0x20000 0x100>;
  64                 };
  65
  66 -               timer@0200 {
  67 +               timer@20200 {
  68                         compatible = "arm,cortex-a9-global-timer";
  69 -                       reg = <0x0200 0x100>;
  70 +                       reg = <0x20200 0x100>;
  71                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  72 -                       clocks = <&clk_periph>;
  73 +                       clocks = <&periph_clk>;
  74                 };
  75
  76 -               local-timer@0600 {
  77 +               local-timer@20600 {
  78                         compatible = "arm,cortex-a9-twd-timer";
  79 -                       reg = <0x0600 0x100>;
  80 +                       reg = <0x20600 0x100>;
  81                         interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
  82 -                       clocks = <&clk_periph>;
  83 +                       clocks = <&periph_clk>;
  84                 };
  85
  86 -               gic: interrupt-controller@1000 {
  87 +               gic: interrupt-controller@21000 {
  88                         compatible = "arm,cortex-a9-gic";
  89                         #interrupt-cells = <3>;
  90                         #address-cells = <0>;
  91                         interrupt-controller;
  92 -                       reg = <0x1000 0x1000>,
  93 -                             <0x0100 0x100>;
  94 +                       reg = <0x21000 0x1000>,
  95 +                             <0x20100 0x100>;
  96                 };
  97
  98 -               L2: cache-controller@2000 {
  99 +               L2: cache-controller@22000 {
 100                         compatible = "arm,pl310-cache";
 101 -                       reg = <0x2000 0x1000>;
 102 +                       reg = <0x22000 0x1000>;
 103                         cache-unified;
 104                         arm,shared-override;
 105                         prefetch-data = <1>;
 106 @@ -94,14 +102,37 @@
 107
 108         clocks {
 109                 #address-cells = <1>;
 110 -               #size-cells = <0>;
 111 +               #size-cells = <1>;
 112 +               ranges;
 113
 114 -               /* As long as we do not have a real clock driver us this
 115 -                * fixed clock */
 116 -               clk_periph: periph {
 117 +               osc: oscillator {
 118 +                       #clock-cells = <0>;
 119                         compatible = "fixed-clock";
 120 +                       clock-frequency = <25000000>;
 121 +               };
 122 +
 123 +               iprocmed: iprocmed {
 124 +                       #clock-cells = <0>;
 125 +                       compatible = "fixed-factor-clock";
 126 +                       clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 127 +                       clock-div = <2>;
 128 +                       clock-mult = <1>;
 129 +               };
 130 +
 131 +               iprocslow: iprocslow {
 132 +                       #clock-cells = <0>;
 133 +                       compatible = "fixed-factor-clock";
 134 +                       clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 135 +                       clock-div = <4>;
 136 +                       clock-mult = <1>;
 137 +               };
 138 +
 139 +               periph_clk: periph_clk {
 140                         #clock-cells = <0>;
 141 -                       clock-frequency = <400000000>;
 142 +                       compatible = "fixed-factor-clock";
 143 +                       clocks = <&a9pll>;
 144 +                       clock-div = <2>;
 145 +                       clock-mult = <1>;
 146                 };
 147         };
 148
 149 @@ -178,6 +209,25 @@
 150                 };
 151         };
 152
 153 +       lcpll0: lcpll0@1800c100 {
 154 +               #clock-cells = <1>;
 155 +               compatible = "brcm,nsp-lcpll0";
 156 +               reg = <0x1800c100 0x14>;
 157 +               clocks = <&osc>;
 158 +               clock-output-names = "lcpll0", "pcie_phy", "sdio",
 159 +                                    "ddr_phy";
 160 +       };
 161 +
 162 +       genpll: genpll@1800c140 {
 163 +               #clock-cells = <1>;
 164 +               compatible = "brcm,nsp-genpll";
 165 +               reg = <0x1800c140 0x24>;
 166 +               clocks = <&osc>;
 167 +               clock-output-names = "genpll", "phy", "ethernetclk",
 168 +                                    "usbclk", "iprocfast", "sata1",
 169 +                                    "sata2";
 170 +       };
 171 +
 172         nand: nand@18028000 {
 173                 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
 174                 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;