[ar71xx] ag71xx driver: add a workaround for the ar8216 chip, until we get a suitable...
[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_phy.c
1 /*
2  *  Atheros AR71xx built-in ethernet mac driver
3  *
4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6  *
7  *  Based on Atheros' AG7100 driver
8  *
9  *  This program is free software; you can redistribute it and/or modify it
10  *  under the terms of the GNU General Public License version 2 as published
11  *  by the Free Software Foundation.
12  */
13
14 #include "ag71xx.h"
15
16 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
17 {
18         switch (ag->speed) {
19         case SPEED_1000:
20                 return "1000";
21         case SPEED_100:
22                 return "100";
23         case SPEED_10:
24                 return "10";
25         }
26
27         return "?";
28 }
29
30 #define AR71XX_PLL_VAL_1000     0x00110000
31 #define AR71XX_PLL_VAL_100      0x00001099
32 #define AR71XX_PLL_VAL_10       0x00991099
33
34 #define AR91XX_PLL_VAL_1000     0x1a000000
35 #define AR91XX_PLL_VAL_100      0x13000a44
36 #define AR91XX_PLL_VAL_10       0x00441099
37
38 static void ag71xx_phy_link_update(struct ag71xx *ag)
39 {
40         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
41         u32 cfg2;
42         u32 ifctl;
43         u32 pll;
44         u32 fifo5;
45         u32 mii_speed;
46
47         if (!ag->link) {
48                 netif_carrier_off(ag->dev);
49                 if (netif_msg_link(ag))
50                         printk(KERN_INFO "%s: link down\n", ag->dev->name);
51                 return;
52         }
53
54         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
55         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
56         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
57
58         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
59         ifctl &= ~(MAC_IFCTL_SPEED);
60
61         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
62         fifo5 &= ~FIFO_CFG5_BM;
63
64         switch (ag->speed) {
65         case SPEED_1000:
66                 mii_speed =  MII_CTRL_SPEED_1000;
67                 cfg2 |= MAC_CFG2_IF_1000;
68                 pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_1000
69                                        : AR71XX_PLL_VAL_1000;
70                 fifo5 |= FIFO_CFG5_BM;
71                 break;
72         case SPEED_100:
73                 mii_speed = MII_CTRL_SPEED_100;
74                 cfg2 |= MAC_CFG2_IF_10_100;
75                 ifctl |= MAC_IFCTL_SPEED;
76                 pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_100
77                                        : AR71XX_PLL_VAL_100;
78                 break;
79         case SPEED_10:
80                 mii_speed = MII_CTRL_SPEED_10;
81                 cfg2 |= MAC_CFG2_IF_10_100;
82                 pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_10
83                                        : AR71XX_PLL_VAL_10;
84                 break;
85         default:
86                 BUG();
87                 return;
88         }
89
90         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
91                         pdata->is_ar91xx ? 0x780fff : 0x008001ff);
92         pdata->set_pll(pll);
93         ag71xx_mii_ctrl_set_speed(ag, mii_speed);
94
95         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
96         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
97         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
98
99         netif_carrier_on(ag->dev);
100         if (netif_msg_link(ag))
101                 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
102                         ag->dev->name,
103                         ag71xx_speed_str(ag),
104                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
105
106         DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
107                 ag->dev->name,
108                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
109                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
110                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
111
112         DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
113                 ag->dev->name,
114                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
115                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
116                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
117
118         DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
119                 ag->dev->name,
120                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
121                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
122                 ag71xx_mii_ctrl_rr(ag));
123 }
124
125 static void ag71xx_phy_link_adjust(struct net_device *dev)
126 {
127         struct ag71xx *ag = netdev_priv(dev);
128         struct phy_device *phydev = ag->phy_dev;
129         unsigned long flags;
130         int status_change = 0;
131
132         spin_lock_irqsave(&ag->lock, flags);
133
134         if (phydev->link) {
135                 if (ag->duplex != phydev->duplex
136                     || ag->speed != phydev->speed) {
137                         status_change = 1;
138                 }
139         }
140
141         if (phydev->link != ag->link)
142                 status_change = 1;
143
144         ag->link = phydev->link;
145         ag->duplex = phydev->duplex;
146         ag->speed = phydev->speed;
147
148         if (status_change)
149                 ag71xx_phy_link_update(ag);
150
151         spin_unlock_irqrestore(&ag->lock, flags);
152 }
153
154 void ag71xx_phy_start(struct ag71xx *ag)
155 {
156         if (ag->phy_dev) {
157                 phy_start(ag->phy_dev);
158         } else {
159                 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
160
161                 ag->duplex = pdata->duplex;
162                 ag->speed = pdata->speed;
163                 ag->link = 1;
164                 ag71xx_phy_link_update(ag);
165         }
166 }
167
168 void ag71xx_phy_stop(struct ag71xx *ag)
169 {
170         if (ag->phy_dev) {
171                 phy_stop(ag->phy_dev);
172         } else {
173                 ag->duplex = -1;
174                 ag->link = 0;
175                 ag->speed = 0;
176                 ag71xx_phy_link_update(ag);
177         }
178 }
179
180 static int ag71xx_phy_connect_fixed(struct ag71xx *ag)
181 {
182         struct net_device *dev = ag->dev;
183         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
184         int ret = 0;
185
186         /* use fixed settings */
187         switch (pdata->speed) {
188         case SPEED_10:
189         case SPEED_100:
190         case SPEED_1000:
191                 break;
192         default:
193                 printk(KERN_ERR "%s: invalid speed specified\n",
194                         dev->name);
195                 ret = -EINVAL;
196                 break;
197         }
198
199         return ret;
200 }
201
202 static int ag71xx_phy_connect_multi(struct ag71xx *ag)
203 {
204         struct net_device *dev = ag->dev;
205         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
206         struct phy_device *phydev = NULL;
207         int phy_count = 0;
208         int phy_addr;
209         int ret = 0;
210
211         for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
212                 if (!(pdata->phy_mask & (1 << phy_addr)))
213                         continue;
214
215                 if (ag->mii_bus->phy_map[phy_addr] == NULL)
216                         continue;
217
218                 DBG("%s: PHY found at %s, uid=%08x\n",
219                         dev->name,
220                         ag->mii_bus->phy_map[phy_addr]->dev.bus_id,
221                         ag->mii_bus->phy_map[phy_addr]->phy_id);
222
223                 if (phydev == NULL)
224                         phydev = ag->mii_bus->phy_map[phy_addr];
225
226                 phy_count++;
227         }
228
229         switch (phy_count) {
230         case 0:
231                 printk(KERN_ERR "%s: no PHY found with phy_mask=%08x\n",
232                         dev->name, pdata->phy_mask);
233                 ret = -ENODEV;
234                 break;
235         case 1:
236                 ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
237                         &ag71xx_phy_link_adjust, 0, pdata->phy_if_mode);
238
239                 if (IS_ERR(ag->phy_dev)) {
240                         printk(KERN_ERR "%s: could not connect to PHY at %s\n",
241                                 dev->name, phydev->dev.bus_id);
242                         return PTR_ERR(ag->phy_dev);
243                 }
244
245                 /* mask with MAC supported features */
246                 if (pdata->has_gbit)
247                         phydev->supported &= PHY_GBIT_FEATURES;
248                 else
249                         phydev->supported &= PHY_BASIC_FEATURES;
250
251                 phydev->advertising = phydev->supported;
252
253                 printk(KERN_DEBUG "%s: connected to PHY at %s "
254                         "[uid=%08x, driver=%s]\n",
255                         dev->name, phydev->dev.bus_id,
256                         phydev->phy_id, phydev->drv->name);
257
258                 ag->link = 0;
259                 ag->speed = 0;
260                 ag->duplex = -1;
261                 break;
262
263         default:
264                 printk(KERN_DEBUG "%s: connected to %d PHYs\n",
265                         dev->name, phy_count);
266                 ret = ag71xx_phy_connect_fixed(ag);
267                 break;
268         }
269
270         return ret;
271 }
272
273 int ag71xx_phy_connect(struct ag71xx *ag)
274 {
275         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
276
277         if (pdata->phy_mask)
278                 return ag71xx_phy_connect_multi(ag);
279
280         return ag71xx_phy_connect_fixed(ag);
281 }
282
283 void ag71xx_phy_disconnect(struct ag71xx *ag)
284 {
285         if (ag->phy_dev)
286                 phy_disconnect(ag->phy_dev);
287 }