target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 #define AG71XX_DEFAULT_MSG_ENABLE       \
  17         ( NETIF_MSG_DRV                 \
  18         | NETIF_MSG_PROBE               \
  19         | NETIF_MSG_LINK                \
  20         | NETIF_MSG_TIMER               \
  21         | NETIF_MSG_IFDOWN              \
  22         | NETIF_MSG_IFUP                \
  23         | NETIF_MSG_RX_ERR              \
  24         | NETIF_MSG_TX_ERR )
  25
  26 static int ag71xx_msg_level = -1;
  27
  28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
  29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  30
  31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  32 {
  33         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  34                 ag->dev->name,
  35                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  36                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  37                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  38
  39         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  40                 ag->dev->name,
  41                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  42                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  43                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  44 }
  45
  46 static void ag71xx_dump_regs(struct ag71xx *ag)
  47 {
  48         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  49                 ag->dev->name,
  50                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  52                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  53                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  54                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  55         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  56                 ag->dev->name,
  57                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  58                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  60         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  61                 ag->dev->name,
  62                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  65         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  66                 ag->dev->name,
  67                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  70 }
  71
  72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  73 {
  74         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  75                 ag->dev->name, label, intr,
  76                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  77                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  78                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  79                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  80                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  81                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  82 }
  83
  84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
  85 {
  86         kfree(ring->buf);
  87
  88         if (ring->descs_cpu)
  89                 dma_free_coherent(NULL, ring->size * ring->desc_size,
  90                                   ring->descs_cpu, ring->descs_dma);
  91 }
  92
  93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
  94 {
  95         int err;
  96         int i;
  97
  98         ring->desc_size = sizeof(struct ag71xx_desc);
  99         if (ring->desc_size % cache_line_size()) {
 100                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
 101                         ring, ring->desc_size,
 102                         roundup(ring->desc_size, cache_line_size()));
 103                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
 104         }
 105
 106         ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
 107                                              &ring->descs_dma, GFP_ATOMIC);
 108         if (!ring->descs_cpu) {
 109                 err = -ENOMEM;
 110                 goto err;
 111         }
 112
 113         ring->size = size;
 114
 115         ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
 116         if (!ring->buf) {
 117                 err = -ENOMEM;
 118                 goto err;
 119         }
 120
 121         for (i = 0; i < size; i++) {
 122                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
 123                 DBG("ag71xx: ring %p, desc %d at %p\n",
 124                         ring, i, ring->buf[i].desc);
 125         }
 126
 127         return 0;
 128
 129  err:
 130         return err;
 131 }
 132
 133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
 134 {
 135         struct ag71xx_ring *ring = &ag->tx_ring;
 136         struct net_device *dev = ag->dev;
 137
 138         while (ring->curr != ring->dirty) {
 139                 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
 140
 141                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
 142                         ring->buf[i].desc->ctrl = 0;
 143                         dev->stats.tx_errors++;
 144                 }
 145
 146                 if (ring->buf[i].skb)
 147                         dev_kfree_skb_any(ring->buf[i].skb);
 148
 149                 ring->buf[i].skb = NULL;
 150
 151                 ring->dirty++;
 152         }
 153
 154         /* flush descriptors */
 155         wmb();
 156
 157 }
 158
 159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
 160 {
 161         struct ag71xx_ring *ring = &ag->tx_ring;
 162         int i;
 163
 164         for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
 165                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 166                         ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
 167
 168                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 169                 ring->buf[i].skb = NULL;
 170         }
 171
 172         /* flush descriptors */
 173         wmb();
 174
 175         ring->curr = 0;
 176         ring->dirty = 0;
 177 }
 178
 179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
 180 {
 181         struct ag71xx_ring *ring = &ag->rx_ring;
 182         int i;
 183
 184         if (!ring->buf)
 185                 return;
 186
 187         for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
 188                 if (ring->buf[i].skb)
 189                         kfree_skb(ring->buf[i].skb);
 190
 191 }
 192
 193 static int ag71xx_ring_rx_init(struct ag71xx *ag)
 194 {
 195         struct ag71xx_ring *ring = &ag->rx_ring;
 196         unsigned int i;
 197         int ret;
 198
 199         ret = 0;
 200         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 201                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 202                         ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
 203
 204                 DBG("ag71xx: RX desc at %p, next is %08x\n",
 205                         ring->buf[i].desc,
 206                         ring->buf[i].desc->next);
 207         }
 208
 209         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 210                 struct sk_buff *skb;
 211                 dma_addr_t dma_addr;
 212
 213                 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + AG71XX_RX_PKT_RESERVE);
 214                 if (!skb) {
 215                         ret = -ENOMEM;
 216                         break;
 217                 }
 218
 219                 skb->dev = ag->dev;
 220                 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
 221
 222                 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 223                                           AG71XX_RX_PKT_SIZE,
 224                                           DMA_FROM_DEVICE);
 225                 ring->buf[i].skb = skb;
 226                 ring->buf[i].desc->data = (u32) dma_addr;
 227                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 228         }
 229
 230         /* flush descriptors */
 231         wmb();
 232
 233         ring->curr = 0;
 234         ring->dirty = 0;
 235
 236         return ret;
 237 }
 238
 239 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
 240 {
 241         struct ag71xx_ring *ring = &ag->rx_ring;
 242         unsigned int count;
 243
 244         count = 0;
 245         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
 246                 unsigned int i;
 247
 248                 i = ring->dirty % AG71XX_RX_RING_SIZE;
 249
 250                 if (ring->buf[i].skb == NULL) {
 251                         dma_addr_t dma_addr;
 252                         struct sk_buff *skb;
 253
 254                         skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE +
 255                                             AG71XX_RX_PKT_RESERVE);
 256                         if (skb == NULL)
 257                                 break;
 258
 259                         skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
 260                         skb->dev = ag->dev;
 261
 262                         dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 263                                                   AG71XX_RX_PKT_SIZE,
 264                                                   DMA_FROM_DEVICE);
 265
 266                         ring->buf[i].skb = skb;
 267                         ring->buf[i].desc->data = (u32) dma_addr;
 268                 }
 269
 270                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 271                 count++;
 272         }
 273
 274         /* flush descriptors */
 275         wmb();
 276
 277         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
 278
 279         return count;
 280 }
 281
 282 static int ag71xx_rings_init(struct ag71xx *ag)
 283 {
 284         int ret;
 285
 286         ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
 287         if (ret)
 288                 return ret;
 289
 290         ag71xx_ring_tx_init(ag);
 291
 292         ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
 293         if (ret)
 294                 return ret;
 295
 296         ret = ag71xx_ring_rx_init(ag);
 297         return ret;
 298 }
 299
 300 static void ag71xx_rings_cleanup(struct ag71xx *ag)
 301 {
 302         ag71xx_ring_rx_clean(ag);
 303         ag71xx_ring_free(&ag->rx_ring);
 304
 305         ag71xx_ring_tx_clean(ag);
 306         ag71xx_ring_free(&ag->tx_ring);
 307 }
 308
 309 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 310 {
 311         u32 t;
 312
 313         t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
 314           | (((u32) mac[2]) << 8) | ((u32) mac[3]);
 315
 316         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
 317
 318         t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
 319         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 320 }
 321
 322 static void ag71xx_dma_reset(struct ag71xx *ag)
 323 {
 324         u32 val;
 325         int i;
 326
 327         ag71xx_dump_dma_regs(ag);
 328
 329         /* stop RX and TX */
 330         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 331         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 332
 333         /* clear descriptor addresses */
 334         ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
 335         ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
 336
 337         /* clear pending RX/TX interrupts */
 338         for (i = 0; i < 256; i++) {
 339                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 340                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 341         }
 342
 343         /* clear pending errors */
 344         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
 345         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
 346
 347         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 348         if (val)
 349                 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
 350                         ag->dev->name, val);
 351
 352         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 353
 354         /* mask out reserved bits */
 355         val &= ~0xff000000;
 356
 357         if (val)
 358                 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
 359                         ag->dev->name, val);
 360
 361         ag71xx_dump_dma_regs(ag);
 362 }
 363
 364 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
 365                          MAC_CFG1_SRX | MAC_CFG1_STX)
 366
 367 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
 368
 369 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
 370                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
 371                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
 372                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
 373                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
 374                          FIFO_CFG4_VT)
 375
 376 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
 377                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
 378                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
 379                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
 380                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
 381                          FIFO_CFG5_17 | FIFO_CFG5_SF)
 382
 383 static void ag71xx_hw_init(struct ag71xx *ag)
 384 {
 385         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 386
 387         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
 388         udelay(20);
 389
 390         ar71xx_device_stop(pdata->reset_bit);
 391         mdelay(100);
 392         ar71xx_device_start(pdata->reset_bit);
 393         mdelay(100);
 394
 395         /* setup MAC configuration registers */
 396         if (pdata->is_ar724x)
 397                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
 398                           MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC);
 399         else
 400                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
 401
 402         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 403                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 404
 405         /* setup max frame length */
 406         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
 407
 408         /* setup MII interface type */
 409         ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
 410
 411         /* setup FIFO configuration registers */
 412         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 413         if (pdata->is_ar724x) {
 414                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
 415                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
 416         } else {
 417                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
 418                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
 419         }
 420         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
 421         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 422
 423         ag71xx_dma_reset(ag);
 424 }
 425
 426 static void ag71xx_hw_start(struct ag71xx *ag)
 427 {
 428         /* start RX engine */
 429         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 430
 431         /* enable interrupts */
 432         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
 433 }
 434
 435 static void ag71xx_hw_stop(struct ag71xx *ag)
 436 {
 437         /* disable all interrupts */
 438         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
 439
 440         ag71xx_dma_reset(ag);
 441 }
 442
 443 static int ag71xx_open(struct net_device *dev)
 444 {
 445         struct ag71xx *ag = netdev_priv(dev);
 446         int ret;
 447
 448         ret = ag71xx_rings_init(ag);
 449         if (ret)
 450                 goto err;
 451
 452         napi_enable(&ag->napi);
 453
 454         netif_carrier_off(dev);
 455         ag71xx_phy_start(ag);
 456
 457         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 458         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
 459
 460         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 461
 462         ag71xx_hw_start(ag);
 463
 464         netif_start_queue(dev);
 465
 466         return 0;
 467
 468  err:
 469         ag71xx_rings_cleanup(ag);
 470         return ret;
 471 }
 472
 473 static int ag71xx_stop(struct net_device *dev)
 474 {
 475         struct ag71xx *ag = netdev_priv(dev);
 476         unsigned long flags;
 477
 478         spin_lock_irqsave(&ag->lock, flags);
 479
 480         netif_stop_queue(dev);
 481
 482         ag71xx_hw_stop(ag);
 483
 484         netif_carrier_off(dev);
 485         ag71xx_phy_stop(ag);
 486
 487         napi_disable(&ag->napi);
 488         del_timer_sync(&ag->oom_timer);
 489
 490         spin_unlock_irqrestore(&ag->lock, flags);
 491
 492         ag71xx_rings_cleanup(ag);
 493
 494         return 0;
 495 }
 496
 497 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
 498                                           struct net_device *dev)
 499 {
 500         struct ag71xx *ag = netdev_priv(dev);
 501         struct ag71xx_ring *ring = &ag->tx_ring;
 502         struct ag71xx_desc *desc;
 503         dma_addr_t dma_addr;
 504         int i;
 505
 506         i = ring->curr % AG71XX_TX_RING_SIZE;
 507         desc = ring->buf[i].desc;
 508
 509         if (!ag71xx_desc_empty(desc))
 510                 goto err_drop;
 511
 512         ag71xx_add_ar8216_header(ag, skb);
 513
 514         if (skb->len <= 0) {
 515                 DBG("%s: packet len is too small\n", ag->dev->name);
 516                 goto err_drop;
 517         }
 518
 519         dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
 520                                   DMA_TO_DEVICE);
 521
 522         ring->buf[i].skb = skb;
 523
 524         /* setup descriptor fields */
 525         desc->data = (u32) dma_addr;
 526         desc->ctrl = (skb->len & DESC_PKTLEN_M);
 527
 528         /* flush descriptor */
 529         wmb();
 530
 531         ring->curr++;
 532         if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
 533                 DBG("%s: tx queue full\n", ag->dev->name);
 534                 netif_stop_queue(dev);
 535         }
 536
 537         DBG("%s: packet injected into TX queue\n", ag->dev->name);
 538
 539         /* enable TX engine */
 540         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
 541
 542         dev->trans_start = jiffies;
 543
 544         return NETDEV_TX_OK;
 545
 546  err_drop:
 547         dev->stats.tx_dropped++;
 548
 549         dev_kfree_skb(skb);
 550         return NETDEV_TX_OK;
 551 }
 552
 553 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 554 {
 555         struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
 556         struct ag71xx *ag = netdev_priv(dev);
 557         int ret;
 558
 559         switch (cmd) {
 560         case SIOCETHTOOL:
 561                 if (ag->phy_dev == NULL)
 562                         break;
 563
 564                 spin_lock_irq(&ag->lock);
 565                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
 566                 spin_unlock_irq(&ag->lock);
 567                 return ret;
 568
 569         case SIOCSIFHWADDR:
 570                 if (copy_from_user
 571                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
 572                         return -EFAULT;
 573                 return 0;
 574
 575         case SIOCGIFHWADDR:
 576                 if (copy_to_user
 577                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
 578                         return -EFAULT;
 579                 return 0;
 580
 581         case SIOCGMIIPHY:
 582         case SIOCGMIIREG:
 583         case SIOCSMIIREG:
 584                 if (ag->phy_dev == NULL)
 585                         break;
 586
 587                 return phy_mii_ioctl(ag->phy_dev, data, cmd);
 588
 589         default:
 590                 break;
 591         }
 592
 593         return -EOPNOTSUPP;
 594 }
 595
 596 static void ag71xx_oom_timer_handler(unsigned long data)
 597 {
 598         struct net_device *dev = (struct net_device *) data;
 599         struct ag71xx *ag = netdev_priv(dev);
 600
 601         napi_schedule(&ag->napi);
 602 }
 603
 604 static void ag71xx_tx_timeout(struct net_device *dev)
 605 {
 606         struct ag71xx *ag = netdev_priv(dev);
 607
 608         if (netif_msg_tx_err(ag))
 609                 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
 610
 611         schedule_work(&ag->restart_work);
 612 }
 613
 614 static void ag71xx_restart_work_func(struct work_struct *work)
 615 {
 616         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
 617
 618         ag71xx_stop(ag->dev);
 619         ag71xx_open(ag->dev);
 620 }
 621
 622 static int ag71xx_tx_packets(struct ag71xx *ag)
 623 {
 624         struct ag71xx_ring *ring = &ag->tx_ring;
 625         int sent;
 626
 627         DBG("%s: processing TX ring\n", ag->dev->name);
 628
 629         sent = 0;
 630         while (ring->dirty != ring->curr) {
 631                 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
 632                 struct ag71xx_desc *desc = ring->buf[i].desc;
 633                 struct sk_buff *skb = ring->buf[i].skb;
 634
 635                 if (!ag71xx_desc_empty(desc))
 636                         break;
 637
 638                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 639
 640                 ag->dev->stats.tx_bytes += skb->len;
 641                 ag->dev->stats.tx_packets++;
 642
 643                 dev_kfree_skb_any(skb);
 644                 ring->buf[i].skb = NULL;
 645
 646                 ring->dirty++;
 647                 sent++;
 648         }
 649
 650         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
 651
 652         if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
 653                 netif_wake_queue(ag->dev);
 654
 655         return sent;
 656 }
 657
 658 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 659 {
 660         struct net_device *dev = ag->dev;
 661         struct ag71xx_ring *ring = &ag->rx_ring;
 662         int done = 0;
 663
 664         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
 665                         dev->name, limit, ring->curr, ring->dirty);
 666
 667         while (done < limit) {
 668                 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
 669                 struct ag71xx_desc *desc = ring->buf[i].desc;
 670                 struct sk_buff *skb;
 671                 int pktlen;
 672
 673                 if (ag71xx_desc_empty(desc))
 674                         break;
 675
 676                 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
 677                         ag71xx_assert(0);
 678                         break;
 679                 }
 680
 681                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 682
 683                 skb = ring->buf[i].skb;
 684                 pktlen = ag71xx_desc_pktlen(desc);
 685                 pktlen -= ETH_FCS_LEN;
 686
 687                 skb_put(skb, pktlen);
 688
 689                 skb->dev = dev;
 690                 skb->ip_summed = CHECKSUM_NONE;
 691
 692                 dev->last_rx = jiffies;
 693                 dev->stats.rx_packets++;
 694                 dev->stats.rx_bytes += pktlen;
 695
 696                 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
 697                         dev->stats.rx_dropped++;
 698                         kfree_skb(skb);
 699                 } else {
 700                         skb->protocol = eth_type_trans(skb, dev);
 701                         netif_receive_skb(skb);
 702                 }
 703
 704                 ring->buf[i].skb = NULL;
 705                 done++;
 706
 707                 ring->curr++;
 708         }
 709
 710         ag71xx_ring_rx_refill(ag);
 711
 712         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
 713                 dev->name, ring->curr, ring->dirty, done);
 714
 715         return done;
 716 }
 717
 718 static int ag71xx_poll(struct napi_struct *napi, int limit)
 719 {
 720         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
 721         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 722         struct net_device *dev = ag->dev;
 723         struct ag71xx_ring *rx_ring;
 724         unsigned long flags;
 725         u32 status;
 726         int tx_done;
 727         int rx_done;
 728
 729         pdata->ddr_flush();
 730         tx_done = ag71xx_tx_packets(ag);
 731
 732         DBG("%s: processing RX ring\n", dev->name);
 733         rx_done = ag71xx_rx_packets(ag, limit);
 734
 735         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
 736
 737         rx_ring = &ag->rx_ring;
 738         if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
 739                 goto oom;
 740
 741         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 742         if (unlikely(status & RX_STATUS_OF)) {
 743                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
 744                 dev->stats.rx_fifo_errors++;
 745
 746                 /* restart RX */
 747                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 748         }
 749
 750         if (rx_done < limit) {
 751                 if (status & RX_STATUS_PR)
 752                         goto more;
 753
 754                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 755                 if (status & TX_STATUS_PS)
 756                         goto more;
 757
 758                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
 759                         dev->name, rx_done, tx_done, limit);
 760
 761                 napi_complete(napi);
 762
 763                 /* enable interrupts */
 764                 spin_lock_irqsave(&ag->lock, flags);
 765                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
 766                 spin_unlock_irqrestore(&ag->lock, flags);
 767                 return rx_done;
 768         }
 769
 770  more:
 771         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
 772                         dev->name, rx_done, tx_done, limit);
 773         return rx_done;
 774
 775  oom:
 776         if (netif_msg_rx_err(ag))
 777                 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
 778
 779         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
 780         napi_complete(napi);
 781         return 0;
 782 }
 783
 784 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
 785 {
 786         struct net_device *dev = dev_id;
 787         struct ag71xx *ag = netdev_priv(dev);
 788         u32 status;
 789
 790         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
 791         ag71xx_dump_intr(ag, "raw", status);
 792
 793         if (unlikely(!status))
 794                 return IRQ_NONE;
 795
 796         if (unlikely(status & AG71XX_INT_ERR)) {
 797                 if (status & AG71XX_INT_TX_BE) {
 798                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
 799                         dev_err(&dev->dev, "TX BUS error\n");
 800                 }
 801                 if (status & AG71XX_INT_RX_BE) {
 802                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
 803                         dev_err(&dev->dev, "RX BUS error\n");
 804                 }
 805         }
 806
 807         if (likely(status & AG71XX_INT_POLL)) {
 808                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
 809                 DBG("%s: enable polling mode\n", dev->name);
 810                 napi_schedule(&ag->napi);
 811         }
 812
 813         ag71xx_debugfs_update_int_stats(ag, status);
 814
 815         return IRQ_HANDLED;
 816 }
 817
 818 static void ag71xx_set_multicast_list(struct net_device *dev)
 819 {
 820         /* TODO */
 821 }
 822
 823 static const struct net_device_ops ag71xx_netdev_ops = {
 824         .ndo_open               = ag71xx_open,
 825         .ndo_stop               = ag71xx_stop,
 826         .ndo_start_xmit         = ag71xx_hard_start_xmit,
 827         .ndo_set_multicast_list = ag71xx_set_multicast_list,
 828         .ndo_do_ioctl           = ag71xx_do_ioctl,
 829         .ndo_tx_timeout         = ag71xx_tx_timeout,
 830         .ndo_change_mtu         = eth_change_mtu,
 831         .ndo_set_mac_address    = eth_mac_addr,
 832         .ndo_validate_addr      = eth_validate_addr,
 833 };
 834
 835 static int __init ag71xx_probe(struct platform_device *pdev)
 836 {
 837         struct net_device *dev;
 838         struct resource *res;
 839         struct ag71xx *ag;
 840         struct ag71xx_platform_data *pdata;
 841         int err;
 842
 843         pdata = pdev->dev.platform_data;
 844         if (!pdata) {
 845                 dev_err(&pdev->dev, "no platform data specified\n");
 846                 err = -ENXIO;
 847                 goto err_out;
 848         }
 849
 850         if (pdata->mii_bus_dev == NULL) {
 851                 dev_err(&pdev->dev, "no MII bus device specified\n");
 852                 err = -EINVAL;
 853                 goto err_out;
 854         }
 855
 856         dev = alloc_etherdev(sizeof(*ag));
 857         if (!dev) {
 858                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
 859                 err = -ENOMEM;
 860                 goto err_out;
 861         }
 862
 863         SET_NETDEV_DEV(dev, &pdev->dev);
 864
 865         ag = netdev_priv(dev);
 866         ag->pdev = pdev;
 867         ag->dev = dev;
 868         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
 869                                         AG71XX_DEFAULT_MSG_ENABLE);
 870         spin_lock_init(&ag->lock);
 871
 872         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
 873         if (!res) {
 874                 dev_err(&pdev->dev, "no mac_base resource found\n");
 875                 err = -ENXIO;
 876                 goto err_out;
 877         }
 878
 879         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
 880         if (!ag->mac_base) {
 881                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
 882                 err = -ENOMEM;
 883                 goto err_free_dev;
 884         }
 885
 886         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
 887         if (!res) {
 888                 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
 889                 err = -ENXIO;
 890                 goto err_unmap_base;
 891         }
 892
 893         ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
 894         if (!ag->mii_ctrl) {
 895                 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
 896                 err = -ENOMEM;
 897                 goto err_unmap_base;
 898         }
 899
 900         dev->irq = platform_get_irq(pdev, 0);
 901         err = request_irq(dev->irq, ag71xx_interrupt,
 902                           IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
 903                           dev->name, dev);
 904         if (err) {
 905                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
 906                 goto err_unmap_mii_ctrl;
 907         }
 908
 909         dev->base_addr = (unsigned long)ag->mac_base;
 910         dev->netdev_ops = &ag71xx_netdev_ops;
 911         dev->ethtool_ops = &ag71xx_ethtool_ops;
 912
 913         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
 914
 915         init_timer(&ag->oom_timer);
 916         ag->oom_timer.data = (unsigned long) dev;
 917         ag->oom_timer.function = ag71xx_oom_timer_handler;
 918
 919         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
 920
 921         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
 922
 923         err = register_netdev(dev);
 924         if (err) {
 925                 dev_err(&pdev->dev, "unable to register net device\n");
 926                 goto err_free_irq;
 927         }
 928
 929         printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
 930                dev->name, dev->base_addr, dev->irq);
 931
 932         ag71xx_dump_regs(ag);
 933
 934         ag71xx_hw_init(ag);
 935
 936         ag71xx_dump_regs(ag);
 937
 938         err = ag71xx_phy_connect(ag);
 939         if (err)
 940                 goto err_unregister_netdev;
 941
 942         err = ag71xx_debugfs_init(ag);
 943         if (err)
 944                 goto err_phy_disconnect;
 945
 946         platform_set_drvdata(pdev, dev);
 947
 948         return 0;
 949
 950  err_phy_disconnect:
 951         ag71xx_phy_disconnect(ag);
 952  err_unregister_netdev:
 953         unregister_netdev(dev);
 954  err_free_irq:
 955         free_irq(dev->irq, dev);
 956  err_unmap_mii_ctrl:
 957         iounmap(ag->mii_ctrl);
 958  err_unmap_base:
 959         iounmap(ag->mac_base);
 960  err_free_dev:
 961         kfree(dev);
 962  err_out:
 963         platform_set_drvdata(pdev, NULL);
 964         return err;
 965 }
 966
 967 static int __exit ag71xx_remove(struct platform_device *pdev)
 968 {
 969         struct net_device *dev = platform_get_drvdata(pdev);
 970
 971         if (dev) {
 972                 struct ag71xx *ag = netdev_priv(dev);
 973
 974                 ag71xx_debugfs_exit(ag);
 975                 ag71xx_phy_disconnect(ag);
 976                 unregister_netdev(dev);
 977                 free_irq(dev->irq, dev);
 978                 iounmap(ag->mii_ctrl);
 979                 iounmap(ag->mac_base);
 980                 kfree(dev);
 981                 platform_set_drvdata(pdev, NULL);
 982         }
 983
 984         return 0;
 985 }
 986
 987 static struct platform_driver ag71xx_driver = {
 988         .probe          = ag71xx_probe,
 989         .remove         = __exit_p(ag71xx_remove),
 990         .driver = {
 991                 .name   = AG71XX_DRV_NAME,
 992         }
 993 };
 994
 995 static int __init ag71xx_module_init(void)
 996 {
 997         int ret;
 998
 999         ret = ag71xx_debugfs_root_init();
1000         if (ret)
1001                 goto err_out;
1002
1003         ret = ag71xx_mdio_driver_init();
1004         if (ret)
1005                 goto err_debugfs_exit;
1006
1007         ret = platform_driver_register(&ag71xx_driver);
1008         if (ret)
1009                 goto err_mdio_exit;
1010
1011         return 0;
1012
1013  err_mdio_exit:
1014         ag71xx_mdio_driver_exit();
1015  err_debugfs_exit:
1016         ag71xx_debugfs_root_exit();
1017  err_out:
1018         return ret;
1019 }
1020
1021 static void __exit ag71xx_module_exit(void)
1022 {
1023         platform_driver_unregister(&ag71xx_driver);
1024         ag71xx_mdio_driver_exit();
1025         ag71xx_debugfs_root_exit();
1026 }
1027
1028 module_init(ag71xx_module_init);
1029 module_exit(ag71xx_module_exit);
1030
1031 MODULE_VERSION(AG71XX_DRV_VERSION);
1032 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1033 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1034 MODULE_LICENSE("GPL v2");
1035 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);