target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 #define AG71XX_DEFAULT_MSG_ENABLE       \
  17         ( NETIF_MSG_DRV                 \
  18         | NETIF_MSG_PROBE               \
  19         | NETIF_MSG_LINK                \
  20         | NETIF_MSG_TIMER               \
  21         | NETIF_MSG_IFDOWN              \
  22         | NETIF_MSG_IFUP                \
  23         | NETIF_MSG_RX_ERR              \
  24         | NETIF_MSG_TX_ERR )
  25
  26 static int ag71xx_msg_level = -1;
  27
  28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
  29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  30
  31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  32 {
  33         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  34                 ag->dev->name,
  35                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  36                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  37                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  38
  39         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  40                 ag->dev->name,
  41                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  42                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  43                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  44 }
  45
  46 static void ag71xx_dump_regs(struct ag71xx *ag)
  47 {
  48         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  49                 ag->dev->name,
  50                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  52                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  53                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  54                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  55         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  56                 ag->dev->name,
  57                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  58                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  60         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  61                 ag->dev->name,
  62                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  65         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  66                 ag->dev->name,
  67                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  70 }
  71
  72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  73 {
  74         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  75                 ag->dev->name, label, intr,
  76                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  77                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  78                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  79                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  80                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  81                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  82 }
  83
  84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
  85 {
  86         kfree(ring->buf);
  87
  88         if (ring->descs_cpu)
  89                 dma_free_coherent(NULL, ring->size * ring->desc_size,
  90                                   ring->descs_cpu, ring->descs_dma);
  91 }
  92
  93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
  94 {
  95         int err;
  96         int i;
  97
  98         ring->desc_size = sizeof(struct ag71xx_desc);
  99         if (ring->desc_size % cache_line_size()) {
 100                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
 101                         ring, ring->desc_size,
 102                         roundup(ring->desc_size, cache_line_size()));
 103                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
 104         }
 105
 106         ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
 107                                              &ring->descs_dma, GFP_ATOMIC);
 108         if (!ring->descs_cpu) {
 109                 err = -ENOMEM;
 110                 goto err;
 111         }
 112
 113         ring->size = size;
 114
 115         ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
 116         if (!ring->buf) {
 117                 err = -ENOMEM;
 118                 goto err;
 119         }
 120
 121         for (i = 0; i < size; i++) {
 122                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
 123                 DBG("ag71xx: ring %p, desc %d at %p\n",
 124                         ring, i, ring->buf[i].desc);
 125         }
 126
 127         return 0;
 128
 129  err:
 130         return err;
 131 }
 132
 133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
 134 {
 135         struct ag71xx_ring *ring = &ag->tx_ring;
 136         struct net_device *dev = ag->dev;
 137
 138         while (ring->curr != ring->dirty) {
 139                 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
 140
 141                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
 142                         ring->buf[i].desc->ctrl = 0;
 143                         dev->stats.tx_errors++;
 144                 }
 145
 146                 if (ring->buf[i].skb)
 147                         dev_kfree_skb_any(ring->buf[i].skb);
 148
 149                 ring->buf[i].skb = NULL;
 150
 151                 ring->dirty++;
 152         }
 153
 154         /* flush descriptors */
 155         wmb();
 156
 157 }
 158
 159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
 160 {
 161         struct ag71xx_ring *ring = &ag->tx_ring;
 162         int i;
 163
 164         for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
 165                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 166                         ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
 167
 168                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 169                 ring->buf[i].skb = NULL;
 170         }
 171
 172         /* flush descriptors */
 173         wmb();
 174
 175         ring->curr = 0;
 176         ring->dirty = 0;
 177 }
 178
 179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
 180 {
 181         struct ag71xx_ring *ring = &ag->rx_ring;
 182         int i;
 183
 184         if (!ring->buf)
 185                 return;
 186
 187         for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
 188                 if (ring->buf[i].skb) {
 189                         dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
 190                                          AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
 191                         kfree_skb(ring->buf[i].skb);
 192                 }
 193 }
 194
 195 static int ag71xx_ring_rx_init(struct ag71xx *ag)
 196 {
 197         struct ag71xx_ring *ring = &ag->rx_ring;
 198         unsigned int i;
 199         int ret;
 200
 201         ret = 0;
 202         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 203                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 204                         ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
 205
 206                 DBG("ag71xx: RX desc at %p, next is %08x\n",
 207                         ring->buf[i].desc,
 208                         ring->buf[i].desc->next);
 209         }
 210
 211         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 212                 struct sk_buff *skb;
 213                 dma_addr_t dma_addr;
 214
 215                 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + AG71XX_RX_PKT_RESERVE);
 216                 if (!skb) {
 217                         ret = -ENOMEM;
 218                         break;
 219                 }
 220
 221                 skb->dev = ag->dev;
 222                 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
 223
 224                 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 225                                           AG71XX_RX_PKT_SIZE,
 226                                           DMA_FROM_DEVICE);
 227                 ring->buf[i].skb = skb;
 228                 ring->buf[i].dma_addr = dma_addr;
 229                 ring->buf[i].desc->data = (u32) dma_addr;
 230                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 231         }
 232
 233         /* flush descriptors */
 234         wmb();
 235
 236         ring->curr = 0;
 237         ring->dirty = 0;
 238
 239         return ret;
 240 }
 241
 242 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
 243 {
 244         struct ag71xx_ring *ring = &ag->rx_ring;
 245         unsigned int count;
 246
 247         count = 0;
 248         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
 249                 unsigned int i;
 250
 251                 i = ring->dirty % AG71XX_RX_RING_SIZE;
 252
 253                 if (ring->buf[i].skb == NULL) {
 254                         dma_addr_t dma_addr;
 255                         struct sk_buff *skb;
 256
 257                         skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE +
 258                                             AG71XX_RX_PKT_RESERVE);
 259                         if (skb == NULL)
 260                                 break;
 261
 262                         skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
 263                         skb->dev = ag->dev;
 264
 265                         dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 266                                                   AG71XX_RX_PKT_SIZE,
 267                                                   DMA_FROM_DEVICE);
 268
 269                         ring->buf[i].skb = skb;
 270                         ring->buf[i].dma_addr = dma_addr;
 271                         ring->buf[i].desc->data = (u32) dma_addr;
 272                 }
 273
 274                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 275                 count++;
 276         }
 277
 278         /* flush descriptors */
 279         wmb();
 280
 281         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
 282
 283         return count;
 284 }
 285
 286 static int ag71xx_rings_init(struct ag71xx *ag)
 287 {
 288         int ret;
 289
 290         ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
 291         if (ret)
 292                 return ret;
 293
 294         ag71xx_ring_tx_init(ag);
 295
 296         ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
 297         if (ret)
 298                 return ret;
 299
 300         ret = ag71xx_ring_rx_init(ag);
 301         return ret;
 302 }
 303
 304 static void ag71xx_rings_cleanup(struct ag71xx *ag)
 305 {
 306         ag71xx_ring_rx_clean(ag);
 307         ag71xx_ring_free(&ag->rx_ring);
 308
 309         ag71xx_ring_tx_clean(ag);
 310         ag71xx_ring_free(&ag->tx_ring);
 311 }
 312
 313 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
 314 {
 315         switch (ag->speed) {
 316         case SPEED_1000:
 317                 return "1000";
 318         case SPEED_100:
 319                 return "100";
 320         case SPEED_10:
 321                 return "10";
 322         }
 323
 324         return "?";
 325 }
 326
 327 void ag71xx_link_adjust(struct ag71xx *ag)
 328 {
 329         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 330         u32 cfg2;
 331         u32 ifctl;
 332         u32 fifo5;
 333         u32 mii_speed;
 334
 335         if (!ag->link) {
 336                 netif_carrier_off(ag->dev);
 337                 if (netif_msg_link(ag))
 338                         printk(KERN_INFO "%s: link down\n", ag->dev->name);
 339                 return;
 340         }
 341
 342         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
 343         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
 344         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
 345
 346         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
 347         ifctl &= ~(MAC_IFCTL_SPEED);
 348
 349         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
 350         fifo5 &= ~FIFO_CFG5_BM;
 351
 352         switch (ag->speed) {
 353         case SPEED_1000:
 354                 mii_speed =  MII_CTRL_SPEED_1000;
 355                 cfg2 |= MAC_CFG2_IF_1000;
 356                 fifo5 |= FIFO_CFG5_BM;
 357                 break;
 358         case SPEED_100:
 359                 mii_speed = MII_CTRL_SPEED_100;
 360                 cfg2 |= MAC_CFG2_IF_10_100;
 361                 ifctl |= MAC_IFCTL_SPEED;
 362                 break;
 363         case SPEED_10:
 364                 mii_speed = MII_CTRL_SPEED_10;
 365                 cfg2 |= MAC_CFG2_IF_10_100;
 366                 break;
 367         default:
 368                 BUG();
 369                 return;
 370         }
 371
 372         if (pdata->is_ar91xx)
 373                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
 374         else if (pdata->is_ar724x)
 375                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
 376         else
 377                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
 378
 379         if (pdata->set_pll)
 380                 pdata->set_pll(ag->speed);
 381
 382         ag71xx_mii_ctrl_set_speed(ag, mii_speed);
 383
 384         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
 385         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
 386         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
 387
 388         netif_carrier_on(ag->dev);
 389         if (netif_msg_link(ag))
 390                 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
 391                         ag->dev->name,
 392                         ag71xx_speed_str(ag),
 393                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
 394
 395         DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
 396                 ag->dev->name,
 397                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
 398                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
 399                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
 400
 401         DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
 402                 ag->dev->name,
 403                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
 404                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
 405                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
 406
 407         DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
 408                 ag->dev->name,
 409                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
 410                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
 411                 ag71xx_mii_ctrl_rr(ag));
 412 }
 413
 414 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 415 {
 416         u32 t;
 417
 418         t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
 419           | (((u32) mac[3]) << 8) | ((u32) mac[2]);
 420
 421         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
 422
 423         t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
 424         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 425 }
 426
 427 static void ag71xx_dma_reset(struct ag71xx *ag)
 428 {
 429         u32 val;
 430         int i;
 431
 432         ag71xx_dump_dma_regs(ag);
 433
 434         /* stop RX and TX */
 435         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 436         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 437
 438         /* clear descriptor addresses */
 439         ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
 440         ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
 441
 442         /* clear pending RX/TX interrupts */
 443         for (i = 0; i < 256; i++) {
 444                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 445                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 446         }
 447
 448         /* clear pending errors */
 449         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
 450         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
 451
 452         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 453         if (val)
 454                 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
 455                         ag->dev->name, val);
 456
 457         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 458
 459         /* mask out reserved bits */
 460         val &= ~0xff000000;
 461
 462         if (val)
 463                 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
 464                         ag->dev->name, val);
 465
 466         ag71xx_dump_dma_regs(ag);
 467 }
 468
 469 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
 470                          MAC_CFG1_SRX | MAC_CFG1_STX)
 471
 472 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
 473
 474 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
 475                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
 476                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
 477                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
 478                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
 479                          FIFO_CFG4_VT)
 480
 481 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
 482                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
 483                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
 484                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
 485                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
 486                          FIFO_CFG5_17 | FIFO_CFG5_SF)
 487
 488 static void ag71xx_hw_init(struct ag71xx *ag)
 489 {
 490         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 491
 492         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
 493         udelay(20);
 494
 495         ar71xx_device_stop(pdata->reset_bit);
 496         mdelay(100);
 497         ar71xx_device_start(pdata->reset_bit);
 498         mdelay(100);
 499
 500         /* setup MAC configuration registers */
 501         if (pdata->is_ar724x)
 502                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
 503                           MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC);
 504         else
 505                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
 506
 507         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 508                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 509
 510         /* setup max frame length */
 511         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
 512
 513         /* setup MII interface type */
 514         ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
 515
 516         /* setup FIFO configuration registers */
 517         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 518         if (pdata->is_ar724x) {
 519                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
 520                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
 521         } else {
 522                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
 523                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
 524         }
 525         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
 526         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 527
 528         ag71xx_dma_reset(ag);
 529 }
 530
 531 static void ag71xx_hw_start(struct ag71xx *ag)
 532 {
 533         /* start RX engine */
 534         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 535
 536         /* enable interrupts */
 537         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
 538 }
 539
 540 static void ag71xx_hw_stop(struct ag71xx *ag)
 541 {
 542         /* disable all interrupts */
 543         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
 544
 545         ag71xx_dma_reset(ag);
 546 }
 547
 548 static int ag71xx_open(struct net_device *dev)
 549 {
 550         struct ag71xx *ag = netdev_priv(dev);
 551         int ret;
 552
 553         ret = ag71xx_rings_init(ag);
 554         if (ret)
 555                 goto err;
 556
 557         napi_enable(&ag->napi);
 558
 559         netif_carrier_off(dev);
 560         ag71xx_phy_start(ag);
 561
 562         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 563         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
 564
 565         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 566
 567         ag71xx_hw_start(ag);
 568
 569         netif_start_queue(dev);
 570
 571         return 0;
 572
 573  err:
 574         ag71xx_rings_cleanup(ag);
 575         return ret;
 576 }
 577
 578 static int ag71xx_stop(struct net_device *dev)
 579 {
 580         struct ag71xx *ag = netdev_priv(dev);
 581         unsigned long flags;
 582
 583         netif_carrier_off(dev);
 584         ag71xx_phy_stop(ag);
 585
 586         spin_lock_irqsave(&ag->lock, flags);
 587
 588         netif_stop_queue(dev);
 589
 590         ag71xx_hw_stop(ag);
 591
 592         napi_disable(&ag->napi);
 593         del_timer_sync(&ag->oom_timer);
 594
 595         spin_unlock_irqrestore(&ag->lock, flags);
 596
 597         ag71xx_rings_cleanup(ag);
 598
 599         return 0;
 600 }
 601
 602 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
 603                                           struct net_device *dev)
 604 {
 605         struct ag71xx *ag = netdev_priv(dev);
 606         struct ag71xx_ring *ring = &ag->tx_ring;
 607         struct ag71xx_desc *desc;
 608         dma_addr_t dma_addr;
 609         int i;
 610
 611         i = ring->curr % AG71XX_TX_RING_SIZE;
 612         desc = ring->buf[i].desc;
 613
 614         if (!ag71xx_desc_empty(desc))
 615                 goto err_drop;
 616
 617         ag71xx_add_ar8216_header(ag, skb);
 618
 619         if (skb->len <= 0) {
 620                 DBG("%s: packet len is too small\n", ag->dev->name);
 621                 goto err_drop;
 622         }
 623
 624         dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
 625                                   DMA_TO_DEVICE);
 626
 627         ring->buf[i].skb = skb;
 628
 629         /* setup descriptor fields */
 630         desc->data = (u32) dma_addr;
 631         desc->ctrl = (skb->len & DESC_PKTLEN_M);
 632
 633         /* flush descriptor */
 634         wmb();
 635
 636         ring->curr++;
 637         if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
 638                 DBG("%s: tx queue full\n", ag->dev->name);
 639                 netif_stop_queue(dev);
 640         }
 641
 642         DBG("%s: packet injected into TX queue\n", ag->dev->name);
 643
 644         /* enable TX engine */
 645         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
 646
 647         return NETDEV_TX_OK;
 648
 649  err_drop:
 650         dev->stats.tx_dropped++;
 651
 652         dev_kfree_skb(skb);
 653         return NETDEV_TX_OK;
 654 }
 655
 656 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 657 {
 658         struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
 659         struct ag71xx *ag = netdev_priv(dev);
 660         int ret;
 661
 662         switch (cmd) {
 663         case SIOCETHTOOL:
 664                 if (ag->phy_dev == NULL)
 665                         break;
 666
 667                 spin_lock_irq(&ag->lock);
 668                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
 669                 spin_unlock_irq(&ag->lock);
 670                 return ret;
 671
 672         case SIOCSIFHWADDR:
 673                 if (copy_from_user
 674                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
 675                         return -EFAULT;
 676                 return 0;
 677
 678         case SIOCGIFHWADDR:
 679                 if (copy_to_user
 680                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
 681                         return -EFAULT;
 682                 return 0;
 683
 684         case SIOCGMIIPHY:
 685         case SIOCGMIIREG:
 686         case SIOCSMIIREG:
 687                 if (ag->phy_dev == NULL)
 688                         break;
 689
 690                 return phy_mii_ioctl(ag->phy_dev, data, cmd);
 691
 692         default:
 693                 break;
 694         }
 695
 696         return -EOPNOTSUPP;
 697 }
 698
 699 static void ag71xx_oom_timer_handler(unsigned long data)
 700 {
 701         struct net_device *dev = (struct net_device *) data;
 702         struct ag71xx *ag = netdev_priv(dev);
 703
 704         napi_schedule(&ag->napi);
 705 }
 706
 707 static void ag71xx_tx_timeout(struct net_device *dev)
 708 {
 709         struct ag71xx *ag = netdev_priv(dev);
 710
 711         if (netif_msg_tx_err(ag))
 712                 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
 713
 714         schedule_work(&ag->restart_work);
 715 }
 716
 717 static void ag71xx_restart_work_func(struct work_struct *work)
 718 {
 719         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
 720
 721         ag71xx_stop(ag->dev);
 722         ag71xx_open(ag->dev);
 723 }
 724
 725 static int ag71xx_tx_packets(struct ag71xx *ag)
 726 {
 727         struct ag71xx_ring *ring = &ag->tx_ring;
 728         int sent;
 729
 730         DBG("%s: processing TX ring\n", ag->dev->name);
 731
 732         sent = 0;
 733         while (ring->dirty != ring->curr) {
 734                 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
 735                 struct ag71xx_desc *desc = ring->buf[i].desc;
 736                 struct sk_buff *skb = ring->buf[i].skb;
 737
 738                 if (!ag71xx_desc_empty(desc))
 739                         break;
 740
 741                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 742
 743                 ag->dev->stats.tx_bytes += skb->len;
 744                 ag->dev->stats.tx_packets++;
 745
 746                 dev_kfree_skb_any(skb);
 747                 ring->buf[i].skb = NULL;
 748
 749                 ring->dirty++;
 750                 sent++;
 751         }
 752
 753         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
 754
 755         if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
 756                 netif_wake_queue(ag->dev);
 757
 758         return sent;
 759 }
 760
 761 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 762 {
 763         struct net_device *dev = ag->dev;
 764         struct ag71xx_ring *ring = &ag->rx_ring;
 765         int done = 0;
 766
 767         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
 768                         dev->name, limit, ring->curr, ring->dirty);
 769
 770         while (done < limit) {
 771                 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
 772                 struct ag71xx_desc *desc = ring->buf[i].desc;
 773                 struct sk_buff *skb;
 774                 int pktlen;
 775
 776                 if (ag71xx_desc_empty(desc))
 777                         break;
 778
 779                 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
 780                         ag71xx_assert(0);
 781                         break;
 782                 }
 783
 784                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 785
 786                 skb = ring->buf[i].skb;
 787                 pktlen = ag71xx_desc_pktlen(desc);
 788                 pktlen -= ETH_FCS_LEN;
 789
 790                 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
 791                                  AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
 792
 793                 skb_put(skb, pktlen);
 794
 795                 skb->dev = dev;
 796                 skb->ip_summed = CHECKSUM_NONE;
 797
 798                 dev->last_rx = jiffies;
 799                 dev->stats.rx_packets++;
 800                 dev->stats.rx_bytes += pktlen;
 801
 802                 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
 803                         dev->stats.rx_dropped++;
 804                         kfree_skb(skb);
 805                 } else {
 806                         skb->protocol = eth_type_trans(skb, dev);
 807                         netif_receive_skb(skb);
 808                 }
 809
 810                 ring->buf[i].skb = NULL;
 811                 done++;
 812
 813                 ring->curr++;
 814         }
 815
 816         ag71xx_ring_rx_refill(ag);
 817
 818         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
 819                 dev->name, ring->curr, ring->dirty, done);
 820
 821         return done;
 822 }
 823
 824 static int ag71xx_poll(struct napi_struct *napi, int limit)
 825 {
 826         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
 827         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 828         struct net_device *dev = ag->dev;
 829         struct ag71xx_ring *rx_ring;
 830         unsigned long flags;
 831         u32 status;
 832         int tx_done;
 833         int rx_done;
 834
 835         pdata->ddr_flush();
 836         tx_done = ag71xx_tx_packets(ag);
 837
 838         DBG("%s: processing RX ring\n", dev->name);
 839         rx_done = ag71xx_rx_packets(ag, limit);
 840
 841         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
 842
 843         rx_ring = &ag->rx_ring;
 844         if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
 845                 goto oom;
 846
 847         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 848         if (unlikely(status & RX_STATUS_OF)) {
 849                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
 850                 dev->stats.rx_fifo_errors++;
 851
 852                 /* restart RX */
 853                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 854         }
 855
 856         if (rx_done < limit) {
 857                 if (status & RX_STATUS_PR)
 858                         goto more;
 859
 860                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 861                 if (status & TX_STATUS_PS)
 862                         goto more;
 863
 864                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
 865                         dev->name, rx_done, tx_done, limit);
 866
 867                 napi_complete(napi);
 868
 869                 /* enable interrupts */
 870                 spin_lock_irqsave(&ag->lock, flags);
 871                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
 872                 spin_unlock_irqrestore(&ag->lock, flags);
 873                 return rx_done;
 874         }
 875
 876  more:
 877         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
 878                         dev->name, rx_done, tx_done, limit);
 879         return rx_done;
 880
 881  oom:
 882         if (netif_msg_rx_err(ag))
 883                 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
 884
 885         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
 886         napi_complete(napi);
 887         return 0;
 888 }
 889
 890 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
 891 {
 892         struct net_device *dev = dev_id;
 893         struct ag71xx *ag = netdev_priv(dev);
 894         u32 status;
 895
 896         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
 897         ag71xx_dump_intr(ag, "raw", status);
 898
 899         if (unlikely(!status))
 900                 return IRQ_NONE;
 901
 902         if (unlikely(status & AG71XX_INT_ERR)) {
 903                 if (status & AG71XX_INT_TX_BE) {
 904                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
 905                         dev_err(&dev->dev, "TX BUS error\n");
 906                 }
 907                 if (status & AG71XX_INT_RX_BE) {
 908                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
 909                         dev_err(&dev->dev, "RX BUS error\n");
 910                 }
 911         }
 912
 913         if (likely(status & AG71XX_INT_POLL)) {
 914                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
 915                 DBG("%s: enable polling mode\n", dev->name);
 916                 napi_schedule(&ag->napi);
 917         }
 918
 919         ag71xx_debugfs_update_int_stats(ag, status);
 920
 921         return IRQ_HANDLED;
 922 }
 923
 924 static void ag71xx_set_multicast_list(struct net_device *dev)
 925 {
 926         /* TODO */
 927 }
 928
 929 static const struct net_device_ops ag71xx_netdev_ops = {
 930         .ndo_open               = ag71xx_open,
 931         .ndo_stop               = ag71xx_stop,
 932         .ndo_start_xmit         = ag71xx_hard_start_xmit,
 933         .ndo_set_multicast_list = ag71xx_set_multicast_list,
 934         .ndo_do_ioctl           = ag71xx_do_ioctl,
 935         .ndo_tx_timeout         = ag71xx_tx_timeout,
 936         .ndo_change_mtu         = eth_change_mtu,
 937         .ndo_set_mac_address    = eth_mac_addr,
 938         .ndo_validate_addr      = eth_validate_addr,
 939 };
 940
 941 static int __init ag71xx_probe(struct platform_device *pdev)
 942 {
 943         struct net_device *dev;
 944         struct resource *res;
 945         struct ag71xx *ag;
 946         struct ag71xx_platform_data *pdata;
 947         int err;
 948
 949         pdata = pdev->dev.platform_data;
 950         if (!pdata) {
 951                 dev_err(&pdev->dev, "no platform data specified\n");
 952                 err = -ENXIO;
 953                 goto err_out;
 954         }
 955
 956         if (pdata->mii_bus_dev == NULL) {
 957                 dev_err(&pdev->dev, "no MII bus device specified\n");
 958                 err = -EINVAL;
 959                 goto err_out;
 960         }
 961
 962         dev = alloc_etherdev(sizeof(*ag));
 963         if (!dev) {
 964                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
 965                 err = -ENOMEM;
 966                 goto err_out;
 967         }
 968
 969         SET_NETDEV_DEV(dev, &pdev->dev);
 970
 971         ag = netdev_priv(dev);
 972         ag->pdev = pdev;
 973         ag->dev = dev;
 974         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
 975                                         AG71XX_DEFAULT_MSG_ENABLE);
 976         spin_lock_init(&ag->lock);
 977
 978         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
 979         if (!res) {
 980                 dev_err(&pdev->dev, "no mac_base resource found\n");
 981                 err = -ENXIO;
 982                 goto err_out;
 983         }
 984
 985         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
 986         if (!ag->mac_base) {
 987                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
 988                 err = -ENOMEM;
 989                 goto err_free_dev;
 990         }
 991
 992         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
 993         if (!res) {
 994                 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
 995                 err = -ENXIO;
 996                 goto err_unmap_base;
 997         }
 998
 999         ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1000         if (!ag->mii_ctrl) {
1001                 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1002                 err = -ENOMEM;
1003                 goto err_unmap_base;
1004         }
1005
1006         dev->irq = platform_get_irq(pdev, 0);
1007         err = request_irq(dev->irq, ag71xx_interrupt,
1008                           IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
1009                           dev->name, dev);
1010         if (err) {
1011                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1012                 goto err_unmap_mii_ctrl;
1013         }
1014
1015         dev->base_addr = (unsigned long)ag->mac_base;
1016         dev->netdev_ops = &ag71xx_netdev_ops;
1017         dev->ethtool_ops = &ag71xx_ethtool_ops;
1018
1019         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1020
1021         init_timer(&ag->oom_timer);
1022         ag->oom_timer.data = (unsigned long) dev;
1023         ag->oom_timer.function = ag71xx_oom_timer_handler;
1024
1025         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1026
1027         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1028
1029         err = register_netdev(dev);
1030         if (err) {
1031                 dev_err(&pdev->dev, "unable to register net device\n");
1032                 goto err_free_irq;
1033         }
1034
1035         printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1036                dev->name, dev->base_addr, dev->irq);
1037
1038         ag71xx_dump_regs(ag);
1039
1040         ag71xx_hw_init(ag);
1041
1042         ag71xx_dump_regs(ag);
1043
1044         err = ag71xx_phy_connect(ag);
1045         if (err)
1046                 goto err_unregister_netdev;
1047
1048         err = ag71xx_debugfs_init(ag);
1049         if (err)
1050                 goto err_phy_disconnect;
1051
1052         platform_set_drvdata(pdev, dev);
1053
1054         return 0;
1055
1056  err_phy_disconnect:
1057         ag71xx_phy_disconnect(ag);
1058  err_unregister_netdev:
1059         unregister_netdev(dev);
1060  err_free_irq:
1061         free_irq(dev->irq, dev);
1062  err_unmap_mii_ctrl:
1063         iounmap(ag->mii_ctrl);
1064  err_unmap_base:
1065         iounmap(ag->mac_base);
1066  err_free_dev:
1067         kfree(dev);
1068  err_out:
1069         platform_set_drvdata(pdev, NULL);
1070         return err;
1071 }
1072
1073 static int __exit ag71xx_remove(struct platform_device *pdev)
1074 {
1075         struct net_device *dev = platform_get_drvdata(pdev);
1076
1077         if (dev) {
1078                 struct ag71xx *ag = netdev_priv(dev);
1079
1080                 ag71xx_debugfs_exit(ag);
1081                 ag71xx_phy_disconnect(ag);
1082                 unregister_netdev(dev);
1083                 free_irq(dev->irq, dev);
1084                 iounmap(ag->mii_ctrl);
1085                 iounmap(ag->mac_base);
1086                 kfree(dev);
1087                 platform_set_drvdata(pdev, NULL);
1088         }
1089
1090         return 0;
1091 }
1092
1093 static struct platform_driver ag71xx_driver = {
1094         .probe          = ag71xx_probe,
1095         .remove         = __exit_p(ag71xx_remove),
1096         .driver = {
1097                 .name   = AG71XX_DRV_NAME,
1098         }
1099 };
1100
1101 static int __init ag71xx_module_init(void)
1102 {
1103         int ret;
1104
1105         ret = ag71xx_debugfs_root_init();
1106         if (ret)
1107                 goto err_out;
1108
1109         ret = ag71xx_mdio_driver_init();
1110         if (ret)
1111                 goto err_debugfs_exit;
1112
1113         ret = platform_driver_register(&ag71xx_driver);
1114         if (ret)
1115                 goto err_mdio_exit;
1116
1117         return 0;
1118
1119  err_mdio_exit:
1120         ag71xx_mdio_driver_exit();
1121  err_debugfs_exit:
1122         ag71xx_debugfs_root_exit();
1123  err_out:
1124         return ret;
1125 }
1126
1127 static void __exit ag71xx_module_exit(void)
1128 {
1129         platform_driver_unregister(&ag71xx_driver);
1130         ag71xx_mdio_driver_exit();
1131         ag71xx_debugfs_root_exit();
1132 }
1133
1134 module_init(ag71xx_module_init);
1135 module_exit(ag71xx_module_exit);
1136
1137 MODULE_VERSION(AG71XX_DRV_VERSION);
1138 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1139 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1140 MODULE_LICENSE("GPL v2");
1141 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);